CN111180424A

CN111180424A - Stacked structure, semiconductor package structure and fabrication process of the stacked structure

Info

Publication number: CN111180424A
Application number: CN201811346232.7A
Authority: CN
Inventors: 不公告发明人
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2018-11-13
Filing date: 2018-11-13
Publication date: 2020-05-19

Abstract

The present disclosure provides a stack structure, a semiconductor packaging structure, and a fabrication process of the stack structure. The stacked structure includes a substrate and a plurality of first chips. A plurality of first chips are stacked on the substrate. Wherein, a part of any two of the plurality of first chips is overlapped, and the other part is rotated staggered, and the plurality of first chips are electrically connected to the substrate through first leads. Through the above design, the present disclosure can realize the fabrication of a multi-layer chip stack package. That is, the present disclosure can meet the stacking requirements of multi-layer chips, and at the same time make the wire bonding positions of each chip reasonably distributed, reduce the wire bonding process and the difficulty of substrate fabrication, improve the wire bonding yield, and reduce the substrate cost.

Description

Stacking structure, semiconductor packaging structure and preparation process of stacking structure

Technical Field

The disclosure relates to the technical field of semiconductor device design, in particular to a stacked structure, a semiconductor packaging structure and a preparation process of the stacked structure.

Background

In the design of a semiconductor device, the following design scheme is generally adopted for the stack of multilayer memory chips.

The first is to locate the wire bonding area of the lower chip on the bottom surface and the wire bonding area of the upper chip on the top surface, the substrate is provided with a slot, the wire bonding area of the lower chip is electrically connected with the bottom surface of the substrate by passing through the slot by a lead, and the wire bonding area of the upper chip is electrically connected with the top surface of the substrate by another lead. However, the conventional design can only meet the requirements of the arrangement and routing of two stacked chips, and cannot meet the stacking requirements of a larger number of multi-layer chips.

And secondly, a plurality of chips are superposed and bonded through glue layers, the wiring areas of the chips are arranged on the two sides of the respective top surfaces, and the wiring areas are electrically connected with the substrates on the two sides through leads through the respective glue layers. However, the more chips of the conventional design stack, the more leads are wired on the same side, and the smaller the bonding finger pitch (bonding finger pitch) of the wire on the substrate is, the more difficult the wire bonding process and the substrate manufacturing process are, the lower the wire bonding yield is, and the substrate cost is increased.

Disclosure of Invention

It is a primary object of the present disclosure to overcome at least one of the above-mentioned drawbacks of the prior art and to provide a stacked structure that is suitable for stacking multiple chips and is easy to manufacture and has a high yield.

Another primary object of the present disclosure is to overcome at least one of the above-mentioned drawbacks of the prior art and to provide a semiconductor package structure having the above-mentioned stacked structure.

It is yet another primary object of the present disclosure to overcome at least one of the above-mentioned drawbacks of the prior art and to provide a process for manufacturing a stacked structure.

In order to achieve the purpose, the following technical scheme is adopted in the disclosure:

according to one aspect of the present disclosure, a stacked structure is provided. The stacked structure comprises a substrate and a plurality of first chips. A plurality of the first chips are stacked on the substrate. Wherein a part of any two of the first chips is overlapped, the other part is staggered in rotation, and the first chips are electrically connected to the substrate through first leads.

According to one embodiment of the present disclosure, the wire bonding area of each first chip is disposed on the bottom surface of the first chip, an orthographic projection of any one of the wire bonding areas of the first chip on the substrate is not overlapped with an orthographic projection of each other of the first chips on the substrate, and the first lead is electrically connected between the wire bonding area of the first chip and the substrate.

According to one embodiment of the present disclosure, the substrate is provided with a plurality of through grooves, the through grooves are respectively and correspondingly formed below the wire bonding areas of the first chips, one end of each first lead is electrically connected to the wire bonding area of the first chip, and the other end of each first lead passes through the through groove corresponding to the position of the through groove and is electrically connected to the bottom surface of the substrate.

According to one embodiment of the present disclosure, the stacked structure further includes at least one second chip, the at least one second chip is stacked on the uppermost first chip, the package layer is packaged outside the substrate, the plurality of first chips and the at least one second chip, the wire bonding area of each second chip is disposed on the top surface of the second chip, a portion of any two of the plurality of second chips is overlapped, and another portion of any two of the plurality of second chips is staggered, so that an orthographic projection of the wire bonding area of any one of the second chips on the substrate is not overlapped with an orthographic projection of any other of the second chips on the substrate, the plurality of second chips are electrically connected to the substrate through second leads, one end of each second lead is electrically connected to the wire bonding area of the second chip, and the other end of each second lead is electrically connected to the top surface of the substrate.

According to one embodiment of the present disclosure, the stacked structure further includes a plurality of the second chips, the plurality of the second chips are sequentially and partially staggered from bottom to top along an arrangement direction, and orthogonal projections of the wire bonding areas of the plurality of the second chips on the substrate are distributed at intervals along the arrangement direction.

According to one embodiment of the present disclosure, each of the second chips has a first end and a second end in the arrangement direction, and the first ends of the second chips are exposed by a partially staggered arrangement in sequence. The wire bonding area of the second chip at the top is positioned on the top surface of the second end, and the wire bonding areas of the other second chips are positioned on the top surfaces of the respective first ends.

According to one embodiment of the present disclosure, a second adhesive layer is disposed on a bottom surface of each of the second chips, and the second chip is bonded to another second chip below the second chip or the uppermost first chip through the second adhesive layer.

According to one embodiment of the present disclosure, the stacked structure further includes a protection sheet and a third adhesive layer, the third adhesive layer is disposed on the bottom surface of the protection sheet, the protection sheet is bonded to the uppermost second chip through the third adhesive layer, the second lead is electrically connected to the wire bonding area of the second chip, one end of the second lead is electrically connected to the wire bonding area, and the other end of the second lead is electrically connected to the top surface of the substrate through the third adhesive layer. Wherein the packaging layer is packaged outside the substrate, the plurality of first chips, the at least one second chip and the protective sheet.

According to one embodiment of the present disclosure, the first chips are sequentially staggered in a clockwise or counterclockwise direction from bottom to top.

According to one embodiment of the present disclosure, included angles staggered between orthographic projections of every two adjacent first chips on the substrate are all equal.

According to one embodiment of the present disclosure, the chip packaging structure includes four first chips, and an included angle that is staggered between orthographic projections of every two adjacent first chips on the substrate is 90 °.

According to one embodiment of the present disclosure, a first adhesive layer is disposed on a bottom surface of each first chip, and the first chip is bonded to another first chip or the substrate below the first chip through the first adhesive layer.

According to another aspect of the present disclosure, a semiconductor package structure is provided. Wherein the semiconductor package structure includes the stack structure proposed by the present disclosure and described in the above embodiments.

According to yet another aspect of the present disclosure, a process for preparing a stacked structure is provided. The method comprises the following steps:

providing a substrate, and forming a plurality of through grooves on the substrate;

stacking a plurality of first chips on the substrate, wherein the routing areas of the first chips are positioned on the bottom surfaces of the first chips, one part of any two of the first chips is overlapped, and the other part of the first chips is staggered in a rotating manner;

at least one second chip is superposed on the first chip, and a routing area of the second chip is positioned on the top surface of the second chip;

the wire bonding area of the second chip is electrically connected with the top surface of the substrate by a lead, and then the wire bonding area of the first chip is electrically connected with the bottom surface of the substrate by a lead penetrating through the through groove; and

and arranging a protective sheet on the second chip through the adhesive layer, wherein the lead part electrically connected with the second chip penetrates through the adhesive layer.

According to the technical scheme, the advantages and positive effects of the stacked structure, the semiconductor packaging structure and the preparation process of the stacked structure provided by the disclosure are as follows:

the stacking structure provided by the disclosure stacks a plurality of chips on a substrate, the chips are partially overlapped, and the other part is rotated and staggered, so that the orthographic projection of a routing area of any chip on the substrate is not overlapped with the orthographic projection of other chips on the substrate. The plurality of chips are electrically connected to the substrate through leads, respectively. Through the design, the manufacturing of the multilayer chip stack packaging body can be realized. The method can meet the stacking requirement of the multilayer chips, meanwhile, the routing positions of the chips are reasonably distributed, the routing process and the substrate manufacturing difficulty are reduced, the routing yield is improved, and the substrate cost is reduced.

Drawings

Various objects, features and advantages of the present disclosure will become more apparent from the following detailed description of preferred embodiments thereof, when considered in conjunction with the accompanying drawings. The drawings are merely exemplary illustrations of the disclosure and are not necessarily drawn to scale. In the drawings, like reference characters designate the same or similar parts throughout the different views. Wherein:

FIG. 1 is a schematic diagram of a stacked configuration of a semiconductor package structure according to an exemplary embodiment;

fig. 2 is a top view of a plurality of first chip stacks of the semiconductor package structure shown in fig. 1;

fig. 3 is a plan view in which a plurality of first chips and a plurality of second chips of the semiconductor package structure shown in fig. 1 are stacked.

The reference numerals are explained below:

100. a substrate;

110. a through groove;

200. a first chip;

210. a wire bonding area;

211. a first lead;

220. a first glue layer;

300. a second chip;

310. a wire bonding area;

311. a second lead;

320. a second adhesive layer;

400. a protective sheet;

410. a third adhesive layer;

500. a packaging layer;

c 1-c7. chips;

b 1-b7. line-marking area.

Detailed Description

Exemplary embodiments that embody features and advantages of the present disclosure are described in detail below in the specification. It is to be understood that the disclosure is capable of various modifications in various embodiments without departing from the scope of the disclosure, and that the description and drawings are to be regarded as illustrative in nature, and not as restrictive.

In the following description of various exemplary embodiments of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration various exemplary structures, systems, and steps in which aspects of the disclosure may be practiced. It is to be understood that other specific arrangements of parts, structures, example devices, systems, and steps may be utilized, and structural and functional modifications may be made without departing from the scope of the present disclosure. Moreover, although the terms "over," "between," "within," and the like may be used in this specification to describe various example features and elements of the disclosure, these terms are used herein for convenience only, e.g., in accordance with the orientation of the examples described in the figures. Nothing in this specification should be construed as requiring a specific three dimensional orientation of structures in order to fall within the scope of this disclosure.

Stacked Structure embodiments

Referring to fig. 1, a schematic diagram of a stacked structure of a semiconductor package structure proposed by the present disclosure is representatively shown, and in particular, a schematic diagram of a stacked structure provided in a semiconductor package structure proposed by the present disclosure is shown. In the exemplary embodiment, the stack structure proposed in the present disclosure is illustrated by taking as an example a stack package structure applied to a multi-layer memory chip. Those skilled in the art will readily appreciate that various modifications, additions, substitutions, deletions, or other changes may be made to the specific embodiments described below in order to apply the relevant designs of the present disclosure to other types of multi-layer chip stacks or other stacked structures, and such changes are within the scope of the principles of the stacked structures set forth in the present disclosure.

As shown in fig. 1, in the present embodiment, the stacked structure proposed by the present disclosure mainly includes a substrate 100 and a plurality of first chips 200. Referring to fig. 2-3 in combination, a top view of a plurality of first chip stacks of a stacked configuration capable of embodying the principles of the present disclosure is representatively illustrated in fig. 2. Representatively illustrated in fig. 3 is a top view of a stack of a plurality of first chips and a plurality of second chips capable of embodying the principles of the present disclosure. The structure, connection mode and functional relationship of the main components of the stacked structure proposed by the present disclosure will be described in detail below with reference to the above drawings.

As shown in fig. 1 and 2, in the present embodiment, a plurality of first chips 200 are stacked on a substrate 100. Specifically, the wire bonding area 210 of each first chip 200 is disposed on the respective bottom surface, i.e., the surface facing the substrate 100. A part of any two of the first chips 200 is overlapped and another part is rotated and staggered, so that the orthographic projection of the wire bonding area 210 of any first chip 200 on the substrate 100 is not overlapped with the orthographic projection of any other first chip 200 on the substrate 100, that is, the orthographic projection of the wire bonding area 210 of each first chip 200 on the substrate 100 is not overlapped. The substrate 100 is formed with a plurality of through grooves 110, and the through grooves 110 are respectively formed below the wire bonding regions 210 of the first chips 200. The plurality of first chips 200 are electrically connected to the substrate 100 through first leads 211, respectively, one end of each first lead 211 is electrically connected to the wire bonding region 210 of the first chip 200, and the other end of each first lead 211 passes through the corresponding through groove 110 and is electrically connected to the bottom surface of the substrate 100. Through the design, the manufacturing of the multilayer chip stack packaging body can be realized. The method can meet the stacking requirement of the multilayer chips, meanwhile, the routing positions of the chips are reasonably distributed, the routing process and the manufacturing difficulty of the substrate 100 are reduced, the routing yield is improved, and the cost of the substrate 100 is reduced.

In the present embodiment, the fact that the wire bonding regions 210 of the first chips 200 do not overlap means that the orthographic projection of the wire bonding region 210 of each first chip 200 on the substrate 100 does not have a portion overlapping the orthographic projection of the wire bonding regions 210 of other first chips 200 on the substrate 100, that is, the orthographic projection of the wire bonding region 210 of each first chip 200 on the substrate 100 is completely staggered. In other embodiments, the relationship that the bonding areas 210 of the first chips 200 do not overlap may also be understood as that the orthographic projections of the bonding areas 210 of the first chips 200 on the substrate 100 do not completely overlap, and the staggered positional relationship of the bonding areas 210 may be flexibly adjusted according to the number, the rotation angle and the actual structure of the first chips 200, which is not limited to the present embodiment.

Note that, in the present embodiment, the stacked structure including four first chips 200 is taken as an example for description, and for convenience of understanding with reference to the drawings, the four first chips 200 are defined as a chip c1, a chip c2, a chip c3 and a chip c4 in sequence from the substrate 100 upward. Accordingly, bonding areas 210 of chip c1, chip c2, chip c3 and chip c4 are bonding area b1, bonding area b2, bonding area b3 and bonding area b4, respectively, and it can be seen that bonding area b1 is located on the bottom surface of chip c1, bonding area b2 is located on the bottom surface of chip c2, bonding area b3 is located on the bottom surface of chip c3, and bonding area b4 is located on the bottom surface of chip c 4.

Further, as shown in fig. 1 and fig. 2, in the present embodiment, the plurality of first chips 200 may preferably be sequentially staggered in rotation from bottom to top in a clockwise (as shown in fig. 2) or counterclockwise direction. In other embodiments, the first chips 200 may be rotated in an irregular order, and the present embodiment is not limited thereto.

Further, as shown in fig. 2, based on the design that the plurality of first chips 200 are sequentially rotated and shifted from bottom to top in the clockwise or counterclockwise direction, in the present embodiment, the angles of the shift between the orthographic projections of every two adjacent first chips 200 on the substrate 100 may preferably be all equal, and for the four first chips 200 in the present embodiment, the angles of the shift between the first chips 200 are all 90 °. That is, in the orthographic projection on the substrate 100, the angle between the center line of the chip c1 and the center line of the chip c2 is 90 °, the angle between the center line of the chip c2 and the center line of the chip c3 is 90 °, the angle between the center line of the chip c3 and the center line of the chip c4 is 90 °, and the angle between the center line of the chip c4 and the center line of the chip c1 is 90 °. In other embodiments, when the number of the first chips 200 is other, for example, three, the included angle between the adjacent first chips 200 may be 120 °, that is, the number of the first chips 200 is n, and the included angle between the adjacent two first chips 200 may preferably be (360/n) °. In other embodiments, no matter the plurality of first chips 200 are staggered in a clockwise, counterclockwise or irregular manner, the included angle between any two first chips 200 can be flexibly adjusted, and is not limited to this embodiment.

Further, as shown in fig. 1, in the present embodiment, the bottom surface of each first chip 200 may preferably be provided with a first glue layer 220. Specifically, the first chip 200 is bonded to another first chip 200 or the substrate 100 therebelow through the first glue layer 220, that is, the chip c1 is bonded to the substrate 100 through the first glue layer 220, the chip c2 is bonded to the chip c1 through the first glue layer 220, the chip c3 is bonded to the chip c2 through the first glue layer 220, and the chip c4 is bonded to the chip c3 through the first glue layer 220. In addition, the first adhesive layer 220 on the bottom surface of each first chip 200 is respectively provided with an opening for exposing the wire bonding region 210 of each first chip 200 in the opening.

As shown in fig. 1 and 3, in the present embodiment, the stacked structure further includes at least one second chip 300. Specifically, the second chip 300 is stacked on the uppermost first chip 200 (i.e., chip c 4). The wire bonding area 310 of each second chip 300 is disposed on the top surface of the second chip 300. When there are a plurality of second chips 300, a part of any two of the plurality of second chips 300 is overlapped and another part is staggered, so that the orthographic projection of the wire bonding area 310 of any second chip 300 on the substrate 100 is not overlapped with the orthographic projection of any other second chip 300 on the substrate 100, that is, the orthographic projection of the wire bonding area 310 of each second chip 300 on the substrate 100 is not overlapped. The plurality of second chips 300 are electrically connected to the substrate 100 through second leads 311, respectively, one end of each second lead 311 is electrically connected to the wire bonding area 310 of the second chip 300, and the other end is electrically connected to the top surface of the substrate 100. Through the design, besides the plurality of first chips 200 are arranged in a staggered manner, the present disclosure can further arrange at least one second chip 300, and utilize the routing area 310 of the second chip 300 to be located on the top surface thereof to avoid the problem of interference with the routing area 210 of the first chip 200 or inconvenience in routing, so as to further adapt to the stacking requirement of the multilayer chips.

Note that, in the present embodiment, the stacked structure including three second chips 300 is taken as an example for description, and for convenience of understanding with reference to the drawings, the three second chips 300 are defined as a chip c5, a chip c6, and a chip c7 in this order from the substrate 100. Accordingly, bonding areas 310 of chip c5, chip c6, and chip c7 are bonding area b5, bonding area b6, and bonding area b7, respectively, and it can be seen that bonding area b5 is located on the top surface of chip c5, bonding area b6 is located on the top surface of chip c6, and bonding area b7 is located on the top surface of chip c7.

Note that, in the present embodiment, the design including three second chips 300 is adopted, and the plurality of second chips 300 are designed such that a part of any two of the second chips 300 overlaps and another part is shifted. In other embodiments, the plurality of second chips 300 may be arranged in a staggered manner similar to the selective arrangement of the plurality of first chips 200. In the case where there is only one second chip 300, the second chip 300 is provided at any position on the uppermost first chip 200 (i.e., chip c4), and the present embodiment is not limited thereto.

Further, as shown in fig. 1 and fig. 3, based on the design that the stacked structure includes a plurality of second chips 300, in the present embodiment, the plurality of second chips 300 are sequentially and partially staggered from bottom to top along the arrangement direction, and orthographic projections of the wire bonding regions 310 of the plurality of second chips 300 on the substrate 100 are distributed at intervals along the arrangement direction.

Further, as shown in fig. 1 and 3, the arrangement direction of the plurality of second chips 300 may preferably be the extending direction of the center line of one of the first chips 200 (for example, chip c1 and chip c4) in the present embodiment, based on the design that the plurality of second chips 300 are partially staggered from bottom to top in the arrangement direction.

Further, as shown in fig. 1 and 3, each of the second chips 300 has a first end and a second end in the arrangement direction in the present embodiment based on a design in which the plurality of second chips 300 are partially staggered in order from bottom to top in the arrangement direction. Each second chip 300 reveals each first end by being arranged in a partially staggered manner in sequence. The wire bonding regions 310 of the uppermost second chip 300 are located on the top surface of the second end thereof, and the wire bonding regions 310 of the remaining second chips 300 are located on the top surfaces of the respective first ends thereof.

Further, as shown in fig. 1, based on the design that the stacked structure includes the second chips 300, in the present embodiment, the bottom surface of each second chip 300 may preferably be provided with the second glue layer 320. Specifically, the second chip 300 is bonded to another second chip 300 or the first chip 200 under the second chip 300 through the second glue layer 320, that is, the chip c5 is bonded to the chip c4 through the second glue layer 320, the chip c6 is bonded to the chip c5 through the second glue layer 320, and the chip c7 is bonded to the chip c6 through the second glue layer 320.

Further, based on the design that the second adhesive layer 320 is disposed on the bottom surface of the second chip 300, in the present embodiment, the material of the second adhesive layer 320 may preferably be an ultra thin Film adhesive (DAF).

Further, as shown in fig. 1, in the present embodiment, the stacked structure may also preferably include a protective sheet 400 and a third adhesive layer 410. Specifically, the third adhesive layer 410 is disposed on the bottom surface of the protective sheet 400, and the protective sheet 400 is bonded to the uppermost second chip 300 (i.e., the chip c7) by the third adhesive layer 410. One end of the second lead 311 electrically connected to the wire bonding region b7 of the chip c7 is electrically connected to the wire bonding region b7, and the other end is electrically connected to the top surface of the substrate 100 through the third adhesive layer 410.

It should be noted herein that the stack structures shown in the drawings and described in this specification are only a few examples of the many types of stack structures that can employ the principles of the present disclosure. It should be clearly understood that the principles of this disclosure are in no way limited to any details of the stacked configuration or any components of the stacked configuration shown in the drawings or described in this specification.

Semiconductor package structure implementation mode

Referring to fig. 1, a schematic view of a stacked structure of a semiconductor package structure proposed by the present disclosure is representatively illustrated. In this exemplary embodiment, the semiconductor package structure proposed in the present disclosure is illustrated by taking as an example a stack package structure applied to a multilayer memory chip. Those skilled in the art will readily appreciate that many modifications, additions, substitutions, deletions, or other changes may be made to the specific embodiments described below in order to apply the relevant designs of the present disclosure to other types of multi-layer chip stacks or other semiconductor package structures, and such changes are within the principles of the semiconductor package structure as set forth in the present disclosure.

As shown in fig. 1, in the present embodiment, the semiconductor package structure proposed by the present disclosure mainly includes the stack structure and the package layer 500 proposed by the present disclosure and described in detail in the above embodiments.

As shown in fig. 1, based on a design in which the first chip 200, the second chip 300, and the protective sheet 400 are simultaneously provided in a stacked structure, in the present embodiment, the encapsulation layer 500 is encapsulated outside the substrate 100, the plurality of first chips 200, the plurality of second chips 300, and the protective sheet 400. In another embodiment, when the stacked structure is provided with only the first and

second chips

200 and 300, the encapsulation layer 500 is encapsulated outside the substrate 100, each of the first and

second chips

200 and 300. In still another embodiment, when the stacked structure is provided with only the first chip 200 and the protective sheet 400, the encapsulation layer 500 is encapsulated outside the substrate 100, each of the first chip 200 and the protective sheet 400. In still another embodiment, when the stacked structure is provided with only the first chips 200, the encapsulation layer 500 is encapsulated outside the substrate 100 and each of the first chips 200.

It should be noted herein that the semiconductor package structures shown in the drawings and described in this specification are only a few examples of the many types of semiconductor package structures that can employ the principles of the present disclosure. It should be clearly understood that the principles of this disclosure are in no way limited to any of the details of the semiconductor package structure or any of the components of the semiconductor package structure shown in the drawings or described in this specification.

Embodiment of the fabrication Process for stacked structures

Based on the above exemplary description of the stacked structure and the semiconductor package structure proposed by the present disclosure, an exemplary embodiment of a process for manufacturing the stacked structure proposed by the present disclosure will be described below. In this exemplary embodiment, the process for manufacturing a stacked structure proposed in the present disclosure is illustrated by taking as an example a stacked package structure applied to manufacture a multi-layer memory chip. Those skilled in the art will readily appreciate that various modifications, additions, substitutions, deletions, or other changes may be made to the specific embodiments described below in order to apply the relevant designs of the present disclosure to other types of multi-layer chip stacks or other semiconductor package structures, and such changes are within the scope of the principles of the fabrication process for the stacked structures set forth in the present disclosure.

In this embodiment, the process for manufacturing a stacked structure provided by the present disclosure mainly includes the following steps:

the method comprises the following steps that a plurality of first chips are stacked on a substrate, wire bonding areas of the first chips are located on the bottom surfaces of the first chips, one part of any two of the first chips is overlapped, and the other part of the first chips is staggered in a rotating mode;

the wire bonding area of the second chip is electrically connected with the top surface of the substrate by using a lead, and then the wire bonding area of the first chip is electrically connected with the bottom surface of the substrate by using the lead to penetrate through the through groove; and

and a protective sheet is arranged on the second chip through the adhesive layer, and the lead part electrically connected with the second chip penetrates through the adhesive layer.

The above-described respective main steps of the process for manufacturing the stacked structure proposed by the present disclosure will be specifically described below.

In the present embodiment, in the step of forming the plurality of through-grooves in the substrate, the positions where the plurality of through-grooves are formed may preferably be designed to correspond to the bonding regions of the plurality of first chips, respectively. The correspondence relationship in the above description may mean that the through groove is located directly below the wire bonding area of the corresponding first chip.

In this embodiment, for the step of stacking the plurality of first chips, the plurality of first chips are designed such that orthographic projections of the wire bonding regions of the first chips on the substrate do not coincide with each other.

Further, the plurality of first chips may be preferably stacked on the substrate in a sequentially rotationally staggered manner in a clockwise or counterclockwise direction from bottom to top. On the basis, the staggered included angles between the orthographic projections of every two adjacent first chips on the substrate can be designed into equal arrangement forms.

In the present embodiment, for the step of stacking the second chips, it may be preferable to stack a plurality of second chips on the first chip. On the basis, the plurality of second chips can be designed to be that the orthographic projections of the routing areas of the second chips on the substrate are not overlapped.

Further, the plurality of second chips may preferably adopt an arrangement form of sequentially and partially staggered from bottom to top along the arrangement direction, so that orthographic projections of the routing areas of the plurality of second chips on the substrate are distributed at intervals along the arrangement direction.

In the present embodiment, the step of providing the protective sheet is to provide the protective sheet on the second chip by using the adhesive layer provided between the protective sheet and the uppermost second chip. Before the protective sheet is disposed, the wire bonding area of the second chip may be preferably electrically connected to the substrate through a lead, and the formation of the adhesive layer further includes a process of wrapping the lead, that is, a portion of the lead penetrates through the adhesive layer.

In summary, in the stacked structure provided in the present disclosure, the wire bonding area of each chip is disposed on the bottom surface of the chip, and an orthogonal projection of the wire bonding area of any chip on the substrate does not overlap an orthogonal projection of any other chip on the substrate. The plurality of chips are electrically connected to the substrate through leads respectively, one ends of the leads are electrically connected to the wiring area of the chips, and the other ends of the leads penetrate through the through grooves in the corresponding positions and are electrically connected to the bottom surface of the substrate. Through the design, the manufacturing of the multilayer chip stack packaging body can be realized. The method can meet the stacking requirement of the multilayer chips, meanwhile, the routing positions of the chips are reasonably distributed, the routing process and the substrate manufacturing difficulty are reduced, the routing yield is improved, and the substrate cost is reduced.

Exemplary embodiments of a stacked structure and a semiconductor package structure having the same proposed by the present disclosure are described and/or illustrated in detail above. Embodiments of the disclosure are not limited to the specific embodiments described herein, but rather, components and/or steps of each embodiment may be utilized independently and separately from other components and/or steps described herein. Each component and/or step of one embodiment can also be used in combination with other components and/or steps of other embodiments. When introducing elements/components/etc. described and/or illustrated herein, the articles "a," "an," and "the" are intended to mean that there are one or more of the elements/components/etc. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc. Furthermore, the terms "first" and "second" and the like in the claims and the description are used merely as labels, and are not numerical limitations of their objects.

While the present disclosure has been described in terms of various specific embodiments, those skilled in the art will recognize that the disclosed implementations can be practiced with modification within the spirit and scope of the claims.

Claims

1. A stacked structure, comprising:

a substrate; and

a plurality of first chips stacked on the substrate;

wherein a part of any two of the first chips is overlapped, the other part is staggered in rotation, and the first chips are electrically connected to the substrate through first leads.

2. The stack structure of claim 1, wherein the wire bonding area of each of the first chips is disposed on a bottom surface of the first chip, an orthographic projection of the wire bonding area of any one of the first chips on the substrate is not overlapped with an orthographic projection of each other of the first chips on the substrate, and the first leads are electrically connected between the wire bonding area of the first chip and the substrate.

3. The stacked structure of claim 2, wherein the substrate has a plurality of through slots, the through slots are correspondingly formed below the wire bonding regions of the first chips, one end of the first lead is electrically connected to the wire bonding region of the first chip, and the other end of the first lead passes through the through slot corresponding to the position of the first lead and is electrically connected to the bottom surface of the substrate.

4. The stacked structure of claim 2, further comprising at least one second chip stacked on the uppermost first chip, wherein the wire bonding area of each second chip is disposed on the top surface of the second chip, an orthogonal projection of the wire bonding area of any second chip on the substrate is not overlapped with an orthogonal projection of each other second chip on the substrate, and the second chips are electrically connected to the top surface of the substrate through second leads.

5. The stack structure of claim 4, wherein the stack structure comprises a plurality of the second chips, the plurality of the second chips are sequentially and partially staggered from bottom to top along an arrangement direction, and orthographic projections of the wire bonding areas of the plurality of the second chips on the substrate are distributed at intervals along the arrangement direction.

6. The stack structure of claim 5, wherein each of the second chips has a first end and a second end in the arrangement direction, and the second chips expose the first ends by being partially staggered in sequence; the wire bonding area of the second chip at the top is positioned on the top surface of the second end, and the wire bonding areas of the other second chips are positioned on the top surfaces of the respective first ends.

7. The stack structure of claim 4, wherein a bottom surface of each of the second chips is provided with a second adhesive layer, and the second chip is adhered to another second chip below the second chip or the uppermost first chip through the second adhesive layer.

8. The stack structure according to claim 4, further comprising a protective sheet and a third adhesive layer, wherein the third adhesive layer is disposed on a bottom surface of the protective sheet, the protective sheet is bonded to the uppermost second chip by the third adhesive layer, the second lead electrically connected to the wire bonding region of the second chip has one end electrically connected to the wire bonding region, and the other end electrically connected to the top surface of the substrate via the third adhesive layer; wherein the packaging layer is packaged outside the substrate, the plurality of first chips, the at least one second chip and the protective sheet.

9. The stack structure according to claim 1, wherein the first chips are sequentially rotationally staggered from bottom to top in a clockwise or counterclockwise direction.

10. The stack structure according to claim 9, wherein the included angles of the orthographic projections of each two adjacent first chips on the substrate are equal.

11. The stack structure of claim 9, wherein the chip package structure comprises four first chips, and an included angle between orthographic projections of each two adjacent first chips on the substrate is 90 °.

12. The stack structure of claim 1, wherein a bottom surface of each of the first chips is provided with a first adhesive layer, and the first chip is bonded to another first chip or the substrate thereunder through the first adhesive layer.

13. A semiconductor package structure, comprising the stacked structure of any one of claims 1 to 12.

14. A process for preparing a stacked structure, comprising the steps of: