CN110912548B - Dynamic latch, data operation unit, chip, computing board and computing device - Google Patents
Dynamic latch, data operation unit, chip, computing board and computing deviceInfo
- Publication number
- CN110912548B CN110912548B CN201911124320.7A CN201911124320A CN110912548B CN 110912548 B CN110912548 B CN 110912548B CN 201911124320 A CN201911124320 A CN 201911124320A CN 110912548 B CN110912548 B CN 110912548B
- Authority
- CN
- China
- Prior art keywords
- data
- node
- terminal
- unit
- output terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
本发明提供一种动态锁存器、数据运算单元、芯片、算力板及计算设备。动态锁存器，包括一输入端，一同相输出端，一反相输出端，一时钟信号端，一数据传输单元，一第一数据保持单元，一第二数据保持单元，所述数据传输单元、所述第一数据保持单元以及所述第二数据保持单元依次串接在所述输入端和所述同相输出端之间，所述数据传输单元与所述第一数据保持单元之间具有一第一节点，所述第一数据保持单元与所述第二数据保持单元之间具有一第二节点，所述反相输出端电性连接至所述第二节点；其中，还包括一漏电补偿单元，所述漏电补偿单元电性连接在所述同相输出端以及所述第一节点之间。可以有效补偿节点的动态漏电流，提高数据的安全性和正确率。
The present invention provides a dynamic latch, a data operation unit, a chip, a computing board, and a computing device. The dynamic latch includes an input terminal, an in-phase output terminal, an inverting output terminal, a clock signal terminal, a data transmission unit, a first data retention unit, and a second data retention unit. The data transmission unit, the first data retention unit, and the second data retention unit are sequentially connected in series between the input terminal and the in-phase output terminal. A first node is provided between the data transmission unit and the first data retention unit, a second node is provided between the first data retention unit and the second data retention unit, and the inverting output terminal is electrically connected to the second node. The dynamic latch further includes a leakage compensation unit, which is electrically connected between the in-phase output terminal and the first node. This can effectively compensate for the dynamic leakage current of the node, thereby improving the security and accuracy of the data.
Description
Technical Field
The present invention relates to a memory device controlled by a clock, and more particularly, to a dynamic latch, a data operation unit, a chip, a power board, and a computing device applied in a large-scale data operation device.
Background
Dynamic latches are very widely used and can be used as registers for digital signals. Fig. 1 is a circuit configuration diagram of a conventional dynamic latch. As shown in fig. 1, the dynamic latch 100 includes a transmission gate 101, an inverter 102, and an inverter 103 connected in series between an input D and an in-phase output Q. A node S0 is formed between the transmission gate 101 and the inverter 102, a node S1 is formed between the inverter 102 and the inverter 103, and data temporarily exists at the node S0 and/or the node S1 through parasitic capacitances of the inverter 102 and transistors in the inverter 103. The dynamic latch outputs data in phase with the data of the input terminal D through the in-phase output terminal Q, and the inverse output terminal QN outputs data inverse to the data of the input terminal D, but the node S0 and the node S1 easily generate dynamic leakage, resulting in the loss of the temporarily stored data.
Therefore, how to effectively reduce the dynamic leakage of the dynamic latch is a problem to be solved.
Disclosure of Invention
In order to solve the problems, the invention provides a dynamic latch which can effectively compensate the dynamic leakage current of a node and improve the safety and the accuracy of data.
In order to achieve the above object, the present invention provides a dynamic latch, which comprises an input end for inputting a data, an in-phase output end for outputting the data in-phase, an opposite-phase output end for outputting the data in-phase, a clock signal end for providing a clock signal, a data transmission unit for transmitting the data under the control of the clock signal, a first data holding unit for holding the data transmitted by the data transmission unit in opposite phase, a second data holding unit for holding the data transmitted by the data transmission unit in-phase, wherein the data transmission unit, the first data holding unit and the second data holding unit are sequentially connected in series between the input end and the in-phase output end, a first node is arranged between the data transmission unit and the first data holding unit, a second node is arranged between the first data holding unit and the second data holding unit, and the opposite-phase output end is electrically connected to the second node, and the dynamic latch further comprises a leakage compensation unit electrically connected between the input end and the first node and the second node.
The dynamic latch described above, wherein the leakage compensation unit has a first end, a second end, and a control end, the first end is electrically connected to the in-phase output end, and the second end is electrically connected to the first node.
The dynamic latch described above, wherein the leakage compensation unit includes a PMOS transistor and an NMOS transistor, and the PMOS transistor and the NMOS transistor are connected in series between the non-inverting output terminal and the first node.
In the dynamic latch, the PMOS transistor has a source terminal, a drain terminal, and a gate terminal, the NMOS transistor has a source terminal, a drain terminal, and a gate terminal, the source terminal of the PMOS transistor is electrically connected to the in-phase output terminal, the drain terminal is electrically connected to the drain terminal of the NMOS transistor, and the source terminal of the NMOS transistor is electrically connected to the first node.
The dynamic latch described above, wherein the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to the first node.
The dynamic latch described above, wherein the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to the second node.
In the dynamic latch, the gate terminals of the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to a ground.
In the dynamic latch, the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to a power supply.
In the above dynamic latch, the leakage compensation unit includes an NMOS transistor having a source terminal, a drain terminal, and a gate terminal, wherein the drain terminal of the NMOS transistor is electrically connected to the in-phase output terminal, the source terminal is electrically connected to the first node, and the gate terminal is electrically connected to a ground.
The dynamic latch described above, wherein the leakage compensation unit includes a PMOS transistor having a source terminal, a drain terminal, and a gate terminal, the source terminal of the PMOS transistor is electrically connected to the in-phase output terminal, the drain terminal is electrically connected to the first node, and the gate terminal is electrically connected to a power supply.
The dynamic latch described above, wherein the clock signal includes a first clock signal and a second clock signal, and the first clock signal is inverted from the second clock signal.
The dynamic latch described above, wherein the data transmission unit is a transmission gate.
The dynamic latch described above, wherein the first data holding unit and/or the second data holding unit is an inverter.
The dynamic latch of the invention can feed back the leakage current to the node from the output end, compensate the dynamic leakage current of the node, improve the stability of data storage, and further enhance the safety and the accuracy of the data.
In order to better achieve the above purpose, the invention also provides a data operation unit, which comprises a control circuit, an operation circuit and a plurality of dynamic latches which are connected in series and/or in parallel, wherein the plurality of dynamic latches are any one of the dynamic latches.
In order to better achieve the above object, the present invention further provides a chip, which includes at least one data operation unit as described above.
To better achieve the above object, the present invention also provides a computing pad for a computing device, comprising at least one chip as described above.
In order to better achieve the above object, the present invention further provides a computing device, including a power panel, a control panel, a connection board, a heat radiator, and a plurality of power boards, where the control panel is connected to the power boards through the connection board, the heat radiator is disposed around the power boards, and the power panel is used to provide power to the connection board, the control panel, the heat radiator, and the power boards are the power boards.
The invention will now be described in more detail with reference to the drawings and specific examples, which are not intended to limit the invention thereto.
Drawings
FIG. 1 is a schematic diagram of a circuit configuration of a conventional dynamic latch;
FIG. 2 is a schematic diagram of a dynamic latch according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a dynamic latch according to another embodiment of the present invention;
FIG. 4 is a schematic diagram of a dynamic latch according to another embodiment of the present invention;
FIG. 5 is a schematic diagram of a dynamic latch according to another embodiment of the present invention;
FIG. 6 is a schematic diagram of a dynamic latch according to an exemplary embodiment of the present invention;
FIG. 7 is a schematic diagram of a dynamic latch according to another embodiment of the present invention;
FIG. 8 is a schematic diagram of a data operation unit according to the present invention;
FIG. 9 is a schematic diagram of a chip according to the present invention;
FIG. 10 is a schematic view of the structure of the force plate of the present invention;
FIG. 11 is a schematic diagram of a computing device of the present invention.
Wherein, the reference numerals:
100. 200 dynamic latch
101 Transmission gate
102. 103 Inverter
201 Data transmission unit
202 First data holding unit
203 A second data holding unit
204 Leakage compensation unit
201P, 204P: PMOS transistor
201N, 204N: NMOS transistors
800 Data arithmetic unit
801 Control circuit
802 Arithmetic circuit
900 Chip
901 Control unit
1000 Force calculating plate
1100 Computing device
1101 Connecting plate
1102 Control panel
1103 Radiator
1104 Power panel
D input terminal
Q in-phase output terminal
QN reverse phase output terminal
CKP, CKN clock signal
S0, S1 node
Detailed Description
The structural and operational principles of the present invention are described in detail below with reference to the accompanying drawings:
Certain terms are used throughout the description and following claims to refer to particular components. It will be appreciated by those of ordinary skill in the art that manufacturers may refer to a component by different names. The present specification and the following claims do not take the form of an element or a component, but rather take the form of an element or a component, a function, or a combination thereof.
In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. The term "coupled," as used herein, includes any direct or indirect electrical connection. Indirect electrical connection means include connection via other devices.
Embodiment one:
FIG. 2 is a schematic diagram of a dynamic latch according to an embodiment of the present invention. As shown in fig. 2, the dynamic latch 200 includes an input terminal D, an in-phase output terminal Q, an anti-phase output terminal QN, a clock signal terminal CKN, a clock signal terminal CKP, a data transmission unit 201, a first data holding unit 202, a second data holding unit 203, and a leakage compensation unit 204. The data transmission unit 201, the first data holding unit 202, and the second data holding unit 203 are sequentially connected in series between the input terminal D and the in-phase output terminal Q, a first node S0 is formed between the data transmission unit 201 and the first data holding unit 202, a second node S1 is formed between the first data holding unit 202 and the second data holding unit 203, and the inverted output terminal QN is electrically connected to the second node S1. The leakage compensation unit 204 is electrically connected between the first node S0 and the in-phase output terminal Q. The input terminal D is used for inputting data, the in-phase output terminal Q is used for in-phase outputting data, the anti-phase output terminal QN is used for anti-phase outputting data, the clock signal terminal CKN and the clock signal terminal CKP are used for providing clock signals CKN and CKP, and the clock signals CKN and CKP are anti-phase clock signals.
Specifically, as shown in fig. 2, the data transmission unit 201 of the dynamic latch 200 has a transmission gate structure, and the data transmission unit 201 includes a PMOS transistor 201P and an NMOS transistor 201N connected in parallel. The source terminal of the PMOS transistor 201P is connected in parallel with the source terminal of the NMOS transistor 201N and is electrically connected to the input terminal D of the dynamic latch 200, and the drain terminal of the PMOS transistor 201P is connected in parallel with the drain terminal of the NMOS transistor 201N and is electrically connected to the first node S0. The gate terminal of the NMOS transistor 201N is electrically connected to the clock signal CKN, and the gate terminal of the PMOS transistor 201P is electrically connected to the clock signal CKP. When CKP is low, CKN is high, and both PMOS transistor 201P and NMOS transistor 201N are turned on, the data at the input D of the dynamic latch 200 is transferred to the first node S0 through the data transfer unit 201. When CKP is high, CKN is low, both PMOS transistor 201P and NMOS transistor 201N are turned off, and the data at input D of dynamic latch 200 cannot be transferred to first node S0 through data transfer unit 201. In the present embodiment, the data transmission unit 201 is exemplified by a transmission gate structure, and of course, other forms of data transmission units are also possible, as long as the switching function can be realized under the control of the clock signal, and the invention is not limited thereto.
With continued reference to fig. 2, the first data holding unit 202 and the second data holding unit 203 of the dynamic latch 200 are both in an inverter structure, and the first data holding unit 202 may temporarily store the data transmitted from the data transmission unit 201, that is, the data at the first node S0, by using its parasitic capacitance, and may invert the data at the first node S0 and transmit the inverted data to the second data holding unit 203. The second data holding unit 203 also uses its parasitic capacitance to temporarily store the data transmitted from the first data holding unit 202, i.e. the data at the second node S1, and can invert the data at the second node S1 and transmit the data to the in-phase output terminal Q. It can be seen that the data at the first node S0 and the second node S1 are inverted data, and the inverted output terminal QN is electrically connected to the second node S1, so that the data output by the in-phase output terminal Q and the inverted output terminal QN are also inverted data.
It can be seen that the data transmission unit 201 is controlled by the clock signal to transmit data to the first data holding unit 202 and the second data holding unit 203, and the data at the input terminal D of the dynamic latch 200 is inverted by the first data holding unit 202 and the second data holding unit 203, so that the data at the in-phase output terminal Q is in phase with the data at the input terminal D, and the data at the inverted output terminal QN is in phase with the data at the input terminal D. Meanwhile, the first data holding unit 202 and the second data holding unit 203 may also function to improve data driving force.
As shown in fig. 2, the dynamic latch 200 further includes a leakage compensation unit 204. In the present embodiment, the leakage compensation unit 204 includes a PMOS transistor 204P and an NMOS transistor 204N, and the PMOS transistor 204P and the NMOS transistor 204N are connected in series between the non-inverting output terminal Q and the first node S0. The source terminal of the PMOS transistor 204P is electrically connected to the in-phase output terminal Q, the drain terminal of the PMOS transistor 204P is electrically connected to the drain terminal of the NMOS transistor 204N, the source terminal of the NMOS transistor 204N is electrically connected to the first node S0, and the gate terminals of the PMOS transistor 204P and the NMOS transistor 204N are connected in parallel and electrically connected to the first node S0.
Since the gate terminals of the PMOS transistor 204P and the NMOS transistor 204N are electrically connected to the first node S0, the PMOS transistor 204P and the NMOS transistor 204N are not turned on at the same time, and only one of them is turned on and the other is turned off under the same-level signal driving. For example, when the potential at the first node S0 is high, the PMOS transistor 204P is in an off state and the NMOS transistor 204N is in an on state, and when the potential at the first node S0 is low, the PMOS transistor 204P is in an on state and the NMOS transistor 204N is in an off state. At this time, the leakage compensation unit 204 may feed back the leakage current of the in-phase output terminal Q to the first node S0, compensate the dynamic leakage current at the first node S0, improve the stability of data storage at the first node S0, and enhance the correctness and safety of data.
Embodiment two:
FIG. 3 is a schematic diagram of a dynamic latch according to another embodiment of the present invention. As shown in fig. 3, the difference from the embodiment shown in fig. 2 is that, in the present embodiment, the gate terminals of the PMOS transistor 204P and the NMOS transistor 204N are connected in parallel and electrically connected to the second node S1 in the leakage compensation unit 204.
Since the gate terminals of the PMOS transistor 204P and the NMOS transistor 204N are electrically connected to the second node S1, the PMOS transistor 204P and the NMOS transistor 204N are not turned on at the same time, and only one of them is turned on and the other is turned off under the same-level signal driving. For example, when the potential at the second node S1 is high, the PMOS transistor 204P is in an off state and the NMOS transistor 204N is in an on state, and when the potential at the second node S1 is low, the PMOS transistor 204P is in an on state and the NMOS transistor 204N is in an off state. At this time, the leakage compensation unit 204 may feed back the leakage current of the in-phase output terminal Q to the first node S0, compensate the dynamic leakage current at the first node S0, improve the stability of data storage at the first node S0, and enhance the correctness and safety of data.
Modification examples:
FIG. 4 is a schematic diagram illustrating a circuit structure of a leakage compensation dynamic register according to another embodiment of the present invention. As shown in fig. 2 and 4, the difference from the embodiment shown in fig. 2 is that, in the leakage compensation unit 204 of the present embodiment, the gate terminals of the PMOS transistor 204P and the NMOS transistor 204N are connected in parallel and electrically connected to the ground VSS.
Since the gate terminals of the PMOS transistor 203P and the NMOS transistor 203N are electrically connected to the ground VSS, the PMOS transistor 203P is in an on state and the NMOS transistor 203N is in an off state under the signal driving of the ground VSS low level. At this time, the leakage compensation unit 204 may feed back the leakage current of the in-phase output terminal Q to the first node S0, compensate the dynamic leakage current at the first node S0, improve the stability of data storage at the first node S0, and enhance the correctness and safety of data.
FIG. 5 is a schematic diagram of a circuit structure of a dynamic register with leakage compensation according to another embodiment of the present invention. As shown in fig. 2 and fig. 5, the difference from the embodiment shown in fig. 2 is that, in the leakage compensation unit 204 of the present embodiment, the gate terminals of the PMOS transistor 204P and the NMOS transistor 204N are connected in parallel and electrically connected to the power supply VDD.
Since the gate terminals of the PMOS transistor 203P and the NMOS transistor 203N are electrically connected to the power supply VDD, the PMOS transistor 203P is turned off and the NMOS transistor 203N is turned on under the high-level signal driving of the power supply VDD. At this time, the leakage compensation unit 204 may feed back the leakage current of the in-phase output terminal Q to the first node S0, compensate the dynamic leakage current at the first node S0, improve the stability of data storage at the first node S0, and enhance the correctness and safety of data.
FIG. 6 is a schematic diagram of a leakage compensation dynamic register according to an embodiment of the present invention. As shown in fig. 6, the leakage compensation unit 204 of the leakage compensation dynamic register 200 includes an NMOS transistor 204N, wherein a source terminal of the NMOS transistor 204N is electrically connected to the first node S0, a drain terminal of the NMOS transistor 204N is electrically connected to the in-phase output terminal Q, and a gate terminal of the NMOS transistor 204N is electrically connected to the ground VSS.
Since the gate terminal of the NMOS transistor 204N is electrically connected to the ground VSS, the NMOS transistor 204N is turned off under the driving of the ground VSS low signal. At this time, the leakage compensation unit 204 may feed back the leakage current of the in-phase output terminal Q to the first node S0, compensate the dynamic leakage current at the first node S0, improve the stability of data storage at the first node S0, and enhance the correctness and safety of data.
Fig. 7 is a schematic circuit diagram of a leakage compensation dynamic register according to another embodiment of the present invention. As shown in fig. 7, the leakage compensation unit 204 of the leakage compensation dynamic register 200 includes a PMOS transistor 204P, wherein a source terminal of the PMOS transistor 204P is electrically connected to the in-phase output terminal, a drain terminal of the PMOS transistor 204P is electrically connected to the first node S0, and a gate terminal of the PMOS transistor 204P is electrically connected to the power supply VDD.
Since the gate terminal of the PMOS transistor 204P is electrically connected to the power supply VDD, the PMOS transistor 204P is turned off under the driving of the high level signal of the power supply VDD. At this time, the leakage compensation unit 204 may feed back the leakage current of the in-phase output terminal Q to the first node S0, compensate the dynamic leakage current at the first node S0, improve the stability of data storage at the first node S0, and enhance the correctness and safety of data.
The invention also provides a data operation unit, and fig. 8 is a schematic structural diagram of the data operation unit. As shown in fig. 8, the data operation unit 800 includes a control circuit 801, an operation circuit 802, and a plurality of dynamic latches 200. The control circuit 801 refreshes data in the dynamic latch 200, reads data from the dynamic latch 200, and the arithmetic circuit 802 operates on the read data and outputs the result of the operation by the control circuit 801.
The invention also provides a chip, and fig. 9 is a schematic structural diagram of the chip. As shown in fig. 9, the chip 900 includes a control unit 901, and one or more data operation units 900. The control unit 901 inputs data to the data operation unit 900 and processes the data output from the data operation unit 900.
The invention also provides a force calculating plate, and fig. 10 is a schematic structural diagram of the force calculating plate. As shown in fig. 10, each computing pad 1000 includes one or more chips 900 thereon for performing large-scale operations on the operational data issued by the computing device.
The present invention also provides a computing device that can be used for any mass operation. FIG. 11 is a schematic diagram of a computing device of the present invention. As shown in fig. 11, each computing device 1100 includes a connection board 1101, a control board 1102, a heat sink 1103, a power supply board 1104, and one or more computing boards 1000. The control board 1102 is connected to the power board 1000 through a connection board 1101, and a heat sink 1103 is provided around the power board 1000. The power panel 1104 is used to supply power to the connection board 1101, the control board 1102, the heat sink 1103, and the power board 1000.
It should be noted that, in the description of the present invention, the terms "transverse", "longitudinal", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the apparatus or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
In other words, the present invention is capable of other various embodiments, and various changes and modifications can be made by one skilled in the art without departing from the spirit and the spirit of the invention, and these changes and modifications are intended to fall within the scope of the appended claims.
Claims (7)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910948324 | 2019-09-30 | ||
| CN2019109483240 | 2019-09-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110912548A CN110912548A (en) | 2020-03-24 |
| CN110912548B true CN110912548B (en) | 2025-08-08 |
Family
ID=69817647
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911124320.7A Active CN110912548B (en) | 2019-09-30 | 2019-11-15 | Dynamic latch, data operation unit, chip, computing board and computing device |
| CN201921985791.2U Active CN211209690U (en) | 2019-09-30 | 2019-11-15 | Dynamic latch, data operation unit, chip, force calculation board and computing equipment |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921985791.2U Active CN211209690U (en) | 2019-09-30 | 2019-11-15 | Dynamic latch, data operation unit, chip, force calculation board and computing equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN110912548B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110706731B (en) * | 2019-09-30 | 2025-07-08 | 杭州嘉楠耘智信息科技有限公司 | Electric leakage compensation dynamic register, data operation unit, chip, power calculation board and computing equipment |
| CN110912548B (en) * | 2019-09-30 | 2025-08-08 | 杭州嘉楠耘智信息科技有限公司 | Dynamic latch, data operation unit, chip, computing board and computing device |
| CN112929012A (en) * | 2021-01-21 | 2021-06-08 | 北京源启先进微电子有限公司 | Leakage compensation latch, data operation unit and chip |
| CN115911026A (en) * | 2021-09-30 | 2023-04-04 | 北京比特大陆科技有限公司 | Dynamic latches, semiconductor chips, hashboards and computing equipment |
| CN115913209A (en) * | 2021-09-30 | 2023-04-04 | 北京比特大陆科技有限公司 | Dynamic latch, semiconductor chip, computing board and computing equipment |
| CN115118253A (en) * | 2022-07-14 | 2022-09-27 | 上海嘉楠捷思信息技术有限公司 | Dynamic latch, dynamic D trigger, data operation unit, chip, force calculation board and computing equipment |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN208608969U (en) * | 2018-06-25 | 2019-03-15 | 北京嘉楠捷思信息技术有限公司 | Low-leakage-current dynamic D trigger, and data operation unit, chip, force calculation board and computing equipment using same |
| CN211209690U (en) * | 2019-09-30 | 2020-08-07 | 杭州嘉楠耘智信息科技有限公司 | Dynamic latch, data operation unit, chip, force calculation board and computing equipment |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1047196B1 (en) * | 1999-04-21 | 2005-07-20 | STMicroelectronics S.r.l. | Method and circuit for minimizing glitches in phase locked loops |
| JP4551731B2 (en) * | 2004-10-15 | 2010-09-29 | 株式会社東芝 | Semiconductor integrated circuit |
| FR2888423B1 (en) * | 2005-07-05 | 2008-04-11 | Iroc Technologies Sa | CURED STORAGE CELL |
-
2019
- 2019-11-15 CN CN201911124320.7A patent/CN110912548B/en active Active
- 2019-11-15 CN CN201921985791.2U patent/CN211209690U/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN208608969U (en) * | 2018-06-25 | 2019-03-15 | 北京嘉楠捷思信息技术有限公司 | Low-leakage-current dynamic D trigger, and data operation unit, chip, force calculation board and computing equipment using same |
| CN211209690U (en) * | 2019-09-30 | 2020-08-07 | 杭州嘉楠耘智信息科技有限公司 | Dynamic latch, data operation unit, chip, force calculation board and computing equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN211209690U (en) | 2020-08-07 |
| CN110912548A (en) | 2020-03-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110912548B (en) | Dynamic latch, data operation unit, chip, computing board and computing device | |
| CN110706731B (en) | Electric leakage compensation dynamic register, data operation unit, chip, power calculation board and computing equipment | |
| CN110677141B (en) | Dynamic D trigger, data operation unit, chip, power board and computing device | |
| CN110311655B (en) | No-hold dynamic D flip-flop, data processing unit, chip, computing board and computing device | |
| CN110635783B (en) | Positive feedback dynamic D trigger | |
| CN110675909A (en) | Dynamic register, data operation unit, chip, force calculation board and computing equipment | |
| US20250150068A1 (en) | Dynamic latch, dynamic d flip-flop, data operation unit, chip, hash board, and computing device | |
| CN110633104B (en) | Multi-path parallel register | |
| US20250158600A1 (en) | Dynamic d flip-flop, data operation unit, chip, hash board and computing device | |
| TWI807305B (en) | Inverting output dynamic D flip-flop | |
| US11251781B2 (en) | Dynamic D flip-flop, data operation unit, chip, hash board and computing device | |
| CN110708041A (en) | Electric leakage feedback dynamic D trigger, data operation unit, chip, force calculation board and computing equipment | |
| US11386254B2 (en) | Semiconductor circuit and semiconductor circuit layout system | |
| CN110635786B (en) | Dynamic D flip-flop | |
| CN210899130U (en) | Dynamic latch, data operation unit, chip, force calculation board and computing equipment | |
| CN218183324U (en) | Dynamic D trigger, data operation unit, chip, force calculation board and computing equipment | |
| CN218071463U (en) | Dynamic latch, dynamic D trigger, data operation unit, chip, force calculation board and computing equipment | |
| CN218071462U (en) | Dynamic latch, data operation unit, chip, force calculation board and computing equipment | |
| CN115589218A (en) | Dynamic latch, data operation unit, chip, computing power board and computing equipment | |
| CN115001456A (en) | Dynamic latch, data operation unit, chip, computing force board and computing equipment | |
| CN218071464U (en) | Dynamic latch, data operation unit, chip, force calculation board and computing equipment | |
| CN210899105U (en) | Electric leakage feedback dynamic D trigger, data operation unit, chip, force calculation board and computing equipment | |
| CN110690887A (en) | Dynamic latch, data operation unit, chip, computing power board and computing equipment | |
| CN210865633U (en) | Electric leakage compensation dynamic register, data arithmetic unit, chip, force calculation board and computing equipment | |
| CN210867618U (en) | Dynamic D trigger, data operation unit, chip, force calculation board and computing equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |