CN110828399A - Chip device, circuit board and digital currency mining machine - Google Patents

Abstract

The present disclosure proposes a chip device, comprising: at least one chip, the chip includes a die, and a backside of the die is exposed; and a metal dielectric layer formed and covered on the exposed backside of the die; Wherein, the back surface of the metal dielectric layer facing away from the crystal grains is uneven. Through the above structure, the heat dissipation area of the chip device is increased, and the heat dissipation efficiency of the chip device is improved. In addition, a circuit board including the chip device and a digital currency mining machine are also disclosed.

Description

Chip devices, circuit boards and digital currency mining machines

technical field

The invention relates to the technical field of chip heat dissipation, in particular to a chip device, a circuit board including the chip device, and a digital currency mining machine, wherein the chip device has an efficient heat dissipation structure.

Background technique

With the continuous development of chip technology, the running speed of the chip is getting faster and the processing capacity is getting stronger and stronger. At the same time, the heat generated by the chip usually increases during operation, which requires the use of a more efficient heat dissipation structure for the chip. Dissipate heat to prevent the chip from being overheated during operation, which may cause the chip to slow down or even damage the chip.

In the prior art, for example, Chinese Patent Application Publication CN106445037A discloses a partially immersed liquid-cooled server cooling system, in which the main board, chips and heat dissipation fins are immersed in cooling liquid in a closed cavity, and the cooling liquid is pumped in a pump It circulates under the drive of the radiator, so as to dissipate heat from the motherboard, chips and heat sinks. However, the heat sink is attached to the surface of the chip through thermal grease, which may cause the thermal grease to be affected by the cooling liquid during use and its viscosity will decrease over time, so that the heat dissipation component is not in good contact with the chip or falls off. This will lead to the risk of unstable heat dissipation, and the thermal grease will also be detrimental to the transfer of heat from the chip to the heat dissipation component to a certain extent, which will affect the heat dissipation of the chip.

SUMMARY OF THE INVENTION

In view of the above problems, a chip device, a circuit board and a digital currency mining machine that overcome the above problems or at least partially solve the above problems are proposed, which are used to solve the defects in the prior art that the heat dissipation of the chips is not stable and efficient.

According to a first aspect of the present invention, a chip device is provided, comprising:

at least one chip, the chip including a die, the backside of the die being exposed; and

a metal dielectric layer formed and overlying the exposed backside of the die;

Wherein, the back surface of the metal dielectric layer facing away from the crystal grains is uneven.

The above-mentioned backside of the die refers to the surface of the die that faces away from the circuit board when the chip is mounted on the circuit board, that is, the surface opposite to the surface of the die that faces the circuit board. The package form of the exposed die on the back can be in the form of ExposedDie, but it is not limited to this package form, for example, it can also be Bare Die, FCBGA (Flip Chip Ball GridArray, flip chip ball grid array packaging structure), FCCSP (Flip Chip Chip Array) Scale Package, flip-chip chip-scale package), WLCSP (Wafer Level Chip Scale Package, wafer-level chip-scale package), InFO (Integrated Fan-Out, integrated fan-out wafer-level package structure)/FOWLP (Fan Out Wafer) LevelPackage, Fan-Out Wafer Level Package)/FOPLP (Fan-Out Panel Level Package, Fan-Out Panel Level Package), LGA (Land Grid Array, Grid Array Package) and other packaging forms, as long as the back of the die The technical solution of the present invention can be used in the technical solution of the present invention if it is exposed without being encapsulated, even when the backside and the surrounding of the die are not encapsulated. The situation where the backside of the die is exposed is also applicable to the technical solution of the present invention, and the present invention is not limited thereto.

The backside of the metal medium layer may be provided with any form and number of uneven shapes, for example, may include protrusions of various shapes, as long as the contact area with the cooling liquid can be increased and the space allows.

Preferably, in the chip device, the metal dielectric layer is formed on the backside of the die through a backside metallization process.

Preferably, in the chip device, the backside of the metal dielectric layer includes at least one protrusion selected from the group consisting of: cone-shaped protrusions, frusto-conical protrusions, hill-shaped protrusions, hemispherical protrusions, and wave-shaped protrusions. Protrusions, columnar protrusions and/or lamellar protrusions.

Preferably, in the chip device, the at least one protrusion has the same or different heights.

Preferably, in the chip device, the chip further includes an encapsulation part for encapsulating the die, the encapsulation part exposes the back of the die, and the metal dielectric layer covers the die and at least a part of the encapsulation part around the die.

Preferably, in the chip device, the metal dielectric layer is in direct contact with the die.

Preferably, in the chip device, the metal dielectric layer is a titanium layer, or the metal dielectric layer includes a titanium layer and an aluminum layer formed on the titanium layer.

According to another aspect of the present invention, there is provided a circuit board, comprising: a PCB board (printed circuit board); the above-mentioned chip device fixed on the PCB board; The cavity of the chip device and the insulating cooling liquid, the sealed casing accommodates the chip device in the cavity, is sealed and fixed relative to the PCB board, and is provided with a fluid inlet for the insulating cooling liquid to flow into and Fluid outlet for insulating coolant.

Preferably, the circuit board further includes: a heat sink disposed on the sealed casing, the heat sink is attached to the sealed casing through thermal interface material or welding.

Preferably, the circuit board further comprises: a fluid pipeline, which is connected with the fluid inlet and the fluid outlet of the sealed housing to form a fluid circulation path; an insulating cooling liquid for connecting the fluid pipeline and the fluid outlet. The circuit board circulates in the sealed casing; the liquid pump is connected in the fluid pipeline and is used for pumping the insulating cooling liquid to dissipate the heat of the chip device; the heat absorption device is connected with the fluid pipeline for absorbing heat from the insulating coolant.

Preferably, in the circuit board, the sealed case is made of metal.

According to another aspect of the present invention, there is provided a digital currency mining machine, comprising an operation board, and the operation board includes the above-mentioned circuit board.

In the present invention, since the backside of the die is exposed, and the backside of the metal dielectric layer formed on the backside of the die is uneven, the heat dissipation area of the metal dielectric layer is increased, which is beneficial for the heat generated by the chip to go out. disseminate. In addition, since the metal dielectric layer is formed on the backside of the die through the backside metallization process (BSM), the metal dielectric layer and the backside of the die are closely combined, which is conducive to efficient heat transfer between each other, and the metal dielectric layer is It is firmly combined with the back of the die, and the metal dielectric layer will not be loosened from the back of the die during use, thereby increasing the reliability of heat dissipation and the service life of the product.

In addition, the larger area of the heat dissipation layer compared to the exposed area of the backside of the die allows for more rapid and efficient absorption of heat from the backside of the die, which in turn can be efficiently dissipated for transfer to the coolant.

Moreover, the metal dielectric layer of the chip device of the present invention constitutes a high-efficiency heat dissipation structure, and cooperates with the cooling liquid to achieve high-efficiency heat dissipation, so the heat dissipation structure has less processing technology, simple processing process and low processing cost.

The above description is only an overview of the technical solution of the present invention, so that the technical means of the present invention can be more clearly understood, so that it can be implemented according to the content of the description. In order to make the above and other objects, features and advantages of the present invention more clearly understood, specific embodiments of the present invention are described below.

Description of drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are for the purpose of illustrating preferred embodiments only and are not to be considered limiting of the invention. Also, the same components are denoted by the same reference numerals throughout the drawings. In the attached image:

1 is a schematic diagram of a chip device according to an embodiment of the present invention, wherein a cross-sectional view of the chip device is shown;

Fig. 1a is a schematic perspective view of a metal dielectric layer of the chip device shown in Fig. 1;

Fig. 1b is a schematic diagram showing that the backside of the metal dielectric layer is provided with cylindrical protrusions according to an embodiment of the present invention;

Fig. 1c is a schematic diagram showing that the backside of the metal dielectric layer is provided with wave-shaped protrusions according to an embodiment of the present invention;

2 is a schematic diagram of a chip device according to another embodiment of the present invention, wherein a cross-sectional view of the chip device is shown;

3 is a schematic diagram of a chip device according to another embodiment of the present invention, wherein a cross-sectional view of the chip device is shown;

4 is a schematic diagram of a chip device according to another embodiment of the present invention, wherein a cross-sectional view of the chip device is shown;

5 is a schematic diagram of a circuit board having the chip device of the present invention according to another embodiment of the present invention, wherein a cross-sectional view of the circuit board is shown;

6 is a schematic diagram of a digital currency mining machine having the circuit board of the present invention according to another embodiment of the present invention.

Detailed ways

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be more thoroughly understood, and will fully convey the scope of the present disclosure to those skilled in the art.

FIG. 1 is a schematic diagram of a chip device 100 according to an embodiment of the present invention, particularly a cross-sectional view taken along a plane perpendicular to the backside of the chip device 100 .

As shown in FIG. 1 , the chip device 100 includes:

at least one chip 101, the chip 101 including a die 102, the backside 102a of the die 102 being exposed; and

A metal dielectric layer 104 is formed and covers the exposed backside 102a of the die 102, the backside 104a of the metal dielectric layer 104 facing away from the die 102 being uneven. The metal dielectric layer 104 may be formed on the backside 102a of the die 102 through a backside metallization (BSM).

Here, the metal dielectric layer 104 absorbs the heat generated by the die 102 from the chip 101 , and the metal dielectric layer 104 preferably completely covers all exposed parts of the backside 102 a of the die 102 , more preferably, the metal dielectric layer 104 is in contact with the backside The area of the parallel planes 102a is larger than that of the backside 102a, so that the heat generated by the chip 101 can be quickly transferred to the metal dielectric layer 104 through its backside 102a, and then dissipated from the metal dielectric layer 104 to the surrounding thermally conductive medium (for example, as will be described below). coolant).

The uneven shape of the back surface 104a of the metal dielectric layer 104 can be realized in various forms, as long as the contact area of the back surface 104a and the cooling liquid can be increased and space is allowed. For example, as shown in FIG. 1 and FIG. 1a, the backside 104a of the metal dielectric layer 104 may be provided with a plurality of protrusions, such as a plurality of square pillars 106, and the square pillars may be regularly arranged to form 4×8 as shown in FIG. 1a Arrays can also be arranged irregularly, which is not limited in this article. The square pillars 106 may be the same size and height as each other, as shown in FIG. 1a, or different from each other, which is not limited herein.

Here, the form of the protrusions provided on the back surface 104a of the metal dielectric layer 104 is not limited. For example, FIG. 1b shows a schematic diagram of the protrusions being cylindrical protrusions 106a, and FIG. 1c shows the protrusions It is a schematic diagram of the wavy protrusion 106b. Of course, the protrusions provided on the back surface 104a of the metal dielectric layer 104 may also be conical protrusions, frusto-conical protrusions, hill-shaped protrusions, hemispherical protrusions, and/or sheet-shaped protrusions such as fin-shaped protrusions Bumps, wavy flaky bumps, etc. These different kinds of protrusions can also be used in combination.

The chip 101 may also include an encapsulation portion 103 encapsulating the die 102 , and the encapsulation portion 103 exposes the backside 102 a of the die 102 . As shown in FIG. 1 , the chip 101 is packaged in an Exposed die package, and the package portion 103 may be a molding compound. In this case, the formed metal dielectric layer 104 covers the entire backside 102 a of the die 102 and at least a part of the encapsulation portion 103 around the die 102 , and of course can also cover the entire backside 102 a of the die 102 and all around the die 102 Package part 103 .

The die 102 is electrically connected to, for example, an external circuit board through conductive traces 110 and pins 109 provided in the substrate 108 .

In FIG. 1, it is shown that the back 102a of the chip 102 is completely exposed, but of course, a part of the back 102a may also be exposed.

Here, the chip 101 may also have no encapsulation part 103 , that is, the die 102 is completely exposed, not only the back 102a of the chip 102 is exposed, but also the surrounding areas are also exposed.

In this context, the backside 102a of the die 102 refers to the surface of the die 102 facing away from the circuit board when the chip 101 is mounted on the circuit board, ie, opposite to the surface of the die 102 facing the circuit board surface. In this paper, the package form of the back exposed die 102 may be in the form of Exposed Die, but is not limited to this package form, for example, it may also be Bare Die/FCBGA (as shown in FIG. 2 ), WLCSP (as shown in FIG. 3 ) ), InFO/FOWLP/FOPLP (as shown in Figure 4) and other packaging forms. That is to say, the technical solution of the present invention is not only applicable to the Exposed Die package form, but also to other package forms that expose the back of the die, such as Bare Die/FCBGA, WLCSP, InFO/FOWLP/FOPLP, FCCSP, LGA, etc. The package form, as long as the back of the die of the chip is exposed and unpackaged, or the die may not be packaged, or the package may be processed after the die is packaged to expose the back of the die. Not limited to this.

Since the backside 102a of the die 102 is bare, and there is no non-metallic medium that affects heat transfer between the backside 102a of the die and the metal dielectric layer 104, the heat generated by the chip 101 can be quickly and efficiently transferred to the metal dielectric layer 104 , thereby further dissipating heat through the coolant around the chip device. In addition, compared with the exposed area of the backside of the die 102a, the heat dissipation area of the metal dielectric from the backside 104 is larger, so that the heat can be absorbed from the backside of the die 102a more quickly and effectively (also equivalent to increasing the heat dissipation area of the backside of the die). , and then efficiently dissipate the absorbed heat and transfer it to the coolant.

However, in the prior art, the metal dielectric layer 104 with uneven back surface similar to that in the present invention is not provided. Moreover, in the prior art, the heat sink is often attached to the chip through a non-metallic thermal interface material. In this case, due to the poor thermal conductivity of the non-metallic thermal interface material, and the die of the chip is not exposed, the The heat transfer efficiency from the die to the heat sink is low, which affects the heat dissipation effect. However, in the above technical solution of the present invention, the metal dielectric layer is directly formed on the backside of the exposed die, and the backside of the metal dielectric layer is made into an uneven shape, thereby increasing the heat dissipation area, thereby avoiding the prior art. of these problems.

In the embodiment of the present invention, the metal dielectric layer 104 may be formed on the backside 102a of the die 102 through a backside metallization process. For example, in the backside metallization process, the backside 102a of the die may be formed One or more layers of metal are evaporated or sputtered to form the metal dielectric layer 104 .

In the embodiment of the present invention, the metal dielectric layer 104 is in direct contact with the die 102 , so that the heat generated by the die 102 can be smoothly transferred to the metal dielectric layer 104 by utilizing the good thermal conductivity of metal. Moreover, the metal dielectric layer 104 can be firmly fixed on the backside 102 a of the die 102 due to the tight and firm bonding between the metals. In the prior art, a non-metallic thermal interface material layer often exists between the die or chip and the heat sink, and the heat transfer performance of the non-metallic thermal interface material layer is often poor, which affects the generation of heat transfer efficiency to the heat sink.

In embodiments of the present invention, the uneven backside of the metal dielectric layer 104 may be formed by various processes, such as by electroplating, sputtering, anodizing, physical vapor deposition (PVD), chemical vapor product (CVD), photolithography, It is formed by etching, laser and other processes or artistic processes, and the specific process is not limited here. The formation process of the metal dielectric layer 104 may also include, but is not limited to, electroplating, sputtering, anodizing, physical vapor deposition (PVD), chemical vapor product (CVD), photolithography, etching, laser and other processes, and may also be the above processes The combination.

The height of the protrusion on the backside of the metal dielectric layer 104 can be set according to the crystal back metallization process and actual needs, for example, it can have a height in the range of 1 mm to 100 mm, but the present invention is not limited to this, the metal dielectric layer The protrusions on the back of 104 may also have other suitable heights.

In the embodiment of the present invention, the metal dielectric layer 104 may be, but is not limited to, formed of the following materials: titanium Ti, nickel Ni, tin Sn, silver Ag, gold Au, vanadium V, aluminum Al, palladium Pd, copper Cu, One of zinc Zn, chromium Cr, molybdenum Mo, tungsten W, and zirconium Zr, or a combination of the above-listed materials (ie, alloys), for example, the metal dielectric layer 104 may be a titanium layer. The metal dielectric layer 104 may also be a multi-layer structure, such as a structure of two or more layers of different metal materials, such as a titanium alloy layer. Among them, titanium has the characteristics of light weight, high strength and high temperature resistance, and the combination of titanium and other metals is firm. Therefore, in the embodiment of the present invention, the connection with the back of the die 102 is good. At the same time, due to the stable chemical and physical properties of titanium, so It is not easy to diffuse into adjacent metal layers, and can play a good diffusion barrier function

The technical solutions of the present invention can also be applied to chips in other packaging forms, as long as the backside of the die of the chip is unpackaged and exposed. Further description will be given below with reference to Figures 2-4.

FIG. 2 is a schematic diagram of a chip device according to another embodiment of the present invention, wherein a cross-sectional view of the chip device 200 is shown.

The difference between the chip device 200 in the embodiment shown in FIG. 2 and the chip device 100 in the embodiment shown in FIG. 1 lies in the chip 201 and the packaging part 203 . Since the chip 201 in the chip device 200 adopts the BareDie/FCBGA package form, the height of the package portion 203 (ie, the underfill) gradually decreases from the peripheral edge of the die 102 outward to form a slope 203a, while FIG. 1 The height of the encapsulation part 103 in the embodiment shown in the figure remains unchanged, so that the encapsulation part 103 is attached to the metal dielectric layer 104 .

Although it is shown in FIG. 2 that the metal dielectric layer 104 is limited to the backside of the die 102 , the metal dielectric layer 104 may further extend to the slope 203 a to further expand the heat dissipation surface of the metal dielectric layer 104 .

It should be noted that the components in the embodiment shown in FIG. 2 that have the same numbers as the components in the embodiment shown in FIG. 1 are the same as those shown in FIG. 1 , and thus will not be repeated here.

FIG. 3 is a schematic diagram of a chip device according to another embodiment of the present invention, wherein a cross-sectional view of the chip device 300 is shown.

The difference between the chip device 300 in the embodiment shown in FIG. 3 and the chip device 100 in the embodiment shown in FIG. 1 lies in the chip 301 . Since the chip 301 in the chip device 300 adopts the WLCSP packaging form, there is no packaging part around the die 102, and not only the back 102a is exposed, but also the surrounding sides are exposed. In addition, since the WLCSP package is used, the WLCSP RDL (Redistribution Layer) 310 is correspondingly used in the substrate 108 instead of the ordinary conductive traces 110 .

It is shown in FIG. 3 that the metal dielectric layer 104 completely covers the range of the backside 102 a of the die 102 .

It should be noted that the components in the embodiment shown in FIG. 3 that have the same numbers as the components in the embodiment shown in FIG. 1 are the same as those shown in FIG. 1 , and thus are not repeated here.

FIG. 4 is a schematic diagram of a chip device according to another embodiment of the present invention, wherein a cross-sectional view of the chip device 400 is shown.

The difference between the chip device 400 in the embodiment shown in FIG. 4 and the chip device 100 in the embodiment shown in FIG. 1 lies in the chip 401 . Since the chip 401 in the chip device 400 is packaged in InFO/FOWLP/FOPLP form, the backside 102a of the die 102 is also exposed, and the periphery of the die 102a is packaged with, for example, molding compound. In addition, since the InFO/FOWLP/FOPLP package is used, the RDL (Redistribution Layer) 410 is correspondingly used in the substrate 108 instead of the ordinary conductive trace 110 .

It should be noted that the components in the embodiment shown in FIG. 4 that have the same numbers as the components in the embodiment shown in FIG. 1 are the same as those shown in FIG. 1 , and thus are not repeated here.

It should be pointed out that in the chip devices 200 , 300 and 400 of the embodiments shown in FIGS. 2 , 3 and 4 , the metal dielectric layer 104 shown in FIG. 1 b or FIG. 1 c may also be used to replace the 3. The metal dielectric layer 104 shown in FIG. 4 , or any other metal dielectric layer with protrusions of any other shape on the backside is used to replace the metal dielectric layer 104 shown in FIG. 2 , FIG. 3 , and FIG. 4 .

According to another embodiment of the present invention, as shown in FIG. 5 , a circuit board 500 is provided, including: a PCB board 501 ; any chip device 100 , 200 , 300 or 400; and a sealed casing 504, which has a cavity for accommodating the chip device and the insulating cooling liquid 505 inside, the sealed casing 504 accommodates the chip device in the cavity, and is sealed and fixed relative to the PCB board 501, And a fluid inlet 502 for the insulating cooling liquid to flow into the cavity and a fluid outlet 503 for the insulating cooling liquid to flow out of the cavity are provided.

The circuit board 500 also includes a fluid line 506, a fluid pump 508 arranged along the fluid line 506, and a heat absorption device 507, wherein the fluid pump 508 is used to drive the cooling liquid in the fluid line 506 in one direction, while absorbing heat The device 507 is used to absorb heat from the cooling liquid, so that the cooled cooling liquid is reused to absorb heat from the chip device.

In this embodiment, the chip device 100 , 200 , 300 or 400 is immersed in the insulating cooling liquid 505 , and the insulating cooling liquid 505 circulates in a closed loop formed by the cavity and the fluid pipeline 506 , and the metal dielectric layer 104 of the chip device It is in sufficient contact with the insulating cooling liquid 505, so that the heat on the metal dielectric layer 104 is transferred to the cooling liquid 505, and the heat dissipation of the chip device is realized.

In a circuit board, the hermetic housing 504 may be made of metal or other materials that can seal against the coolant and facilitate heat dissipation.

In order to further enhance the heat dissipation capability, the circuit board may further include: a heat sink (not shown) disposed on the sealed casing 504, and the heat sink can be attached to the sealed casing 504 through thermal interface material or welding superior.

According to another embodiment of the present invention, as shown in FIG. 6 , a digital currency mining machine 600 is provided, which includes at least one computing board 601 , and the computing board 601 includes the circuit board 500 described in the above embodiment.

Numerous specific details are described in this specification. It will be understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order to avoid obscuring an understanding of this description.

Those skilled in the art will appreciate that the modules in the apparatus in the embodiment can be adaptively changed and arranged in one or more apparatuses different from the embodiment. Several modules in the embodiments may be combined into one module or unit or component, and further they may be divided into multiple modules or units or components. All features disclosed in this specification (including accompanying claims, abstract and drawings) and any method so disclosed may be employed in any combination, unless at least some of such features and/or procedures or modules are mutually exclusive. All processes or units of equipment are combined. Each feature disclosed in this specification (including accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

It should be noted that the above-described embodiments illustrate rather than limit the invention, and that alternative embodiments may be devised by those skilled in the art without departing from the scope of the appended claims.

Claims (12)

1. A chip device, comprising: at least one chip, the chip including a die, the backside of the die is exposed; and a metal dielectric layer formed and covering the exposed backside of the die; Wherein, the back surface of the metal dielectric layer facing away from the crystal grains is uneven. 2. The chip device of claim 1, wherein the metal dielectric layer is formed on the backside of the die by a backside metallization process. 3. The chip device according to claim 1, wherein the backside of the metal dielectric layer comprises at least one protrusion selected from the group consisting of: conical protrusions, frustoconical protrusions, hill-shaped protrusions, hemispherical protrusions Raised, wavy, cylindrical and/or flaky. 4. The chip device of claim 3, wherein the at least one bump has the same or different heights. 5. The chip device according to any one of claims 1 to 4, the chip further comprising an encapsulation part for encapsulating the die, the encapsulation part exposing the back of the die, and the metal dielectric layer covering the die and at least a part of the encapsulation part around the die. 6. The chip device according to any one of claims 1 to 4, wherein the metal dielectric layer is a titanium layer or a titanium alloy layer. 7. The chip device according to any one of claims 1 to 4, wherein the metal dielectric layer comprises a titanium layer and an aluminum layer formed on the titanium layer. 8. A circuit board, characterized in that, comprising: PCB board; The chip device according to any one of claims 1 to 7, which is fixed on the PCB; and a sealed case with a cavity for accommodating the chip device and insulating cooling liquid inside, the sealed case accommodates the chip device in the cavity, and is sealed and fixed relative to the PCB board, and A fluid inlet for the inflow of the insulating cooling liquid and a fluid outlet for the outflow of the insulating cooling liquid are provided. 9 . The circuit board according to claim 8 , further comprising: a heat sink disposed on the sealing case, the heat sink being attached to the sealing case by thermal interface material or welding. 10 . 10. The circuit board of claim 8 or 9, further comprising: a fluid line connected with the fluid inlet and the fluid outlet of the sealed housing to form a fluid circulation path; an insulating cooling fluid for circulating the fluid line and the sealed housing of the circuit board; a liquid pump connected in the fluid pipeline for pumping the insulating cooling liquid to dissipate heat from the chip device, A heat sink connected in the fluid line for absorbing heat from the insulating cooling liquid. 11. The circuit board of claim 8 or 9, wherein the sealed housing is made of metal. 12. A digital currency mining machine comprising a computing board comprising the circuit board according to any one of claims 8 to 11.

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