CN110709992A - Semiconductor structure, chip and electronic device of image sensor - Google Patents

Abstract

The present application discloses a semiconductor structure of an image sensor and related chips and electronic devices. The semiconductor structure (600) of the image sensor includes a semiconductor substrate (101) and a plurality of pixels disposed on the semiconductor substrate, wherein the plurality of pixels includes: a first pixel (P5') and a second pixel (P5') P6), each comprising: at least one photosensor (502, 504, 506, 508) for converting light into electric charge; and an output circuit for generating pixel output according to the electric charge, the output circuit including a source follower transistor (108) and a row selection transistor (110); wherein, from a top view, the row selection transistor of the first pixel and the row selection transistor of the second pixel are located in the row selection transistor of the first pixel between a source follower transistor and the source follower transistor of the second pixel. The present application improves the output circuit of the semiconductor structure of an image sensor to reduce area and improve performance.

Description

Semiconductor structure, chip and electronic device of image sensor

technical field

The present application relates to a semiconductor structure of an image sensor and related chips and electronic devices, and more particularly to a semiconductor structure of an image sensor and related chips and electronic devices that can increase the channel length of a source follower transistor.

Background technique

CMOS image sensors have been mass-produced and applied. With the improvement of image quality requirements, the number of pixels is also increasing. In order to increase the number of pixels in a limited area as much as possible, the size of a unit pixel should be reduced as much as possible. That is to say, the size of the photosensitive sensor and the output circuit in the unit pixel should be reduced accordingly.

However, reducing the size of the output circuit often affects the performance of the output circuit. Therefore, how to balance the area and the performance has become an important work item in this field.

SUMMARY OF THE INVENTION

One of the objectives of the present application is to disclose a semiconductor structure of an image sensor and related chips and electronic devices to solve the above problems.

An embodiment of the present application discloses a semiconductor structure of an image sensor. The semiconductor structure of the image sensor includes a semiconductor substrate and a plurality of pixels disposed on the semiconductor substrate, wherein the plurality of pixels includes: a first A pixel and a second pixel, the first pixel and the second pixel each include: at least one photosensitive sensor for converting light into electric charge; and an output circuit for generating pixel output according to the electric charge, the output The circuit includes a source follower transistor and a row selection transistor, a source/drain of the source follower transistor is electrically connected to a source/drain of the row selection transistor; wherein, from a top view, all the first pixels are Both the row select transistor and the row select transistor of the second pixel are located between the source follower transistor of the first pixel and the source follower transistor of the second pixel.

An embodiment of the present application discloses a chip including the above-mentioned semiconductor structure of an image sensor.

An embodiment of the present application discloses an electronic device including the above-mentioned semiconductor structure of an image sensor.

The embodiments of the present application improve the configuration of the output circuit of the semiconductor structure of the image sensor, which can reduce the area and improve the performance of the output circuit.

Description of drawings

FIG. 1 is a top view of a first embodiment of a semiconductor structure of an image sensor of the present application.

FIG. 2 is a top view of a second embodiment of the semiconductor structure of the image sensor of the present application.

FIG. 3 is a circuit diagram of a pixel of the image sensor of FIGS. 1 and 2 .

FIG. 4 is a Bayer pixel group based on the semiconductor structure of the image sensor of FIG. 1 .

FIG. 5 is a Bayer pixel group based on the semiconductor structure of the image sensor of FIG. 2 .

FIG. 6 is a top view of a third embodiment of the semiconductor structure of the image sensor of the present application.

FIG. 7 is a top view of a fourth embodiment of the semiconductor structure of the image sensor of the present application.

FIG. 8 is a circuit diagram of a pixel of the image sensor of FIGS. 6 and 7 .

FIG. 9 is a Bayer pixel group based on the semiconductor structure of the image sensor of FIG. 6 .

FIG. 10 is a Bayer pixel group based on the semiconductor structure of the image sensor of FIG. 7 .

FIG. 11 is a schematic diagram of an embodiment in which the image sensor of the present application is applied to an electronic device.

Among them, the reference numerals are described as follows:

100, 200, 500, 600 image sensors

101 Semiconductor substrate

102, 502, 504, 506, 508 light sensor

104, 510, 512, 514, 516 transmission gate

106 Reset transistor

108 Source follower transistor

110 row select transistors

116, 518 output circuit

300, 400, 700, 800 Bayer pixel sets

1100 Electronics

1104 Display Assembly

P1, P1', P2, P3, P3', P4, pixels

P5, P5', P6, P7, P7', P8

L channel length

TX, TX1, TX2, TX3, TX4 transmission gate control signal

RST reset signal

RSEL row select signal

POUT output

WL word line

BL bit line

VSS first voltage

VDD second voltage

FD Floating Diffusion

B blue

Gr, Gb green

R red

Detailed ways

The following disclosure provides various implementations, or examples, that can be used to implement various features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. As can be appreciated, these descriptions are merely exemplary and are not intended to limit the present disclosure. For example, in the description below, forming a first feature on or over a second feature may include some embodiments in which the first and second features are in direct contact with each other; and may also include Certain embodiments may have additional components formed between the first and second features described above, such that the first and second features may not be in direct contact. Furthermore, this Summary may reuse reference numerals and/or reference numerals in various embodiments. Such reuse is for brevity and clarity, and does not in itself represent a relationship between the different embodiments and/or configurations discussed.

Furthermore, the use of spatially relative terms, such as "below", "below", "below", "above", "above" and the like, may be used to facilitate the description of the drawings. relationship between one component or feature shown with respect to another component or feature. These spatially relative terms are intended to encompass many different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be positioned in other orientations (eg, rotated 90 degrees or at other orientations) and these spatially relative descriptors should be interpreted accordingly.

Notwithstanding that the numerical ranges and parameters setting forth the broader scope of the application are approximations, the numerical values set forth in the specific examples have been reported as precisely as possible. Any numerical value, however, inherently contains the standard deviation resulting from individual testing methods. As used herein, "about" generally means within plus or minus 10%, 5%, 1%, or 0.5% of the actual value of a particular value or range. Alternatively, the word "about" means that the actual value lies within an acceptable standard error of the mean, as considered by one of ordinary skill in the art to which this application pertains. It should be understood that all ranges, quantities, numerical values and percentages used herein (for example, to describe material amounts, time durations, temperatures, operating conditions, quantity ratios and other similar) are modified by "about". Therefore, unless otherwise stated to the contrary, the numerical parameters disclosed in this specification and the accompanying claims are approximate numerical values and may be changed as required. At a minimum, these numerical parameters should be construed to mean the number of significant digits indicated and the numerical values obtained by applying ordinary rounding. Numerical ranges are expressed herein as from one endpoint to the other or between the endpoints; unless otherwise indicated, the numerical ranges recited herein are inclusive of the endpoints.

The application and demand of high-resolution and even ultra-high-resolution CMOS image sensors are becoming more and more extensive, and the size of the unit pixel must be reduced. performance will inevitably suffer some impact. For example, when the channel length of the source follower transistor in the output circuit is reduced, the random telegraph signal noise will increase. The semiconductor structure of the image sensor of the present application can reduce the pixel area and increase the output by changing the configuration of the output circuit. The source in the circuit follows the channel length of the transistor, thus reducing random telegraph signal noise. In addition, by changing the configuration of the output circuit, the present application can also use the same readout circuit for the green pixels (Gr and Gb) in the same pixel group with Bayer arrangement, so as to avoid the green pixels (Gr and Gb) from being affected by the readout circuit. The difference between the green pixels (Gr and Gb) causes the image misalignment problem between the green pixels (Gr and Gb).

FIG. 1 is a top view of a first embodiment of a semiconductor structure of an image sensor of the present application. The image sensor 100 in FIG. 1 includes a pixel P1 and a pixel P2, and the pixel P1 and the pixel P2 together form a unit pixel group. It should be noted that although the image sensor 100 in FIG. 1 only shows the pixel P1 and the pixel P2, the image sensor 100 may include a plurality of the unit pixel groups. FIG. 3 is a circuit diagram of a pixel P1 or a pixel P2 of the image sensor of FIG. 1 . In this embodiment, the circuit diagrams of the pixel P1 and the pixel P2 are the same.

See also Figure 1 and Figure 3. The image sensor 100 includes a semiconductor substrate 101 , and the pixels P1 and P2 are disposed on the semiconductor substrate 101 . The semiconductor substrate 101 may be a bulk semiconductor substrate, such as a silicon substrate or a silicon-on-insulator (SOI) substrate. Pixel P1 and pixel P2 include photosensor 102 and output circuit 116, respectively. The anode of the photosensor 102 is electrically connected to the first voltage VSS, and the photosensor 102 is used to convert light into electric charges. Please note that the scope of the output circuit 116 is not indicated in FIG. 1 for brevity, and the output circuit 116 is only indicated in FIG. 3 .

The output circuit 116 is used to generate the pixel output according to the charge generated by the photosensor 102 . The output circuit 116 includes a transfer gate 104 , a reset transistor 106 , a source follower transistor 108 and a row select transistor 110 . The transmission gate 104 includes a gate and two sources/drains, the gate of the transmission gate 104 determines whether the transmission gate 104 is turned on or off according to the transmission gate control signal TX, and the two sources/drains of the transmission gate 104 are respectively electrically connected to the photosensitive Sensor 102 and floating diffusion FD. The source follower transistor 108 is disposed between the reset transistor 106 and the row select transistor 110. Specifically, the gate of the source follower transistor 108 and a source/drain of the reset transistor 106 are both electrically connected to the floating diffusion region FD, The other source/drain of the reset transistor 106 is electrically connected to a second voltage VDD, which may be the same as or different from the first voltage VSS. The gate of the reset transistor 106 determines whether to turn on or not according to the control of the reset signal RST. The source follower transistor 108 is connected in series with the row select transistor 110 , and a source/drain of the source follower transistor 108 is electrically connected to a row select transistor 110 . A source/drain, the other source/drain of the source follower transistor 108 is electrically connected to the second voltage VDD. The other source/drain of the row selection transistor 110 is used as the output terminal POUT of the pixel output and is electrically connected to the bit line BL. The gate of the row selection transistor 110 is controlled to determine whether to turn on or not according to the row selection signal RSEL on the word line WL. The pixel output is output from the output terminal POUT to the bit line BL.

From the top view of the semiconductor structures of pixel P1 and pixel P2, the row select transistor 110 of pixel P1 and the row select transistor 110 of pixel P2 are located between the source follower transistor 108 of pixel P1 and the source follower transistor 108 of pixel P2, such that Therefore, the positions of the other source/drain of the row selection transistor 110 of the pixel P1 and the other source/drain of the row selection transistor 110 of the pixel P2 may overlap or be close to each other. For example, in this embodiment, the positions of the other source/drain of the row selection transistor 110 of the pixel P1 and the other source/drain of the row selection transistor 110 of the pixel P2 overlap, specifically , the other source/drain of the row selection transistor 110 of the pixel P1 and the other source/drain of the row selection transistor 110 of the pixel P2 share a region of the semiconductor substrate 101, that is, the row selection transistor of the pixel P1 The other source/drain of the pixel P2 and the other source/drain of the row select transistor 110 of the pixel P2 are shared with each other, so the area of one source/drain can be saved, in other words, the pixels P1 and The pixel P2 shares the output terminal POUT, and the pixel P1 and the pixel P2 are electrically connected to the bit line BL through the through hole provided on the area. However, in some embodiments, more than one via hole may be provided in the region to electrically connect the pixel P1 and the pixel P2 to the bit line BL. In some embodiments, the location of the other source/drain of the row select transistor 110 of pixel P1 and the other source/drain of the row select transistor 110 of pixel P2 may also be close but not overlapping.

Compared with the traditional pixel P1 and the pixel P2 that have their respective output circuits 116 completely separated, the present application configures the pixel P1 and the pixel P2 as a group, and integrates the output circuits 116 of the pixel P1 and the pixel P2, which can save area and Part or all of the extra area is used to increase the channel length L of the source follower transistor 108 of the pixels P1 and P2 to reduce the area of the pixels P1 and P2 and reduce random telegraph signal noise.

Further, from the top view of the semiconductor structure of pixel P1 and pixel P2, in some embodiments, the configuration of source follower transistor 108 and row select transistor 110 of pixel P1 is symmetrical to the source follower transistor 108 and the row select transistor of pixel P2. The configuration of the row select transistor 110 is that the source follower transistor 108 and the row select transistor 110 of the pixel P1 are opposite to the source follower transistor 108 and the row select transistor 110 of the pixel P2. Or, in some embodiments, the output circuit 116 of the pixel P1 and the output circuit 116 of the pixel P2 may be arranged opposite to each other, that is, the output circuit 116 of the pixel P1 is opposite to the output circuit 116 of the pixel P2. Or, in some embodiments, the configuration of the photosensor 102 and the output circuit 116 of the pixel P1 may be symmetrical to the configuration of the photosensor 102 and the output circuit 116 of the pixel P2, that is, the photosensor 102 and the output circuit of the pixel P1 116 opposes the photosensor 102 and the output circuit 116 of the pixel P2.

From the top view of the semiconductor structures of pixel P1 and pixel P2, in some embodiments, the source follower transistor 108, the row select transistor 110 of pixel P1 and the row select transistor 110, source follower transistor 108 of pixel P2 are arranged in sequence A column forms a transistor column. Further, in some embodiments, the reset transistor 106 , the source follower transistor 108 , the row select transistor 110 of the pixel P1 and the row select transistor 110 , the source follower transistor 108 and the reset transistor 106 of the pixel P2 are arranged in sequence. A column forms a transistor column. The photosensor 102 of pixel P1 and the photosensor 102 of pixel P2 are arranged on the same side of the transistor column (106, 108, 110, 110, 108, 106 in order from top to bottom).

In some embodiments, color filters may be disposed above the pixels P1 and P2, and arranged into pixel groups according to a Bayer array, as shown in FIG. 4 , which is a Bayer view based on the semiconductor structure of the image sensor of FIG. pixel group. The Bayer pixel group 300 in FIG. 4 includes two unit pixel groups shown in FIG. 1 , that is, a unit pixel group formed by pixels P1 and P2 and a unit pixel group formed by pixels P3 and P4 . A blue (B) color filter is provided above the photosensitive sensor 102 of the pixel P1, a green (Gr) color filter is provided above the photosensitive sensor 102 of the pixel P2, and a green (Gb) color filter is provided above the photosensitive sensor 102 of the pixel P3. A color filter, and a red (R) color filter is provided above the photosensitive sensor 102 of the pixel P4. In other words, if viewed from the top view, the blue (B) color filter overlaps the pixel P1, the green (Gr) color filter overlaps the pixel P2, and the green (Gb) color filter overlaps the pixel P2. Pixel P3, the red (R) color filter overlaps pixel P4.

In some embodiments, from the top view of the semiconductor structures of the pixel P1 and the pixel P2, the photosensor 102 of the pixel P1 and the photosensor 102 of the pixel P2 are arranged in the transistor columns (106, 108, 110, 110, 108, 106) on opposite sides. FIG. 2 is a top view of a second embodiment of the semiconductor structure of the image sensor of the present application. The image sensor 200 in FIG. 2 includes a pixel P1 ′ and a pixel P2 , and the pixel P1 ′ and the pixel P2 together form a unit pixel group. The circuits of the image sensor 100 of FIG. 1 and the image sensor 200 of FIG. 2 are not actually changed, and the difference from the image sensor 100 of FIG. 1 is that the pixels P1 and P2 of the image sensor 100 of FIG. The same side of the transistor columns (106, 108, 110, 110, 108, 106 from top to bottom), but pixel P1' and pixel P2 of the image sensor 200 of FIG. 106, 108, 110, 110, 108, 106) on different sides, and the pixel P1' and the pixel P2 of the image sensor 200 still share the output terminal POUT, that is, the output terminal POUT of the pixel P1' and the output terminal POUT of the pixel P2 share the same connection. The hole is electrically connected to the bit line BL.

It should be noted that although the image sensor 200 in FIG. 2 only shows the pixel P1 ′ and the pixel P2 , the image sensor 200 may include a plurality of the unit pixel groups. Since the circuits of the image sensor 100 of FIG. 1 and the image sensor 200 of FIG. 2 have not actually changed, but only the configuration of the semiconductor structure has been changed, FIG. 3 is also a circuit diagram of the pixel P1 ′ or the pixel P2 of the image sensor of FIG. 2 . In this embodiment, the circuit diagram of the pixel P1' or the pixel P2 is the same.

In some embodiments, a color filter may be disposed above the pixel P1 ′ and the pixel P2 and arranged into a pixel group according to Bayer, as shown in FIG. 5 , which is a Bayer based on the semiconductor structure of the image sensor of FIG. 2 pixel group. The Bayer pixel group 400 in FIG. 5 includes two unit pixel groups shown in FIG. 2 , that is, a unit pixel group formed by pixels P1 ′ and P2 and a unit pixel group formed by pixels P3 ′ and P4 . A green (Gb) color filter is provided above the photosensitive sensor 102 of the pixel P1', a green (Gr) color filter is provided above the photosensitive sensor 102 of the pixel P2, and a blue (Gr) color filter is provided above the photosensitive sensor 102 of the pixel P3'. B) A color filter, and a red (R) color filter is provided above the photosensor 102 of the pixel P4. In other words, if viewed from a top view, the green (Gb) color filter overlaps the pixel P1', the green (Gr) color filter overlaps the pixel P2, and the blue (B) color filter overlaps In pixel P3', the red (R) color filter overlaps pixel P4.

In the Bayer pixel group 400 of FIG. 5 , green (Gb and Gr) color filters are arranged above the pixels P1 ′ and P2 , and the pixels P1 ′ and P2 share the output terminal POUT, that is, the pixels P1 ′ and the pixels P2 P2 will enter the same read circuit through the same bit line BL. The advantage is to avoid the problem of image misalignment between the green pixels (Gr and Gb) caused by the green pixels (Gr and Gb) entering different read circuits. It should be noted that Yes, in fact, there is inevitably a deviation between the readout circuits. Therefore, if the green pixels (Gr and Gb) in the same Bayer pixel group are read by different readout circuits, the above-mentioned image misalignment problem will be caused. Therefore, compared with the Bayer pixel set 300 of FIG. 4 in the Bayer pixel set 400 of FIG. 5 , the Bayer pixel set 400 of FIG. 5 can improve the above-mentioned image misalignment problem.

In some embodiments, the pixel P1 and the pixel P2 of FIG. 1 may be respectively changed into a plurality of shared pixels, eg, shared pixels on a 2×2 basis. FIG. 6 is a top view of a third embodiment of the semiconductor structure of the image sensor of the present application. The image sensor 500 of FIG. 6 includes a 2×2-based shared pixel P5 and a 2×2-based shared pixel P6. Specifically, the pixel P5 and the pixel P6 respectively include four sub-pixels to form a 2×2-based shared pixel The pixels P5 and P6, and the pixel P5 and the pixel P6 together form a unit pixel group. The difference between the image sensor 500 of FIG. 6 and the image sensor 100 of FIG. 1 is that the pixels P5 and P6 of FIG. 6 respectively include four photosensors 502 , 504 , 506 and 508 corresponding to the first pixel P5 and the second pixel P6 respectively of the four sub-pixels. It should be noted that although the image sensor 500 in FIG. 6 only shows the pixel P5 and the pixel P6, the image sensor 500 may include a plurality of the unit pixel groups. FIG. 8 is a circuit diagram of the pixel P5 or the pixel P6 of the image sensor of FIG. 6 . In this embodiment, the circuit diagram of the pixel P5 or the pixel P6 is the same.

The output circuits 518 of the pixels P5 and P6 of FIG. 6 are substantially the same as the output circuits 116 of the pixels P1 and P2 of FIG. 1 , the difference is that the pixels P5 and P6 respectively have four transfer gates 510 , 512 , 514 and 516 to correspond to Four photosensors 502 , 504 , 506 and 508 . Apart from that, pixel P5 or pixel P6 of FIG. 6 retains all the advantages of pixel P1 or pixel P2 of FIG. 1 .

FIG. 7 is a top view of a fourth embodiment of the semiconductor structure of the image sensor of the present application. The image sensor 600 of FIG. 7 includes a 2×2-based shared pixel P5 ′ and a 2×2-based shared pixel P6 , and the pixel P5 ′ and the pixel P6 together form a unit pixel group. The circuits of the image sensor 600 of FIG. 7 and the image sensor 500 of FIG. 6 are not actually changed, and the difference from the image sensor 500 of FIG. 6 is that the pixels P5 and P6 of the image sensor 500 of FIG. The same side of the transistor columns (106, 108, 110, 110, 108, 106 from top to bottom), but pixel P5' and pixel P6 of the image sensor 600 of FIG. 106, 108, 110, 110, 108, 106) on different sides, and the pixel P5' and the pixel P6 of the image sensor 600 still share the output terminal POUT, that is, the output terminal POUT of the pixel P5' and the output terminal POUT of the pixel P6 share the same output terminal. The hole is electrically connected to the bit line BL.

It should be noted that although the image sensor 600 in FIG. 7 only shows the pixel P5' and the pixel P6, the image sensor 600 may include a plurality of the unit pixel groups. Since the circuits of the image sensor 500 of FIG. 6 and the image sensor 600 of FIG. 7 have not actually changed, only the configuration of the semiconductor structure has been changed. Therefore, FIG. 8 is also a circuit diagram of the pixel P5 ′ or the pixel P6 of the image sensor of FIG. 7 . In this embodiment, the circuit diagram of the pixel P5' or the pixel P6 is the same.

FIG. 9 is a Bayer pixel group based on the semiconductor structure of the image sensor of FIG. 6 . FIG. 10 is a Bayer pixel group based on the semiconductor structure of the image sensor of FIG. 7 . Similar to FIG. 4 and FIG. 5 to FIG. 1 and FIG. 2 , FIG. 9 and FIG. 10 are also examples of arrangement of Bayer pixel groups after adding color filters, and details thereof will not be repeated.

The present application also provides a chip including the image sensor 100/200/300/400/500/600/700/800. The present application also provides an electronic device. FIG. 11 is a schematic diagram of an embodiment in which the image sensor of the present application is applied to an electronic device 1100. As shown in FIG. 11 , the electronic device 1100 includes a display screen assembly 1104 and an image sensor 100/200. /300/400/500/600/700/800. The electronic device 1100 may be any electronic device such as a smart phone, a personal digital assistant, a handheld computer system, a tablet computer, or a digital camera.

The foregoing description briefly sets forth the features of certain embodiments of the present application, so that those skilled in the art to which the present application pertains can more fully understand the various aspects of the present disclosure. It should be apparent to those skilled in the art to which this application pertains that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and/or other aspects of the embodiments described herein. achieve the same advantages. Those with ordinary knowledge in the technical field to which this application belongs should understand that these equivalent embodiments still belong to the spirit and scope of the content of the present invention, and various changes, substitutions and alterations can be made without departing from the spirit of the content of the present invention. with scope.

Claims (16)

1. A semiconductor structure of an image sensor, comprising a semiconductor substrate and a plurality of pixels disposed on the semiconductor substrate, wherein the plurality of pixels comprises:

a first pixel and a second pixel, each of the first pixel and the second pixel including:

at least one photosensitive sensor for converting light into electric charge; and

an output circuit for generating a pixel output according to the charge, the output circuit including a source follower transistor and a row select transistor, a source/drain of the source follower transistor being electrically connected to a source/drain of the row select transistor;

wherein, from a top view, the row select transistor of the first pixel and the row select transistor of the second pixel are both located between the source follower transistor of the first pixel and the source follower transistor of the second pixel.

2. The semiconductor structure of claim 1, wherein, from a top view, the source follower transistor of the first pixel and the row select transistor of the first pixel are arranged symmetrically to the source follower transistor of the second pixel and the row select transistor of the second pixel.

3. The semiconductor structure of an image sensor as claimed in claim 1 or 2, further comprising a bit line, a via hole for electrically connecting row selection transistors of a first pixel and a second pixel to the bit line being disposed on the semiconductor substrate, wherein the output circuit of the first pixel outputs the pixel output by using the other source/drain of the row selection transistor as an output terminal; the output circuit of the second pixel outputs the pixel output by having the other source/drain of the row select transistor therein as an output terminal, and the output terminal of the first pixel and the output terminal of the second pixel share a via to be electrically connected to the bit line.

4. The semiconductor structure of an image sensor as claimed in claim 3, wherein the output circuit of the first pixel further comprises a reset transistor electrically connected to the source follower transistor of the first pixel; the output circuit of the second pixel further includes a reset transistor electrically connected to the source follower transistor of the second pixel.

5. The semiconductor structure of an image sensor as claimed in claim 4, wherein in the first pixel, the source follower transistor is disposed between the reset transistor and the row select transistor as viewed from a top view; and in the second pixel, the source follower transistor is disposed between the reset transistor and the row select transistor.

6. The semiconductor structure of claim 3, wherein said output circuit of said first pixel further comprises at least one transmission gate electrically connected between said at least one photosensor of said first pixel and said source follower transistor of said first pixel; the second pixel further comprises at least one transmission gate electrically connected between the at least one photosensor of the second pixel and the source follower transistor of the second pixel.

7. The semiconductor structure of an image sensor as in claim 1, wherein the first pixel and the second pixel each comprise four sub-pixels to form a 2 x2 shared pixel, and the first pixel and the second pixel each comprise four photosensors for the four sub-pixels of each of the first pixel and the second pixel.

8. The semiconductor structure of claim 3, wherein the source follower transistor of the first pixel, the row select transistor of the first pixel, the source follower transistor of the second pixel, and the row select transistor of the second pixel are arranged in a column to form a column of transistors when viewed from a top view.

9. The semiconductor structure of an image sensor as in claim 8, wherein the at least one photosensor of the first pixel and the at least one photosensor of the second pixel are disposed on a same side of the column of transistors from a top view.

10. The semiconductor structure of claim 9, further comprising a blue color filter and a green color filter respectively disposed over the first pixel and the second pixel, the blue color filter overlapping the first pixel and the green color filter overlapping the second pixel when viewed from a top view.

11. The semiconductor structure of claim 9, further comprising a green color filter and a red color filter disposed over the first pixel and the second pixel, respectively, the green color filter overlapping the first pixel and the red color filter overlapping the second pixel when viewed from a top view.

12. The semiconductor structure of an image sensor as in claim 8, wherein the at least one photosensor of the first pixel and the at least one photosensor of the second pixel are disposed on opposite sides of the column of transistors, respectively, as viewed from a top view.

13. The semiconductor structure of claim 12, further comprising a green color filter disposed over the first pixel and the second pixel, the green color filter overlapping the first pixel and the second pixel when viewed from a top view.

14. The semiconductor structure of claim 12, further comprising a blue color filter and a red color filter respectively disposed over the first pixel and the second pixel, the blue color filter overlapping the first pixel and the red color filter overlapping the second pixel when viewed from a top view.

15. A chip, comprising:

the semiconductor structure of an image sensor as in any one of claims 1-14.

16. An electronic device, comprising:

the semiconductor structure of an image sensor as in any one of claims 1-14.

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