[go: up one dir, main page]

CN110660751B - Chip package and method for manufacturing the same - Google Patents

Chip package and method for manufacturing the same Download PDF

Info

Publication number
CN110660751B
CN110660751B CN201910293383.9A CN201910293383A CN110660751B CN 110660751 B CN110660751 B CN 110660751B CN 201910293383 A CN201910293383 A CN 201910293383A CN 110660751 B CN110660751 B CN 110660751B
Authority
CN
China
Prior art keywords
integrated circuit
conductive
circuit component
layer
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910293383.9A
Other languages
Chinese (zh)
Other versions
CN110660751A (en
Inventor
陈冠宇
苏安治
叶德强
黄立贤
叶名世
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US16/258,672 external-priority patent/US10872855B2/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN110660751A publication Critical patent/CN110660751A/en
Application granted granted Critical
Publication of CN110660751B publication Critical patent/CN110660751B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
    • H01L2225/1094—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种芯片封装件，包括集成电路组件、导热层、绝缘包封体及重布线路结构。所述集成电路组件包括位于所述集成电路组件的后表面处的非晶半导体部分。所述导热层覆盖所述集成电路组件的所述非晶半导体部分，其中所述导热层的导热率大于或大体上等于10W/mK。所述绝缘包封体在横向上对所述集成电路组件及所述导热层进行包封。所述重布线路结构设置在所述绝缘包封体及所述集成电路组件上，其中所述重布线路结构电连接到所述集成电路组件。

A chip package comprises an integrated circuit component, a heat-conducting layer, an insulating encapsulant and a redistribution wiring structure. The integrated circuit component comprises an amorphous semiconductor portion located at a rear surface of the integrated circuit component. The heat-conducting layer covers the amorphous semiconductor portion of the integrated circuit component, wherein the thermal conductivity of the heat-conducting layer is greater than or substantially equal to 10 W/mK. The insulating encapsulant encapsulates the integrated circuit component and the heat-conducting layer in a lateral direction. The redistribution wiring structure is disposed on the insulating encapsulant and the integrated circuit component, wherein the redistribution wiring structure is electrically connected to the integrated circuit component.

Description

Chip package and manufacturing method thereof
Technical Field
The embodiment of the invention relates to a chip package and a manufacturing method thereof.
Background
The semiconductor industry has experienced a rapid growth due to the continued increase in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). To a large extent, this increase in integration density results from the ever decreasing minimum feature size (minimum feature size), which enables the integration of more smaller components into a given area. These smaller electronic components also require smaller packages that utilize smaller areas than previous packages. Some smaller types of packages for semiconductor components include Quad Flat Packages (QFP), pin grid array (PIN GRID ARRAY, PGA) packages, ball grid array (ball GRID ARRAY, BGA) packages, and the like.
Currently, integrated fan-out packages are becoming increasingly popular because of their compactness. Heat generated from the integrated circuit components of the integrated fan-out package cannot be efficiently dissipated due to the low thermal conductivity (e.g., k < 1W/mK) of the die attach film.
Disclosure of Invention
According to an embodiment of the invention, a method of making a chip package includes attaching an integrated circuit component to a carrier with a first thermal paste having a thermal conductivity in a range of about 10W/mK to about 250W/mK, forming an insulating encapsulant to encapsulate the integrated circuit component attached to the carrier, and forming a rerouting circuit structure on the insulating encapsulant and the integrated circuit component, wherein the rerouting circuit structure is electrically connected to the integrated circuit component.
According to an embodiment of the invention, a method of making a chip package includes providing an integrated circuit assembly having a metal layer formed thereon, attaching the integrated circuit assembly to a carrier with a die attach film such that the metal layer is located between the integrated circuit assembly and the die attach film, wherein the metal layer has a thermal conductivity greater than a thermal conductivity of the die attach film, forming an insulating encapsulation to encapsulate the integrated circuit assembly attached to the carrier, and forming a rerouting circuit structure on the insulating encapsulation and the integrated circuit assembly, wherein the rerouting circuit structure is electrically connected to the integrated circuit assembly.
According to an embodiment of the invention, a chip package includes an integrated circuit assembly, a thermally conductive layer, an insulating encapsulant, and a rerouting circuit structure. An integrated circuit component includes an amorphous semiconductor portion at a rear surface of the integrated circuit component. A thermally conductive layer covers the amorphous semiconductor portion of the integrated circuit component, wherein the thermally conductive layer has a thermal conductivity in a range of about 10W/mK to about 250W/mK. An insulating encapsulant encapsulates the integrated circuit assembly and the thermally conductive layer. A rerouting circuit structure is disposed on the insulating enclosure and the integrated circuit assembly, wherein the rerouting circuit structure is electrically connected to the integrated circuit assembly.
Drawings
The various aspects of the disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that the various features are not drawn to scale in accordance with standard practices in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1-15 illustrate a process flow for fabricating an integrated fan-out package according to some embodiments of the present disclosure.
Fig. 16-30 illustrate a process flow for fabricating an integrated fan-out package according to some alternative embodiments of the present disclosure.
Fig. 31 schematically illustrates an integrated fan-out package according to some embodiments of the present disclosure.
Fig. 32 schematically illustrates an integrated fan-out package according to some alternative embodiments of the present disclosure.
[ Description of symbols ]
100, A wafer;
100': thinning the wafer;
110. 110a semiconductor substrate;
110': thinning the semiconductor substrate;
110S an amorphous semiconductor portion;
120 conductive pads;
130. 130a passivation layer;
132. 142 contact openings;
140. 140a, a post passivation layer;
150, a conductive column;
160. 160a, 160a': protective layers;
200 an integrated circuit assembly;
210 insulating material;
210': an insulating encapsulation;
b, conductive features;
BP is a conductive bump;
C, a carrier;
DAF, DAF1, die attach film;
DB, stripping layer;
DT is cutting adhesive tape;
M, M1 a metal layer;
P1 and P11 are package structures;
p2, semiconductor device;
RDL: rerouting the circuit structure;
ST, sawing the adhesive tape;
TP, thermal paste;
TP1, first thermal paste;
TP2, second thermal paste;
TV: conductive perforation;
UF, underfill.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and/or letters in the various examples. Such reuse is for brevity and clarity and does not itself represent a relationship between the various embodiments and/or configurations discussed.
Further, for ease of description, spatially relative terms such as "below", "above", "upper", and the like may be used herein to describe one element or feature's relationship to another element or feature in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein interpreted accordingly.
Other features and processes may also be included in the present disclosure. For example, test structures may be included to facilitate verification testing of three-dimensional (3D) packages or three-dimensional integrated circuit (3 DIC) devices. The test structures may include, for example, test pads formed in a redistribution layer or on a substrate to enable testing of a three-dimensional package or three-dimensional integrated circuit, use of probes and/or probe cards (probe cards), and the like. Verification tests may be performed on intermediate structures as well as final structures. Additionally, the structures and methods disclosed herein may be used in conjunction with test methods that include intermediate verification of known good die (knowngood die) to improve yield and reduce cost.
Fig. 1-15 illustrate a process flow for fabricating an integrated fan-out package according to some embodiments of the present disclosure.
Referring to fig. 1, a wafer 100 is provided, the wafer 100 including a plurality of semiconductor die or integrated circuit assemblies 200 arranged in an array. Before performing a wafer dicing process (WAFER DICING processes) on the wafer 100, the individual integrated circuit components 200 of the wafer 100 are connected to one another. In some embodiments, the wafer 100 may include a semiconductor substrate 110, a plurality of conductive pads 120 formed on the semiconductor substrate 110, and a passivation layer 130. The passivation layer 130 is formed over the semiconductor substrate 110 and has a plurality of contact openings 132 such that the conductive pads 120 are partially exposed by the contact openings 132 of the passivation layer 130. For example, the semiconductor substrate 110 may be a silicon substrate including active components (e.g., transistors, etc.) and passive components (e.g., resistors, capacitors, inductors, etc.) formed therein, the conductive pad 120 may be an aluminum pad, a copper pad, or other suitable metal pad, and the passivation layer 130 may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed of other suitable dielectric material.
As shown in fig. 1, in some embodiments, the wafer 100 may further include a post-passivation layer (post-passivation layer) 140 formed on the passivation layer 130. The rear passivation layer 140 covers the passivation layer 130 and has a plurality of contact openings 142. The conductive pad 120 exposed by the contact opening 132 of the passivation layer 130 may be partially exposed by the contact opening 142 of the rear passivation layer 140. For example, the post passivation layer 140 may be a Polyimide (PI) layer, a Polybenzoxazolole (PBO) layer, or a dielectric layer formed of other suitable polymers.
Referring to fig. 2, a plurality of conductive pillars 150 are formed on the conductive pad 120. In some embodiments, conductive pillars 150 are plated on conductive pads 120. The electroplating process of the conductive pillars 150 is described in detail below. First, a seed layer may be sputtered onto the post passivation layer 140 and the conductive pad 120 exposed by the contact opening 142. A patterned photoresist layer (not shown) may then be formed over the seed layer by photolithography (photolithography), wherein the patterned photoresist layer exposes portions of the seed layer corresponding to the conductive pads 120. The wafer 100 may be immersed in an electroplating solution in a plating bath (plating bath), the wafer 100 including a patterned photoresist layer formed thereon such that the conductive pillars 150 are plated on portions of the seed layer corresponding to the conductive pads 120. After the electroplated conductive posts 150 are formed, the patterned photoresist layer is stripped. Thereafter, by using the conductive pillars 150 as a hard mask, portions of the seed layer not covered by the conductive pillars 150 may be removed, for example, by etching (etching), until the post passivation layer 140 is exposed. In some embodiments, the plated conductive pillars 150 may be plated copper pillars.
Referring to fig. 3, after the conductive pillars 150 are formed, a protective layer 160 is formed on the rear passivation layer 140 to cover the conductive pillars 150. In some embodiments, the protective layer 160 may be a polymer layer having a thickness sufficient to encapsulate and protect the conductive pillars 150. For example, the protective layer 160 may be a Polybenzoxazole (PBO) layer, a Polyimide (PI) layer, or other suitable polymer. In some alternative embodiments, the protective layer 160 may be made of an inorganic material.
Referring to fig. 3 and 4, after the protective layer 160 is formed, a back-side grinding (back-SIDE GRINDING) process is performed on the rear surface of the wafer 100. During the backside grinding process, the semiconductor substrate 110 is ground by a grinding wheel such that the thinned wafer 100 'is formed, the thinned wafer 100' including the thinned semiconductor substrate 110', the conductive pad 120, the passivation layer 130, the post passivation layer 140, the conductive post 150, and the protective layer 160 formed on the thinned semiconductor substrate 110'. After the back side grinding process is performed, as shown in fig. 4, an amorphous semiconductor portion 110S (e.g., an amorphous silicon layer) formed by the back side grinding process is formed at the rear surface of the thinned semiconductor substrate 110'. In some embodiments, the thickness of the amorphous semiconductor portion 110S may be in the range of about 10 nanometers to about 50 nanometers. In addition, the grit size of the grinding wheel used to grind the semiconductor substrate 110 may be in the range of about 3 microns to about 15 microns.
Referring to fig. 5, after the back side grinding process is performed, a thinned wafer 100 'is mounted on the dicing tape DT so that the rear surface of the thinned semiconductor substrate 110' is adhered to the dicing tape DT. In some embodiments, the dicing tape DT may support the thinned wafer 100 'mounted on the dicing tape DT and temporarily adhere to the rear surface of the thinned wafer 100'.
Referring to fig. 5 and 6, after the thinned wafer 100' is mounted on the dicing tape DT, a wafer dicing process is performed on the thinned wafer 100' to singulate the integrated circuit components 200 in the thinned wafer 100' from each other. After the singulation process, a plurality of singulated integrated circuit assemblies 200 are formed that are bonded together with dicing tape DT. As shown in fig. 6, each of the singulated integrated circuit components 200 includes a semiconductor substrate 110a, a conductive pad 120 formed on the semiconductor substrate 110a, a passivation layer 130a, a post passivation layer 140a, conductive pillars 150, and a protective layer 160a. The materials and characteristics of the semiconductor substrate 110a, the passivation layer 130a, the post passivation layer 140a, and the protective layer 160a are the same as those of the semiconductor substrate 110, the passivation layer 130, the post passivation layer 140, and the protective layer 160. Accordingly, detailed descriptions of the semiconductor substrate 110a, the passivation layer 130a, the post passivation layer 140a, and the protective layer 160a in the singulated integrated circuit assembly 200 are omitted.
The protective layer 160 may sufficiently protect the conductive pillars 150 of the integrated circuit assembly 200 during the backside grinding process and the wafer dicing process. In addition, the conductive pillars 150 of the singulated integrated circuit assemblies 200 may be protected from damage by subsequently performed processes, such as pick and place (picking-up AND PLACING) processes, molding (molding) processes, and the like, of the singulated integrated circuit assemblies 200.
Referring to fig. 6 and 7, a carrier C having a release layer DB formed thereon is provided. In some embodiments, the carrier C is a glass substrate, and the release layer DB is a light-to-heat conversion (LTHC) release layer formed on the glass substrate. In some alternative embodiments, a dielectric layer (not shown) may be formed on the release layer DB such that the release layer DB is located between the carrier C and the dielectric layer. For example, the dielectric layer is a Polybenzoxazole (PBO) layer formed on the release layer DB.
After the carrier C having the release layer DB formed thereon is provided, a plurality of conductive through holes TV are formed on the release layer DB. In some embodiments, the plurality of conductive vias TV may be formed by sputtering of a seed layer, photoresist coating, photolithography, electroplating of vias, photoresist stripping, and patterning of the seed layer. For example, the conductive vias TV include copper pillars (copper post) or other suitable metal pillars.
As shown in fig. 6 and 7, in some embodiments, one of the singulated integrated circuit components 200 is picked up from the dicing tape DT and placed on the release layer DB, the singulated integrated circuit component 200 including the semiconductor substrate 110a, the conductive pad 120, the passivation layer 130a, the post passivation layer 140a, the conductive pillars 150, and the protective layer 160a. In some alternative embodiments, more than one singulated integrated circuit assembly 200 is picked from dicing tape DT and placed on release layer DB, wherein the singulated integrated circuit assemblies 200 placed on release layer DB may be arranged in an array. When singulated integrated circuit components 200 placed on the release layer DB are arranged in an array, the conductive vias TV can be categorized into groups and the number of singulated integrated circuit components 200 corresponds to the number of groups of conductive vias TV.
The singulated integrated circuit assembly 200 is attached or adhered to the release layer DB by a first thermal paste TP1, wherein the thermal conductivity (k) of the first thermal paste TP1 is greater than or substantially equal to 10W/mK. In some embodiments, the first thermal paste TP1 may be formed on the release layer DB by dispensing (dispensing) or other suitable process. For example, the thermal conductivity (k) of the first thermal paste TP1 may be in the range of about 10W/mK to about 250W/mK. In addition, the material of the first thermal paste TP1 may be a polymer paste containing metal powder.
As shown in fig. 7, for example, the top surface of the protective layer 160a is higher than the top surface of the conductive via TV, while the top surface of the protective layer 160a is higher than the top surface of the conductive post 150. However, the present disclosure is not limited thereto. In some alternative embodiments, the top surface of the protective layer 160a may be substantially aligned with the top surface of the conductive via TV, and the top surface of the protective layer 160a is higher than the top surface of the conductive post 150.
Referring to fig. 8, an insulating material 210 is formed on the release layer DB to cover the singulated integrated circuit components 200 and the conductive vias TV. In some embodiments, the insulating material 210 is a molding compound formed by a molding process. For example, the top surface of the protective layer 160a of the singulated integrated circuit assembly 200 is covered by the insulating material 210. In other words, the top surface of the protective layer 160a of the singulated integrated circuit assembly 200 is not exposed but is protected by the insulating material 210. In some embodiments, the insulating material 210 comprises an epoxy or other suitable dielectric material.
Referring to fig. 8 and 9, the insulating material 210 is polished until the top surfaces of the conductive pillars 150, the top surfaces of the conductive vias TV, and the top surfaces of the protective layer 160a are exposed. In some embodiments, the insulating material 210 is polished by a mechanical polishing process and/or a Chemical Mechanical Polishing (CMP) process. After grinding the insulating material 210, an insulating encapsulation 210' is formed. During the polishing process of the insulating material 210, portions of the protective layer 160a are polished to form a protective layer 160a'. In some embodiments, portions of the conductive vias TV and portions of the conductive pillars 150 are also lightly polished during the polishing process of the insulating material 210 and the protective layer 160 a.
As shown in fig. 9, the insulating encapsulant 210 'laterally encapsulates the sidewalls of the singulated integrated circuit assembly 200, and the insulating encapsulant 210' is penetrated by the conductive vias TV. In other words, the singulated integrated circuit components 200 and the conductive vias TV are embedded in the insulating encapsulation 210'. It should be noted that the top surface of the conductive perforation TV, the top surface of the insulating encapsulation 210', the top surface of the conductive post 150, and the top surface of the protective layer 160a' are substantially at the same level.
Referring to fig. 10, after the insulating encapsulation 210 'and the protective layer 160a' are formed, a redistribution circuit structure RDL is formed on the top surface of the conductive via TV, on the top surface of the insulating encapsulation 210', on the top surface of the conductive post 150, and on the top surface of the protective layer 160 a'. The redistribution routing structure RDL is made to electrically connect with one or more underlying connectors. Here, the aforementioned connection may be the conductive pillars 150 of the singulated integrated circuit assembly 200 and/or the conductive vias TV embedded in the insulating encapsulation 210'. The redistribution line structure RDL may include a plurality of redistribution lines and a plurality of patterned dielectric layers alternately stacked, as shown in fig. 10. For example, the re-wiring lines may be copper lines and the material of the patterned dielectric layer may include Polyimide (PI), polybenzoxazole (PBO), or other suitable dielectric polymer. In addition, the conductive vias TV are electrically connected to the singulated integrated circuit components 200 via the redistribution line structure RDL.
Referring to fig. 11, after the redistribution line structure RDL is formed, a plurality of conductive features B are formed, which are electrically connected to the redistribution line structure RDL. The conductive features B are disposed on the redistribution line structure RDL and are arranged in an array. In some embodiments, the conductive features B may be conductive balls (e.g., solder balls) arranged in an array. As shown in fig. 11, a package structure P1 is fabricated on a release layer DB carried by a carrier C, the package structure P1 including a first thermal paste TP1, singulated integrated circuit components 200, conductive vias TV, insulating encapsulation 210', redistribution circuit structures RDL, and conductive features B.
Referring to fig. 12, the release layer DB and the carrier C are peeled from the package structure P1 such that the bottom surface of the conductive via TV, the bottom surface of the insulating encapsulation 210', and the surface of the first thermal paste TP1 are peeled from the carrier C and exposed. The bottom surface of the insulating encapsulation 210' is substantially at the same level as the exposed surface of the first thermal paste TP 1. In some embodiments, external energy (e.g., ultraviolet laser, visible light, or heat) may be applied to the release layer DB to make the encapsulation structure P1 separable from the release layer DB carried by the carrier C.
Referring to fig. 13, after the peeling process is performed, the package structure P1 may be flipped (upside down) and mounted on the sawing tape ST so that the conductive features B of the package structure P1 are adhered to the sawing tape ST. In some embodiments, the sawing tape ST may support the above-described package structure P1 mounted on the sawing tape ST and temporarily adhere to the conductive features B of the package structure P1. Because the thermal conductivity (k) of the first thermal paste TP1 is high (i.e., greater than or substantially equal to 10W/mK), the first thermal paste TP1 can efficiently conduct and disperse heat generated from the singulated integrated circuit components 200. Therefore, the removal of the first thermal paste TP1 may not be required to enhance the heat dissipation performance of the package structure P1.
Referring to fig. 14, a second thermal paste TP2 may be formed to cover the exposed surface of the first thermal paste TP1, wherein the thermal conductivity (k) of the second thermal paste TP2 is greater than or substantially equal to 10W/mK. For example, the thermal conductivity (k) of the second thermal paste TP2 may be in the range of about 10W/mK to about 250W/mK. In some embodiments, the thermal conductivity (k) of the first thermal paste TP1 may be substantially equal to the thermal conductivity (k) of the second thermal paste TP 2. In some alternative embodiments, the thermal conductivity (k) of the first thermal paste TP1 may be greater than or less than the thermal conductivity (k) of the second thermal paste TP 2. Because the thermal conductivity (k) of both the first thermal paste TP1 and the second thermal paste TP2 is high (i.e., greater than or substantially equal to 10W/mK), the first thermal paste TP1 and the second thermal paste TP2 can efficiently conduct and disperse heat generated from the singulated integrated circuit components 200.
As shown in fig. 14, the first thermal paste TP1 is embedded in the insulating encapsulation body 210 'and the first thermal paste TP1 contacts the amorphous semiconductor portion 110S of the thinned semiconductor substrate 110'. In some embodiments, the second thermal paste TP2 may be thicker than the first thermal paste TP 1. In some alternative embodiments, the second thermal paste TP2 may be thinner than the first thermal paste TP 1. In some other embodiments, the thickness of the first thermal paste TP1 and the second thermal paste TP2 may be substantially the same. For example, the thickness of the first thermal paste TP1 may be in the range of about 1 micron to about 100 microns, while the thickness of the second thermal paste TP2 may be in the range of about 1 micron to about 100 microns. In addition, the second thermal paste TP2 may cover not only the surface of the first thermal paste TP1 but also the surface of the insulating encapsulation 210' locally. However, the distribution of the second thermal paste TP2 is not limited thereto.
When at least one of the first thermal paste TP1 and the second thermal paste TP2 contains metal particles (e.g., copper particles), the amorphous semiconductor portion 110S of the thinned semiconductor substrate 110' may trap the metal particles contained in the first thermal paste TP1 and/or the second thermal paste TP 2. In other words, when at least one of the first thermal paste TP1 and the second thermal paste TP2 contains metal particles, the amorphous semiconductor portion 110S of the thinned semiconductor substrate 110' may serve as a diffusion barrier for the metal particles. Thus, the package structure P1 can easily pass the high temperature operating lifetime (high temperature operating life, HTOL) test.
In some alternative embodiments, the fabrication of the second thermal paste TP2 may be omitted, as shown in fig. 31.
As shown in fig. 14, the combination of the first thermal paste TP1 and the second thermal paste TP2 may be regarded as a thermally conductive layer covering the amorphous semiconductor portion 110S of the singulated integrated circuit assembly 200. In some alternative embodiments, when the fabrication of the second thermal paste TP2 is omitted, the thermally conductive layer includes only the first thermal paste TP1.
Referring to fig. 15, a semiconductor device P2 is provided and the semiconductor device P2 is placed on the package structure P1 to electrically connect the semiconductor device P2 to the conductive via TV. The semiconductor device P2 is electrically connected to the integrated circuit assembly 200 via the conductive via TV and the redistribution line structure RDL. In some embodiments, the semiconductor device P2 may be electrically connected to the conductive vias TV of the package structure P1 via a plurality of conductive bumps BP. For example, the conductive bump BP may be a micro bump, a controlled collapse die connection (controlled collapse chip connection, C4) bump, or the like.
In some embodiments, the semiconductor device P2 may be a memory device (e.g., a DRAM) including conductive bumps BP on its bottom surface. The semiconductor device P2 is, for example, a Ball Grid Array (BGA) package. In the semiconductor device P2, at least one memory chip may be mounted on a BGA circuit board, electrically connected to the BGA board via bond wires, and encapsulated by a molding compound. Before mounting the semiconductor device P2 onto the package structure P1, solder material may be applied onto the conductive vias TV of the package structure P1 by, for example, a screen printing process (STENCIL PRINTING processes), and then the semiconductor device P2 including the conductive bumps BP is placed on the conductive vias TV. Thereafter, a reflow process is performed to form a solder joint between the semiconductor device P2 and the conductive via TV of the package structure P1.
After the reflow process is performed, an underfill UF is formed between the package structure P1 and the semiconductor device P2 to encapsulate the second thermal paste TP2 and the conductive bump BP. In some embodiments, the material of underfill UF may include epoxy containing filler and the thermal conductivity of underfill UF may be less than about 1W/mK. The underfill UF encapsulates the conductive bumps BP in the lateral direction and acts as a stress buffer to minimize fatigue (fatigue) of the conductive bumps BP due to coefficient of thermal expansion (coefficient of thermal expansion, CTE) mismatch between the package structure P1 and the semiconductor device P2.
After the underfill UF is formed, a sawing process is performed on the package structure P1 to form a plurality of singulated package-on-package (PoP) structures. After the sawing process of the package structure P1 is performed, the singulated package on package (PoP) structure is stuck with the sawing tape ST. In addition, the underfill UF can ensure reliability of a package-on-package (PoP) structure including the package structure P1 and the semiconductor device P2.
Fig. 16-30 illustrate a process flow for fabricating an integrated fan-out package according to some alternative embodiments of the present disclosure.
Referring to fig. 16, a wafer 100 is provided, the wafer 100 including a plurality of semiconductor die or integrated circuit assemblies 200 arranged in an array. Before performing a wafer dicing process on the wafer 100, the integrated circuit assemblies 200 of the wafer 100 are connected to each other. In some embodiments, the wafer 100 may include a semiconductor substrate 110, a plurality of conductive pads 120 formed on the semiconductor substrate 110, and a passivation layer 130. The passivation layer 130 is formed over the semiconductor substrate 110 and has a plurality of contact openings 132 such that the conductive pads 120 are partially exposed by the contact openings 132 of the passivation layer 130. For example, the semiconductor substrate 110 may be a silicon substrate including active components (e.g., transistors, etc.) and passive components (e.g., resistors, capacitors, inductors, etc.) formed therein, the conductive pad 120 may be an aluminum pad, a copper pad, or other suitable metal pad, and the passivation layer 130 may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed of other suitable dielectric material.
As shown in fig. 16, in some embodiments, the wafer 100 may further include a post passivation layer 140 formed on the passivation layer 130. The rear passivation layer 140 covers the passivation layer 130 and has a plurality of contact openings 142. The conductive pad 120 exposed by the contact opening 132 of the passivation layer 130 may be partially exposed by the contact opening 142 of the rear passivation layer 140. For example, the post passivation layer 140 may be a Polyimide (PI) layer, a Polybenzoxazole (PBO) layer, or a dielectric layer formed of other suitable polymer.
Referring to fig. 17, a plurality of conductive pillars 150 are formed on the conductive pad 120. In some embodiments, conductive pillars 150 are plated on conductive pads 120. The electroplating process of the conductive pillars 150 is described in detail below. First, a seed layer may be sputtered onto the post passivation layer 140 and the conductive pad 120 exposed by the contact opening 142. A patterned photoresist layer (not shown) may then be formed over the seed layer by photolithography, wherein the patterned photoresist layer exposes portions of the seed layer corresponding to the conductive pads 120. The wafer 100 may be immersed in an electroplating solution in a plating bath, the wafer 100 including a patterned photoresist layer formed thereon, such that the conductive pillars 150 are plated on portions of the seed layer corresponding to the conductive pads 120. After the electroplated conductive posts 150 are formed, the patterned photoresist layer is stripped. Thereafter, by using the conductive pillars 150 as a hard mask, portions of the seed layer not covered by the conductive pillars 150 may be removed, for example, by etching, until the post passivation layer 140 is exposed. In some embodiments, the plated conductive pillars 150 may be plated copper pillars.
Referring to fig. 18, after the conductive pillars 150 are formed, a protective layer 160 is formed on the rear passivation layer 140 to cover the conductive pillars 150. In some embodiments, the protective layer 160 may be a polymer layer having a thickness sufficient to encapsulate and protect the conductive pillars 150. For example, the protective layer 160 may be a Polybenzoxazole (PBO) layer, a Polyimide (PI) layer, or other suitable polymer. In some alternative embodiments, the protective layer 160 may be made of an inorganic material.
Referring to fig. 18 and 19, after the protective layer 160 is formed, a backside grinding process is performed on the rear surface of the wafer 100. During the backside grinding process, the semiconductor substrate 110 is ground such that the thinned wafer 100 'is formed, the thinned wafer 100' including the thinned semiconductor substrate 110', the conductive pad 120, the passivation layer 130, the post passivation layer 140, the conductive post 150, and the protective layer 160 formed on the thinned semiconductor substrate 110'. After the back side grinding process is performed, as shown in fig. 19, an amorphous semiconductor portion 110S (e.g., an amorphous silicon layer) formed by the back side grinding process is formed at the rear surface of the thinned semiconductor substrate 110'. In some embodiments, the thickness of the amorphous semiconductor portion 110S may be in the range of about 10 nanometers to about 50 nanometers.
After the back side grinding process is performed, a metal layer M is formed on the rear surface of the thinned semiconductor substrate 110'. For example, metal is formed on the back surface of the thinned semiconductor substrate 110' by sputtering or other suitable deposition process. The metal layer M covers and contacts the amorphous semiconductor portion 110S of the thinned semiconductor substrate 110'. The metal layer M serves as a protective layer to protect the amorphous semiconductor portion 110S of the thinned semiconductor substrate 110' from damage or removal by a process performed later. The thickness of the metal layer M may be less than about 5000 angstroms. For example, the thickness of the metal layer M may be in the range of about 3000 angstroms to about 5000 angstroms. In some embodiments, the metal layer M may be a single metal layer (e.g., copper layer, silver layer, titanium layer, or nickel layer) or a plurality of metal layers, and the thermal conductivity of the metal layer M may be greater than or substantially equal to 20W/mK. For example, the thermal conductivity of the metal layer M may be in the range of about 20W/mK to about 406W/mK.
Referring to fig. 20, after forming the metal layer M, a dicing tape DT including a die attach film DAF is provided and a thinned wafer 100 'is mounted on the die attach film DAF carried by the dicing tape DT so that the metal layer M formed on the rear surface of the thinned semiconductor substrate 110' and the die attach film DAF on the dicing tape DT are bonded together. In some embodiments, the dicing tape DT may support the thinned wafer 100 'mounted on the dicing tape DT and the die attach film DAF may temporarily adhere to the metal layer M formed on the rear surface of the thinned wafer 100'. Additionally, the material of the die attach film DAF may be tacky and the thermal conductivity (k) of the die attach film DAF is less than or substantially equal to 1W/mK. In some embodiments, the thermal conductivity (k) of the die attach film DAF may be in the range of about 0.01W/mK to about 1W/mK.
Referring to fig. 20 and 21, after the thinned wafer 100' is mounted on the dicing tape DT, a wafer dicing process is performed on the thinned wafer 100', the metal layer M, and the die attach film DAF to singulate the integrated circuit components 200 in the thinned wafer 100' from each other. After the singulation process, a plurality of singulated integrated circuit assemblies 200, a plurality of singulated metal layers M1, and a plurality of singulated die attach films DAF1 are formed, wherein the singulated metal layers M1 are located between the singulated die attach films DAF1 and the singulated integrated circuit assemblies 200. As shown in fig. 21, each of the singulated integrated circuit components 200 includes a semiconductor substrate 110a, a conductive pad 120 formed on the semiconductor substrate 110a, a passivation layer 130a, a post passivation layer 140a, conductive pillars 150, and a protective layer 160a. The singulated metal layer M1 covers the rear surface of the semiconductor substrate 110a, and the singulated die attach film DAF1 and the singulated metal layer M1 are bonded together. The materials and characteristics of the semiconductor substrate 110a, the passivation layer 130a, the post passivation layer 140a, and the protective layer 160a are the same as those of the semiconductor substrate 110, the passivation layer 130, the post passivation layer 140, and the protective layer 160. Accordingly, detailed descriptions of the semiconductor substrate 110a, the passivation layer 130a, the post passivation layer 140a, and the protective layer 160a in the singulated integrated circuit assembly 200 are omitted.
The protective layer 160 may substantially protect the conductive pillars 150 of the singulated integrated circuit components 200 during the backside grinding process and the wafer dicing process. In addition, the conductive pillars 150 of the singulated integrated circuit assemblies 200 may be protected from damage by subsequently performed processes (e.g., pick and place processes, molding processes, etc. of the singulated integrated circuit assemblies 200).
Referring to fig. 21 and 22, a carrier C having a release layer DB formed thereon is provided. In some embodiments, the carrier C is a glass substrate, and the release layer DB is a photo-thermal conversion (LTHC) release layer formed on the glass substrate. In some alternative embodiments, a dielectric layer (not shown) may be formed on the release layer DB such that the release layer DB is located between the carrier C and the dielectric layer. For example, the dielectric layer is a Polybenzoxazole (PBO) layer formed on the release layer DB.
After the carrier C having the release layer DB formed thereon is provided, a plurality of conductive through holes TV are formed on the release layer DB. In some embodiments, the plurality of conductive vias TV may be formed by sputtering of a seed layer, photoresist coating, photolithography, electroplating of vias, photoresist stripping, and patterning of the seed layer. For example, the conductive vias TV include copper pillars or other suitable metal pillars.
As shown in fig. 21 and 22, in some embodiments, one of the singulated integrated circuit assemblies 200 is picked from the dicing tape DT and placed on the release layer DB. In some alternative embodiments, more than one singulated integrated circuit assembly 200 is picked from dicing tape DT and placed on release layer DB, wherein the singulated integrated circuit assemblies 200 placed on release layer DB may be arranged in an array. When singulated integrated circuit components 200 placed on the release layer DB are arranged in an array, the conductive vias TV can be categorized into groups and the number of singulated integrated circuit components 200 corresponds to the number of groups of conductive vias TV.
The singulated integrated circuit assembly 200 is attached or adhered to the release layer DB by the singulated die attach film DAF1, wherein the thermal conductivity (k) of the singulated die attach film DAF1 is less than or substantially equal to 1W/mK. In some embodiments, the singulated die attach film DAF1 may have a thermal conductivity (k) in the range of about 0.01W/mK to about 1W/mK. In addition, the material of the singulated die attach film DAF1 may be tacky.
As shown in fig. 22, for example, the top surface of the protective layer 160a is higher than the top surface of the conductive via TV, while the top surface of the protective layer 160a is higher than the top surface of the conductive post 150. However, the present disclosure is not limited thereto. In some alternative embodiments, the top surface of the protective layer 160a may be substantially aligned with the top surface of the conductive via TV, and the top surface of the protective layer 160a is higher than the top surface of the conductive post 150.
Referring to fig. 23, an insulating material 210 is formed on the release layer DB to cover the singulated integrated circuit components 200 and the conductive vias TV. In some embodiments, the insulating material 210 is a molding compound formed by a molding process. For example, the top surface of the protective layer 160a of the singulated integrated circuit assembly 200 is covered by the insulating material 210. In other words, the top surface of the protective layer 160a of the singulated integrated circuit assembly 200 is not exposed but is protected by the insulating material 210. In some embodiments, the insulating material 210 includes an epoxy or other suitable dielectric material.
Referring to fig. 23 and 24, the insulating material 210 is polished until the top surfaces of the conductive pillars 150, the top surfaces of the conductive vias TV, and the top surfaces of the protective layer 160a are exposed. In some embodiments, the insulating material 210 is polished by a mechanical polishing process and/or a Chemical Mechanical Polishing (CMP) process. After grinding the insulating material 210, an insulating encapsulation 210' is formed. During the polishing process of the insulating material 210, portions of the protective layer 160a are polished to form a protective layer 160a'. In some embodiments, portions of the conductive vias TV and portions of the conductive pillars 150 are also lightly polished during the polishing process of the insulating material 210 and the protective layer 160 a.
As shown in fig. 24, the insulating encapsulant 210 'laterally encapsulates the sidewalls of the singulated integrated circuit assembly 200, and the insulating encapsulant 210' is penetrated by the conductive vias TV. In other words, the singulated integrated circuit components 200 and the conductive vias TV are embedded in the insulating encapsulation 210'. It should be noted that the top surface of the conductive perforation TV, the top surface of the insulating encapsulation 210', the top surface of the conductive post 150, and the top surface of the protective layer 160a' are substantially at the same level.
Referring to fig. 25, after the insulating encapsulation 210 'and the protective layer 160a' are formed, a redistribution circuit structure RDL is formed on the top surface of the conductive via TV, on the top surface of the insulating encapsulation 210', on the top surface of the conductive post 150, and on the top surface of the protective layer 160 a'. The redistribution routing structure RDL is made to electrically connect with one or more underlying connectors. Here, the aforementioned connection may be the conductive pillars 150 of the singulated integrated circuit assembly 200 and/or the conductive vias TV embedded in the insulating encapsulation 210'. The redistribution line structure RDL may include a plurality of redistribution lines and a plurality of patterned dielectric layers alternately stacked, as shown in fig. 25. For example, the re-wiring lines may be copper lines and the material of the patterned dielectric layer may include Polyimide (PI), polybenzoxazole (PBO), or other suitable dielectric polymer. In addition, the conductive vias TV are electrically connected to the singulated integrated circuit components 200 via the redistribution line structure RDL.
Referring to fig. 26, after the redistribution line structure RDL is formed, a plurality of conductive features B are formed, which are electrically connected to the redistribution line structure RDL. The conductive features B are disposed on the redistribution line structure RDL and are arranged in an array. In some embodiments, the conductive features B may be conductive balls (e.g., solder balls) arranged in an array. As shown in fig. 26, a package structure P11 is fabricated on a release layer DB carried by a carrier C, the package structure P11 including a singulated metal layer M1, a singulated die attach film DAF1, a singulated integrated circuit assembly 200, conductive vias TV, an insulating encapsulant 210', a redistribution circuit structure RDL, and conductive features B.
Referring to fig. 27, the release layer DB and the carrier C are peeled from the package structure P11 so that the bottom surface of the conductive via TV, the bottom surface of the insulating encapsulation body 210', and the surface of the singulated die attach film DAF1 are peeled from the carrier C and exposed. The bottom surface of the insulating encapsulation 210' is at substantially the same level as the exposed surface of the singulated die attach film DAF 1. In some embodiments, external energy (e.g., ultraviolet laser, visible light, or heat) may be applied to the release layer DB to separate the encapsulation structure P11 from the release layer DB carried by the carrier C.
Referring to fig. 28, after the peeling process is performed, the package structure P11 may be flipped (upside down) and mounted on the sawing tape ST so that the conductive features B of the package structure P11 are adhered to the sawing tape ST. In some embodiments, the sawing tape ST may support the above-described package structure P11 mounted on the sawing tape ST and temporarily adhere to the conductive features B of the package structure P11. Because the singulated die attach film DAF1 has a low thermal conductivity (k) (i.e., less than or substantially equal to 1W/mK), the singulated die attach film DAF1 may not be able to efficiently conduct and disperse heat generated from the singulated integrated circuit assemblies 200. Thus, the singulated die attach film DAF1 may be removed until the singulated metal layer M1 is exposed to enhance the heat dissipation performance of the package structure P11. For example, the singulated die attach film DAF1 may be removed by dry etching (e.g., plasma treatment) or other suitable removal process. When the singulated die attach film DAF1 is removed, the singulated metal layer M1 may protect the amorphous semiconductor portion 110S (shown in fig. 29) of the thinned semiconductor substrate 110' from damage or removal.
Referring to fig. 29, after removal of the singulated die attach film DAF1, a thermal paste TP may be formed by dispensing or other suitable process to cover the exposed surface of the singulated metal layer M1, wherein the thermal conductivity (k) of the thermal paste TP is greater than or substantially equal to 10W/mK. For example, the thermal paste TP has a thermal conductivity (k) in the range of about 10W/mK to about 250W/mK. In some embodiments, the thermal conductivity (k) of the thermal paste TP may be less than the thermal conductivity (k) of the singulated metal layer M1. In some alternative embodiments, the thermal conductivity (k) of the thermal paste TP may be greater than or substantially equal to the thermal conductivity (k) of the singulated metal layer M1. Because the thermal conductivity (k) of both the thermal paste TP and the singulated metal layer M1 is high (i.e., greater than or substantially equal to 10W/mK), the thermal paste TP and the singulated metal layer M1 can efficiently conduct and disperse heat generated from the singulated integrated circuit device 200.
As shown in fig. 29, the singulated metal layer M1 is embedded in the insulating encapsulation body 210 'and contacts the amorphous semiconductor portion 110S of the thinned semiconductor substrate 110'. In addition, the thermal paste TP covers the singulated metal layer M1 and is partially embedded in the insulating encapsulation 210'. In some embodiments, the thermal paste TP may be thicker than the singulated metal layer M1. For example, the thickness of the thermal paste TP may be in the range of about 1 micron to about 100 microns. In some alternative embodiments, the thermal paste TP may be thinner than the singulated metal layer M1. In some other embodiments, the thickness of the thermal paste TP and the singulated metal layer M1 may be substantially the same. In addition, the thermal paste TP may cover not only the surface of the singulated metal layer M1 but also the surface of the insulating encapsulation 210' locally. However, the distribution of the thermal paste TP is not limited thereto.
When the thermal paste TP contains metal particles (e.g., copper particles), the singulated metal layer M1 may serve as a diffusion barrier for the metal particles. In addition, the amorphous semiconductor portion 110S of the thinned semiconductor substrate 110' may trap metal particles from the singulated metal layer M1 and may serve as a diffusion barrier for metal particles diffused from the singulated metal layer M1. Thus, the package structure P11 can easily pass a High Temperature Operating Lifetime (HTOL) test.
In some alternative embodiments, the fabrication of the thermal paste TP may be omitted, as shown in fig. 32.
As shown in fig. 29, the combination of the singulated metal layer M1 and the thermal paste TP can be regarded as a thermally conductive layer covering the amorphous semiconductor portion 110S of the singulated integrated circuit assembly 200. In some alternative embodiments, when the fabrication of the thermal paste TP is omitted, the thermally conductive layer includes only the singulated metal layer M1.
Referring to fig. 30, a semiconductor device P2 is provided and the semiconductor device P2 is placed on the package structure P11 to electrically connect the semiconductor device P2 to the conductive via TV. The semiconductor device P2 is electrically connected to the singulated integrated circuit assembly 200 via the conductive vias TV and the redistribution line structure RDL. In some embodiments, the semiconductor device P2 may be electrically connected to the conductive vias TV of the package structure P11 via a plurality of conductive bumps BP. For example, the conductive bumps BP may be micro-bumps, controlled collapse-die connection (C4) bumps, or the like.
In some embodiments, the semiconductor device P2 may be a memory device (e.g., a DRAM) including conductive bumps BP on its bottom surface. Before mounting the memory device on the package structure P11, a solder material may be applied onto the conductive vias TV of the package structure P11 by, for example, a screen printing process, and then the semiconductor device P2 including the conductive bumps BP may be placed on the conductive vias TV. Thereafter, a reflow process is performed to form a solder joint between the semiconductor device P2 and the conductive via TV of the package structure P11.
After the reflow process is performed, an underfill UF is formed between the package structure P11 and the semiconductor device P2 to encapsulate the thermal paste TP and the conductive bumps BP. In some embodiments, the material of underfill UF may include epoxy containing filler and the thermal conductivity of underfill UF may be less than about 1W/mK. The underfill UF encapsulates the conductive bumps BP in the lateral direction and acts as a stress buffer to minimize fatigue of the conductive bumps BP due to Coefficient of Thermal Expansion (CTE) mismatch between the package structure P11 and the semiconductor device P2.
After the underfill UF is formed, a sawing process is performed on the package structure P11 to form a plurality of singulated package on package (PoP) structures. After the sawing process of the package structure P11 is performed, the singulated package on package (PoP) structure is stuck with the sawing tape ST. In addition, the underfill UF can ensure reliability of a package-on-package (PoP) structure including the package structure P11 and the semiconductor device P2.
According to some embodiments of the present disclosure, a method of fabricating a chip package is provided that includes the following steps. The integrated circuit assembly is attached to the carrier by a first thermal paste having a thermal conductivity in the range of about 10W/mK to about 250W/mK. An insulating encapsulant is formed to encapsulate the integrated circuit assembly attached to the carrier. A rerouting circuit structure is formed on the insulating enclosure and the integrated circuit component, wherein the rerouting circuit structure is electrically connected to the integrated circuit component. In an embodiment, the method further comprises forming a plurality of conductive vias on the carrier prior to forming the insulating encapsulation such that the plurality of conductive vias are encapsulated by the insulating encapsulation, wherein after forming the rerouting circuit structure, the plurality of conductive vias are electrically connected to the integrated circuit assembly via the rerouting circuit structure. In an embodiment, the method further includes, after forming the rerouting circuit structure, stripping the first thermal paste and the insulating encapsulation from the carrier, and electrically connecting a semiconductor device to the plurality of conductive vias such that the first thermal paste is located between the integrated circuit assembly and the semiconductor device, wherein the semiconductor device is electrically connected to the integrated circuit assembly via the plurality of conductive vias and the rerouting circuit structure. In an embodiment, the method further includes forming an underfill between the integrated circuit assembly and the semiconductor device to cover the first thermal paste. In an embodiment, the method further includes, after forming the rerouting circuit structure, stripping the first thermal paste and the insulating encapsulation from the carrier to expose a surface of the first thermal paste, forming a second thermal paste on the exposed surface of the first thermal paste, wherein the second thermal paste has a thermal conductivity greater than or substantially equal to 10W/mK, and electrically connecting a semiconductor device to the plurality of conductive vias such that the first thermal paste and the second thermal paste are located between the integrated circuit assembly and the semiconductor device, wherein the semiconductor device is electrically connected to the integrated circuit assembly via the plurality of conductive vias and the rerouting circuit structure. In an embodiment, the method further includes forming an underfill between the integrated circuit assembly and the semiconductor device to encapsulate the second thermal paste. In an embodiment, the integrated circuit component includes an amorphous semiconductor portion at a rear surface of the integrated circuit component, and the amorphous semiconductor portion of the integrated circuit component contacts the first thermal paste.
According to some embodiments of the present disclosure, a method of fabricating a chip package is provided that includes the following steps. An integrated circuit assembly is provided having a metal layer formed thereon. And attaching the integrated circuit assembly to the carrier through the die attach film so that the metal layer is positioned between the integrated circuit assembly and the die attach film, wherein the metal layer has a thermal conductivity greater than that of the die attach film. An insulating encapsulant is formed to encapsulate the integrated circuit assembly attached to the carrier. A rerouting circuit structure is formed on the insulating enclosure and the integrated circuit component, wherein the rerouting circuit structure is electrically connected to the integrated circuit component. In an embodiment, the method further comprises forming a plurality of conductive vias on the carrier prior to forming the insulating encapsulation such that the plurality of conductive vias are encapsulated by the insulating encapsulation, wherein after forming the rerouting circuit structure, the plurality of conductive vias are electrically connected to the integrated circuit assembly via the rerouting circuit structure. In an embodiment, the method further includes, after forming the rerouting circuit structure, peeling the die attach film and the insulating encapsulation from the carrier, and removing the die attach film to expose the metal layer, electrically connecting a semiconductor device to the plurality of conductive vias such that the die attach film is located between the integrated circuit assembly and the semiconductor device, wherein the semiconductor device is electrically connected to the integrated circuit assembly via the plurality of conductive vias and the rerouting circuit structure. In an embodiment, the method further includes forming an underfill to cover the metal layer between the integrated circuit assembly and the semiconductor device. In an embodiment, the method further includes, after forming the rerouting circuit structure, peeling the die attach film and the insulating encapsulation from the carrier to expose the die attach film, removing the die attach film to expose the metal layer, forming a thermal paste on the metal layer, and electrically connecting a semiconductor device to the plurality of conductive vias such that the metal layer and the thermal paste are located between the integrated circuit assembly and the semiconductor device, wherein the semiconductor device is electrically connected to the integrated circuit assembly via the plurality of conductive vias and the rerouting circuit structure. In an embodiment, the method further includes forming an underfill between the integrated circuit assembly and the semiconductor device to encapsulate the thermal paste. In an embodiment, the integrated circuit component includes an amorphous semiconductor portion at a rear surface of the integrated circuit component, and the amorphous semiconductor portion of the integrated circuit component contacts the metal layer. In an embodiment, the metal layer has a thermal conductivity in a range of about 20W/mK to about 406W/mK.
According to some embodiments of the present disclosure, a chip package is provided that includes an integrated circuit component, a thermally conductive layer, an insulating encapsulant, and a rerouting circuit structure. The integrated circuit component includes an amorphous semiconductor portion at a rear surface of the integrated circuit component. The thermally conductive layer covers the amorphous semiconductor portion of the integrated circuit component, wherein the thermally conductive layer has a thermal conductivity in a range of about 10W/mK to about 250W/mK. The insulating encapsulant encapsulates the integrated circuit component and the thermally conductive layer. The rerouting circuit structure is disposed on the insulating enclosure and the integrated circuit assembly, wherein the rerouting circuit structure is electrically connected to the integrated circuit assembly. In an embodiment, the thermally conductive layer includes a first thermal paste that contacts the amorphous semiconductor portion of the integrated circuit component. In an embodiment, the thermally conductive layer comprises a first thermal paste and a second thermal paste. A first thermal paste contacts the amorphous semiconductor portion of the integrated circuit component, the first thermal paste having a thermal conductivity in a range of about 10W/mK to about 250W/mK. A second thermal paste covers the first thermal paste, wherein the second thermal paste has a thermal conductivity in a range of about 10W/mK to about 250W/mK. In an embodiment, the thermally conductive layer comprises a metal layer that contacts the amorphous semiconductor portion of the integrated circuit component, and the metal layer has a thermal conductivity in a range of about 20W/mK to about 406W/mK. In an embodiment, the thermally conductive layer comprises a metal layer and a thermal paste. A metal layer contacts the amorphous semiconductor portion of the integrated circuit component. A thermal paste covers the metal layer, wherein the thermal paste is partially embedded in the insulating encapsulation.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (10)

1.一种芯片封装件，其特征在于，包括：1. A chip package, comprising: 集成电路组件，包括位于所述集成电路组件的后表面处的非晶半导体部分；an integrated circuit component including an amorphous semiconductor portion located at a rear surface of the integrated circuit component; 导热层，覆盖所述集成电路组件的所述非晶半导体部分，其中所述导热层的导热率介于10W/mK到250W/mK的范围内；a thermally conductive layer covering the amorphous semiconductor portion of the integrated circuit component, wherein the thermal conductivity of the thermally conductive layer is in the range of 10 W/mK to 250 W/mK; 绝缘包封体，对所述集成电路组件及所述导热层进行包封；An insulating encapsulation body, encapsulating the integrated circuit component and the heat-conducting layer; 重布线路结构，设置在所述绝缘包封体及所述集成电路组件上，其中所述重布线路结构电连接到所述集成电路组件；a redistribution wiring structure disposed on the insulating package and the integrated circuit component, wherein the redistribution wiring structure is electrically connected to the integrated circuit component; 半导体器件，设置于所述集成电路组件及所述绝缘包封体之上，其中所述半导体器件电连接所述集成电路组件；a semiconductor device disposed on the integrated circuit component and the insulating package, wherein the semiconductor device is electrically connected to the integrated circuit component; 多个导电穿孔贯穿所述绝缘包封体；以及A plurality of conductive through-holes penetrate the insulating enclosure; and 多个导电凸块，设置于所述半导体器件与所述多个导电穿孔贯穿之间，其中所述半导体器件通过所述多个导电凸块、所述多个导电穿孔贯及所述重布线路结构电连接所述集成电路组件。A plurality of conductive bumps are disposed between the semiconductor device and the plurality of conductive through-holes, wherein the semiconductor device is electrically connected to the integrated circuit component through the plurality of conductive bumps, the plurality of conductive through-holes and the redistribution line structure. 2.根据权利要求1所述的芯片封装件，其特征在于，其中所述导热层包括第一热膏，所述第一热膏接触所述集成电路组件的所述非晶半导体部分。2 . The chip package according to claim 1 , wherein the thermally conductive layer comprises a first thermal paste, wherein the first thermal paste contacts the amorphous semiconductor portion of the integrated circuit component. 3.根据权利要求1所述的芯片封装件，其特征在于，其中所述导热层包括：3. The chip package according to claim 1, wherein the heat conducting layer comprises: 第一热膏，接触所述集成电路组件的所述非晶半导体部分，所述第一热膏的导热率介于10W/mK到250W/mK的范围内；以及a first thermal paste contacting the amorphous semiconductor portion of the integrated circuit component, the first thermal paste having a thermal conductivity ranging from 10 W/mK to 250 W/mK; and 第二热膏，覆盖所述第一热膏，其中所述第二热膏的导热率介于10W/mK到250W/mK的范围内。A second thermal paste covers the first thermal paste, wherein the thermal conductivity of the second thermal paste is in the range of 10 W/mK to 250 W/mK. 4.根据权利要求1所述的芯片封装件，其特征在于，其中所述导热层包括金属层，所述金属层接触所述集成电路组件的所述非晶半导体部分，且所述金属层的导热率介于20W/mK到406W/mK的范围内。4 . The chip package according to claim 1 , wherein the heat conductive layer comprises a metal layer, the metal layer contacts the amorphous semiconductor portion of the integrated circuit component, and the thermal conductivity of the metal layer is in a range of 20 W/mK to 406 W/mK. 5.根据权利要求1所述的芯片封装件，其特征在于，其中所述导热层包括：5. The chip package according to claim 1, wherein the heat conducting layer comprises: 金属层，接触所述集成电路组件的所述非晶半导体部分；以及a metal layer contacting the amorphous semiconductor portion of the integrated circuit component; and 热膏，覆盖所述金属层，其中所述热膏部分地嵌入在所述绝缘包封体中。A thermal paste covers the metal layer, wherein the thermal paste is partially embedded in the insulating enclosure. 6.根据权利要求5所述的芯片封装件，其特征在于，其中所述金属层与所述热膏之间的接口低于所述绝缘包封体的顶表面。6 . The chip package according to claim 5 , wherein an interface between the metal layer and the thermal paste is lower than a top surface of the insulating encapsulation body. 7.一种芯片封装件，其特征在于，包括：7. A chip package, comprising: 集成电路组件；Integrated circuit components; 金属层，包括底表面及与所述底表面相对的顶表面，所述金属层的底表面与所述集成电路组件的后表面接触；a metal layer, comprising a bottom surface and a top surface opposite to the bottom surface, wherein the bottom surface of the metal layer contacts the rear surface of the integrated circuit component; 绝缘包封体，侧向地包封所述集成电路组件及所述金属层，所述绝缘包封体包括第一表面及与所述第一表面相对的第二表面，其中所述金属层的所述顶表面低于所述绝缘包封体的所述第一表面；an insulating encapsulation body, laterally encapsulating the integrated circuit component and the metal layer, the insulating encapsulation body comprising a first surface and a second surface opposite to the first surface, wherein the top surface of the metal layer is lower than the first surface of the insulating encapsulation body; 重布线路结构，设置在所述绝缘包封体的所述第二表面及所述集成电路组件的前表面上，其中所述重布线路结构电连接到所述集成电路组件；a redistribution wiring structure disposed on the second surface of the insulating package and on the front surface of the integrated circuit component, wherein the redistribution wiring structure is electrically connected to the integrated circuit component; 半导体器件，设置于所述集成电路组件及所述绝缘包封体之上，其中所述半导体器件电连接所述集成电路组件；a semiconductor device disposed on the integrated circuit component and the insulating package, wherein the semiconductor device is electrically connected to the integrated circuit component; 多个导电穿孔贯穿所述绝缘包封体；以及A plurality of conductive through-holes penetrate the insulating enclosure; and 多个导电凸块，设置于所述半导体器件与所述多个导电穿孔贯穿之间，其中所述半导体器件通过所述多个导电凸块、所述多个导电穿孔贯及所述重布线路结构电连接所述集成电路组件。A plurality of conductive bumps are disposed between the semiconductor device and the plurality of conductive through-holes, wherein the semiconductor device is electrically connected to the integrated circuit component through the plurality of conductive bumps, the plurality of conductive through-holes and the redistribution line structure. 8.根据权利要求7所述的芯片封装件，其特征在于，其中所述金属层的导热率介于20W/mK到406W/mK的范围内。8 . The chip package according to claim 7 , wherein a thermal conductivity of the metal layer is in a range of 20 W/mK to 406 W/mK. 9.根据权利要求7所述的芯片封装件，还包括：底部填充胶，侧向地包封所述多个导电凸块，其中所述底部填充胶与所述金属层顶表面接触。9 . The chip package according to claim 7 , further comprising: an underfill paste laterally encapsulating the plurality of conductive bumps, wherein the underfill paste contacts a top surface of the metal layer. 10.根据权利要求7所述的芯片封装件，其特征在于，其中所述金属层与所述半导体器件之间的第一最短距离大于所述绝缘包封体与所述半导体器件之间的第二最短距离。10 . The chip package according to claim 7 , wherein a first shortest distance between the metal layer and the semiconductor device is greater than a second shortest distance between the insulating encapsulation body and the semiconductor device.
CN201910293383.9A 2018-06-29 2019-04-12 Chip package and method for manufacturing the same Active CN110660751B (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201862691624P 2018-06-29 2018-06-29
US62/691,624 2018-06-29
US16/258,672 2019-01-28
US16/258,672 US10872855B2 (en) 2018-06-29 2019-01-28 Chip package and method of fabricating the same

Publications (2)

Publication Number Publication Date
CN110660751A CN110660751A (en) 2020-01-07
CN110660751B true CN110660751B (en) 2025-04-01

Family

ID=69028535

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910293383.9A Active CN110660751B (en) 2018-06-29 2019-04-12 Chip package and method for manufacturing the same

Country Status (1)

Country Link
CN (1) CN110660751B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111725154B (en) * 2020-06-29 2022-06-10 上海先方半导体有限公司 Packaging structure of embedded device and manufacturing method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7005319B1 (en) * 2004-11-19 2006-02-28 International Business Machines Corporation Global planarization of wafer scale package with precision die thickness control

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI234246B (en) * 2004-08-03 2005-06-11 Ind Tech Res Inst 3-D stackable semiconductor package
KR100997272B1 (en) * 2008-07-17 2010-11-29 주식회사 동부하이텍 Semiconductor chip and semiconductor chip stack package
US20110085304A1 (en) * 2009-10-14 2011-04-14 Irvine Sensors Corporation Thermal management device comprising thermally conductive heat spreader with electrically isolated through-hole vias
US20110215450A1 (en) * 2010-03-05 2011-09-08 Chi Heejo Integrated circuit packaging system with encapsulation and method of manufacture thereof
US9048222B2 (en) * 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9875988B2 (en) * 2015-10-29 2018-01-23 Semtech Corporation Semiconductor device and method of forming DCALGA package using semiconductor die with micro pillars

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7005319B1 (en) * 2004-11-19 2006-02-28 International Business Machines Corporation Global planarization of wafer scale package with precision die thickness control

Also Published As

Publication number Publication date
CN110660751A (en) 2020-01-07

Similar Documents

Publication Publication Date Title
US12334434B2 (en) Package structure and method of forming the same
US11393749B2 (en) Stacked via structure
US10347574B2 (en) Integrated fan-out packages
US10522476B2 (en) Package structure, integrated fan-out package and method of fabricating the same
US10037961B2 (en) Integrated fan-out package and method of fabricating the same
US12362309B2 (en) Package structure
TWI744628B (en) Chip package and method for fabricating the same
US12176261B2 (en) Method of fabricating package structure
CN107546193A (en) Integrated Fan-Out Package
CN113658944A (en) Semiconductor package and method of forming the same
US10867849B2 (en) Package-on-package structure
CN110660751B (en) Chip package and method for manufacturing the same
US20240072029A1 (en) Semiconductor package and manufacturing method thereof
US10157862B1 (en) Integrated fan-out package and method of fabricating the same
TW202407915A (en) Semiconductor package and manufacturing method thereof
CN120767208A (en) Package and method of forming the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
TG01 Patent term adjustment
TG01 Patent term adjustment