CN110660676A - Method for manufacturing semiconductor crystal grain - Google Patents

Abstract

A method for manufacturing a semiconductor crystal grain is provided. A lower passivation layer is formed on a dielectric layer on a semiconductor substrate. Then, a first opening is formed in the lower passivation layer to expose a portion of the dielectric layer. Next, a metal pad is formed in the first opening. Thereafter, a first oxide-based passivation layer is formed on the metal pad. Then, a second oxide-based passivation layer is formed on the first oxide-based passivation layer. The second oxide-based passivation layer has a hardness less than that of the first oxide-based passivation layer.

Description

Manufacturing method of semiconductor die

technical field

Embodiments of the present disclosure relate to a method for manufacturing a semiconductor die.

Background technique

The semiconductor industry has experienced rapid growth due to the continued increase in integration density in various electronic components (eg, transistors, diodes, resistors, capacitors, etc.). In most cases, this increase in integration density comes from repeated reductions in minimum feature size (eg, shrinking semiconductor process nodes toward the sub-20nm node), which allow more components to be integrated into a given area. With the recent growth in demand for miniaturization, faster speeds, greater bandwidth, and lower power consumption and latency, the need for smaller and more innovative packaging techniques for semiconductor dies has increased.

Using packaging technology, a semiconductor die with electronic components can be electrically connected to external components, such as a printed circuit board (PCB). During the packaging process to form a package structure with semiconductor dies and external components, various deposition, etching and heating operations may be performed. In such packaging processes, substrate warpage is a common problem, usually due to the different coefficients of thermal expansion of the various layers within the semiconductor die. Hence the need for a solution to deal with this problem.

SUMMARY OF THE INVENTION

According to an aspect of the present disclosure, a method for manufacturing a semiconductor die, characterized in that the manufacturing method includes forming a lower passivation layer on a dielectric layer above a semiconductor substrate; forming a first opening in the lower passivation layer to expose a part of the dielectric layer; forming a metal pad in the first opening; forming a first oxide-based passivation layer on the metal pad; and forming a second oxide-based passivation layer between the first oxide-based passivation layer On the other hand, the second oxide-based passivation layer has a hardness lower than that of the first oxide-based passivation layer.

Description of drawings

Aspects of the present disclosure can be best understood from the following detailed description with reference to the accompanying drawings. Note that in accordance with industry standard practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased to clarify the discussion.

1A and 1B are flowcharts illustrating a method for controlling warpage in a package according to some embodiments of the present disclosure;

2-16 are cross-sectional views showing various stages of a method of controlling warpage in a package;

17 is a schematic cross-sectional view of a package structure according to some embodiments of the present disclosure.

【Symbol Description】

100: Methods

102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132: Operation

200: semiconductor die

201: Semiconductor substrate

202: Inner Dielectric Layer

210: Lower metallization layer

211: First Metal Wire

212: Upper metallization layer

213: Second Metal Wire

214: Dielectric Layer

215: Upper metal connector

220: first passivation layer

221: First Opening

230: Metal Layer

231: Gap

232: Metal Pad

234: First Metal Pad

236: Second metal pad

240: Second Passivation Layer

242: third passivation layer

244: Fourth passivation layer

246: Fifth passivation layer

248: Second Opening

250: first buffer layer

252: Third Opening

260: Post passivation interconnect layer

270: Second buffer layer

272: Fourth Opening

280: Metallurgical layer under bump

290: Solder Ball

300, 320: External components

301, 321, 323: Conductive parts

310, 410: Package structure

T1, T2: Thickness

Detailed ways

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are examples only and not intended to be limiting. For example, in the following description, the first feature is formed on or on the second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include additional features that may be formed on the first and second features. The embodiment between the two features is such that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference symbols and/or letters in various instances. This repetition is for the purpose of brevity and does not inherently specify the relationship between the various embodiments and/or configurations discussed.

Spatially relative terms, in addition to the orientation depicted in the figures, are also used to encompass different orientations of elements in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein are to be interpreted as such.

A package structure including a printed circuit board and a die bonded to the printed circuit board can be formed by a plurality of deposition, etching and heating operations, one of which can be a reflow operation to bump the die to the printed circuit board. on the circuit board. In a reflow operation, the package structure is subjected to multiple heat treatments at different temperatures. Changes in temperature during reflow operations cause the die (substrate) to warp, especially when one or more passivation layers with greater thickness and greater hardness are formed in the die to reduce the risk of die cracking. Such die warpage becomes worse when the package structure includes two dies on opposite sides of a double-sided printed circuit board, which leads to double-sided board level reliability (B2LR) concerns. For example, delamination may occur in two layers of each die, where the two layers may be two metal layers within the electrical connection structure of the die. Reducing the thickness of the passivation layer with greater hardness can improve the substrate warpage problem. However, the mechanical strength of the die is also reduced as the thickness of the harder passivation layer is reduced. Without sufficient mechanical strength, grain cracking may occur.

Embodiments of the present disclosure are directed to methods of providing a semiconductor die and controlling warpage within a package. In some embodiments, a plurality of passivation layers having different hardnesses are sequentially formed on the semiconductor substrate of the die. To form such passivation layers, different deposition operations with different deposition rates are used to form at least one of the densely packed passivation layers and the loosely packed other passivation layers. In some embodiments, the thickness of the densely packed (or with greater hardness) passivation layer is reduced, and a loosely packed (or with lesser hardness) passivation layer is additionally formed on the densely packed passivation layer, which can Solve the substrate warpage problem and also reduce the risk of die cracking. The aforementioned passivation layer forms a composite passivation layer with sufficient mechanical strength, lower thermal stress and higher fracture toughness. Therefore, the warpage of the substrate can be reduced and the reliability of the package structure can be improved.

1A and 1B are flowcharts illustrating a method 100 for controlling warpage in a package according to some embodiments of the present disclosure. 2-16 are cross-sectional views showing various stages of a method of controlling warpage within a package. FIG. 2 shows an initial structure including a semiconductor substrate 201 . The semiconductor substrate 201 may be a silicon substrate. Alternatively, the semiconductor substrate 201 may be a silicon on insulator substrate. The semiconductor substrate 201 may also include various circuits (not shown). The circuits formed on the semiconductor substrate 201 may be any type of circuits suitable for a particular application.

According to some embodiments, the circuit may include various n-type metal-oxide semiconductor (NMOS) and/or p-type metal-oxide semiconductor (PMOS) devices, such as transistors, capacitors, resistors, diodes, Photodiodes, fuses, etc. Circuits may be interconnected to perform one or more functions. These functions may include memory structures, processing structures, sensors, amplifiers, power distribution, input/output circuits, or similar functions. It should be understood that the above examples are provided for illustrative purposes only to further explain the application of the present disclosure, and are not intended to limit the present disclosure in any way.

The interlayer dielectric layer 202 is formed on the semiconductor substrate 201 . The ILD 202 may be formed of, for example, a low dielectric constant (low-K) dielectric material, such as silicon dioxide. The interlayer dielectric layer 202 may be formed by any suitable method known in the art, such as spin, chemical vapor deposition (CVD), and plasma enhanced chemical vapor deposition (PECVD). It should be noted that those skilled in the art will recognize that the interlayer dielectric layer 202 may further include multiple dielectric layers.

The lower metallization layer 210 and the upper metallization layer 212 are formed on the ILD layer 202 . As shown in FIG. 2 , the lower metallization layer 210 includes a first metal line 211 . Likewise, the upper metallization layer 212 includes second metal lines 213 . The metal wires 211 and 213 are formed of a metal material such as copper or copper alloy or the like. Metallization layers 210 and 212 may be formed via any suitable technique (eg, deposition, damascene, etc.). Generally, one or more intermetal dielectric layers and associated metallization layers are used to interconnect circuits within semiconductor substrate 201 to form functional circuits and further provide external electrical connections.

It should be noted that although FIG. 2 shows the lower metallization layer 210 and the upper metallization layer 212, one or more intermetal dielectric layers (not shown) and associated metallization layers (not shown) may be formed on the lower metallization layer between layer 210 and upper metallization layer 212 . In particular, those layers between the lower metallization layer 210 and the upper metallization layer 212 may be formed by alternating layers of dielectric (eg, very low-K dielectric material) and layers of conductive material (eg, copper).

A dielectric layer 214 is formed on the upper metallization layer 212 . As shown in FIG. 2 , the upper metal connector 215 is embedded in the dielectric layer 214 . In particular, the upper metal connector 215 provides a conductive channel to the electrical connection structure of the metal wire 213 and the semiconductor element. The upper metal connector 215 may be formed of a metal material such as copper, copper alloy, aluminum, silver, gold, and any combination thereof. The upper metal connectors 215 may be formed by suitable techniques, such as chemical vapor deposition. Alternatively, the upper metal connector 215 may be formed by sputtering, electroplating, or the like.

Please refer to FIG. 1A and FIG. 2 . In operation 102 , a first passivation layer 220 is deposited on the dielectric layer 214 over the semiconductor substrate 201 . In some embodiments, the first passivation layer 220 includes a material such as undoped silicate glass (USG), silicon nitride, silicon dioxide, or silicon oxynitride. In some embodiments, the first passivation layer 220 may be deposited by chemical vapor deposition, spin coating, or other suitable techniques. The first passivation layer 220 can protect the metal lines 211 and 213 and the upper metal connector 215 . In some embodiments, the first passivation layer 220 includes a nitride layer and an oxide layer on the nitride layer. In such embodiments, the thickness of the nitride layer may range from about 50 nm to about 100 nm. In such embodiments, the thickness of the oxide layer may range from about 200 nm to about 1000 nm. The first passivation layer 220 with these layers has better electrical insulating properties and provides better electrical protection.

Please refer to FIG. 1A and FIG. 3 . In operation 104 , a portion of the first passivation layer 220 is removed to form the first opening 221 , and the dielectric layer 214 and the conductive layer (eg, the upper metal connector 215 ) are exposed through the first opening 221 . In some embodiments, removal of the first passivation layer 220 may be accomplished by forming a photoresist layer (not shown) over the first passivation layer 220, patterning the photoresist layer using a suitable lithography technique, and then by an etching operation proceeds to form the first opening 221 .

Please refer to FIG. 1A , FIG. 3 and FIG. 4 . In operation 106 , a metal layer 230 is deposited over the first passivation layer 220 such that the metal layer 230 fills the first opening 221 . In some embodiments, metal layer 230 may be deposited by physical vapor deposition, chemical vapor deposition, sputtering, electroplating, or other suitable processes. In some embodiments, the metal layer 230 may include aluminum, aluminum alloys, copper, copper alloys, or combinations thereof. For example, the metal layer 230 is formed of aluminum or an aluminum alloy, and thus may be referred to as an aluminum pad.

Please refer to FIG. 1A , FIG. 4 and FIG. 5 . In operation 108 , the metal layer 230 is patterned by a photolithography operation and an etching operation, thereby forming a plurality of metal pads 232 . In some embodiments, the metal pads 232 include a first metal pad 234 formed in the first opening 221 over the dielectric layer 214 , and a second metal pad 236 formed on the first passivation layer 220 . In some embodiments, the first metal pad 234 electrically contacts the underlying upper metal connector 215 to provide electrical connection between the underlying integrated circuit and other external components (eg, a printed circuit board). In some embodiments, the height of each second metal pad 236 may range from about 1400 nm to about 2800 nm. The second metal pad 236 having this height can improve the electrical connection between the solder balls and the passivation interconnect layer. In some embodiments, after the metal layer 230 is patterned into the metal pads 232 , a plurality of gaps 231 are formed between two adjacent second metal pads 236 . Each gap 231 may have the same or different size according to the design of the package structure.

As described above, a composite passivation layer comprising a plurality of passivation layers having different hardnesses is then formed to improve grain warpage. Operations 110 , 112 , 114 and 116 of FIGS. 1A and 1B for forming the composite passivation layer are described below with reference to the cross-sectional views shown in FIGS. 6-9 at intermediate stages of forming the composite passivation layer. Each passivation layer has its hardness and thickness, so that the composite passivation layer has low thermal stress, high fracture toughness and sufficient mechanical strength. The thickness of each passivation layer may correspond to the thickness of the passivation layer over the second metal pad 236 unless specifically stated otherwise.

Please refer to FIG. 1A and FIG. 6 . In operation 110 , a second passivation layer 240 is conformally deposited over the first passivation layer 220 to cover the metal pads 232 . In some embodiments, the second passivation layer 240 having the first hardness is formed using a deposition operation having a deposition rate ranging from about 10 nm/s to about 30 nm/s. When the deposition rate is within this range, the desired hardness of the second passivation layer 240 can be achieved. For example, the first hardness of the second passivation layer 240 may range from about 8 GPa to about 12 GPa. If the first hardness is less than about 8 GPa, the second passivation layer 240 may not provide sufficient protection to the underlying structure; however, if the first hardness is greater than about 12 GPa, separation may occur between two adjacent passivation layers. Floor. In some embodiments, the thickness of the second passivation layer 240 ranges from about 50 nm to about 400 nm. When the thickness of the second passivation layer 240 is less than about 50 nm, the second passivation layer 240 cannot provide sufficient protection to the structures below it, and causes charges in subsequent operations (eg, deposition of other passivation layers with higher power) accumulate. The charge accumulation may cause a change in the threshold voltage (Vt) or saturation current (Isat) of electronic components arranged in the semiconductor substrate 201 . On the other hand, when the thickness of the second passivation layer 240 is greater than about 400 nm, it is possible to seal the top of the gap 231 between two adjacent second metal pads 236 (ie, the second passivation layer 240 is in the second phase The portions on top of the adjacent second metal pads 236 are in contact with each other), which increases the challenge of subsequent gap filling operations. Unfilled gaps (or voids) may reduce the mechanical strength of the semiconductor die. In some embodiments the second passivation layer 240 is formed of silicon oxide, such as undoped silica glass or silicon dioxide. In some further embodiments, the reduced modulus of the second passivation layer 240 may be in a range from about 68 GPa to about 102 GPa, and the second passivation having a reduced modulus in this range Layer 240 may provide appropriate stress. When the fold-reduction modulus of the second passivation layer 240 is not within this range, the second passivation layer 240 and its adjacent layers (eg, the first passivation layer 220 or the passivation layer subsequently formed over the second passivation layer) The adhesion between them may not meet the requirements. In other embodiments, the coefficient of thermal expansion (CTE) of the second passivation layer 240 may be from about 0.48 (*10 ⁻⁶ ·° C ⁻¹ ) to about 0.72 (*10 ⁻⁶ ·° C ^{−1 )} ), so that the adhesion between the second passivation layer 240 and its adjacent layers (eg, the first passivation layer 220 or the passivation layer subsequently formed over the second passivation layer) can meet the requirements.

In some embodiments, the second passivation layer 240 may be formed of undoped silica glass formed by plasma enhanced chemical vapor deposition. In some embodiments, plasma enhanced chemical vapor deposition is performed at a temperature of about 300°C to about 500°C using silane [eg, silicon methane (SiH ₄ )] and nitrous oxide as precursors. When the temperature is about 300° C. to about 500° C., the second passivation layer 240 may have a desired silicon-to-oxygen (Si/O) atomic ratio so as to achieve a predetermined refractive index and extinction coefficient for its subsequent application, for example, The silicon to oxygen ratio can range from about 1 to about 4. A ratio as used herein may refer to the resulting value of two values after division. In another embodiment, the flow rate of the silane precursor ranges from about 600 seem (standard cubic centimeter per minute) to about 750 seem. In some embodiments, the flow rate of nitrous oxide is in a range from about 12,000 seem to about 20,000 seem. The flow rate of the precursor can affect the deposition rate as well as the silicon to oxygen atomic ratio. Properties such as hardness, refractive index or extinction coefficient can be satisfactorily controlled when the flow rate of the precursor is controlled.

Please refer to FIG. 1A and FIG. 7 . In operation 112 , a third passivation layer 242 is deposited over the second passivation layer 240 . The third passivation layer 242 is relatively thick and compact (ie, has high hardness), and thus has greater mechanical strength than, for example, the second passivation layer 240 . However, when the temperature changes, since the third passivation layer 242 is harder than the second passivation layer 240 , the third passivation layer 242 is subjected to higher thermal stress than the second passivation layer 240 . For example, when the package temperature cools, the third passivation layer 242 is subjected to higher compressive stress than the second passivation layer 240, thus resulting in increased warpage within the third passivation layer 242 and failing to pass double panel level reliability test.

In some embodiments, the third passivation layer 242 having the second hardness is formed using a deposition operation having a deposition rate ranging from about 5 nm/s to about 15 nm/s. When the deposition rate is within this range, the desired hardness of the third passivation layer 242 can be achieved. For example, the second hardness of the third passivation layer 242 may range from about 10.4 GPa to about 15.6 GPa. If the second hardness is less than about 10.4 GPa, the third passivation layer 242 may not provide sufficient protection to the underlying structure; however, if the second hardness is greater than about 15.6 GPa, it may be between two adjacent passivation layers Delamination occurs. In some embodiments, the thickness of the third passivation layer 242 ranges from about 500 nm to about 1800 nm. When the thickness of the third passivation layer 242 is smaller than about 500 nm, the mechanical strength of the formed semiconductor grains may be insufficient. On the other hand, when the thickness of the third passivation layer 242 is greater than about 1800 nm, the thermal stress of the third passivation layer 242 may cause severe warpage in the package (eg when the package temperature cools down during the reflow process) ). In some embodiments, the ratio of the thickness of the third passivation layer 242 to the thickness of the second passivation layer 240 is in a range from about 3 to about 6. When the ratio is within this range, warpage can be further reduced while maintaining appropriate mechanical strength. In some embodiments, the third passivation layer 242 is formed of silicon oxide, such as undoped silica glass or silicon dioxide. In some further embodiments, the fold-reduced modulus of the third passivation layer 242 may be in a range from about 70.4 GPa to about 105.6 GPa, the third passivation layer 242 having a fold-reduced modulus within this range Appropriate stress is available. When the fold-reduction modulus of the third passivation layer 242 is not within this range, the third passivation layer 242 and its adjacent layers (eg, the second passivation layer 240 or the passivation layer subsequently formed over the third passivation layer) The adhesion between them may not meet the requirements. In other embodiments, the thermal expansion coefficient of the third passivation layer 242 may be in a range from about 0.4 (*10 ^-6 ·°C ^-1 ) to about 0.6 (*10 ^-6 ·°C ^-1 ) such that the third The adhesion between the passivation layer 242 and its adjacent layers (eg, the second passivation layer 240 or a passivation layer subsequently formed over the third passivation layer) may be satisfactory.

In some embodiments, the third passivation layer 242 may be formed of undoped silica glass formed by high-density plasma chemical vapor deposition (HDPCVD), since HDPCVD can form a Undoped silica glass film formed by vapor deposition High hardness undoped silica glass film. High-density plasma chemical vapor deposition performs deposition operations and etching operations simultaneously. The thicker third passivation layer 242 formed over the top corners of the second metal pads 236 can be etched to prevent the top of the gap between the two second metal pads 236 from being sealed. Furthermore, the portion of the third passivation layer 242 over the top of each second metal pad 236 and within the gap 231 is thicker than the portion of the third passivation layer 242 on the sidewall of each second metal pad 236 . In some embodiments, high density plasma chemical vapor deposition is performed at a temperature of about 200°C to about 600°C using silane (eg, silicon methane) and oxygen as precursors. When the temperature is about 200° C. to about 600° C., the third passivation layer 242 may have a desired silicon-to-oxygen (Si/O) atomic ratio so as to achieve a predetermined refractive index and extinction coefficient for its subsequent application, for example, The silicon to oxygen ratio can range from about 1 to about 4. In some embodiments, the bias radio frequency power of the high density plasma chemical vapor deposition may be about 3500W to about 7500W. At this bias RF power, a suitable deposition rate can be achieved. In another embodiment, the flow rate of the silane precursor ranges from about 20,000 seem to about 34,000 seem. In some other embodiments, the flow rate of oxygen ranges from about 165 seem to about 205 seem. The flow rate of the precursor can affect the deposition rate as well as the silicon to oxygen atomic ratio. When the flow rate of the precursor is controlled, properties such as hardness, refractive index or extinction coefficient can be appropriately controlled.

Please refer to FIG. 1A and FIG. 8 . In operation 114 , a fourth passivation layer 244 is conformally deposited over the third passivation layer 242 . The fourth passivation layer 244 is thinner than the third passivation layer 242 and has a lower hardness. Therefore, the fourth passivation layer 244 is subjected to lower thermal stress than the third passivation layer 242 when the package temperature is cooled in the reflow process. The combination of the third passivation layer 242 and the fourth passivation layer 244 has additional advantages in addition to reducing substrate warpage, such as sufficient mechanical strength. The process parameters for forming the fourth passivation layer 244 are described below.

In some embodiments, the fourth passivation layer 244 having the third hardness is formed using a deposition operation having a deposition rate ranging from about 10 nm/s to about 30 nm/s. When the deposition rate is within this range, the desired hardness of the fourth passivation layer 244 can be achieved. For example, the third hardness of the fourth passivation layer 244 may range from about 8 GPa to about 12 GPa. If the third hardness is less than about 8 GPa, the fourth passivation layer 244 may not provide sufficient protection to the underlying structure; however, if the third hardness is greater than about 12 GPa, separation may occur between two adjacent passivation layers. Floor. In some embodiments, the thickness of the fourth passivation layer 244 ranges from about 200 nm to about 800 nm. When the thickness of the fourth passivation layer 244 is smaller than about 200 nm, the mechanical strength of the semiconductor crystal grains is insufficient. On the other hand, when the thickness of the fourth passivation layer 244 is larger than about 800 nm, the substrate warpage cannot be reduced. In some embodiments, the thickness of the fourth passivation layer 244 may be the same as the thickness of the second passivation layer 240 . In some other embodiments, the thickness of the fourth passivation layer 244 may be greater than the thickness of the second passivation layer 240 . In some embodiments, the ratio of the thickness of the third passivation layer 242 to the thickness of the fourth passivation layer 244 ranges from about 1.5 to about 4. When the ratio is within this range, substrate warpage can be further improved while maintaining appropriate mechanical strength. In some embodiments, the fourth passivation layer 244 is formed of silicon oxide, such as undoped silica glass or silicon dioxide. In some further embodiments, the fold-reduction modulus of the fourth passivation layer 244 may be in a range from about 68 GPa to about 102 GPa, and the fourth passivation layer 244 having a fold-reduction modulus within this range may Provide appropriate stress. When the fold-reduction modulus of the fourth passivation layer 244 is not within this range, the fourth passivation layer 244 and its adjacent layers (eg, the third passivation layer 242 or the passivation layer subsequently formed above the fourth passivation layer) The adhesion between them may not meet the requirements. In other embodiments, the thermal expansion coefficient of the fourth passivation layer 244 may be in a range from about 0.48 (*10 ⁻⁶ ·° C ⁻¹ ) to about 0.72 (*10 ⁻⁶ ·° C ⁻¹ ) such that the fourth The adhesion between the passivation layer 244 and its adjacent layers (eg, the third passivation layer 242 or a passivation layer subsequently formed over the fourth passivation layer) may be satisfactory.

In some embodiments, the fourth passivation layer 244 may be formed of undoped silica glass formed by plasma enhanced chemical vapor deposition. In some embodiments, plasma enhanced chemical vapor deposition is performed at a temperature of about 300°C to about 500°C using silane (eg, silicon methane) and nitrous oxide as precursors. When the temperature is about 300° C. to about 500° C., the fourth passivation layer 244 can have a desired silicon-to-oxygen atomic ratio, so as to achieve a predetermined refractive index and extinction coefficient for its subsequent application. For example, the silicon-to-oxygen ratio can be at in the range from about 1 to about 4. In another embodiment, the flow rate of the silane precursor ranges from about 600 seem to about 750 seem. In some other embodiments, the flow rate of nitrous oxide is in a range from about 12,000 seem to about 20,000 seem. The flow rate of the precursor can affect the deposition rate as well as the silicon to oxygen atomic ratio. When the flow rate of the precursor is controlled, properties such as hardness, refractive index or extinction coefficient can be appropriately controlled. In some other embodiments, the fourth passivation layer 244 may be formed of a material different from that of the second passivation layer 240 .

In some embodiments, the first hardness of the second passivation layer 240 is less than the second hardness of the third passivation layer 242 . In some other embodiments, the third hardness of the fourth passivation layer 244 is less than the second hardness of the third passivation layer 242 . In still other embodiments, the first hardness may be equal to, less than, or greater than the third hardness. The difference between the second hardness and the first hardness and the difference between the second hardness and the third hardness are about 2.4 GPa to about 7.6 GPa, respectively, so that the composite passivation layer can have desirable toughness and strength. In some embodiments, the fold-reduction modulus of the second passivation layer 240 is smaller than the fold-reduction modulus of the third passivation layer 242 . In some other embodiments, the fold-reduction modulus of the fourth passivation layer 244 is smaller than the fold-reduction modulus of the third passivation layer 242 . In still other embodiments, the fold-reduction modulus of the second passivation layer 240 may be equal to, smaller than, or greater than the fold-reduction modulus of the fourth passivation layer 244 . The difference between the fold-reduction moduli of the third passivation layer 242 and the second passivation layer 240 and the difference between the fold-reduction moduli of the third passivation layer 242 and the fourth passivation layer 244 are respectively about 2.4 GPa to about 37.6 GPa so that the composite passivation layer can have desirable toughness and strength. In some embodiments, the second, third and fourth passivation layers 240, 242 and 244 may have similar or identical thermal expansion coefficients such that when the reflow operation is performed, between two adjacent passivation layers can reach proper adhesion. In particular, through the sequentially arranged second, third and fourth passivation layers 240 , 242 and 244 , the composite passivation layer has low thermal stress and high fracture toughness, thereby reducing substrate warpage. Furthermore, the composite passivation layer has sufficient mechanical strength to avoid cracking within the passivation layer during the packaging process.

Please refer to FIG. 1B and FIG. 9 . In operation 116 , the composite passivation layer further includes a fifth passivation layer 246 deposited over the fourth passivation layer 244 . In some embodiments, depositing the fifth passivation layer 246 may be performed by chemical vapor deposition, spin coating, or other suitable techniques. In some embodiments, the fifth passivation layer 246 may be formed of a nitride-based dielectric material rather than an oxide-based material of the underlying passivation layers 240-244. For example, the fifth passivation layer 246 includes silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, the thickness of the fifth passivation layer 246 ranges from about 500 nm to about 1000 nm. The sum of the thicknesses of the second, third, fourth and fifth passivation layers 240, 242, 244 and 246 on each of the second metal pads 236 is defined as T1, and the second, third, fourth and The sum of the thicknesses of the fifth passivation layers 240, 242, 244 and 246 between the two second metal pads 236 is defined as T2. In some embodiments, the ratio of T2 to T1 is in the range of about 0.6 to about 0.9. When T2/T1 is less than 0.6, the mechanical strength of the composite passivation layer is insufficient, and cracking may occur during the packaging process. However, due to device limitations, T2/T1 greater than 0.9 is difficult to achieve.

Please refer to FIG. 1B and FIG. 10 . In operation 118 , portions of the second, third, fourth and fifth passivation layers 240 , 242 , 244 and 246 on the first metal pad 234 are removed to form the second opening 248 and the first metal pad 234 A part of it is exposed from the second opening 248 . In some embodiments, photolithography operations and etching operations are performed to define the second openings 248 . In some embodiments where the second, third and fourth passivation layers 240, 242 and 244 are formed of undoped silica glass and the fifth passivation layer 246 is formed of silicon nitride, a wet process of hot phosphoric acid may be used to The fifth passivation layer 246 is removed, and then the second, third and fourth passivation layers 240, 242 and 244 are removed using dilute hydrogen fluoride. As shown in FIG. 10 , the second, third, fourth and fifth passivation layers 240 , 242 , 244 and 246 partially cover the first metal pad 234 .

Please refer to FIG. 1B , FIG. 10 and FIG. 11 . In operation 120 , a first buffer layer 250 is formed over the fifth passivation layer 246 . The third opening 252 is formed in the first buffer layer 250 , and a portion of the first metal pad 234 is exposed through the third opening 252 . The third opening 252 is a combined opening of the second opening 248 ; in other words, the third opening 252 partially overlaps the second opening 248 . In some embodiments, forming the first buffer layer 250 may include depositing the material of the first buffer layer 250 within the second openings 248 and over the fifth passivation layer 246 , and then patterning the first buffer layer 250 to define the third Opening 252. In some embodiments, the material of the first buffer layer 250 may include polyimide (polyimide), polybenzobisoxazole (PBO), benzocyclobutene (BCB), epoxy (epoxy) ), etc., however other relatively soft, mostly organic dielectric materials can also be used. The first buffer layer 250 acts as a stress buffer to reduce the transfer of mechanical stress to the passivation layer during packaging.

Please refer to FIG. 1B , FIG. 11 and FIG. 12 . In operation 122 , a post passivation interconnection (PPI) layer 260 is formed on the first buffer layer 250 and the first metal pad 234 . The post-passivation interconnect layer 260 is conformal to the third opening 252 and is electrically connected to the first metal pad 234 . In some embodiments, the post-passivation interconnect layer 260 is formed of a conductive material including, but not limited to, for example, copper, aluminum, copper alloys, nickel, or other conductive materials. In some embodiments, post passivation interconnect layer 260 may be formed by an electroplating operation. In other embodiments, the post-passivation interconnect layer 260 electrically connects the electronic components within the semiconductor substrate 201 to the solder balls 290 formed subsequently.

Please refer to FIG. 1B and FIG. 13 . In operation 124 , a second buffer layer 270 is formed over the post passivation interconnect layer 260 . In some embodiments, the second buffer 270 is deposited over the post-passivation interconnect layer 260 , and then the second buffer layer 270 is patterned to form fourth openings 272 that expose a portion of the post-passivation interconnect layer 260 . In some embodiments, the material of the second buffer layer 270 may include polyimide, polybenzobisoxazole, benzocyclobutene, epoxy resin, etc. However, other relatively soft, mostly organic materials may also be used. dielectric material.

Please refer to FIG. 1B , FIG. 13 and FIG. 14 . In operation 126 , an under bump metallurgy (UBM) layer 280 is formed within the fourth opening 272 and over the second buffer layer 270 . As shown in FIG. 14 , the under-bump metallurgy layer 280 is spread on the sidewall of the fourth opening 272 and the exposed portion of the interconnect layer 260 is passivated after contact. In some embodiments, the under bump metallurgy layer 280 may include multiple layers of conductive materials, such as titanium layers and copper layers. Each layer within the under bump metallurgy layer 280 may be formed using an electroplating process, such as electrochemical plating, however other forming processes such as sputtering, Evaporation, electroless plating, or plasma enhanced chemical vapor deposition.

Please refer to FIG. 1B and FIG. 15 . In operation 128 , solder balls 290 are formed on the under bump metallurgy layer 280 . In some embodiments, forming the solder balls 290 may include forming a photoresist layer (not shown) over the second buffer layer 270 and the under bump metallurgy layer 280, and patterning the photoresist layer to form an exposed under bump metallurgy layer 280 hole (not shown). The photoresist layer acts as a mold for the metal deposition process used to form the solder balls 290 . In some embodiments, the photoresist material is compatible with conventional equipment and standard ancillary process chemicals used for electroplating. Next, a conductive material may fill a portion of the hole by evaporation, electroplating, or screen printing to form solder balls 290 over the under bump metallurgy layer 280 . The conductive material can be any of a variety of metals or metal alloys. For example, the conductive material can be copper, tin, silver or gold. After the solder balls 290 are formed, the photoresist layer may be removed.

In some embodiments, after the solder balls 290 are formed, a wafer dicing operation (ie, a die dicing operation) may be performed to separate the semiconductor dies on the wafer, as shown in operation 130 .

Please refer to FIG. 1B and FIG. 16 . In operation 132 , the semiconductor die 200 is bonded to the conductive member 301 of the external device 300 , thereby forming the package structure 310 of FIG. 16 . In some embodiments, the external components 300 may include, but are not limited to, printed circuit boards, memory components, central processing units, or other components with electrical input/output. For example, the printed circuit board may be a double-sided printed circuit board. In some embodiments, bonding the semiconductor die 200 to the external device 300 includes performing a reflow operation to form an electrical connection between the semiconductor die 200 and the external device 300 . In some embodiments, the reflow operation includes heating the package structure 310 from a first temperature to a second temperature, maintaining the second temperature for a period of time, and then cooling the package structure 310 from the second temperature to a third temperature. In some embodiments, the first temperature is in a range from about 25°C to about 75°C. In some embodiments, the second temperature is in a range from about 230°C to about 275°C. In some embodiments, the third temperature is in a range from about 25°C to about 75°C. In some embodiments, the duration of the reflow operation may be from about 60 minutes to about 180 minutes. When the temperature of the reflow operation is controlled under such conditions, the electrical connection between the semiconductor die 200 and the external components 300 can be improved without increasing the warpage of the substrate.

17 is a schematic cross-sectional view of a package structure according to some embodiments of the present disclosure. In some embodiments, the two semiconductor dies 200 are respectively bonded to the conductive members 321 and 323 disposed on opposite sides of the external element 320 , thereby forming the package structure 410 . In such an embodiment, the external component 320 is a double-sided printed circuit board. Bonding the two semiconductor dies 200 to the external components 320 may include a reflow operation as described in operation 132 with reference to FIG. 16 .

In some embodiments, the composite passivation with the fourth passivation layer 244 is compared to the composite passivation layer A without the fourth passivation layer 244 (ie, where the thickness of the third passivation layer 242 is T3 ). Layer B (ie, where the sum of the thicknesses of the third and fourth passivation layers 242 and 244 is T3) experiences less thermal stress during the reflow operation. In addition, the fracture strength of the composite passivation layer B is greater than that of the composite passivation layer A. Moreover, the board-level reliability of the package structure with the composite passivation layer B is greater than that of the package structure with the composite passivation layer A.

Embodiments of the present disclosure may have at least the advantages outlined below. The combination of the passivation layer with small hardness and small thickness and the passivation layer with large hardness and large thickness effectively reduces thermal stress and increases fracture toughness and mechanical strength of the composite passivation layer. Therefore, substrate warpage of the semiconductor die that occurs during the reflow operation can be reduced, and board-level reliability of the package structure can be improved.

In some embodiments, a method is provided. A lower passivation layer is formed on the dielectric layer above the semiconductor substrate. Then, a first opening is formed in the lower passivation layer to expose a portion of the dielectric layer. Next, a metal pad is formed in the first opening. After that, a first oxide-based passivation layer is formed on the metal pad. Then, a second oxide-based passivation layer is formed on the first oxide-based passivation layer. The second oxide-based passivation layer has a hardness lower than that of the first oxide-based passivation layer.

In some embodiments, the method further includes forming a third oxide-based passivation layer on the metal pad before forming the first oxide-based passivation layer. In some embodiments, different chemical vapor deposition processes are used to form the first oxide-based passivation layer and the second oxide-based passivation layer. In some embodiments, different chemical vapor deposition processes are used to form the first oxide-based passivation layer and the third oxide-based passivation layer. In some embodiments, the same chemical vapor deposition process is used to form the second oxide-based passivation layer and the third oxide-based passivation layer. In some embodiments, the first oxide-based passivation layer is formed using high density plasma chemical vapor deposition. In some embodiments, plasma enhanced chemical vapor deposition is used to form the second oxide-based passivation layer and the third oxide-based passivation layer. In some embodiments, the method further includes removing portions of the first oxide-based passivation layer and the second oxide-based passivation layer to expose the metal pads; forming a post-passivation interconnect layer on the metal pads; forming a buffer layer over the post-passivation interconnect layer; forming a second opening in the buffer layer; forming an under-bump metallurgy layer in the second opening of the buffer layer and contacting the post-passivation interconnect layer; and forming solder balls under the bump on the metallurgical layer.

In some embodiments, a method is provided. A lower passivation layer is formed on the dielectric layer above the semiconductor substrate. Next, a first opening is formed in the lower passivation layer to expose a portion of the dielectric layer. Then, a metal pad is formed in the first opening and on the lower passivation layer. After that, a first oxide-based passivation layer is deposited on the metal pad at a first deposition rate. Then, a second oxide-based passivation layer is deposited on the first oxide-based passivation layer at a second deposition rate faster than the first deposition rate.

In some embodiments, the deposition of the second oxide-based passivation layer is performed such that the second oxide-based passivation layer has a thickness less than that of the first oxide-based passivation layer. In some embodiments, the method further includes depositing a third oxide-based passivation layer over the metal pad at a third deposition rate faster than the first deposition rate before depositing the first oxide-based passivation layer. In some embodiments, the deposition of the first oxide-based passivation layer is performed such that the thickness of the first oxide-based passivation layer is greater than the thickness of the third oxide-based passivation layer. In some embodiments, the deposition of the second oxide-based passivation layer and the third oxide-based passivation layer is performed using silane and nitrous oxide as precursors. In some embodiments, the deposition of the first oxide-based passivation layer is performed using silane and oxygen as precursors. In some embodiments, the method further includes forming a nitride-based passivation layer over the second oxide-based passivation layer.

In some embodiments, a semiconductor die is provided. The semiconductor die includes a semiconductor substrate, a dielectric layer on the semiconductor substrate, a metal structure in the dielectric layer, a first metal pad on the metal structure, and a first oxide-based passivation on the first metal pad a passivation layer, a second oxide-based passivation layer on the first oxide-based passivation layer, and a bump electrically connected to the first metal pad. The second oxide-based passivation layer has a hardness lower than that of the first oxide-based passivation layer.

In some embodiments, the semiconductor die further includes a nitride-based passivation layer on the second oxide-based passivation layer. In some embodiments, the thickness of the first oxide-based passivation layer is greater than the thickness of the second oxide-based passivation layer. In some embodiments, the semiconductor die further includes a third oxide-based passivation layer, the third oxide-based passivation layer is between the first metal pad and the first oxide-based passivation layer and has a hardness smaller than that of the first oxide-based passivation layer. The hardness of the oxide-based passivation layer. In some embodiments, the semiconductor die further includes a second metal pad, the second metal pad is disposed under the first oxide-based passivation layer and separated from the first metal pad, and the second metal pad has a higher thickness than the first metal pad. the bottom of the bottom of the pad.

The foregoing outlines the features of some embodiments so that those skilled in the art may better understand various aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make numerous changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (1)

1. A method of fabricating a semiconductor die, the method comprising:

forming a lower passivation layer on a dielectric layer over a semiconductor substrate;

forming a first opening in the lower passivation layer to expose a portion of the dielectric layer;

forming a metal pad in the first opening;

forming a first oxide passivation layer on the metal pad; and

forming a second oxide-based passivation layer on the first oxide-based passivation layer, the second oxide-based passivation layer having a hardness less than a hardness of the first oxide-based passivation layer.

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