CN110634820A - Semiconductor structures and methods of forming them - Google Patents

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a base, including a substrate and a discrete fin located on the substrate, the material of the fin is SiGe or a III-V semiconductor material; forming a gate across the fin Pole layer, the gate layer covers part of the top and part of the sidewall of the fin; grooves are formed in the fins on both sides of the gate layer, and the bottom of the groove exposes the substrate; a semiconductor layer is formed in the groove, and the material of the semiconductor layer The thermal conductivity is greater than that of the fin material, the bottom of the semiconductor layer is in contact with the remaining substrate at the bottom of the groove, and the top of the semiconductor layer is lower than the top of the fin; a source-drain doped layer is formed in the groove formed with the semiconductor layer. In the present invention, the semiconductor layer with higher thermal conductivity is used to replace the fins below the source-drain doping layer, thereby improving the heat dissipation performance of the device, improving the self-heating effect, and further improving the performance of the device.

Description

Semiconductor structures and methods of forming them

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof.

Background technique

In semiconductor manufacturing, with the development trend of VLSI, the feature size of integrated circuits continues to decrease. In order to accommodate the reduction in feature size, the channel length of MOSFETs has also been shortened accordingly. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so the control ability of the gate to the channel becomes worse, and the gate voltage pinches off the channel. Difficulty is also increasing, making the phenomenon of subthreshold leakage (subthreshold leakage), the so-called short-channel effects (short-channel effects, SCE) more likely to occur.

Therefore, in order to better adapt to the reduction of the feature size, the semiconductor process gradually begins to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as Fin Field Effect Transistors (FinFETs). In FinFET, the gate structure can control the ultra-thin body (fin) from at least two sides. Compared with the planar MOSFET, the gate structure has a stronger ability to control the channel and can well suppress the short channel effect; Moreover, compared with other devices, FinFET has better compatibility with existing integrated circuit manufacturing.

With the continuous shrinking of device size, the low mobility of Si material has become the main factor restricting device performance, and choosing other channel materials has become a way to continue Moore's Law. Therefore, in order to further improve device performance, PMOS transistors usually use SiGe channel technology, that is, use SiGe materials in the channel region, and NMOS transistors usually use III-V group material channel technology, that is, use III-V group semiconductors in the channel region materials to increase the mobility of carriers in the channel.

However, after selecting other channel materials, the device performance still needs to be improved.

Contents of the invention

The problem to be solved by the invention is to provide a semiconductor structure and its forming method to improve device performance.

In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, including: providing a base, including a substrate and a discrete fin located on the substrate, and the material of the fin is SiGe, Ge or III- V-group semiconductor material; forming a gate layer across the fin, the gate layer covering part of the top and part of the sidewall of the fin; forming grooves in the fin on both sides of the gate layer, The bottom of the groove exposes the substrate; a semiconductor layer is formed in the groove, the thermal conductivity of the material of the semiconductor layer is greater than that of the fin material, and the bottom of the semiconductor layer is in contact with the groove The remaining substrate at the bottom is in contact, and the top of the semiconductor layer is lower than the top of the fin; a source-drain doped layer is formed in the groove formed with the semiconductor layer.

Correspondingly, the present invention also provides a semiconductor structure, including: a base, including a substrate and a discrete fin located on the substrate, and the material of the fin is SiGe, Ge or III-V semiconductor material; A gate layer across the fin, the gate layer covering part of the top and part of the sidewall of the fin; a semiconductor layer located in the fin on both sides of the gate layer, the material of the semiconductor layer The thermal conductivity is greater than the thermal conductivity of the fin material, the bottom of the semiconductor layer is in contact with the substrate, and the top of the semiconductor layer is lower than the top of the fin; the source-drain doped layer is located at the gate In the fins on both sides of the semiconductor layer, the bottom of the source-drain doped layer is in contact with the top of the semiconductor layer.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the present invention, after forming grooves exposing the substrate in the fins on both sides of the gate layer, a semiconductor layer is formed in the grooves, and the thermal conductivity of the material of the semiconductor layer is greater than that of the material of the fins. A source-drain doped layer is formed in the groove of the semiconductor layer; by using a semiconductor layer with a higher thermal conductivity to replace the fins below the source-drain doped layer, the heat dissipation performance of the device is improved, and the spontaneous emission of the device is improved. Thermal effect (Self-heating Effect), thereby improving device performance.

Description of drawings

1 to 9 are structural schematic diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

Detailed ways

It can be seen from the background technology that the performance of the device still needs to be improved. The reasons for the analysis device performance to be improved are:

Compared with Si, SiGe and III-V group semiconductor materials have lower thermal conductivity, so when SiGe or III-V group semiconductor materials are used in the channel region, it is easy to cause the heat generated by the device to dissipate too late, thereby reducing the cooling effect of the device.

Moreover, after the fin structure is introduced into the semiconductor structure, compared with the planar transistor, the substrate area of the fin field effect transistor is reduced, the area occupied by the isolation structure is increased, and the reduction of the substrate area will be reduced. The heat dissipation effect of the device. In addition, since the material of the isolation structure is usually silicon oxide, the thermal conductivity of silicon oxide is also low, which leads to further deterioration of the heat dissipation effect of the device, which in turn leads to a more serious self-heating effect of the device, and corresponding degradation of device performance. more serious.

In order to solve the technical problem, the present invention forms a groove exposing the substrate in the fins on both sides of the gate layer, and then forms a semiconductor layer in the groove, and the thermal conductivity of the material of the semiconductor layer is greater than that of the fin The thermal conductivity of the material, the source-drain doped layer is formed in the groove where the semiconductor layer is formed; by replacing the fin under the source-drain doped layer with a semiconductor layer with a higher thermal conductivity, the performance of the device is improved. The heat dissipation performance improves the self-heating effect, thereby improving the performance of the device.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

1 to 9 are structural schematic diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

Referring to Figure 1 and Figure 2 together, Figure 1 is a perspective view (only three fins are shown), and Figure 2 is a schematic diagram of the cross-sectional structure of Figure 1 along the secant line perpendicular to the extending direction of the fins (as shown in the Y1Y2 direction in Figure 1) , providing a substrate 100, including a substrate 110 and a discrete fin 120 located on the substrate 110, the material of the fin 120 is SiGe, Ge or III-V semiconductor material.

The substrate 110 is used to provide a process platform for subsequent formation of semiconductor structures.

In this embodiment, the semiconductor structure is a FinFET, and the fin 120 on the substrate 110 is used to provide a channel of the FinFET.

When the FinFET is a PMOS transistor, the material of the fin 120 is SiGe. Compared with Si, since SiGe has a higher hole mobility, the use of SiGe channel technology is beneficial to improve the performance of PMOS transistors, such as increasing the switching speed of the device and reducing power consumption. In other embodiments, when the FinFET is a PMOS transistor, the material of the fin may also be Ge.

When the FinFET is an NMOS transistor, the material of the fin portion 120 is a III-V semiconductor material. The electron mobility of III-V semiconductor materials is much higher than that of Si, which is beneficial to improve the performance of NMOS transistors.

Specifically, the III-V group semiconductor material may be InSb, GaSb, GaAs, InAs or InGaAs. In this embodiment, the III-V group semiconductor material is InGaAs. The electron mobility of InGaAs is 6 times to 18 times that of Si, and it has both the low leakage current characteristics of GaAs and the high carrier transport characteristics of InAs, so it can effectively improve the performance of NMOS transistors.

In this embodiment, the substrate 110 includes a bottom substrate 111 and a top substrate 112 on the bottom substrate 111 , the top substrate 112 is made of the same material as the fin portion 120 .

Specifically, the steps of forming the substrate 100 and the fins 120 include: providing the bottom substrate 111; epitaxially growing a fin material layer (not shown) on the bottom substrate 111; patterning the fins material layer, the remaining fin material layer after patterning is used as the top substrate 112, the protrusion on the top substrate 112 is used as the fin 120, the top substrate 112 and the bottom substrate 111 The substrate 110 is formed.

The bottom substrate 111 is used as an epitaxial buffer layer (EPI buffer layer). Specifically, the fin material layer is formed by means of epitaxial growth. In the initial stage of epitaxial growth, the quality of the fin material layer is poor, and the crystal lattice of the fin material layer needs to grow to a certain thickness. Therefore, through the bottom substrate 111, it is beneficial to improve the formation quality of the fins 120, thereby improving device performance.

Correspondingly, in this embodiment, the top substrate 112 and the fin portion 120 are integrally structured, and the material of the top substrate 112 is SiGe, Ge or III-V semiconductor material.

至

Therefore, the thickness T1 of the top substrate 112 (as shown in FIG. 2 ) should neither be too small nor too large. If the thickness T1 of the top substrate 112 is too small, it is difficult to ensure that the fins 120 have good quality; if the thickness T1 of the top substrate 112 is too large, when the thickness of the substrate 110 is constant , it will cause the thickness of the bottom substrate 111 to be too small, which will easily have a bad influence on the performance of the device. Therefore, in this embodiment, the thickness T1 of the top substrate 112 is

to

In this embodiment, the material of the bottom substrate 111 is silicon. In other embodiments, the bottom substrate can also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or gallium indium, and the bottom substrate can also be a silicon-on-insulator substrate or an on-insulator substrate. Ge substrates and other types of substrates.

It should also be noted that, in other embodiments, the substrate may only include the bottom substrate.

In addition, after forming the substrate 110 and the fin portion 120, it also includes: forming an isolation structure 101 on the substrate 110 exposed by the fin portion 120, the isolation structure 101 covering part of the sidewall of the fin portion 120, And the top of the isolation structure 101 is lower than the top of the fin 120 .

The isolation structure 101 is used to isolate adjacent devices or adjacent fins 120 .

In this embodiment, the material of the isolation structure 101 is silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride.

Referring to FIG. 3 , FIG. 3 is a schematic cross-sectional structure diagram based on FIG. 2 along the fin extension direction (as shown in the X1X2 direction in FIG. 1 ), forming a gate layer 220 across the fin 120, and the gate layer 220 is formed across the fin portion 120. Layer 220 covers part of the top and part of the sidewall of the fin 120 .

The gate layer 220 is used to form the gate structure 200 .

In this embodiment, the gate structure 200 is a polysilicon gate structure, and the material of the gate layer 220 is polysilicon. In other embodiments, the material of the gate layer may also be other materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride or amorphous carbon.

In this embodiment, the gate structure 200 is a stacked structure. Therefore, after forming the isolation structure 101 and before forming the gate layer 220, it further includes: forming a gate oxide layer 210 covering the surface of the fin 120 , the gate layer 220 and the gate oxide layer 210 below the gate layer 220 constitute the gate structure 200 .

In this embodiment, the gate oxide layer 210 is made of silicon oxide. In other embodiments, the material of the gate oxide layer may also be silicon oxynitride.

In this embodiment, the gate oxide layer 210 is formed by oxidizing the fin portion 120 , which is beneficial to improve the formation quality and density of the gate oxide layer 210 . Specifically, the oxidation treatment process may be an in-situ steam generation oxidation process (In-situ Stream Generation, ISSG). Correspondingly, the gate oxide layer 210 covers the top surface and the sidewall surface of the fin 120 exposed by the isolation structure 101 .

In other embodiments, the gate structure may also be a single-layer structure, that is, the gate structure only includes the gate layer.

In other embodiments, the gate structure may also be a metal gate structure, and the material of the gate layer is correspondingly a metal material, such as W, Al, Cu, Ag, Au, Pt, Ni or Ti.

Specifically, the step of forming the gate structure 200 includes: after forming a gate oxide layer 210 conformally covering the surface of the fin portion 120, forming a gate material layer covering the gate oxide layer 210; A gate mask layer 230 is formed on the material layer; the gate material layer is etched using the gate mask layer 230 as a mask to expose part of the gate oxide layer 210, and the remaining gate material layer after etching is used as the The gate layer 220 crosses the fin portion 120 and covers part of the top and part of the sidewall of the gate oxide layer 210 .

It should be noted that, after the gate layer 220 is formed, the gate mask layer 230 on the top of the gate layer 220 remains. The material of the gate mask layer 230 is silicon nitride, and the gate mask layer 230 is used to protect the top of the gate layer 220 during subsequent processes.

With reference to FIG. 4 , it should be noted that after forming the gate layer 220 , it further includes: forming sidewalls 250 on the sidewalls of the gate layer 220 .

In this embodiment, the sidewall 250 is used as an etching mask for the subsequent etching process, and is used to define the formation area of the subsequent source-drain doped layer, and to protect the sidewall of the gate layer 220 during the subsequent process. For protection, the sidewall 250 is also used as a PMOS silicon recess (PMOS Si Recess, PSR) mask layer or an NMOS silicon recess (NMOS Si Recess, NSR) mask layer, which can avoid subsequent An epitaxial growth process is performed on the sidewall.

The material of the side wall 250 may be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride and boron carbonitride. The side wall 250 can be a single-layer structure or a laminated structure. In this embodiment, the sidewall 250 is a single-layer structure, and the material of the sidewall 250 is silicon nitride.

In this embodiment, the gate mask layer 230 is formed on the top of the gate layer 220 , so the sidewalls 250 also cover the sidewalls of the gate mask layer 230 . And in order to simplify the process steps, after forming the sidewall 250, the gate oxide layer 210 exposed by the sidewall 250 is retained, and the gate oxide layer 220 and the gate oxide layer 210 exposed by the sidewall 250 can also be used in subsequent processes. The middle protects the surface of the fin portion 120 .

In other embodiments, the gate oxide layer exposed by the sidewall can also be removed to expose the fins 120 on both sides of the gate structure 200 , thereby reducing the difficulty of the subsequent etching process.

Referring to FIG. 5 , grooves 130 are formed in the fins 120 on both sides of the gate layer 220 , and the bottom of the grooves 130 exposes the substrate 110 .

The groove 130 is used to provide a spatial location for the subsequent formation of the source-drain doped layer, and is also used to provide a spatial location for the subsequent formation of a semiconductor layer with a higher thermal conductivity.

In the semiconductor process, source and drain doped layers are usually formed in the partial thickness fins 120 on both sides of the gate layer 220. Therefore, in this embodiment, by exposing the bottom of the groove 130 to the substrate 110 , so that a semiconductor layer with a higher thermal conductivity is formed between the source-drain doped layer and the substrate 110, that is, a material with a higher thermal conductivity is used to replace the material of the fin 120 below the source-drain doped layer, thereby The heat dissipation performance of the device is improved, the self-heating effect of the device is improved, and the performance of the device is further improved.

In this embodiment, the material of the top substrate 112 is the same as that of the fin portion 120, so in order to significantly improve the self-heating effect of the device, in the step of forming the groove 130, the groove 130 is formed along the substrate The normal direction of the surface of the bottom 110 extends into the top substrate 112 , that is, the bottom of the groove 130 exposes the bottom substrate 111 .

Specifically, the step of forming the groove 130 includes: etching the fins 120 on both sides of the gate layer 220, forming a first groove 131 exposing the top substrate 112 in the fins 120; Etching the top substrate 112 along the first groove 131, forming a second groove 132 exposing the bottom substrate 111 in the top substrate 112, the top of the second groove 132 is in contact with Bottoms of the first groove 131 are connected, and the second groove 132 and the first groove 131 form the groove 130 .

In this embodiment, a dry etching process is used to sequentially etch the fins 120 on both sides of the gate layer 220 and the top substrate 112 . The dry etching process has anisotropic etching characteristics, which is beneficial to improving the topography quality of the sidewall of the groove 130 and reducing the impact on the channel region of the device.

In other embodiments, a wet etching process, or a combined wet and dry etching process may also be used to sequentially etch the fins and the top substrate.

It should be noted that, after the formation of the sidewall 250, the gate oxide layer 210 exposed by the sidewall 250 remains, so in the process of forming the groove 130, both sides of the gate layer 220 are also etched. side of the gate oxide layer 210, exposing the top of the fin 120 on both sides of the gate layer 220; after exposing the top of the fin 120, continue to etch the fin 120 and the top substrate 112 to form the groove 130.

Referring to FIG. 6 to FIG. 7, a semiconductor layer 140 (as shown in FIG. 7 ) is formed in the groove 130 (as shown in FIG. 6 ), and the thermal conductivity of the material of the semiconductor layer 140 is greater than that of the material of the fin portion 120. , the bottom of the semiconductor layer 140 is in contact with the remaining substrate 110 at the bottom of the groove 130 , and the top of the semiconductor layer 140 is lower than the top of the fin 120 .

The thermal conductivity of the semiconductor layer 140 is greater than that of the material of the fin 120, so the material of the fin 120 and the material of the top substrate 112 under the source-drain doped layer are replaced by a material with a higher thermal conductivity, thereby The heat dissipation performance of the device is improved, and the self-heating effect of the device is improved.

Wherein, the bottom of the semiconductor layer 140 is in contact with the remaining substrate 110 at the bottom of the groove 130, which not only ensures that the heat generated during device operation is dissipated through the semiconductor layer 140 and through the bottom substrate 111, but also It is also beneficial to ensure good electrical performance of the fin field effect transistor.

In this embodiment, the material of the semiconductor layer 140 is Si. The thermal conductivity of Si is 150W/M·K, and the thermal conductivity of Si is relatively high, so the self-heating effect of the device can be significantly improved; in addition, the Si material has good process compatibility, and the material of the semiconductor layer 140 is compatible with the The material of the bottom substrate 111 is the same, so by selecting Si as the material of the semiconductor layer 140 , it is also beneficial to reduce the adverse effect of the semiconductor layer 140 on the performance of the device.

In other embodiments, the material of the semiconductor layer may also be SiC. The thermal conductivity of SiC is 490W/M·K, and by using SiC as the material of the semiconductor layer, the self-heating effect of the device can also be significantly improved.

In this embodiment, the process for forming the semiconductor layer 140 is a selective epitaxy (selective epitaxial growth, SEG) process, so as to improve the formation quality of the semiconductor layer 140 in the groove 130, and the semiconductor layer 140 and The interface quality of the contact surface of the bottom substrate 111 is beneficial to further improve the performance of the device.

In this embodiment, after the semiconductor layer 140 is formed in the groove 130 , the top of the semiconductor layer 140 is lower than the top of the fin 120 , so as to provide enough space for the subsequent formation of source and drain doped layers.

The distance H between the top of the semiconductor layer 140 and the top of the fin 120 should not be too small, nor should it be too large. If the distance H is too small, the volume of the subsequent source and drain doped layers will be too small, which will easily have a negative impact on device performance, such as affecting the short channel control capability of the device; during the epitaxial growth process, the semiconductor The crystal lattice will not be complete until the layer 140 grows to a certain thickness. If the distance H is too large, that is, the thickness of the semiconductor layer 140 is too small, it will easily cause the quality of the semiconductor layer 140 to deteriorate, thereby reducing the quality of the semiconductor layer 140. Layer 140 properties. Therefore, in this embodiment, the distance H from the top of the semiconductor layer 140 to the top of the fin 120 is to

Specifically, the semiconductor layer 140 exposes part of the fins 120 for forming devices.

As shown in FIG. 6, in this embodiment, after forming the groove 130, before forming the semiconductor layer 140 in the groove 130 (as shown in FIG. 7), it also includes: The barrier layer 350 is formed on the sidewall of the .

The barrier layer 350 covers the sidewall of the groove 130, so in the process of forming the semiconductor layer 140, only the material of the substrate 110 at the bottom of the groove 130 is used as a seed layer to make the semiconductor layer 140 Can grow along the direction of the surface normal of the substrate 110, that is to say, ensure that the growth direction of the semiconductor layer 140 is unidirectional, which is not only easy to control the thickness of the semiconductor layer 140, but also compatible with the barrier Compared with the scheme of growing layers at the bottom of the groove and the sidewall of the groove at the same time, it can also effectively reduce the probability of generating voids in the semiconductor layer 140, thereby improving the formation quality of the semiconductor layer 140; in addition, By making the barrier layer 350 cover the sidewall of the groove 130 , it is also possible to prevent the semiconductor layer 140 from occupying the formation space of the subsequent source-drain doped layer.

It should be noted that after the formation of the semiconductor layer 140, the barrier layer 350 between the semiconductor layer 140 and the sidewall of the groove 130 is retained, so in order to reduce the impact on device performance, the material of the barrier layer 350 as the medium material.

In this embodiment, the barrier layer 350 is made of silicon nitride. The high density of silicon nitride can effectively prevent epitaxial growth on the sidewall of the groove 130 , and silicon nitride is a commonly used dielectric material in the process, and has high process compatibility.

In other embodiments, the material of the barrier layer may also be silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbide boron nitride, or silicon oxycarbide.

至

其中，所述阻挡层350的厚度T2指的是：所述阻挡层350沿垂直于所述凹槽130侧壁方向的尺寸。It should also be noted that the thickness T2 of the barrier layer 350 (as shown in FIG. 6 ) should not be too small or too large. If the thickness T2 of the barrier layer 350 is too small, the protection effect on the sidewall of the groove 130 is poor. During the process of forming the semiconductor layer 140, epitaxial growth is performed on the sidewall of the groove 130. The probability becomes higher; if the thickness T2 of the barrier layer 350 is too large, not only will it cause waste of materials and time, but the barrier layer 350 will also occupy too much space in the groove 130, which is not conducive to the semiconductor The formation of the layer 140 and the source-drain doped layer, on the contrary, tends to degrade the performance of the device. Therefore, in this embodiment, the thickness T2 of the barrier layer 350 is

to

Wherein, the thickness T2 of the barrier layer 350 refers to the dimension of the barrier layer 350 along a direction perpendicular to the sidewall of the groove 130 .

In this embodiment, the barrier layer 350 is formed on the sidewall of the groove 130 through deposition and etching processes. Specifically, the step of forming the barrier layer 350 includes: forming a barrier film (not shown) covering the bottom and sidewalls of the groove 130 , and the barrier film also covers the exposed gate oxide layer of the gate layer 220 210, sidewall 250 and gate mask layer 230; using a maskless dry etching process to remove the top of the gate oxide layer 210, the bottom of the groove 130, the top of the sidewall 250 and the gate mask The barrier film on the top of layer 230, the barrier film on the sidewall of the groove 130 is reserved as the barrier layer 350, and the barrier layer 350 also covers the sidewall of the gate oxide layer 210 at the top position of the groove 130 and the barrier film. The side wall 250 side wall.

In this embodiment, the process of forming the barrier layer 350 is an atomic layer deposition process. Through the atomic layer deposition process, the barrier layer 350 is deposited in the form of an atomic layer, which is conducive to improving the thickness uniformity of the barrier layer 350 and the structural uniformity in the barrier layer 350, and the barrier layer 350 has good Conformal covering capability, and easy to control the thickness T2 of the barrier layer 350 .

In other embodiments, the process of forming the barrier layer may also be a chemical vapor deposition process.

Referring to FIG. 8 , after forming the semiconductor layer 140 in the groove 130 (as shown in FIG. 6 ), it further includes: removing the barrier layer 350 exposed by the semiconductor layer 140 .

By removing the barrier layer 350 exposed by the semiconductor layer 140 to expose the material of the fin 120 on the sidewall of the remaining groove 130, the subsequent epitaxial process of forming the source-drain doped layer can also use the fin 120 on the sidewall of the remaining groove 130 as a The seed layer is therefore beneficial to improve the adhesion of the doped source and drain layer on the sidewall of the remaining groove 130, thereby improving the topographical quality of the doped source and drain layer.

In this embodiment, the step of removing the barrier layer 350 exposed by the semiconductor layer 140 includes: using a dry etching process to etch and remove the barrier layer 350 higher than the top of the semiconductor layer 140 .

By adopting a dry etching process, the removal amount of the barrier layer 350 can be better controlled, and the probability of loss of the barrier layer 350 between the semiconductor layer 140 and the side wall of the groove 130 can be reduced, thereby helping to improve Formation quality of source and drain doped layers.

In some other embodiments, a wet etching process, or a combined wet and dry etching process may also be used to etch and remove the barrier layer higher than the top of the semiconductor layer.

In other embodiments, in order to simplify the process steps, the exposed barrier layer of the semiconductor layer may not be removed.

Referring to FIG. 9 , a source-drain doped layer 300 is formed in the groove 130 (shown in FIG. 6 ) where the semiconductor layer 140 is formed.

In this embodiment, the source-drain doped layer 300 includes a stress layer.

When the FinFET is a PMOS transistor, the material of the stress layer is Si or SiGe, and the dopant ions in the stress layer are P-type ions, such as B, Ga or In. The stress layer provides compressive stress to the channel region of the PMOS device, thereby improving the carrier mobility of the PMOS transistor.

When the FinFET is an NMOS transistor, the material of the stress layer is Si or SiC, and the dopant ions in the stress layer are N-type ions, such as P, As or Sb. The stress layer provides tensile stress for the channel region of the NMOS device, thereby improving the carrier mobility of the NMOS transistor.

Specifically, the step of forming the source-drain doped layer 300 includes: using a selective epitaxy process, filling the stress material into the remaining first groove 131 (as shown in FIG. 8 ) to form the stress layer, and During the process of forming the stress layer, in-situ self-doping is performed to form the source-drain doped layer 300 . In other embodiments, ion doping may be performed on the stress layer after forming the stress layer in the remaining first groove.

In this embodiment, the top of the source-drain doped layer 300 is higher than the top of the fin portion 120, and due to the characteristics of the selective epitaxial process, the source-drain doped layer 300 also covers the sidewall 250 part of the sidewall. In other embodiments, according to actual process requirements, the top of the source-drain doped layer may also be flush with the top of the fin.

It should be noted that, after the source-drain doped layer 300 is formed in the groove 130 where the semiconductor layer 140 is formed, the bottom of the source-drain doped layer 300 is in contact with the top of the semiconductor layer 140, thereby ensuring that all The good electrical performance of the fin field effect transistor is described.

It should also be noted that, after the source-drain doped layer 300 is formed in the groove 130 where the semiconductor layer 140 is formed, the semiconductor layer 140 is located below the source-drain doped layer 300 , and the semiconductor layer 140 It is closer to the channel region of the device, so the heat generated during the operation of the device can be transferred to the semiconductor layer 140 faster, which is also beneficial to further improve the self-heating effect of the device.

Correspondingly, the present invention also provides a semiconductor structure. Continuing to refer to FIG. 9 , FIG. 9 is a schematic cross-sectional structural diagram of a secant along the extending direction of the fin (as shown in the X1X2 direction in FIG. 1 ), showing a schematic structural diagram of an embodiment of the semiconductor structure of the present invention.

The semiconductor structure includes: a base 100, including a substrate 110 and a discrete fin 120 located on the substrate 110, the material of the fin 120 is SiGe, Ge or III-V semiconductor material; The gate layer 220 of the fin 120, the gate layer 220 covers part of the top and part of the sidewall of the fin 120; the semiconductor layer 140 is located in the fin 120 on both sides of the gate layer 220, so The thermal conductivity of the material of the semiconductor layer 140 is greater than the thermal conductivity of the material of the fin 120, the bottom of the semiconductor layer 140 is in contact with the substrate 110, and the top of the semiconductor layer 140 is lower than the top of the fin 120; The source-drain doped layer 300 is located in the fin portion 120 on both sides of the gate layer 220 , and the bottom of the source-drain doped layer 300 is in contact with the top of the semiconductor layer 140 .

The substrate 110 is used to provide a process platform for the formation of the semiconductor structure.

In this embodiment, the semiconductor structure is a FinFET, and the fin 120 on the substrate 110 is used to provide a channel of the FinFET.

When the FinFET is a PMOS transistor, the material of the fin 120 is SiGe. By adopting the SiGe channel technology, it is beneficial to improve the performance of the PMOS transistor. In other embodiments, when the FinFET is a PMOS transistor, the material of the fin may also be Ge.

When the FinFET is an NMOS transistor, the material of the fin portion 120 is a III-V semiconductor material, which is beneficial to improve the performance of the NMOS transistor. In this embodiment, the III-V group semiconductor material is InGaAs. In other embodiments, the III-V group semiconductor material may also be InSb, GaSb, GaAs or InAs.

In this embodiment, the substrate 110 includes a bottom substrate 111 and a top substrate 112 on the bottom substrate 111 , the top substrate 112 is made of the same material as the fin portion 120 .

The bottom substrate 111 is used as an epitaxial buffer layer. Specifically, in the formation process of the semiconductor structure, the top substrate 112 and the fin portion 120 are formed by epitaxial growth, and the top substrate 112 and the fin portion 120 are formed by patterning the fin material layer Formed in a manner, that is, after the fin material layer is formed by means of epitaxial growth, after the fin material layer is patterned, the patterned remaining fin material layer is used as the top substrate 112, located on the top The protrusions on the substrate 112 serve as the fins 120 . In the initial stage of epitaxial growth, the quality of the fin material layer is poor, and the crystal lattice of the fin material layer will be complete only after it grows to a certain thickness. Therefore, through the bottom substrate 111, it is beneficial to The formation quality of the fin portion 120 is improved, thereby improving device performance.

Correspondingly, in this embodiment, the top substrate 112 and the fin portion 120 are integrally structured, and the material of the top substrate 112 is SiGe, Ge or III-V semiconductor material.

至

Therefore, the thickness T1 of the top substrate 112 (as shown in FIG. 2 ) should neither be too small nor too large. If the thickness T1 of the top substrate 112 is too small, it is difficult to ensure that the fins 120 have good quality; if the thickness T1 of the top substrate 112 is too large, when the thickness of the substrate 110 is constant , it will cause the thickness of the bottom substrate 111 to be too small, which will easily have a bad influence on the performance of the device. Therefore, in this embodiment, the thickness T1 of the top substrate 112 is

to

In this embodiment, the material of the bottom substrate 111 is silicon. In other embodiments, the bottom substrate can also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or gallium indium, and the bottom substrate can also be a silicon-on-insulator substrate or an on-insulator substrate. Ge substrates and other types of substrates.

It should also be noted that, in other embodiments, the substrate may only include the bottom substrate.

In this embodiment, the semiconductor structure further includes: an isolation structure 101 located on the substrate 110 exposed by the fin 120, the isolation structure 101 covers part of the sidewall of the fin 120, and the isolation structure 101 is lower than the top of the fin 120

The isolation structure 101 is used to isolate adjacent devices or adjacent fins 120 .

In this embodiment, the material of the isolation structure 101 is silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride.

The gate layer 220 is used to form the gate structure 200 .

In this embodiment, the gate structure 200 is a polysilicon gate structure, and the material of the gate layer 220 is polysilicon. In other embodiments, the material of the gate layer may also be other materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride or amorphous carbon.

In this embodiment, the gate structure 200 is a stacked structure, so the semiconductor structure further includes: a gate oxide layer 210 covering the surface of the fin 120 exposed by the isolation structure 101, the gate layer 220 and the The gate oxide layer 210 under the gate layer 220 constitutes the gate structure 200 .

In this embodiment, the gate oxide layer 210 is made of silicon oxide. In other embodiments, the material of the gate oxide layer may also be silicon oxynitride.

In other embodiments, the gate structure may also be a single-layer structure, that is, the gate structure only includes the gate layer.

In other embodiments, the gate structure may also be a metal gate structure, and the material of the gate layer is correspondingly a metal material, such as W, Al, Cu, Ag, Au, Pt, Ni or Ti.

It should be noted that, the semiconductor structure further includes: a gate mask layer 230 located on the top of the gate layer 220; a sidewall 250 located on the sidewall of the gate layer 220, and the sidewall 250 also covers The sidewall of the gate mask layer 230 .

The gate mask layer 230 is used as an etching mask for forming the gate layer 220 , and also protects sidewalls of the gate layer 220 during the formation of the semiconductor structure. In this embodiment, the material of the gate mask layer 230 is silicon nitride.

In this embodiment, the sidewall 250 is used as an etching mask in the etching process during the process of forming the source-drain doped layer 300, and is used to define the formation region of the source-drain doped layer 300 The sidewall 250 is also used as a PSR mask layer or an NSR mask layer, which can avoid epitaxial growth process on the sidewall of the fin 120 .

The material of the side wall 250 may be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride and boron carbonitride. The side wall 250 can be a single-layer structure or a laminated structure. In this embodiment, the sidewall 250 is a single-layer structure, and the material of the sidewall 250 is silicon nitride.

In the semiconductor process, the source-drain doped layer 300 is usually located in the part-thickness fins 120 on both sides of the gate layer 220 , and in this embodiment, the bottom of the semiconductor layer 140 is in contact with the substrate 110 , the top of the semiconductor layer 140 is in contact with the bottom of the source-drain doped layer 300, that is, the semiconductor layer 140 replaces the fin 120 below the source-drain doped layer 300; The thermal conductivity is greater than the thermal conductivity of the material of the fin 120. Therefore, after the material of the fin 120 below the source-drain doped layer 300 is replaced by a material with a higher thermal conductivity, it is beneficial to improve the heat dissipation performance of the device, thereby improving The self-heating effect of the device improves the performance of the device.

Wherein, the bottom of the semiconductor layer 140 is in contact with the substrate 110, which not only ensures that the heat generated during the operation of the device is dissipated through the semiconductor layer 140 and the bottom substrate 111, but also helps to ensure that the Good electrical performance of FinFET.

In addition, the semiconductor layer 140 is located below the source-drain doped layer 300, and the semiconductor layer 140 is closer to the channel region of the device, so the heat generated by the device can be transferred to the semiconductor layer 140 more quickly. Among them, it is also beneficial to further improve the self-heating effect of the device.

In this embodiment, the material of the top substrate 112 is the same as that of the fin portion 120 , so in order to significantly improve the self-heating effect of the device, the semiconductor layer 140 extends along the normal direction of the surface of the substrate 110 to the Inside the top substrate 112 , that is, the bottom of the semiconductor layer 140 is in contact with the bottom substrate 111 .

In this embodiment, the material of the semiconductor layer 140 is Si. The thermal conductivity of Si is 150W/M·K, and the thermal conductivity of Si is relatively high, so the self-heating effect of the device can be significantly improved; in addition, the Si material has good process compatibility, and the material of the semiconductor layer 140 is compatible with the The material of the bottom substrate 111 is the same, so by selecting Si as the material of the semiconductor layer 140 , it is also beneficial to reduce the adverse effect of the semiconductor layer 140 on the performance of the device.

In other embodiments, the material of the semiconductor layer may also be SiC. The thermal conductivity of SiC is 490W/M·K, and by using SiC as the material of the semiconductor layer, the self-heating effect of the device can also be significantly improved.

It should be noted that, in the semiconductor process, the source-drain doped layer 300 and the semiconductor layer 140 are usually formed in grooves on both sides of the gate layer 220, that is, the semiconductor layer is formed in the groove After 140, the source-drain doped layer 300 is formed in the remaining groove. Therefore, in this embodiment, the top of the semiconductor layer 140 is lower than the top of the fin 120, so as to form the source-drain doped layer 300 offers plenty of room.

The distance H (as shown in FIG. 7 ) from the top of the semiconductor layer 140 to the top of the fin 120 should not be too small, nor should it be too large. If the distance H is too small, the volume of the source-drain doped layer 300 will be too small, which will easily have a negative impact on the performance of the device, such as affecting the short channel control capability of the device; the semiconductor layer 140 is grown by epitaxy In the process of epitaxial growth, the crystal lattice will not be complete until the semiconductor layer 140 grows to a certain thickness. If the distance H is too large, that is, the thickness of the semiconductor layer 140 is too small, it is easy to cause the The quality of the semiconductor layer 140 deteriorates, thereby reducing the performance of the semiconductor layer 140 . Therefore, in this embodiment, the distance H from the top of the semiconductor layer 140 to the top of the fin 120 is to

Specifically, the fins 120 higher than the semiconductor layer 140 are used to form devices.

In this embodiment, the source-drain doped layer 300 includes a stress layer.

When the FinFET is a PMOS transistor, the material of the stress layer is Si or SiGe, and the dopant ions in the stress layer are P-type ions, such as B, Ga or In. The stress layer provides compressive stress to the channel region of the PMOS device, thereby improving the carrier mobility of the PMOS transistor.

When the FinFET is an NMOS transistor, the material of the stress layer is Si or SiC, and the dopant ions in the stress layer are N-type ions, such as P, As or Sb. The stress layer provides tensile stress for the channel region of the NMOS device, thereby improving the carrier mobility of the NMOS transistor.

In this embodiment, the top of the source-drain doped layer 300 is higher than the top of the fin portion 120 , and the source-drain doped layer 300 also covers part of the sidewall of the sidewall 250 . In other embodiments, according to actual process requirements, the top of the source-drain doped layer may also be flush with the top of the fin.

It should be noted that, the semiconductor structure further includes: a barrier layer 350, along a direction perpendicular to the sidewall of the gate layer 220, the barrier layer 350 is located between the sidewall of the semiconductor layer 140 and the substrate 100, and The top of the barrier layer 350 is in contact with the source-drain doped layer 300 .

In this embodiment, along the direction perpendicular to the sidewall of the gate layer 220, the barrier layer 350 is located between the sidewall of the semiconductor layer 140 and the fin 120, and between the sidewall of the semiconductor layer 140 and the top lining. Between bottom 112.

It can be seen from the foregoing analysis that the source-drain doped layer 300 and the semiconductor layer 140 are usually formed in the grooves on both sides of the gate layer 220, that is, after the semiconductor layer 140 is formed in the groove, the remaining The source-drain doped layer 300 is formed in the groove; through the barrier layer 350, it can be ensured that in the process of forming the semiconductor layer 140, only the material of the substrate 110 at the bottom of the groove is used as a seed layer, so that The semiconductor layer 140 can grow along the direction of the normal to the surface of the substrate 110, that is, to ensure that the growth direction of the semiconductor layer 140 is unidirectional, which is not only easy to control the thickness of the semiconductor layer 140, And compared with the solution in which the barrier layer grows at the bottom of the groove and the sidewall of the groove at the same time, it can also effectively reduce the probability of holes in the semiconductor layer 140, thereby improving the formation quality of the semiconductor layer 140 .

It should be noted that, in order to reduce the influence of the barrier layer 350 on device performance, the material of the barrier layer 350 is a dielectric material.

In this embodiment, the barrier layer 350 is made of silicon nitride. Silicon nitride has a high density, which can effectively prevent epitaxial growth on the sidewall of the groove, and silicon nitride is a commonly used dielectric material in the process, and has high process compatibility.

In other embodiments, the material of the barrier layer may also be silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbide boron nitride, or silicon oxycarbide.

至

其中，所述阻挡层350的厚度T2指的是：所述阻挡层350沿垂直于所述凹槽侧壁方向的尺寸。It should also be noted that the thickness T2 of the barrier layer 350 (as shown in FIG. 6 ) should not be too small or too large. If the thickness T2 of the barrier layer 350 is too small, the protection effect on the sidewall of the groove is poor, and during the process of forming the semiconductor layer 140, the probability of epitaxial growth on the sidewall of the groove becomes lower. High; if the thickness T2 of the barrier layer 350 is too large, not only will it cause waste of materials and time, but the barrier layer 350 will also occupy too much space in the groove, which is not conducive to the semiconductor layer 140 and The formation of the source-drain doped layer 300 is likely to degrade the performance of the device. Therefore, in this embodiment, the thickness T2 of the barrier layer 350 is

to

Wherein, the thickness T2 of the barrier layer 350 refers to: the dimension of the barrier layer 350 along a direction perpendicular to the sidewall of the groove.

The semiconductor structure may be formed using the forming methods described in the foregoing embodiments, or may be formed using other forming methods. For the specific description of the semiconductor structure described in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details are not repeated here.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (21)

1. A method for forming a semiconductor structure, comprising: providing a base, including a substrate and a discrete fin located on the substrate, the material of the fin is SiGe, Ge or III-V semiconductor material; forming a gate layer across the fin, the gate layer covering part of the top and part of the sidewall of the fin; forming grooves in the fins on both sides of the gate layer, the bottom of the grooves exposing the substrate; A semiconductor layer is formed in the groove, the thermal conductivity of the material of the semiconductor layer is greater than that of the fin material, the bottom of the semiconductor layer is in contact with the remaining substrate at the bottom of the groove, and the semiconductor layer the top of the layer is lower than the top of the fin; A source-drain doped layer is formed in the groove where the semiconductor layer is formed. 2. The method for forming a semiconductor structure according to claim 1, wherein the material of the semiconductor layer is Si or SiC. 3. The method for forming a semiconductor structure according to claim 1, wherein the III-V group semiconductor material is InSb, GaSb, GaAs, InAs or InGaAs. 4 . The method for forming a semiconductor structure according to claim 1 , wherein in the step of forming a semiconductor layer in the groove, the process for forming the semiconductor layer is a selective epitaxy process. 5. The method for forming a semiconductor structure according to claim 1, wherein in the step of providing a substrate, the substrate comprises a bottom substrate and a top substrate positioned on the bottom substrate, and the top substrate the base is of the same material as the fin; In the step of forming grooves in the fins on both sides of the gate layer, the grooves extend into the top substrate along the normal direction of the substrate surface, and the bottoms of the grooves expose the bottom substrate. 6 . The method for forming a semiconductor structure according to claim 5 , wherein the step of forming the groove comprises: etching the fins on both sides of the gate layer, and forming in the fins to expose the the first groove of the top substrate; Etching the top substrate along the first groove, forming a second groove exposing the bottom substrate in the top substrate, the top of the second groove is aligned with the first groove The bottom of the groove is connected, and the second groove and the first groove form the groove. 7. the formation method of semiconductor structure as claimed in claim 5 is characterized in that, the thickness of described top substrate is to

8 . The method for forming a semiconductor structure according to claim 1 , further comprising: after forming grooves in the fins on both sides of the gate layer and before forming a semiconductor layer in the grooves: A barrier layer is formed on the sidewall of the groove. 9. The method for forming a semiconductor structure according to claim 8, wherein in the step of forming a barrier layer on the sidewall of the groove, the thickness of the barrier layer is

to 10. The method for forming a semiconductor structure according to claim 8, wherein in the step of forming a barrier layer on the sidewall of the groove, the material of the barrier layer is silicon nitride, silicon oxide, nitrogen Silicon oxide, silicon oxycarbide, silicon carbonitride, silicon nitride boron carbide, or silicon oxycarbide. 11. The method for forming a semiconductor structure according to claim 8, wherein the barrier layer is formed by an atomic layer deposition process or a chemical vapor deposition process. 12. The method for forming a semiconductor structure according to claim 8, wherein after the semiconductor layer is formed in the groove, before the source-drain doped layer is formed in the groove in which the semiconductor layer is formed, further The method includes: removing the exposed barrier layer of the semiconductor layer. 13. The method for forming a semiconductor structure according to claim 12, wherein the step of removing the exposed barrier layer of the semiconductor layer comprises: using a dry etching process to etch and remove the barrier layer higher than the top of the semiconductor layer. barrier layer. 14. A semiconductor structure, characterized in that it comprises: a base, including a substrate and a discrete fin located on the substrate, the material of the fin is SiGe, Ge or III-V semiconductor material; a gate layer spanning the fin, the gate layer covering part of the top and part of the sidewall of the fin; a semiconductor layer located in the fins on both sides of the gate layer, the thermal conductivity of the material of the semiconductor layer is greater than the thermal conductivity of the material of the fins, the bottom of the semiconductor layer is in contact with the substrate, and the semiconductor layer the top of the layer is lower than the top of the fin; The source-drain doped layer is located in the fins on both sides of the gate layer, and the bottom of the source-drain doped layer is in contact with the top of the semiconductor layer. 15. The semiconductor structure according to claim 14, wherein the material of the semiconductor layer is Si or SiC. 16. The semiconductor structure according to claim 14, wherein the III-V group semiconductor material is InSb, GaSb, GaAs, InAs or InGaAs. 17. The semiconductor structure of claim 14, wherein the substrate comprises a bottom substrate and a top substrate on the bottom substrate, the top substrate being the same material as the fin ; The semiconductor layer extends into the top substrate along a normal direction of the substrate surface, and the bottom of the semiconductor layer is in contact with the bottom substrate. 18. The semiconductor structure of claim 17, wherein the top substrate has a thickness of

to

19. The semiconductor structure according to claim 14, wherein the semiconductor structure further comprises: a barrier layer, along a direction perpendicular to the sidewall of the gate layer, the barrier layer is located on the sidewall of the semiconductor layer and the substrate, and the top of the barrier layer is in contact with the source-drain doped layer. 20. The semiconductor structure according to claim 19, wherein the barrier layer has a thickness of to

21. The semiconductor structure according to claim 19, wherein the material of the barrier layer is silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbide boron nitride or nitrogen carbon silicon oxide.

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