CN110620089B - Power chip package structure - Google Patents
Power chip package structure Download PDFInfo
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- CN110620089B CN110620089B CN201910751779.3A CN201910751779A CN110620089B CN 110620089 B CN110620089 B CN 110620089B CN 201910751779 A CN201910751779 A CN 201910751779A CN 110620089 B CN110620089 B CN 110620089B
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- Prior art keywords
- heat dissipation
- power chip
- chip
- assembly
- heat
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/427—Cooling by change of state, e.g. use of heat pipes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Electrical Apparatus (AREA)
Abstract
本发明公开了一种电源芯片封装结构，包括散热组件、电源芯片固定组件、底板，所述电源芯片固定组件安装在所述底板上端，所述散热组件包括第一散热组件、第二散热组件，所述电源芯片固定组件与底板之间安装有第二散热组件，所述电源芯片固定组件上端安装有第一散热组件。本发明通过散热组件对芯片上下两端面进行散热，通过散热片吸收芯片产生的热量，并通过散热片增加散热面积，利用散热管将热量平均分散到散热片上，增加散热效率，通过在芯片引脚折弯处设置支撑块对芯片引脚支撑，在芯片引脚处开设通孔，配合限流槽，对溶化后的焊锡起到引流的作用，防止引脚间的焊锡互相接触，导致芯片短路。
The invention discloses a power supply chip packaging structure, comprising a heat dissipation component, a power supply chip fixing component and a bottom plate, the power supply chip fixing component is mounted on the upper end of the bottom plate, and the heat dissipation component includes a first heat dissipation component and a second heat dissipation component, A second heat dissipation assembly is installed between the power chip fixing assembly and the bottom plate, and a first heat dissipation assembly is installed on the upper end of the power chip fixing assembly. The invention dissipates heat on the upper and lower ends of the chip through heat dissipation components, absorbs the heat generated by the chip through the heat sink, increases the heat dissipation area through the heat sink, and uses the heat dissipation pipe to evenly disperse the heat on the heat sink to increase the heat dissipation efficiency. A support block is arranged at the bend to support the chip pins, through holes are opened at the chip pins, and the current limiting grooves are used to drain the melted solder, preventing the solder between the pins from contacting each other and causing the chip to short circuit.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to a power supply chip packaging structure.
Background
The chip package is a shell for mounting semiconductor integrated circuit chip, and plays the role of placing, fixing, sealing, protecting chip and enhancing electrothermal property, and is also a bridge for communicating the internal world of chip with external circuit, i.e. the connection points on chip are connected to the pins of package shell by means of conducting wires, these pins are connected with other devices by means of conducting wires on printed board, so that the package plays an important role for CPU and other LSI integrated circuits, because the development direction of integrated circuit is miniaturized and miniaturized, the heat productivity of chip is large, at the same time, because the chip area is small, the heat productivity is concentrated, the chip is seriously heated and damaged, and because the chip pins are thin wire-like or flat metal, under the action of external force, the chip is easy to bend, the deformation is large, and the pins are separated from the bonding pad, thereby causing the hidden trouble of false soldering or desoldering, meanwhile, the chip pins are densely distributed, so that the chip is in short circuit risk due to adhesion of welding wires during welding.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art. Therefore, an object of the present invention is to provide a power chip package structure, which increases heat dissipation of a chip, supports pins, and increases a solder draining function.
The power chip packaging structure comprises a heat dissipation assembly, a power chip fixing assembly and a bottom plate, wherein the power chip fixing assembly is installed at the upper end of the bottom plate and comprises a first heat dissipation assembly and a second heat dissipation assembly, the second heat dissipation assembly is installed between the power chip fixing assembly and the bottom plate, and the first heat dissipation assembly is installed at the upper end of the power chip fixing assembly.
Preferably, first radiator unit includes fin, mounting panel, shrouding, cooling tube, the fin both ends set up the mounting panel, the mounting groove has been seted up on the mounting panel, the fin passes through the mounting groove with the mounting panel is fixed, the mounting panel is kept away from one side of fin still is provided with the shrouding, the seal groove has been seted up on the shrouding, the mounting panel is installed seal inslot portion, the mounting hole has still been seted up on the fin surface, the cooling tube is installed inside the mounting hole, first radiator unit with the second radiator unit structure is the same.
Preferably, the power chip fixing component comprises pins, a power chip, packaging resin and a substrate, the power chip is arranged at the upper end of the substrate, the pins are further installed between the power chip and the substrate, the power chip is fixed with the substrate through a bonding material, the pins are connected with the power chip through electric signals of wires, and the periphery of the power chip is provided with the packaging resin for packaging the power chip.
Preferably, the bottom plate is provided with a supporting block corresponding to the bending part of the pin, and the supporting block is fixedly installed with the bottom plate.
Preferably, the bottom plate is provided with a flow limiting groove corresponding to the pin welding part, and the flow limiting groove and the supporting block are fixedly installed.
Preferably, the flow limiting groove is of a rectangular table structure, and the area of the end face of the bottom of the flow limiting groove is smaller than that of the upper end face.
Preferably, the pin welding part is further provided with a flow guide hole.
Preferably, the upper end face of the power chip fixing component is further provided with a positioning hole for positioning.
According to the invention, the upper end face and the lower end face of the chip are radiated by the radiating assembly, the heat generated by the chip is absorbed by the radiating fins, the radiating area is increased by the radiating fins, the heat is averagely dispersed onto the radiating fins by the radiating tubes, the radiating efficiency is increased, the chip pins are supported by arranging the supporting blocks at the bending positions of the chip pins, the chip pins are prevented from being seriously deformed to cause chip insufficient soldering and desoldering, the through holes are formed at the chip pins, and the through holes are matched with the current limiting grooves to play a role in draining molten soldering tin, so that the soldering tin between the pins is prevented from contacting with each other.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic structural diagram of a power chip package structure according to the present invention;
FIG. 2 is a schematic structural diagram of a power chip mounting assembly according to the present invention;
fig. 3 is a cross-sectional view of a power chip fixing assembly according to the present invention;
fig. 4 is a schematic structural view of a heat dissipation bottom plate portion according to the present invention;
fig. 5 is a schematic structural diagram of a heat dissipation assembly according to the present invention.
In the figure: 1-a first heat dissipation component, 2-a power supply chip fixing component, 3-pins, 4-a second heat dissipation component, 5-a bottom plate, 6-a supporting block, 7-a flow limiting groove, 8-a power supply chip, 9-packaging resin, 10-a bonding material, 11-a substrate, 12-a sealing groove, 13-a mounting groove, 14-a heat dissipation sheet, 15-a mounting plate, 16-a sealing plate, 17-a mounting hole, 18-a heat dissipation tube and 31-a flow guide hole.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
Examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Referring to fig. 1-5, a power chip packaging structure comprises a heat dissipation assembly, a power chip fixing assembly 2 and a bottom plate 5, wherein the power chip fixing assembly 2 is installed at the upper end of the bottom plate 5, the heat dissipation assembly comprises a first heat dissipation assembly 1 and a second heat dissipation assembly 4, insulating paint is coated outside the heat dissipation assembly, the second heat dissipation assembly 4 is installed between the power chip fixing assembly 2 and the bottom plate 5, and the first heat dissipation assembly 1 is installed at the upper end of the power chip fixing assembly 2; the first heat dissipation assembly 1 comprises a heat dissipation fin 14, a mounting plate 15, a sealing plate 16 and a heat dissipation pipe 18, wherein the mounting plate 15 is arranged at two ends of the heat dissipation fin 14, the mounting plate 15 is provided with a mounting groove 13, the heat dissipation fin 14 is fixed with the mounting plate 15 through the mounting groove 13, the sealing plate 16 is further arranged at one side, away from the heat dissipation fin 14, of the mounting plate 15, a sealing groove 12 is formed in the sealing plate 16, the mounting plate 15 is arranged inside the sealing groove 12, a mounting hole 17 is further formed in the surface of the heat dissipation fin 14, the heat dissipation pipe 18 is arranged inside the mounting hole; the power chip fixing assembly 2 comprises a pin 3, a power chip 8, packaging resin 9 and a substrate 11, wherein the power chip 8 is arranged at the upper end of the substrate 11, the pin 3 is further arranged between the power chip 8 and the substrate 11, the power chip 8 and the substrate 11 are fixed through a bonding material 10, the pin 3 and the power chip 8 are in electric signal connection through a wire, and the packaging resin 8 for packaging the power chip 8 is arranged on the periphery of the power chip 8; a supporting block 6 is arranged at the bending part of the bottom plate 5 corresponding to the pin 3, and the supporting block 6 and the bottom plate 5 are fixedly installed; a current limiting groove 7 is arranged at the welding position of the bottom plate 5 corresponding to the pin 3, and the current limiting groove 7 and the supporting block 6 are fixedly installed; the flow-limiting groove 7 is of a rectangular platform structure, and the area of the bottom end surface of the flow-limiting groove 7 is smaller than that of the upper end surface; and a diversion hole 31 is also formed at the welding position of the pin 3.
During operation, pass through welded fastening with this power chip packaging structure and PCB board, the installation orientation of chip is confirmed through the locating hole of the fixed subassembly 2 up end of power chip, correspond current-limiting groove 7 and the chip pad position on the PCB board, soldering tin melts the back, current-limiting groove 7 and 3 last water conservancy diversion holes 31 of pin are with soldering tin to 3 upper portions water conservancy diversion of pin, adhesion about preventing soldering tin, support the pin through current-limiting groove 7 and supporting shoe 6 simultaneously, prevent the excessive skew of pin, lead to the chip to have the risk of desoldering and rosin joint, the first radiator unit 1 and the second radiator unit 4 that the both ends face set up about the fixed subassembly 2 of power chip dispel the heat to the chip jointly.
To sum up, this power chip packaging structure dispels the heat through radiator unit to both ends face about the chip, absorb the heat that the chip produced through the fin, and increase heat radiating area through the fin, utilize the cooling tube with the heat on average dispersion to the fin, increase the radiating efficiency, support the chip pin through set up the supporting shoe in the department of bending at the chip pin, prevent that the chip pin from seriously warping, cause chip rosin joint and desoldering, set up the through-hole in chip pin department, cooperation limit chute, the effect of drainage is played to the soldering tin after dissolving, prevent that the soldering tin between the pin from contacting each other, lead to the chip short circuit.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and the technical solutions and the inventive concepts thereof according to the present invention should be equivalent or changed within the scope of the present invention.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910751779.3A CN110620089B (en) | 2019-08-15 | 2019-08-15 | Power chip package structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910751779.3A CN110620089B (en) | 2019-08-15 | 2019-08-15 | Power chip package structure |
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| CN110620089A CN110620089A (en) | 2019-12-27 |
| CN110620089B true CN110620089B (en) | 2021-06-22 |
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| CN201910751779.3A Active CN110620089B (en) | 2019-08-15 | 2019-08-15 | Power chip package structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111799236B (en) * | 2020-07-28 | 2022-08-16 | 深圳市航泽电子有限公司 | Chip packaging structure and packaging method for integrated passive element |
| CN117116872A (en) * | 2023-07-13 | 2023-11-24 | 深圳市金誉半导体股份有限公司 | Packaging structure of semiconductor device and manufacturing method |
Citations (3)
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| CN207542232U (en) * | 2017-11-28 | 2018-06-26 | 深圳市鑫宇鹏电子科技有限公司 | A kind of encapsulating structure of IC chip |
| CN208208748U (en) * | 2018-05-08 | 2018-12-07 | 宁波市鄞州路麦电子有限公司 | A kind of radiating lead frame |
| CN208985979U (en) * | 2018-11-06 | 2019-06-14 | 泰州友润电子科技股份有限公司 | A kind of novel total incapsulation TO-220MFK1 lead frame |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6703707B1 (en) * | 1999-11-24 | 2004-03-09 | Denso Corporation | Semiconductor device having radiation structure |
| JP5324773B2 (en) * | 2007-11-06 | 2013-10-23 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Circuit module and manufacturing method thereof |
| CN101826492B (en) * | 2010-04-29 | 2012-11-28 | 南通富士通微电子股份有限公司 | Chip-suspension-type packaging heat dissipation improved structure of semiconductor |
| CN201766069U (en) * | 2010-04-29 | 2011-03-16 | 南通富士通微电子股份有限公司 | Chip suspension type semiconductor packaging and radiating improved structure |
| CN108882504B (en) * | 2018-07-05 | 2023-11-21 | 深德彩科技(深圳)股份有限公司 | Heat dissipation device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN207542232U (en) * | 2017-11-28 | 2018-06-26 | 深圳市鑫宇鹏电子科技有限公司 | A kind of encapsulating structure of IC chip |
| CN208208748U (en) * | 2018-05-08 | 2018-12-07 | 宁波市鄞州路麦电子有限公司 | A kind of radiating lead frame |
| CN208985979U (en) * | 2018-11-06 | 2019-06-14 | 泰州友润电子科技股份有限公司 | A kind of novel total incapsulation TO-220MFK1 lead frame |
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| CN110620089A (en) | 2019-12-27 |
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Effective date of registration: 20250827 Address after: 230000 Anhui Province Hefei City Luyang Industrial Park Guantang Road 12# Patentee after: HEFEI HEJING ELECTRONIC Co.,Ltd. Country or region after: China Address before: 230601 Anhui city of Hefei Province Economic and Technological Development Zone prosperous Avenue and Xiyou Road intersection Patentee before: ANHUI GUOJING MICROELECTRONICS CO.,LTD. Country or region before: China |
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