CN110534509A - Semiconductor Power Devices - Google Patents
Semiconductor Power Devices Download PDFInfo
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- CN110534509A CN110534509A CN201810506071.7A CN201810506071A CN110534509A CN 110534509 A CN110534509 A CN 110534509A CN 201810506071 A CN201810506071 A CN 201810506071A CN 110534509 A CN110534509 A CN 110534509A
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- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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- H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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Abstract
本发明属于半导体功率器件技术领域，具体公开了一种半导体功率器件，包括MOSFET功率器件芯片和IGBT功率器件芯片；所述MOSFET功率器件芯片和所述IGBT功率器件芯片封装在同一个封装体内，其中：所述MOSFET功率器件芯片的源极与所述IGBT功率器件芯片的发射极均接所述封装体的源极引脚；所述MOSFET功率器件芯片的漏极与所述IGBT功率器件芯片的集电极均接所述封装体的漏极引脚；所述MOSFET功率器件芯片的栅极与所述IGBT功率器件芯片的栅极均接所述封装体的栅极引脚。本发明提供的半导体功率器件能够降低半导体功率器件的通态损耗，提高系统效率。
The invention belongs to the technical field of semiconductor power devices, and specifically discloses a semiconductor power device, comprising a MOSFET power device chip and an IGBT power device chip; the MOSFET power device chip and the IGBT power device chip are packaged in the same package, wherein : the source of the MOSFET power device chip and the emitter of the IGBT power device chip are connected to the source pin of the package body; the drain of the MOSFET power device chip and the collection of the IGBT power device chip The electrodes are both connected to the drain pins of the package body; the gates of the MOSFET power device chip and the IGBT power device chips are both connected to the gate pins of the package body. The semiconductor power device provided by the invention can reduce the on-state loss of the semiconductor power device and improve the system efficiency.
Description
技术领域technical field
本发明属于半导体功率器件技术领域，特别是涉及一种低电阻-温度系数的半导体功率器件。The invention belongs to the technical field of semiconductor power devices, in particular to a semiconductor power device with a low resistance-temperature coefficient.
背景技术Background technique
随着新能源和高效节能产业的不断发展，对低功耗的MOSFET功率器件的要求越来越高，对单颗MOSFET功率器件芯片的电流处理能力的要求也越来越大，而MOSFET功率器件芯片可以处理的电流密度相对较小。同时，MOSFET功率器件具有比较大的电阻-温度系数，MOSFET功率器件的导通电阻随着温度的增加而迅速增大，这极大的增加了MOSFET功率器件的通态损耗，降低了系统效率。With the continuous development of new energy and high-efficiency energy-saving industries, the requirements for low-power MOSFET power devices are getting higher and higher, and the requirements for the current handling capability of a single MOSFET power device chip are also increasing. The current density the chip can handle is relatively small. At the same time, the MOSFET power device has a relatively large resistance-temperature coefficient, and the on-resistance of the MOSFET power device increases rapidly with the increase of temperature, which greatly increases the on-state loss of the MOSFET power device and reduces the system efficiency.
发明内容SUMMARY OF THE INVENTION
有鉴于此，本发明的目的是提供一种半导体功率器件，以解决现有技术中的MOSFET功率器件的通态损耗高以及进一步提升MOSFET功率器件可处理的电流密度的问题。In view of this, the purpose of the present invention is to provide a semiconductor power device to solve the problems of high on-state loss of the MOSFET power device in the prior art and to further improve the current density that the MOSFET power device can handle.
为达到本发明的上述目的，本发明提供了一种半导体功率器件，包括：In order to achieve the above-mentioned object of the present invention, the present invention provides a semiconductor power device, comprising:
MOSFET功率器件芯片和IGBT功率器件芯片；MOSFET power device chips and IGBT power device chips;
所述MOSFET功率器件芯片和所述IGBT功率器件芯片封装在同一个封装体内，其中：The MOSFET power device chip and the IGBT power device chip are packaged in the same package, wherein:
所述MOSFET功率器件芯片的源极与所述IGBT功率器件芯片的发射极均接所述封装体的源极引脚；The source of the MOSFET power device chip and the emitter of the IGBT power device chip are both connected to the source pin of the package;
所述MOSFET功率器件芯片的漏极与所述IGBT功率器件芯片的集电极均接所述封装体的漏极引脚；The drain of the MOSFET power device chip and the collector of the IGBT power device chip are both connected to the drain pin of the package;
所述MOSFET功率器件芯片的栅极与所述IGBT功率器件芯片的栅极均接所述封装体的栅极引脚。The gate of the MOSFET power device chip and the gate of the IGBT power device chip are both connected to the gate pin of the package.
可选的，所述IGBT功率器件芯片为沟槽栅结构的IGBT功率晶体管。Optionally, the IGBT power device chip is an IGBT power transistor with a trench gate structure.
可选的，所述IGBT功率器件芯片为平面栅结构的IGBT功率晶体管。Optionally, the IGBT power device chip is an IGBT power transistor with a planar gate structure.
可选的，所述IGBT功率器件芯片具有负的电阻-温度系数。Optionally, the IGBT power device chip has a negative resistance-temperature coefficient.
可选的，所述MOSFET功率器件芯片为垂直双扩散金属-氧化物半导体场效应晶体管。Optionally, the MOSFET power device chip is a vertical double-diffused metal-oxide semiconductor field effect transistor.
可选的，所述MOSFET功率器件芯片为超级结结构的功率晶体管。Optionally, the MOSFET power device chip is a power transistor with a super junction structure.
本发明提供的一种半导体功率器件由MOSFET功率器件芯片和IGBT功率器件芯片并联后封装在同一个封装体内，使得半导体功率器件的电阻随温度上升的电阻-温度系数低，能够降低半导体功率器件的通态损耗，提高系统效率，特别适合应用于大电流、大功率及高温下的系统。The semiconductor power device provided by the present invention consists of a MOSFET power device chip and an IGBT power device chip in parallel and then packaged in the same package, so that the resistance-temperature coefficient of the resistance of the semiconductor power device rising with temperature is low, and the resistance of the semiconductor power device can be reduced. On-state loss, improve system efficiency, especially suitable for systems with high current, high power and high temperature.
附图说明Description of drawings
为了更加清楚地说明本发明示例性实施例的技术方案，下面对描述实施例中所需要用到的附图做一简单介绍。显然，所介绍的附图只是本发明所要描述的一部分实施例的附图，而不是全部的附图，对于本领域普通技术人员，在不付出创造性劳动的前提下，还可以根据这些附图得到其他的附图。In order to illustrate the technical solutions of the exemplary embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings used in describing the embodiments. Obviously, the introduced drawings are only a part of the drawings of the embodiments to be described in the present invention, rather than all drawings. For those of ordinary skill in the art, without creative work, they can also obtain the drawings according to these drawings. Additional drawings.
图1是本发明提供的一种半导体功率器件中的MOSFET功率器件芯片和IGBT功率器件芯片封装在同一个封装体内的内部结构示意图；1 is a schematic diagram of the internal structure of a semiconductor power device provided by the present invention in which a MOSFET power device chip and an IGBT power device chip are packaged in the same package;
图2是本发明提供的一种半导体功率器件的等效电路示意图；2 is a schematic diagram of an equivalent circuit of a semiconductor power device provided by the present invention;
图3是现有技术的一种MOSFET功率器件的输出特性曲线图；Fig. 3 is the output characteristic curve diagram of a kind of MOSFET power device of the prior art;
图4是现有技术的一种IGBT功率器件的输出特性曲线图；Fig. 4 is the output characteristic curve diagram of a kind of IGBT power device of the prior art;
图5是本发明提供的一种半导体功率器件的输出特性曲线图。FIG. 5 is an output characteristic curve diagram of a semiconductor power device provided by the present invention.
具体实施方式Detailed ways
为使本发明的目的、技术方案和优点更加清楚，以下将结合本发明实施例中的附图，通过具体方式，完整地描述本发明的技术方案。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例，基于本发明的实施例，本领域普通技术人员在没有做出创造性劳动的前提下获得的所有其他实施例，均落入本发明的保护范围之内。In order to make the objectives, technical solutions and advantages of the present invention clearer, the following will fully describe the technical solutions of the present invention in specific ways with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are a part of the embodiments of the present invention, rather than all the embodiments, based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work, All fall within the protection scope of the present invention.
应当理解，本发明所使用的诸如“具有”、“包含”以及“包括”等术语并不配出一个或多个其它元件或其组合的存在或添加。说明书附图是示意性的，不应限定本发明的范围。It should be understood that terms such as "having", "comprising" and "including" used herein do not assign the presence or addition of one or more other elements or combinations thereof. The drawings in the description are schematic and should not limit the scope of the invention.
图1是本发明提供的一种半导体功率器件中的MOSFET功率器件芯片和IGBT功率器件芯片封装在同一个封装体内的内部结构示意图，图1中仅示例性的示出了MOSFET功率器件芯片50和IGBT功率器件芯片60封装在同一个封装体内的打线结构示意图，如图1所示，本发明提供的一种半导体功率器件中：MOSFET功率器件芯片50的源极(源极pad层)51与IGBT功率器件芯片60的发射极(发射极pad层)61均通过源极金属导线71接封装体的源极引脚81；MOSFET功率器件芯片50的漏极与IGBT功率器件芯片60的集电极均接封装体的漏极引脚82(MOSFET功率器件芯片50的漏极金属层与IGBT功率器件芯片60的集电极金属层均是位于其芯片的背面，从而均与封装体中的金属框架直接接触接漏极引脚82，而不需要打线)；MOSFET功率器件芯片50的栅极(栅极pad层)53与IGBT功率器件芯片60的栅极(栅极pad层)63均通过栅极金属导线73接封装体的栅极引脚83。1 is a schematic diagram of the internal structure of a semiconductor power device provided by the present invention in which a MOSFET power device chip and an IGBT power device chip are packaged in the same package. FIG. 1 only exemplarily shows the MOSFET power device chip 50 and A schematic diagram of a wire bonding structure in which the IGBT power device chip 60 is packaged in the same package, as shown in FIG. 1 , in a semiconductor power device provided by the present invention: the source (source pad layer) 51 of the MOSFET power device chip 50 and the The emitter (emitter pad layer) 61 of the IGBT power device chip 60 is connected to the source pin 81 of the package body through the source metal wire 71; the drain of the MOSFET power device chip 50 and the collector of the IGBT power device chip 60 are both The drain pin 82 of the package body (the drain metal layer of the MOSFET power device chip 50 and the collector metal layer of the IGBT power device chip 60 are both located on the back of the chip, so that they are both in direct contact with the metal frame in the package body. The gate (gate pad layer) 53 of the MOSFET power device chip 50 and the gate (gate pad layer) 63 of the IGBT power device chip 60 pass through the gate metal The wires 73 are connected to the gate pins 83 of the package.
需要说明的是，图1中的MOSFET功率器件芯片50和IGBT功率器件芯片60仅是示例性的结构，根据不同的设计要求，MOSFET功率器件芯片50和IGBT功率器件芯片60均可以有不同的芯片尺寸和耐压，也可以均有不同的pad层形状或结构。此外，MOSFET功率器件芯片50和IGBT功率器件芯片60也都可以内置栅极电阻。It should be noted that the MOSFET power device chip 50 and the IGBT power device chip 60 in FIG. 1 are only exemplary structures. According to different design requirements, the MOSFET power device chip 50 and the IGBT power device chip 60 may have different chips. The size and pressure resistance can also have different pad layer shapes or structures. In addition, both the MOSFET power device chip 50 and the IGBT power device chip 60 may have built-in gate resistors.
本发明的一种半导体功率器件中的MOSFET功率器件芯片可以是超级结结构的功率晶体管，也可以是垂直双扩散金属-氧化物半导体场效应晶体管。IGBT功率器件芯片可以是沟槽栅结构的IGBT功率晶体管，也可以是平面栅结构的IGBT功率晶体管。本发明对MOSFET功率器件芯片和IGBT功率器件芯片的类型及结构不作限制。The MOSFET power device chip in the semiconductor power device of the present invention may be a power transistor with a super junction structure, or may be a vertical double-diffused metal-oxide semiconductor field effect transistor. The IGBT power device chip may be an IGBT power transistor with a trench gate structure or an IGBT power transistor with a planar gate structure. The present invention does not limit the type and structure of the MOSFET power device chip and the IGBT power device chip.
图2是本发明提供的一种半导体功率器件的等效电路示意图，如图2所示，本发明的一种半导体功率器件的等效电路包括MOSFET功率器件202和IGBT功率器件101，其中：MOSFET功率器件202的源极21与IGBT功率器件101的发射极11连接并接入源极电压31；MOSFET功率器件202的漏极22与IGBT功率器件101的集电极12连接并接入漏极电压32；MOSFET功率器件202的栅极23与IGBT功率器件101的栅极13连接并接入栅极电压33。FIG. 2 is a schematic diagram of an equivalent circuit of a semiconductor power device provided by the present invention. As shown in FIG. 2, the equivalent circuit of a semiconductor power device of the present invention includes a MOSFET power device 202 and an IGBT power device 101, wherein: MOSFET The source 21 of the power device 202 is connected to the emitter 11 of the IGBT power device 101 and connected to the source voltage 31; the drain 22 of the MOSFET power device 202 is connected to the collector 12 of the IGBT power device 101 and connected to the drain voltage 32 ; The gate 23 of the MOSFET power device 202 is connected to the gate 13 of the IGBT power device 101 and connected to the gate voltage 33 .
可选的，本发明的一种半导体功率器件中的IGBT功率器件芯片具有负的电阻-温度系数，以尽可能地抵消MOSFET功率器件芯片的正的电阻-温度系数，进一步降低半导体功率器件在高温下的通态损耗。Optionally, the IGBT power device chip in a semiconductor power device of the present invention has a negative resistance-temperature coefficient, so as to offset the positive resistance-temperature coefficient of the MOSFET power device chip as much as possible, and further reduce the high temperature of the semiconductor power device. on-state loss.
本发明的一种半导体功率器件中的MOSFET功率器件芯片和IGBT功率器件芯片属于并联的结构，由于IGBT功率器件芯片具有较小的甚至是负的电阻-温度系数，这可以降低或者抵消MOSFET功率器件芯片的正的电阻-温度系数，从而使得本发明的半导体功率器件具有低的电阻-温度系数，进而能够降低半导体功率器件在高温下的通态损耗，提高系统效率，特别适合应用于大电流、大功率及高温下的系统。In a semiconductor power device of the present invention, the MOSFET power device chip and the IGBT power device chip belong to a parallel structure. Since the IGBT power device chip has a small or even negative resistance-temperature coefficient, this can reduce or offset the MOSFET power device. The positive resistance-temperature coefficient of the chip enables the semiconductor power device of the present invention to have a low resistance-temperature coefficient, thereby reducing the on-state loss of the semiconductor power device at high temperature and improving the system efficiency, and is especially suitable for high current, Systems under high power and high temperature.
本发明的一种半导体功率器件，当漏源电压Vds较小时，半导体功率器件的电流主要从MOSFET功率器件芯片中流过，当漏源电压Vds增大时，流过IGBT功率器件芯片的电流也会增大，随着漏源电压Vds的继续增大，流过IGBT功率器件芯片的电流可以等于或者大于流过MOSFET功率器件芯片的电流。由于本发明的半导体功率器件的电流是由流过MOSFET功率器件芯片的电流和IGBT功率器件芯片的电流组成的，而IGBT功率器件芯片可以处理的电流密度往往大于MOSFET功率器件芯片可以处理的电流密度，因此，本发明提出的半导体功率器件可以处理的电流密度大于传统MOSFET功率器件可以处理的电流密度。同时，MOSFET功率器件芯片在较低的漏源电压Vds时就可以实现比IGBT功率器件芯片小的多的导通电阻，因此，本发明提出的半导体功率器件可以实现比传统的IGBT功率器件小得多的饱和导通压降。In a semiconductor power device of the present invention, when the drain-source voltage Vds is small, the current of the semiconductor power device mainly flows through the MOSFET power device chip, and when the drain-source voltage Vds increases, the current flowing through the IGBT power device chip will also As the drain-source voltage Vds continues to increase, the current flowing through the IGBT power device chip may be equal to or greater than the current flowing through the MOSFET power device chip. Since the current of the semiconductor power device of the present invention is composed of the current flowing through the MOSFET power device chip and the current of the IGBT power device chip, the current density that the IGBT power device chip can handle is often larger than the current density that the MOSFET power device chip can handle. , therefore, the current density that can be handled by the semiconductor power device proposed by the present invention is greater than the current density that can be handled by a conventional MOSFET power device. At the same time, the MOSFET power device chip can achieve much smaller on-resistance than the IGBT power device chip when the drain-source voltage Vds is lower. Therefore, the semiconductor power device proposed by the present invention can achieve a much smaller on-resistance than the traditional IGBT power device. more saturated turn-on voltage drop.
图3是现有技术的一种MOSFET功率器件的输出特性曲线图，图4是现有技术的一种IGBT功率器件的输出特性曲线图，图5是本发明提供的一种半导体功率器件的输出特性曲线图。示例性的，图3中的MOSFET功率器件选用的是苏州东微半导体有限公司的OSG60R074HSZ产品进行测试得到输出特性曲线图，图4中的IGBT功率器件选用的是英飞凌有限公司的IGW60N60H产品进行测试得到的输出特性曲线图，图5是将OSG60R074HSZ产品和IGW60N60H产品并联后进行测试得到的输出特性曲线图。由图3、图4和图5可知，将MOSFET功率器件芯片和IGBT功率器件芯片并联后的半导体功率器件，其可以处理的电流密度大于MOSFET功率器件可以处理的电流密度，且其饱和导通压降小于IGBT功率器件的饱和导通压降。另外，将MOSFET功率器件芯片和IGBT功率器件芯片封装在同一个封装体内，可以简化应用电路板的设计。3 is an output characteristic curve diagram of a MOSFET power device in the prior art, FIG. 4 is an output characteristic curve diagram of an IGBT power device in the prior art, and FIG. 5 is an output characteristic curve diagram of a semiconductor power device provided by the present invention characteristic curve. Exemplarily, the MOSFET power device in Figure 3 is selected from the OSG60R074HSZ product of Suzhou Dongwei Semiconductor Co., Ltd. for testing to obtain an output characteristic curve diagram, and the IGBT power device in Figure 4 is selected from the Infineon Co., Ltd. IGW60N60H product is used for testing. The output characteristic curve obtained by the test, Figure 5 is the output characteristic curve obtained by testing the OSG60R074HSZ product and the IGW60N60H product in parallel. It can be seen from Figure 3, Figure 4 and Figure 5 that the semiconductor power device after connecting the MOSFET power device chip and the IGBT power device chip in parallel can handle a current density greater than that of the MOSFET power device, and its saturated on-voltage The drop is smaller than the saturated turn-on voltage drop of the IGBT power device. In addition, the MOSFET power device chip and the IGBT power device chip are packaged in the same package, which can simplify the design of the application circuit board.
以上具体实施方式及实施例是对本发明提出的一种半导体功率器件的技术思想的具体支持，不能以此限定本发明的保护范围，凡是按照本发明提出的技术思想，在本技术方案基础上所做的任何等同变化或等效的改动，均仍属于本发明技术方案保护的范围。The above specific embodiments and examples are specific support for the technical idea of a semiconductor power device proposed by the present invention, and cannot limit the protection scope of the present invention. Any equivalent changes or equivalent modifications made still fall within the protection scope of the technical solutions of the present invention.
尽管本发明的实施方案已公开如上，但其并不仅仅限于说明书和实施方式中所列运用，它完全可以被适用于各种适合本发明的领域，对于熟悉本领域的人员而言，可容易地实现另外的修改，因此在不背离权利要求及等同范围所限定的一般概念下，本发明并不限于特定的细节和这里示出与描述的图例。Although the embodiment of the present invention has been disclosed as above, it is not limited to the application listed in the description and the embodiment, and it can be applied to various fields suitable for the present invention. For those skilled in the art, it can be easily Therefore, the invention is not limited to the specific details and illustrations shown and described herein without departing from the general concept defined by the appended claims and the scope of equivalents.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120299108A1 (en) * | 2010-01-29 | 2012-11-29 | Fuji Electric Co., Ltd. | Semiconductor device |
| CN103703566A (en) * | 2011-08-02 | 2014-04-02 | 罗姆股份有限公司 | Semiconductor device, and manufacturing method for same |
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| US7960997B2 (en) * | 2007-08-08 | 2011-06-14 | Advanced Analogic Technologies, Inc. | Cascode current sensor for discrete power semiconductor devices |
| JP6402591B2 (en) * | 2014-10-31 | 2018-10-10 | 富士電機株式会社 | Semiconductor device |
| DE102015223470A1 (en) * | 2015-11-26 | 2017-06-01 | Robert Bosch Gmbh | Semiconductor device having a substrate and a first temperature measuring element and method for determining a current flowing through a semiconductor device and current control device for a vehicle |
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