CN119959736A - A chip testing method and chip - Google Patents

Abstract

The present application discloses a chip testing method and a chip, wherein the chip comprises a plurality of logic circuit modules, each logic circuit module is provided with a corresponding built-in self-test unit, the chip further comprises a test control unit for controlling each built-in self-test unit, the chip corresponds to a test program, the test program has test instructions, the test instructions comprise test microinstructions and functional microinstructions correspondingly provided for each logic circuit module, the test microinstructions are used to perform functional tests on the corresponding logic circuit modules, and the functional microinstructions are used to control the corresponding logic circuit modules to perform specific operations and/or function implementations, the testing method comprises: determining an idle period during which each logic circuit module does not respond to the functional microinstructions; during the idle period of the logic circuit module, running the associated test microinstructions through the corresponding built-in self-test unit and obtaining corresponding test data; and comparing the test data with the stored standard data to determine the target test result corresponding to the logic circuit module.

Description

Chip testing method and chip

Technical Field

The present application relates to the field of chip design and testing, and in particular, to a chip testing method and a chip.

Background

The chip comprises a plurality of logic circuit modules with respective functions, such as a vector operation unit, a floating point operation unit, a decoding unit, a memory access unit and the like. In order to ensure high safety and high reliability of the chip, the chip needs to be tested, including testing each logic circuit module inside the chip. The relevant logic circuit modules need to be monitored and tested in real time or periodically even when the system of the chip is in an operating state so as to ensure the correctness of the execution function. However, the current testing method for the chip is inflexible in use, and a testing program is required to be run periodically, so that the normal function running time of the chip is occupied, and the performance of the chip is greatly influenced.

Disclosure of Invention

The embodiment of the application provides a test method of a chip and the chip, wherein the chip comprises a plurality of logic circuit modules, each logic circuit module is provided with a corresponding built-in self-test unit, the chip also comprises a test control unit for controlling each built-in self-test unit, the chip is corresponding to a test program, the test program is provided with a test instruction, the test instruction comprises a test micro instruction and a functional micro instruction which are correspondingly arranged for each logic circuit module, the test micro instruction is used for carrying out functional test on the corresponding logic circuit module, and the functional micro instruction is used for controlling the corresponding logic circuit module to carry out specific operation and/or functional realization, and the test method comprises the following steps:

determining an idle period in which each of the logic circuit modules does not respond to the functional microinstruction;

In the idle period of the logic circuit module, running the associated test micro instruction through the corresponding built-in self-test unit, and acquiring corresponding test data;

And comparing the test data with the stored standard data to determine a target test result corresponding to the logic circuit module.

Optionally, the method further comprises:

compiling the test micro instruction into the sequence of the functional micro instruction, wherein the compiling comprises embedding the test micro instruction into source code of the functional micro instruction, and compiling the source code.

Optionally, the determining an idle period during which each of the logic circuit modules does not respond to the functional microinstruction includes:

Determining the execution sequence of the functional micro instructions, and determining the idle period of each logic circuit module based on the statistical data of the demands of the functional micro instructions on each logic circuit module in the execution sequence of the functional micro instructions.

Optionally, the determining the execution sequence of the functional micro instruction, and determining the idle period of the logic circuit module based on the statistical data of the requirement of the functional micro instruction to each logic circuit module in the execution sequence of the functional micro instruction includes:

determining a program execution trace of the test program, wherein the program execution trace is capable of characterizing an execution order of the functional microinstructions;

and determining the current idle period of the logic circuit module based on the statistical data of the demands of the functional micro instructions on each logic circuit module in the program execution track of the test program and the corresponding demand time of the test micro instructions.

Optionally, the determining the current idle period of the logic circuit module based on the statistical data of the requirement of the functional micro instruction to each logic circuit module in the program execution track of the test program and the requirement time of the corresponding test micro instruction includes:

Determining, for the program execution trace, the logic circuit module that does not need to respond to the functional microinstruction;

Determining a current idle period of the logic circuit module based on a continuous idle unit of the logic circuit module that does not need to respond to the functional micro instruction, wherein the idle unit is an idle time corresponding to the logic circuit module that does not need to respond to the functional micro instruction if one of the functional micro instructions is executed.

Optionally, the running, during the idle period of the logic circuit module, the associated test microinstruction through the corresponding built-in self-test unit, and acquiring corresponding test data, includes:

Isolating interface signals of the logic circuit module corresponding to the built-in self-test unit through the built-in self-test unit;

determining a test vector and a test vector length of the test micro instruction according to the idle period of the logic circuit module and based on the request of the test control unit;

based on the test vector and the test vector length, testing the logic circuit module and acquiring corresponding test data;

and canceling the isolation state of the interface signals of the logic circuit module.

Optionally, the chip further includes a state holding unit, and based on the test vector and the test vector length, the logic circuit module is tested, and corresponding test data is obtained, including:

storing, by the state holding unit, first state data of the logic circuit module before the test;

inputting the test vector into the logic circuit module to test the logic circuit module and obtain corresponding test data;

And restoring the state of the logic circuit module by using the first state data stored by the state holding unit.

Optionally, the testing the logic circuit module based on the test vector and the test vector length, and obtaining corresponding test data includes:

Based on the target test module information in the test micro instruction, the corresponding test requirement is sent to the corresponding logic circuit module by using the test control unit;

Distributing or forcedly distributing a test request to the logic circuit module by utilizing the test control unit according to the fault tolerance time interval of the logic circuit module;

in the case that the logic circuit module performs at least one test procedure, the test request is canceled or forcibly canceled.

Optionally, the testing the logic circuit module based on the test vector and the test vector length, and obtaining corresponding test data includes:

And under the condition that the logic circuit module does not perform a complete test flow, adjusting the length of the test vector, and continuously testing the logic circuit module by using the test vector in the idle period of the logic circuit module.

The embodiment of the application also provides a chip capable of running a test program, wherein the test program is provided with test instructions, the test instructions comprise test micro instructions and functional micro instructions, and the chip comprises:

The logic circuit modules are respectively corresponding to the test micro-instructions and the functional micro-instructions, the test micro-instructions are used for performing functional tests on the corresponding logic circuit modules, and the functional micro-instructions are used for controlling the corresponding logic circuit modules to perform specific operations and/or function realization;

the built-in self-test units are respectively arranged on the corresponding logic circuit modules;

a test control unit for controlling each built-in self-test unit to determine an idle period in which each logic circuit module does not respond to the functional microinstruction,

The built-in self-test unit is also used for running the related test micro-instructions in the idle period of the logic circuit module and obtaining corresponding test data, and comparing the test data with stored standard data to determine a target test result corresponding to the logic circuit module.

According to the testing method of the chip, the built-in self-testing unit is arranged on the logic circuit module of the chip, and each logic circuit module is tested by utilizing the testing micro-instructions and the functional micro-instructions, so that the testing flexibility is improved, and the peak power consumption of the test is reduced. And the idle period of each logic circuit module is utilized to test the logic circuit module in the test process, so that other processing things of each logic circuit module are not influenced, and the test efficiency is improved.

Drawings

FIG. 1 is a flow chart of a method for testing a chip according to an embodiment of the application;

FIG. 2 is a schematic diagram of a test structure of a chip according to an embodiment of the application;

FIG. 3 is a flow chart of one embodiment of step S100 of FIG. 1 according to an embodiment of the present application;

FIG. 4 is a flow chart of one embodiment of step S120 of FIG. 3 according to an embodiment of the present application;

FIG. 5 is a diagram showing statistics of the functional micro instruction demand for each logic module according to an embodiment of the present application;

FIG. 6 is a flow chart of one embodiment of step S200 of FIG. 1 according to an embodiment of the present application;

FIG. 7 is a flow chart of one embodiment of step S230 of FIG. 6 according to an embodiment of the present application;

fig. 8 is a flowchart of another embodiment of step S230 in fig. 6 according to an embodiment of the present application.

Detailed Description

Various aspects and features of the present application are described herein with reference to the accompanying drawings.

It should be understood that various modifications may be made to the embodiments of the application herein. Therefore, the above description should not be taken as limiting, but merely as exemplification of the embodiments. Other modifications within the scope and spirit of the application will occur to persons of ordinary skill in the art.

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the application and, together with a general description of the application given above, and the detailed description of the embodiments given below, serve to explain the principles of the application.

These and other characteristics of the application will become apparent from the following description of a preferred form of embodiment, given as a non-limiting example, with reference to the accompanying drawings.

It is also to be understood that, although the application has been described with reference to some specific examples, those skilled in the art can certainly realize many other equivalent forms of the application.

The above and other aspects, features and advantages of the present application will become more apparent in light of the following detailed description when taken in conjunction with the accompanying drawings.

Specific embodiments of the application will be described hereinafter with reference to the accompanying drawings, in which, however, it is to be understood that the embodiments so applied are merely examples of the application, which may be practiced in various ways. Well-known and/or repeated functions and constructions are not described in detail to avoid obscuring the application in unnecessary or unnecessary detail. Therefore, specific structural and functional details disclosed herein are not intended to be limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present application in virtually any appropriately detailed structure.

The specification may use the word "in one embodiment," "in another embodiment," "in yet another embodiment," or "in other embodiments," which may each refer to one or more of the same or different embodiments in accordance with the application.

The method for testing the chip of the embodiment of the application is applied to the chip, such as the SOC, and as shown in FIG. 2, the chip comprises a plurality of logic circuit modules, and each logic circuit module is provided with a corresponding built-in self-test unit. The built-in self test unit (BIST, build IN SELF TEST) may test the corresponding logic circuit module with test instructions. For example, the logic circuit module comprises a multiplication and division operation unit, a floating point budget unit, a vector operation unit, an arithmetic operation unit, a jump unit atomic operation unit, a fetch, decode, a memory access unit, a general register write-back unit, a general register, an L1 kernel bus, an L1 instruction Cache, a kernel timer, a kernel interrupt controller, an L1 data Cache, an L1 close-coupled Cache, an L2 kernel bus and the like.

The chip further comprises a test control unit for controlling each of the built-in self-test units. The test control unit is connected with each built-in self-test unit respectively and can control each built-in self-test unit so that the built-in self-test unit can test the corresponding logic circuit module.

The chip corresponds to a test program which can be built in advance on the basis of the chip so as to be adapted to the chip. The test program is provided with test instructions, and the test instructions comprise test micro instructions and functional micro instructions which are correspondingly arranged for each logic circuit module.

In one embodiment, each logic circuit module has a corresponding test micro instruction, so that the test micro instruction can be used for performing a functional test on the corresponding logic circuit module, the logic circuit module can feed back corresponding test data after executing the test micro instruction, and whether the logic circuit module meets a preset requirement can be determined through the test data. And the functional micro instructions are used for controlling the corresponding logic circuit modules to perform specific operations and/or function implementation. In this embodiment, since the test of the entire chip is split into the tests of a plurality of independent small logic circuit modules, the test time of each logic circuit module is greatly shortened. And meanwhile, the peak power consumption in the test process of the single logic circuit module is greatly reduced relative to the overall power consumption of the overall test chip.

For example, when the functional microinstruction is a MUL multiply instruction, the MUL multiply instruction may be used to implement a multiply-divide function of the multiply-divide operation unit, when the functional microinstruction is a single precision add instruction, the single precision add instruction may be used to implement a single precision add function of the floating point budget unit, when the functional microinstruction is a VL vector load instruction, when the functional microinstruction is a vector operation unit, the VL vector load instruction may be used to implement a vector operation function of the vector operation unit, when the functional microinstruction is a SRL logical right shift instruction, when the logic circuit module is an arithmetic operation unit, the SRL logical right shift instruction may be used to implement a logical and arithmetic operation function of the logical and arithmetic operation unit, when the functional microinstruction is a BEQ equal condition skip instruction, the logic circuit module is a skip unit, the skip function of the skip unit, when the functional microinstruction is a AMOSWAP atomic swap instruction, the AMOSWAP atomic swap instruction may be used to implement an atomic swap atomic operation unit, and the like.

Based on the above-mentioned structure of the chip, as shown in fig. 1 and combined with fig. 2, the testing method of the chip according to the embodiment of the application includes the following steps:

s100, determining an idle period of each logic circuit module not responding to the functional micro instruction.

For example, after the chip runs the test program, the test instructions therein may be run, including running a plurality of consecutive functional micro-instructions. Each functional instruction has a corresponding functional micro instruction, after one functional micro instruction runs, the corresponding logic circuit module will respond, and other logic circuit modules will not respond, so that the logic circuit module which does not respond will have an idle period, and the idle period is a time period for which the corresponding logic circuit module does not respond functionally. Each logic circuit module may exhibit its idle period after execution of successive functional microinstructions.

In one embodiment, determining the idle period of a logic circuit module includes determining an order of execution of the functional microinstructions and determining the idle period of the logic circuit module based on statistics of demand of the functional microinstructions for each of the logic circuit modules in the order of execution of the functional microinstructions.

For example, a plurality of test instructions in the test program have a corresponding test order, and a plurality of functional micro instructions having an execution order are executed consecutively after the test program is executed. If the functional micro-instructions are executed in this execution order, the logic circuit module corresponding to each functional micro-instruction will respond and the other logic circuit modules will not respond during the process, which indicates that the functional micro-instructions need to cooperate with their corresponding logic circuit modules, and no other logic circuit modules are needed to cooperate. In this embodiment, based on the request condition of each functional micro instruction to each logic circuit module, corresponding requirement statistics data may be obtained, where the requirement statistics data indicates the requirement of the functional micro instruction to each logic circuit module. And determining the idle period of each logic circuit module based on the demand statistical data.

In another embodiment, the test program may be pre-tested to pre-test multiple functional microinstructions. In the process of test run, all logic circuit modules generate corresponding response identifications, including identifications of response success and response failure, and after all the response identifications are acquired, the idle period of the logic circuit modules can be determined based on the statistical information of the response identifications.

In yet another embodiment, each functional microinstruction has identification information of its corresponding logic circuit module, and after the test program determines, the respective identification information may be ordered, and based on the ordering of the identification information, an idle period may be determined in which the respective logic circuit module will not respond to the functional microinstruction.

And S200, operating the associated test micro instruction through the corresponding built-in self-test unit in the idle period of the logic circuit module, and acquiring corresponding test data.

Illustratively, the logic circuit module does not respond functionally during its idle period. Each logic circuit module may have a plurality of idle periods. The logic circuit module may be tested during an idle period of the logic circuit module. The specific test mode can run test micro instructions associated with the logic circuit module through a built-in self-test unit attached to the logic circuit module. And the logic circuit module returns corresponding test data after executing the test micro instruction.

For example, when the logic circuit module is a multiplication and division operation unit, the built-in self-test unit attached to the multiplication and division operation unit operates the MUL multiplication instruction to test the multiplication and division function of the multiplication and division operation unit, and the multiplication and division operation unit returns corresponding test data after executing the MUL multiplication instruction, and the built-in self-test unit obtains the test data. Similarly, when the logic circuit module is a floating point budget unit, the built-in self-test unit attached to the multiply-divide operation unit runs a single-precision addition instruction to test the single-precision addition function of the floating point budget unit, and the floating point budget unit returns corresponding test data after executing the single-precision addition instruction, and the built-in self-test unit acquires the test data.

In one embodiment, the associated test microinstructions may be executed by the corresponding built-in self-test unit and corresponding test data acquired during an initial stage of an idle period of the logic circuit module. Thereby prolonging the test time of the logic circuit module as much as possible.

S300, comparing the test data with the stored standard data to determine a target test result corresponding to the logic circuit module.

The standard data is data obtained by executing corresponding instructions by corresponding logic circuit modules meeting the quality requirements. In one embodiment, each logic circuit module in the chip meeting the production quality requirement has its corresponding standard data, which may be pre-stored in the chip, for example, in a test microinstruction, or in a built-in self-test unit.

When the logic circuit module is tested, the acquired test data can be compared with stored standard data. If the difference between the test data and the standard data is within the first range, if the test data is the same as the standard data, it can be determined that the target test result corresponding to the logic circuit module is that the logic circuit module meets the test requirement. If the difference between the test data and the standard data exceeds the first range, if the content difference between the test data and the standard data is larger, it can be determined that the target test result corresponding to the logic circuit module is that the logic circuit module does not meet the test requirement.

According to the testing method of the chip, the built-in self-testing unit is arranged on the logic circuit module of the chip, and each logic circuit module is tested by utilizing the testing micro-instructions and the functional micro-instructions, so that the testing flexibility is improved, and the peak power consumption of the test is reduced. And the idle period of each logic circuit module is utilized to test the logic circuit module in the test process, so that other processing things of each logic circuit module are not influenced, and the test efficiency is improved.

In one embodiment of the present application, the method further includes determining a corresponding test program based on a test structure (test architecture) of the chip, including constructing test micro instructions corresponding thereto based on the logic circuit module. Different chips have different corresponding test structures, and the test program is matched with the chip and the test structure thereof.

The build test program includes build test micro instructions therein. For example, a BIST test micro instruction (BIST_INST) is constructed. The BIST_INST needs to contain the information BISTI corresponding to the execution Code (Operation Code), the target test Unit (TARGET TEST Unit). The target test unit is provided with a test target number, the minimum value can be expressed as not testing any sub-module, the maximum value can be expressed as testing all the sub-modules, so that the flexibility of the test is expanded, the minimum value and the maximum value are removed, and each number corresponds to one sub-module which can independently perform BIST test inside the CPU.

The Test microinstruction further includes a Test Initial Vector pointer (Initial Vector), a number of Test vectors (Vector Length), and a Test Result return value (Test Result), wherein the Test Initial Vector pointer (Initial Vector) is used for testing a location where the Initial Vector is stored, the number of Test vectors (Vector Length) refers to how many Test vectors are run at one time, and the Test time increases correspondingly as the number of vectors increases. The Test Result return value (Test Result) contains Test Result information.

In one embodiment of the application, the method further comprises compiling the test microinstruction into the sequence of functional microinstructions, including embedding the test microinstruction into source code of the functional microinstruction, and compiling the source code.

Illustratively, compiling the test microinstructions into the sequence of the functional microinstructions may form corresponding test instructions, based on which the response of each logic circuit module may be counted, thereby determining the idle period of the logic circuit module. The test micro-instructions are embedded into the source codes of the functional micro-instructions and the source codes are compiled to form assembly language capable of being executed by hardware. Test microinstructions in the test instructions may be executed during idle periods of the logic circuit module.

In one embodiment of the application, the determining the idle period that each of the logic circuit modules does not respond to the functional microinstructions includes determining an execution order of the functional microinstructions, and determining the idle period of the logic circuit module based on the demand statistics of each of the logic circuit modules by the functional microinstructions in the execution order of the functional microinstructions. The step of determining the idle period further includes, as shown in fig. 3, the steps of:

S110, determining a program execution track of the test program, wherein the program execution track can represent the execution sequence of the functional micro instructions.

After the test program is constructed, the test program has a corresponding program execution track, the program execution track marks the running process of the test program, and the test program is provided with test instructions, so that the program execution track can represent the execution sequence of the functional micro instructions. During execution of the functional microinstructions in their execution order, each logic circuit module determines whether to respond to each of the functional microinstructions that are executed in order.

S120, determining an idle period of the logic circuit module based on the statistical data of the demands of the functional micro instructions on each logic circuit module in the program execution track of the test program and the corresponding demand time of the test micro instructions.

In an exemplary embodiment, the functional microinstructions are executed in a corresponding order in the program execution path of the test program, and the requirements for each logic circuit module are different during the execution process. For example, if a functional microinstruction of a MUL multiply instruction is running, the logic circuit module of the multiply-divide arithmetic unit is required to respond to it, without requiring other logic circuit module responses. If the functional microinstruction of the single precision add instruction is running, the logic circuit module of the floating point arithmetic unit is required to respond to it, without requiring other logic circuit module responses.

In one embodiment, the order of execution of the functional micro instructions may be based on statistics that each functional micro instruction forms demand statistics for the demand information of each logic circuit module, respectively, to determine the idle period of the logic circuit module based on the demand statistics.

In another embodiment, the demand statistics for the demand information of each logic circuit module may be formed by counting the functional micro-instructions based on the execution sequence of the functional micro-instructions, so as to determine the current idle period of the logic circuit module based on the demand statistics and the demand time of the corresponding test micro-instructions. Specifically, there may be multiple time periods in which the logic circuit module does not respond to the functional microinstruction, each of which can be an idle period. The required time for a test micro instruction is the time required to run a complete test micro instruction. If the test microinstruction is required for less than a pre-use period of time for the corresponding logic circuit module, in which case the test microinstruction can be completely executed, the period of time can be determined as the current idle period. If the required time of the test micro instruction is longer than a pre-use time period of the corresponding logic circuit module, another larger pre-use time period can be selected as the current idle period, so that the test micro instruction can be effectively operated in the larger idle period.

In one embodiment of the present application, the determining the current idle period of the logic circuit module based on the statistical data of the requirement of the functional micro instruction on each logic circuit module in the program execution trace of the test program and the corresponding requirement time of the test micro instruction, as shown in fig. 4 and in combination with fig. 5, includes:

S121, determining the logic circuit module which does not need to respond to the functional micro instruction according to the program execution track.

Illustratively, after the test program is constructed, the test program may have a plurality of program execution traces for the test architecture of the corresponding chip. In this embodiment, based on each program execution track, the logic circuit module to which it is associated may be determined.

For example, three possible program execution tracks can be obtained through analysis, and the three possible program execution tracks are respectively:

Path1:A1->A2->A3->A4->B1->B2->B3->B4->F1->F2->R1

Path2:A1->A2->A3->A4->C1->C2->D1->D2->G1->G2->R1

Path3:A1->A2->A3->A4->C1->C2->E1->E2->G1->G2->R1

Each program execution trace is associated with a plurality of functional micro instructions, and the functional micro instructions associated with the Path1 are A1, A2, A3, A4, B1, B2, B3, B4, F1, F2 and R1 according to the execution sequence. The associated functional microinstructions in Path2 are, in order of execution, A1, A2, A3, A4, C1,C 2,D1,D2,G 1,G 2,R1. The associated functional microinstructions in Path3 are, in order of execution, A1, A2, A3, A4, C1,C 2,E 1,E 2,G 1,G 2,R1.

And analyzing the corresponding functional micro instruction execution sequence aiming at the program execution track to obtain a logic circuit module aiming at each functional micro instruction without responding to the functional micro instruction. For example, for A1 in Path1, only the first logic circuit module corresponding thereto needs to be able to respond, while the other logic circuit modules do not need to respond. For A2 in Path1, only the second logic circuit module corresponding thereto needs to be able to respond, while the other logic circuit modules do not need to respond, and so on.

S122, determining the current idle period of the logic circuit module based on the continuous idle units of the logic circuit module which do not need to respond to the functional micro instruction, wherein the idle units are the idle time corresponding to the logic circuit module which does not need to respond to the functional micro instruction if one functional micro instruction is executed.

For example, for a functional microinstruction, multiple logic circuit modules may not need to respond to it. The run time period of the functional microinstruction may be treated as an idle unit of the logic circuit module that does not need to respond to the functional microinstruction.

In connection with fig. 5, for example, for MUL multiply instructions, no other floating point budget unit, vector operation unit, arithmetic operation unit, skip unit, or atomic operation unit needs to respond to except for the multiply-divide operation unit. The time of the multiplier-divider unit responding to the MUL multiplication instruction is taken as a first time period, and the first time period is the idle time of the logic circuit module not responding to the MUL multiplication instruction, so that the first time period can be taken as an idle unit of the logic circuit module not responding to the MUL multiplication instruction.

For single precision addition instructions, the floating point budget removal unit needs to respond, and other multiplication and division operation units, vector operation units, arithmetic operation units, jump units and atomic operation units cannot respond to the single precision addition instructions. The time of the floating point budget unit responding to the single-precision addition instruction is taken as a second time period, wherein the second time period is the idle time of the logic circuit module which does not respond to the single-precision addition instruction, and the second time period can be taken as another idle unit of the logic circuit module which does not respond to the single-precision addition instruction.

Each logic circuit module has successive free cells for a plurality of successive different functional microinstructions. The continuous idle unit may be regarded as an idle period. In one embodiment, a relationship table may be constructed to indicate the association between each functional microinstruction and each logic circuit module, and the idle unit of each logic circuit module, and thus the idle period of each logic circuit module, may be determined based on the contents of the relationship table.

In one embodiment of the present application, the running the associated test microinstructions through the corresponding built-in self-test unit and acquiring corresponding test data during the idle period of the logic circuit module, as shown in fig. 6, includes:

s210, isolating interface signals of the logic circuit module corresponding to the built-in self-test unit.

The interface signals of the logic circuit module are used for data interaction with other modules in the chip. The built-in self-test unit can close the interface of the logic circuit module corresponding to the built-in self-test unit by utilizing the control instruction, so that the interface signal of the logic circuit module is isolated from other parts of the chip. This will make the logic circuit module immune to external influences during testing.

S220, determining a test vector and a test vector length of the test micro instruction according to the idle period of the logic circuit module and based on the request of the test control unit.

The test control unit will, for example, issue a request to the built-in self-test unit, which initiates a test operation based on the request, and determines a test vector and a test vector length for testing the microinstructions based on the idle period of the logic circuit module. The test vector is a set of preset input signal combinations, and can be presented in the form of binary codes. The test vector is applied to the logic circuit module under test, and the logic circuit module generates corresponding test data according to the circuit logic of the logic circuit module. By comparing the test data with the stored standard data, it is possible to determine whether the logic circuit module has a functional failure or a performance problem. The test vector length refers to the number of binary bits contained in one test vector. In chip testing, each bit represents the state (0 or 1) of an input signal, and the test vector length represents the number of input signal combinations simultaneously applied to the logic circuit under test in one test.

In this embodiment, the test vector and the test vector length of the test micro instruction may be determined according to the size of the idle period, so that the test vector and the test vector length are adapted to the size of the idle period of the logic circuit module.

And S230, testing the logic circuit module based on the test vector and the test vector length, and acquiring corresponding test data.

For example, based on the test vector and the test vector length, the test microinstructions may be executed at the start time of the idle period to test the corresponding logic circuit module and obtain the corresponding test data. The test micro instruction is operated at the initial time of the idle period, so that the idle period of the logic circuit module can be effectively utilized, and the test time is increased as much as possible.

And the built-in self-test unit selects a corresponding initial test vector and test vector length to test the tested logic circuit module according to the request of the test control unit. The test process can adopt a boundary SCAN (SCAN) technology to input a test vector into a logic circuit module to be tested, check the response of the logic circuit module to the test vector, acquire test data, compare the test data with stored standard data, determine the correctness of the logic circuit module according to a comparison result, further obtain a target test result, and return the target test result to the test control unit by the built-in self-test unit.

Preferably, the length of the test vector is adjusted when the logic circuit module does not perform a complete test flow, and the test vector is used to continue testing the logic circuit module in the idle period of the logic circuit module.

For example, if the test vector length is relatively long, it may not be fully tested during the idle period, so that the logic circuit module may only perform part of the test procedure during the idle period and may not perform the full test. This requires that testing be resumed during other idle periods of the logic circuit module, and the test vector length can be adjusted to fit into another idle period to resume testing of the logic circuit module.

S240, canceling the isolation state of the interface signals of the logic circuit module.

For example, after the testing of the circuit base circuit module is completed, the built-in self-test unit may turn on the interface of the logic circuit module corresponding to the built-in self-test unit by using the control instruction, so as to cancel isolation between the interface signal of the logic circuit module and other parts of the chip. So that the logic circuit module resumes its function.

In one embodiment of the present application, the chip further includes a state holding unit, and the testing the logic circuit module based on the test vector and the test vector length, and acquiring corresponding test data, as shown in fig. 7, includes:

s231, storing first state data of the logic circuit module before testing by the state holding unit.

Illustratively, the state holding unit is configured to hold an original state of the logic circuit module prior to testing. The state holding unit can be connected with the built-in self-test units of all logic circuit modules in the chip, and can acquire and store first state data of the logic circuit modules before testing through the built-in self-test units.

S232, inputting the test vector into the logic circuit module to test the logic circuit module and obtain corresponding test data.

In an exemplary process, the test control unit controls the built-in self-test unit to test the logic circuit module, and the built-in self-test unit selects a corresponding initial test vector and a test vector length to test the logic circuit module to be tested according to a request of the test control unit. The built-in self-test unit obtains corresponding test data and compares the corresponding test data with stored standard data to obtain a target test result.

S233, restoring the state of the logic circuit module by using the first state data stored by the state holding unit.

After the logic circuit module is tested, the state of the logic circuit module is restored by using the first state data stored by the state holding unit, so that the logic circuit module enters a state before the test, errors of the logic circuit module are prevented, and the stability of the logic circuit module is maintained.

In one embodiment of the present application, the testing the logic circuit module based on the test vector and the test vector length, and obtaining corresponding test data, as shown in fig. 8, includes:

s234, based on the target test module information in the test micro instruction, the corresponding test requirement is sent to the corresponding logic circuit module by using the test control unit;

S235, according to the fault tolerance time interval of the logic circuit module, a test request is distributed or forcedly distributed to the logic circuit module by utilizing the test control unit;

s236, canceling or forcedly canceling the test request in the case that the logic circuit module executes at least one test process.

Illustratively, the target test module information in the test microinstruction includes information about the test target, and also includes information about the test vector and the test length of the test instruction. Based on the target test module information, the test control unit sends corresponding test requirements to the corresponding logic circuit modules.

For example, the test control Unit parses the test micro instruction (BIST_INST instruction) and dispatches the test requirement (Vector, length) to the corresponding logic circuit module (TARGET TEST Unit). Where the test Vector is the Vector address (Last Vector) where the Last test was completed. Post vector=post vector+length after completion of this test. If (Laster Vector-Initial Vector) is greater than the total test Vector length Total Vector Length, laster Vector is reset to the Initial Vector (Initial Vector) address. Length is calculated from the Vector Length in BIST_INST, and if Vector Length+ (Last Vector-Initial Vector) is less than Total Vector Length then Length=vector Length, otherwise Length= Total Vector Length- (Last Vector-Initial Vector).

The test control unit may choose to forcibly dispatch the test request according to the Fault Tolerant Time Interval (FTTI) requirements of the logic circuit module. In a high security application scenario, at least one test of the logic circuit module under test needs to be completed within a time period of one FTTI. Because of the uncertainty of instruction execution, the test microinstructions (BSIT _INST instructions) of the tested logic circuit module may not be sufficiently executed in one FTTI time interval under a specific scenario, resulting in insufficient testing of the tested logic circuit module. To meet the requirements of FTTI, the test control unit may enable the function of forcibly dispatching test requests in a high security scenario. Specifically, the test control unit assigns a timer to each logic circuit module under test. The timing interval of the timer is set to an interval not greater than FTTI. For example, FTTI is 5 ms, the timer interval may be set to 4 ms. The timer starts counting from the execution of the first test microinstruction (BSIT _INST instruction) of the corresponding logic circuit module under test, and forcibly issues a test request to the unit under test if the unit under test has not completed a complete test within a 4 millisecond interval. Of course, the logic circuit module under test may choose to force cancellation of the test request based on the requirements of the Fault Tolerant Time Interval (FTTI). In one embodiment, according to the requirements of the FTTI, the test of the tested unit is completed only once in the time period of one FTTI

Further, the test control unit may enable forced cancellation of the test request, similar to the flow of forcibly dispatching the test request. During a timer count period, if a complete test has been completed, the subsequent test microinstructions (BSIT _INST instructions) will be forced to cancel during the period to improve CPU performance while reducing power consumption wasted due to unnecessary testing. During execution of the test microinstruction (BSIT _INST instruction), subsequent functional microinstructions may be executed in parallel.

An embodiment of the present application provides a chip capable of executing the above method, where the chip is capable of running a test program, where the test program has a test instruction, and the test instruction includes a test micro instruction and a functional micro instruction, as shown in fig. 2, and the chip includes:

The logic circuit modules are respectively corresponding to the test micro-instructions and the functional micro-instructions, the test micro-instructions are used for performing functional tests on the corresponding logic circuit modules, and the functional micro-instructions are used for controlling the corresponding logic circuit modules to perform specific operations and/or function realization;

the built-in self-test units are respectively arranged on the corresponding logic circuit modules;

a test control unit for controlling each built-in self-test unit to determine an idle period in which each logic circuit module does not respond to the functional microinstruction,

The built-in self-test unit is also used for running the related test micro-instructions in the idle period of the logic circuit module and obtaining corresponding test data, and comparing the test data with stored standard data to determine a target test result corresponding to the logic circuit module.

The embodiment of the application also provides electronic equipment, which comprises a processor and a memory, wherein the memory stores executable programs, and the memory executes the executable programs to perform the steps of the method.

Embodiments of the present application also provide a storage medium carrying one or more computer programs which, when executed by a processor, implement the steps of the method as described above.

Embodiments of the present application also provide a computer program product comprising a computer program/instruction, characterized in that the computer program/instruction, when executed by a processor, implements the steps of the method as described above.

It should be appreciated that in embodiments of the present application, the processor may be a central Processing unit (Central Processing Unit, CPU) and may also be other general purpose processors, digital signal processors (DIGITAL SIGNAL Processing, DSP), application SPECIFIC INTEGRATED Circuits (ASIC), off-the-shelf Programmable gate arrays (Field-Programmable GATE ARRAY, FPGA) or other Programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, and so on.

It should also be understood that the memory referred to in embodiments of the present application may be volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The nonvolatile Memory may be a Read Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable ROM (ELECTRICALLY EPROM EEPROM), or a flash Memory. The volatile memory may be a random access memory (Random Access Memory, RAM for short) which acts as an external cache. By way of example, and not limitation, many forms of RAM are available, such as static random access memory (STATIC RAM, SRAM), dynamic random access memory (DYNAMIC RAM, DRAM), synchronous Dynamic Random Access Memory (SDRAM), double data rate Synchronous dynamic random access memory (Double DATA RATE SDRAM, DDR SDRAM), enhanced Synchronous dynamic random access memory (ENHANCED SDRAM, ESDRAM), synchronous link dynamic random access memory (SYNCHLINK DRAM, SLDRAM), and direct memory bus random access memory (Direct Rambus RAM, DR RAM).

It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, the memory (storage module) is integrated into the processor.

It should be noted that the memory described herein is intended to comprise, without being limited to, these and any other suitable types of memory.

It should also be understood that the first, second, third, fourth and various numerical numbers referred to herein are merely descriptive convenience and are not intended to limit the scope of the application.

It should be understood that the term "and/or" is merely an association relationship describing the associated object, and means that three relationships may exist, for example, a and/or B, and that three cases, a alone, a and B together, and B alone, may exist. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or by instructions in the form of software. The steps of a method disclosed in connection with the embodiments of the present application may be embodied directly in a hardware processor for execution, or in a combination of hardware and software modules in the processor for execution. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in a memory, and the processor reads the information in the memory and, in combination with its hardware, performs the steps of the above method. To avoid repetition, a detailed description is not provided herein.

In various embodiments of the present application, the sequence number of each process does not mean the sequence of execution, and the execution sequence of each process should be determined by its functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

Those of ordinary skill in the art will appreciate that the various illustrative logical blocks (illustrative logical block, abbreviated ILBs) and steps described in connection with the embodiments disclosed herein can be implemented in electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiments of the present application, it should be understood that the disclosed method, chip, electronic device, etc. may be implemented in other manners. For example, the above-described chip embodiments are merely illustrative, and for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk), etc.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A method for testing a chip, wherein the chip includes a plurality of logic circuit modules, each logic circuit module is provided with a corresponding built-in self-test unit, the chip further includes a test control unit for controlling each built-in self-test unit, the chip corresponds to a test program, the test program has a test instruction, the test instruction includes a test micro instruction and a functional micro instruction, the test micro instruction is correspondingly configured for each logic circuit module, the test micro instruction is used for performing a functional test on the corresponding logic circuit module, and the functional micro instruction is used for controlling the corresponding logic circuit module to perform a specific operation and/or a functional implementation, the test method includes:

determining an idle period in which each of the logic circuit modules does not respond to the functional microinstruction;

In the idle period of the logic circuit module, running the associated test micro instruction through the corresponding built-in self-test unit, and acquiring corresponding test data;

And comparing the test data with the stored standard data to determine a target test result corresponding to the logic circuit module.

2. The method of testing a chip of claim 1, further comprising:

compiling the test micro instruction into the sequence of the functional micro instruction, wherein the compiling comprises embedding the test micro instruction into source code of the functional micro instruction, and compiling the source code.

3. The method of testing a chip of claim 1, wherein said determining an idle period during which each of said logic circuit modules does not respond to said functional microinstruction comprises:

Determining the execution sequence of the functional micro instructions, and determining the idle period of each logic circuit module based on the statistical data of the demands of the functional micro instructions on each logic circuit module in the execution sequence of the functional micro instructions.

4. The method of claim 3, wherein determining the execution order of the functional micro instructions and determining the idle period of the logic circuit module based on the statistics of the demands of the functional micro instructions on each of the logic circuit modules in the execution order of the functional micro instructions comprises:

determining a program execution trace of the test program, wherein the program execution trace is capable of characterizing an execution order of the functional microinstructions;

and determining the current idle period of the logic circuit module based on the statistical data of the demands of the functional micro instructions on each logic circuit module in the program execution track of the test program and the corresponding demand time of the test micro instructions.

5. The method according to claim 4, wherein determining the current idle period of the logic circuit module based on the statistical data of the demands of the functional micro-instructions on the logic circuit modules in the program execution trace of the test program and the corresponding times of the demands of the test micro-instructions comprises:

Determining, for the program execution trace, the logic circuit module that does not need to respond to the functional microinstruction;

Determining a current idle period of the logic circuit module based on a continuous idle unit of the logic circuit module that does not need to respond to the functional micro instruction, wherein the idle unit is an idle time corresponding to the logic circuit module that does not need to respond to the functional micro instruction if one of the functional micro instructions is executed.

6. The method according to claim 1, wherein said running the associated test microinstructions through the corresponding built-in self-test unit and acquiring the corresponding test data during the idle period of the logic circuit module comprises:

Isolating interface signals of the logic circuit module corresponding to the built-in self-test unit through the built-in self-test unit;

determining a test vector and a test vector length of the test micro instruction according to the idle period of the logic circuit module and based on the request of the test control unit;

based on the test vector and the test vector length, testing the logic circuit module and acquiring corresponding test data;

and canceling the isolation state of the interface signals of the logic circuit module.

7. The method according to claim 6, further comprising a state holding unit, wherein the testing the logic circuit module based on the test vector and the test vector length and acquiring corresponding test data includes:

storing, by the state holding unit, first state data of the logic circuit module before the test;

inputting the test vector into the logic circuit module to test the logic circuit module and obtain corresponding test data;

And restoring the state of the logic circuit module by using the first state data stored by the state holding unit.

8. The method according to claim 6, wherein the testing the logic circuit module based on the test vector and the test vector length and acquiring corresponding test data includes:

Based on the target test module information in the test micro instruction, the corresponding test requirement is sent to the corresponding logic circuit module by using the test control unit;

Distributing or forcedly distributing a test request to the logic circuit module by utilizing the test control unit according to the fault tolerance time interval of the logic circuit module;

in the case that the logic circuit module performs at least one test procedure, the test request is canceled or forcibly canceled.

9. The method according to claim 6, wherein the testing the logic circuit module based on the test vector and the test vector length and acquiring corresponding test data includes:

And under the condition that the logic circuit module does not perform a complete test flow, adjusting the length of the test vector, and continuously testing the logic circuit module by using the test vector in the idle period of the logic circuit module.

10. A chip capable of running a test program having test instructions therein, the test instructions including test micro-instructions and functional micro-instructions, the chip comprising:

The logic circuit modules are respectively corresponding to the test micro-instructions and the functional micro-instructions, the test micro-instructions are used for performing functional tests on the corresponding logic circuit modules, and the functional micro-instructions are used for controlling the corresponding logic circuit modules to perform specific operations and/or function realization;

the built-in self-test units are respectively arranged on the corresponding logic circuit modules;

a test control unit for controlling each built-in self-test unit to determine an idle period in which each logic circuit module does not respond to the functional microinstruction,

The built-in self-test unit is also used for running the related test micro-instructions in the idle period of the logic circuit module and obtaining corresponding test data, and comparing the test data with stored standard data to determine a target test result corresponding to the logic circuit module.