CN119889395B

CN119889395B - Information storage method and device of memory, memory and storage medium

Info

Publication number: CN119889395B
Application number: CN202411862103.9A
Authority: CN
Inventors: 王者伟; 高伟
Original assignee: Lianhe Storage Technology Jiangsu Co ltd
Current assignee: Lianhe Storage Technology Jiangsu Co ltd
Priority date: 2024-12-17
Filing date: 2024-12-17
Publication date: 2025-09-23
Anticipated expiration: 2044-12-17
Also published as: CN119889395A

Abstract

The invention discloses an information storage method, a device, a memory and a storage medium of a memory, wherein the information storage method of the memory comprises the steps of writing target parameter data in a target word line; and writing target parameter data into the other word lines, wherein the other word lines are the target word line and word lines except the two groups of adjacent word lines. According to the invention, the target parameter data which are the same as the target word line are written in the other word lines, so that the target parameter data on the target word line are reinforced, and the two groups of adjacent word lines adjacent to the target word line are kept in an erased state, so that the interference caused by the voltage change of the adjacent word lines is reduced, the data interference and misreading can be effectively avoided, and the reliability and the accuracy of the stored data are improved.

Description

Information storage method and device of memory, memory and storage medium

Technical Field

The present invention relates to the field of memory technologies, and in particular, to a method and apparatus for storing information in a memory, and a storage medium.

Background

NAND FLASH has an ECC error correction function when the client is applied, and can judge the correctness of the data after the data stored by the user is just written and placed for a certain time with the help of the ECC error correction function.

NAND FLASH themselves have many important data information written to a fixed location, and when Power on read is done on the chip, these important data information are read into the latch of the chip, and when the user uses the chip, parameters in the latch (the above-mentioned important data information) are used. However, when Power on read, these parameters are not yet read into latch, then default parameters are used when Power on read is done. Such as the voltage applied to the select WL (select word line) at Read. The chip is designed to allow this voltage to range from 0-2V,0.1V step, and by default the voltage is 0.1V. However, the experiment results in that the voltage was set to 0.5V for best performance of the chip. Then 0.5V of information would be written in the special Block area of the chip. Voltage information like this is also very much and critical, and once there is an error, the Power on read of the chip will fail and the chip will not work properly.

NAND FLASH when Power on read, the parameter information of the Power on read is read into the corresponding cache (cache), but when Power on read, the cache is a set of Design designed fixed parameters, no ECC error correction algorithm exists, and no optimal parameter setting is performed on NAND FLASH. After the chip is applied to the client, the information is read only when the chip is powered on, the information is not erased and reprogrammed, the placement which can last for the whole NNAD FLASH service life is not wrong, and once the chip is wrong, the chip cannot be read and written normally, so that the reliability is poor.

Disclosure of Invention

The invention provides an information storage method of a memory, which aims to improve the storage quality of NAND FLASH own important data information so as to ensure the correctness of the important data information. According to the invention, the target parameter data which are the same as the target word line are written in the other word lines, so that the target parameter data on the target word line are reinforced, and the two groups of adjacent word lines adjacent to the target word line are kept in an erased state, so that the interference caused by the voltage change of the adjacent word lines is reduced, the data interference and misreading can be effectively avoided, and the reliability and the accuracy of the stored data are improved.

In order to achieve the above object, the present invention provides an information storage method of a memory.

The memory is NAND FLASH memories, the NAND FLASH memories include a plurality of memory cells connected in series, each memory cell corresponding to a word line, the method includes:

Writing target parameter data in a target word line;

maintaining an erased state of two sets of adjacent word lines adjacent to the target word line;

the target parameter data is written in the remaining word lines, which are the target word line and word lines other than the two sets of adjacent word lines.

Optionally, after the writing of the target parameter data in the remaining word lines, the method further includes:

When the data is read in a starting mode, conducting voltages are applied to the two groups of adjacent word lines and the rest word lines;

and applying a read voltage to the target word line to obtain read data on the target word line.

Optionally, after the applying the read voltage to the target word line to obtain the read data on the target word line, the method further includes:

checking the read data on the target word line in a positive and negative code checking mode;

And if the verification is passed, reading the target parameter data to a latch.

Optionally, after the verifying the read data, the method further includes:

if verification fails, applying a read voltage to the other word lines to obtain read data on the other word lines;

and checking the read data on the other word lines in a positive and negative code checking mode until the check is successful or all the check fails.

Optionally, after the reading the target parameter data to the latch, the method further comprises:

reading the target parameter data in the latch to a cache;

the NAND FLASH memory is configured with the target parameter data in the cache.

Optionally, the read voltage is configured to be between a first voltage threshold that is a threshold voltage when electrons are on the floating gate of the memory cell and a second voltage threshold that is a threshold voltage when electrons are not on the floating gate of the memory cell.

Optionally, the target parameter data includes non-default operating parameter data required by the NAND FLASH memory when reading data.

The invention also provides an information storage device of the memory, which comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the computer program realizes the steps of the information storage method of the memory when being executed by the processor.

The invention also provides a memory, which comprises NAND FLASH memories, an information storage device of the memories and a plurality of memory units connected in series, wherein each memory unit corresponds to one word line, and the information storage device of the memory is the information storage device of the memories.

The invention also proposes a storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the information storage method of a memory as described above.

The technical scheme of the information storage method of the memory comprises the steps of writing target parameter data in a target word line, keeping two groups of adjacent word lines adjacent to the target word line in an erased state, writing the target parameter data in other word lines, wherein the other word lines are the target word line and word lines except the two groups of adjacent word lines. According to the invention, the target parameter data which are the same as the target word line are written in the other word lines, so that the target parameter data on the target word line are reinforced, and the two groups of adjacent word lines adjacent to the target word line are kept in an erased state, so that the interference caused by the voltage change of the adjacent word lines is reduced, the data interference and misreading can be effectively avoided, and the reliability and the accuracy of the stored data are improved.

Drawings

Fig. 1 is a flow chart of an information storage method of a memory according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a word line layout of NAND FLASH according to one embodiment of the present invention;

FIG. 3 is a schematic diagram illustrating an internal structure of NAND FLASH according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a method for checking positive and negative codes according to an embodiment of the present invention;

FIG. 5 is a schematic diagram illustrating the influence between memory cells according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of an information storage device of a memory according to an embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that all directional indicators (such as up, down, left, right, front, and rear are used in the embodiments of the present invention) are merely for explaining the relative positional relationship, movement conditions, and the like between the components in a certain specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicators are changed accordingly.

It will also be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.

Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.

Referring to fig. 1, fig. 1 is a flowchart illustrating an information storage method of a memory according to an embodiment of the invention. The information storage method of the memory comprises the following steps:

S10, writing target parameter data in a target word line.

In this embodiment, the memory is NAND FLASH memories, the NAND FLASH memory includes a plurality of memory cells connected in series, the NAND FLASH memory may also be referred to as NAND flash memory or NAND flash memory, the NAND FLASH memory is one of flash memories, and a nonlinear macro cell mode is adopted in the memory, so that an inexpensive and effective solution is provided for implementing a solid-state large-capacity memory. NAND FLASH in the memory, the memory cell is a type of NMOS double-layer floating gate MOS transistor, also referred to as a floating gate transistor (Floating Gate Transistor). The memory cell is composed of a Source (Source), a Drain (Drain), a Gate (typically Word Line), and a Floating Gate (Floating Gate). The floating gate is surrounded by insulating layers up and down for storing charge.

The writing operation (programming) of the memory cell is performed by applying a high voltage to the control electrode to induce quantum tunneling, and injecting electrons from the source electrode into the floating gate through the insulating layer. This changes the state of charge on the floating gate, which in turn affects the on state of the transistor, indicating the information stored (typically a "0" or a "1").

Memory cell erase operations, erase, is typically performed in blocks (blocks). By applying a strong voltage to the substrate, quantum tunneling is induced, electrons on the floating gate are removed, and the original state of the transistor is restored.

And (3) a cell reading operation of the memory cell, namely, reading the state of the cell by applying a low reading voltage to the control electrode and detecting the conduction state between the source electrode and the drain electrode. If electrons are in the floating gate, the read voltage is offset, the transistor is turned off, indicating that the stored information is "0", and if electrons are not in the floating gate, the transistor is turned on, indicating that the stored information is "1".

NAND FLASH are shown in fig. 2, fig. 2 is a schematic diagram of a word line arrangement of NAND FLASH, fig. 3 is an internal structure of NAND FLASH, fig. 3 is a schematic diagram of an internal structure of NAND FLASH, and fig. 3 is a schematic diagram of an internal structure of NAND FLASH.

In fig. 2, the storage of the target parameter data is reinforced by writing many WLs in the embodiment of the present invention. The writing mode of the target word line WL _n is unchanged, the data same as the target word line WL _n is written on the rest of the word lines WL _n-2,WL_n-3,WL_n-4,WL_n+2,WL_n+3,WL_n+4, and two adjacent word lines WL _n+1 and WL _n-1 adjacent to WL _n still maintain the Erase state.

The Power on read (Power on read) still reads and verifies the WL _n under the target word line, and the data on the remaining word lines WL _n-2,WL_n-3,WL_n-4,WL_n+2,WL_n+3,WL_n+4 may play a reinforcing role on the data of WLn.

The target word line may be an intermediate one, and the group of word lines may include at least one word line, i.e., the target word line may be one word line or a plurality of word lines, and in the embodiment of the present invention, the target word line may be an intermediate one, considering that there is less target parameter data in NAND FLASH.

In fig. 2, WL _n is a target word line, the target parameter data may be non-default parameter data of NAND FLASH, the default parameter data of NAND FLASH is fixed parameter data stored in the cache, and if the non-default parameter data of NAND FLASH is not read, NAND FLASH is configured by the default parameter data in the cache.

After the target parameter data is written in the target word line, the corresponding cell of the target word line has electrons, the corresponding flag data is '0', if the target parameter data is not written in the target word line, the corresponding cell of the target word line has no electrons, and the corresponding flag data is '1'.

In fig. 3, cells are serially connected, and the source terminal of the current cell and the Drain terminal of the next cell are connected together to form a cell string (…,WL_n-4,WL_n-3,WL_n-2,WL_n-1,WL_n,WL_n+1,WL_n+2,WL_n+3,WL_n+4,…),, and the Drain terminal of the first cell is connected to a Bit line.

S20, two groups of adjacent word lines adjacent to the target word line are kept in an erased state.

In the embodiment of the present invention, the adjacent word lines are adjacent to the target word line, and may be a group of word lines before the target word line and a group of word lines after the target word line, where the two groups of adjacent word lines respectively precede and follow the target word line. The above-mentioned erased state indicates that no data is written, that is, no electrons are present in the cell corresponding to the adjacent word line, and the corresponding flag data is "1".

Each group of adjacent word lines comprises at least one word line, and specifically, the interference degree between the adjacent word lines can be determined according to the interference degree, and the greater the interference degree between the adjacent two word lines, the more word lines in each group of adjacent word lines. In this way, the disturbance at the time of adjacent word line change can be reduced.

In fig. 2, the adjacent word line may be WL _n adjacent to the target word line, i.e., WL _n+1 and WL _n-1.WL_n+1 and WL _n-1 remain in the erased state, without writing any data.

S30, writing target parameter data in the rest word lines.

In the embodiment of the invention, the other word lines are the target word line and the word lines except the adjacent word line, and the target parameter data identical to the target word line is written in the other word lines, so that the target parameter data of the target word line can be reinforced, and when the target word line is written with the target parameter data and the other word lines are written with the target parameter data, the probability that the target word line reads the mark data 0 is improved when the data is started and read.

The information storage method of the memory of the embodiment is implemented, target parameter data is written in a target word line, two groups of adjacent word lines adjacent to the target word line are kept in an erased state, the target parameter data is written in other word lines, and the other word lines are the target word line and word lines except the two groups of adjacent word lines. According to the invention, the target parameter data which are the same as the target word line are written in the other word lines, so that the target parameter data on the target word line are reinforced, and the two groups of adjacent word lines adjacent to the target word line are kept in an erased state, so that the interference caused by the voltage change of the adjacent word lines is reduced, the data interference and misreading can be effectively avoided, and the reliability and the accuracy of the stored data are improved.

It will be appreciated that in the specific embodiments of the present application, related data such as memory data, control data, parameter data, etc. are involved, and when the embodiments of the present application are applied to specific products or technologies, user permissions or agreements need to be obtained, and the collection, use and processing of related data, as well as training and use of various models need to comply with related laws and regulations and standards of related countries and regions.

Optionally, after the step of writing the target parameter data in the remaining word lines, a turn-on voltage may be applied to two adjacent groups of the word lines and the remaining word lines when the data is read at power-on, and a read voltage may be applied to the target word line to obtain the read data on the target word line.

In the embodiment of the invention, in the initial stage of starting up and reading data, on-voltage needs to be applied to two groups of adjacent word lines and the rest word lines. The adjacent word lines and the rest word lines are in a conducting state, thereby creating necessary conditions for the subsequent data reading operation. The application of the turn-on voltage is typically accomplished by a voltage control circuit within the memory.

The turn-on voltage is a higher voltage and may be specifically determined according to the default parameters of NAND FLASH. If the voltage is too low, the word line may not be fully turned on, resulting in a data read failure. Therefore, in practical applications, it may be necessary to select an appropriate on-voltage value according to the specific characteristics and use requirements of the memory.

After applying the on-voltage to two sets of adjacent word lines and the remaining word lines, a read voltage needs to be applied to the target word line next. The read voltage is a voltage dedicated to reading data in the memory cell and is typically sized between a first voltage threshold and a second voltage threshold. The first voltage threshold corresponds to a threshold voltage of the memory cell when electrons are not on the floating gate, and the second voltage threshold corresponds to a threshold voltage of the memory cell when electrons are on the floating gate. By applying the read voltage, the data state in the memory cell can be determined, thereby reading the stored information.

When a read voltage is applied to a target word line, a corresponding change in current or voltage signal in the memory cell occurs. Specifically, referring to fig. 3, the Bit Line is charged during Read, the other word lines WL except the target word Line WL _n are applied with a higher voltage to turn on the cell, the target word Line WL _n is applied with a Read voltage, if electrons are on the floating gate of the cell, the voltage threshold VT is higher (VT 1, the first voltage threshold), if no electrons are on the floating, VT is very low (VT 2, the second voltage threshold), and the Read voltage is between VT1 and VT 2.

Further, a cell may be considered a resistor, when a voltage is applied to the WL, the cell is turned on, and may be considered a resistor with a small resistance, when the voltage on the WL is insufficient to turn on the cell, the cell may be considered a resistor with a large resistance. If the floating gate has electrons, the cell is not conducted, BL (Block) is not discharged, the read flag data is 0, the floating gate has no electrons, the cell can be conducted, BL is put down, and the read flag data is 1.

By applying the on voltage to two sets of adjacent word lines and the remaining word lines and applying the read voltage to the target word line, data in the memory cell can be efficiently read and accuracy and reliability of the data can be ensured.

Optionally, after the step of applying a read voltage to the target word line to obtain the read data on the target word line, the read data on the target word line may be verified in a positive-negative code verification manner, and if the verification is passed, the target parameter data is read to the latch.

In the embodiment of the invention, in order to ensure the correctness of the target parameter data, the positive and negative codes can be written on the target parameter data, and a plurality of copies of the positive and negative codes can be written.

And checking the positive and negative codes, and detecting whether the data is in error in the transmission or storage process by comparing the original value of the data with the negative code value of the data. In NAND FLASH memories, a positive and negative code check is used to ensure that the data read from the target word line is accurate.

Specifically, when a read voltage is applied to a target word line, the memory outputs the read data on that word line. To verify the correctness of the data, an inverse of the data is generated. The way the escape code is generated is typically by inverting each bit of data, i.e. 0 to 1 and 1 to 0. The system then compares the original data with the generated code-reversal. If the two are completely consistent, the data is proved to have no error in the reading process, and the verification is passed, if the difference exists, the data is possibly interfered or damaged, and the verification fails.

Specifically, as shown in fig. 4, fig. 4 is a schematic diagram of a positive and negative code verification method provided in an embodiment of the present invention, where in fig. 4, a plurality of copies, i.e., copy1, copy2, copy3, copy4, are included, and each copy includes a byte1 positive code, a byte1 negative code, a byte2 positive code, and a byte2 negative code.

After the chip is powered on, when Power on read is performed, if verification is passed, the information is read into a latch of the chip, and when a user uses the chip, parameters in the latch are used.

As shown in fig. 4. When Power on read is done, check positive and negative codes based on byte, once the positive and negative code check is not passed, the next copy is read from the byte of fail until all information is correctly read into latch, otherwise status inside chip is set to 1. In the embodiment of the present invention, the target word line and the remaining word lines write information in the manner of fig. 3, and the neighboring halo lines adjacent to the target word line in the Block are all in the FF state (erased state).

Optionally, after the step of verifying the read data, if the verification fails, applying a read voltage to the rest word lines to obtain the read data on the rest word lines, and verifying the read data on the word lines by a positive and negative code verification mode until the verification is successful or all the verification fails.

In the embodiment of the invention, the target parameter data is also written in consideration of the remaining word numbers, so after the verification of the read data of the target word line fails, the read voltage can be applied to the remaining word lines to obtain the read data on the remaining word lines, and the verification method is the same as that of the target word line and is not repeated herein.

Optionally, after the step of reading the target parameter data to the latch, the target parameter data in the latch may also be read to the cache memory, and the NAND FLASH memory may be configured with the target parameter data in the cache memory.

In the embodiment of the invention, the latch is used as a temporary storage element, has the characteristic of quick data access, but is limited by the storage capacity and the access speed, and is not suitable for being used as a storage medium for long-term or large amount of data. Thus, the target parameter data in the latch may be read into a Cache (Cache).

Cache memory is a component of a computer system that is used to temporarily store data for quick access. It is located between the main memory and the processor to improve the overall performance of the system by reducing the number of accesses to the main memory by the processor. In the NAND FLASH memory context, a cache may be used to store frequently accessed or critical data, such as configuration parameters, index information, etc., to enable quick reading when needed.

The process of reading data in latches to cache memory typically involves data movement and cache management policies. That is to say, NAND FLASH reads the target parameter data of the target word line to the latch if the read data of the target word line passes the verification, and reads the target parameter data from the latch to the corresponding cache, NAND FLASH reads the target parameter data from the cache to configure NAND FLASH when the method is applied.

When the target parameter data is successfully read into the cache, it can be used to configure NAND FLASH the memory. In the configuration process, the cache memory has an advantage in its fast access speed. Since configuration parameters typically need to be read and applied prior to memory initialization or specific operations, storing them in cache memory can significantly reduce configuration time and increase the response speed of the memory.

In the embodiment of the invention, the read voltage is a voltage specially used for reading data in the memory cell, and the magnitude of the read voltage is generally configured between the first voltage threshold and the second voltage threshold. The first voltage threshold corresponds to a threshold voltage of the memory cell when electrons are not on the floating gate, and the second voltage threshold corresponds to a threshold voltage of the memory cell when electrons are on the floating gate. By applying the read voltage, the data state in the memory cell can be determined, thereby reading the stored information.

Optionally, the target parameter data includes non-default operating parameter data required by NAND FLASH memory when reading the data.

In the embodiment of the present invention, the target parameter data may be NAND FLASH non-default working parameter data, the default working parameter data of NAND FLASH is fixed parameter data stored in the cache, and the NAND FLASH is configured by the default working parameter data in the cache when the non-default working parameter data of NAND FLASH is not read.

The target parameter data is, for example, a Read voltage applied to a select WL (select word line) at Read. The chip is designed to allow this voltage to range from 0-2V,0.1V to step, and by default the read voltage is 0.1V. However, the experimental result shows that the read voltage is set to 0.5V for best performance of the chip. Then information of read voltage=0.5v will be written in the corresponding Block area of the chip. Voltage information like this is also very much like erase voltage, program voltage, etc. Typically no more than one eighth of a page (memory page) of the chip.

In the embodiment of the present invention, please refer to fig. 3, the same values written in the bit Line direction have electrons in the floating gate or no electrons in the floating gate. For 0, except that electrons are not arranged on the floating gates of WLn+1 and WLn-1 cells, electrons are arranged on the floating gates of the rest cells, the resistance of the whole cell string can be increased, and the probability that the read data is 0 is increased. For 1, no electrons are available for the floating gate on the entire cell string, which does not affect read 1.

Because NAND FLASH CELL has a relatively small pitch, WLn 1 and WLn+1 are not written, as electrons change from none to none on the floating gate of one cell, which affects the VT of the cell adjacent to it.

Referring to fig. 5, fig. 5 is a schematic diagram showing the effect between memory cells according to the embodiment of the present invention, in fig. 5, programming 1 to 0 in the floating gate of cell ②④⑥⑧ has a very significant effect on VT of cell ⑤. Programming a1 to 0 in the floating gate of cell ①③⑦⑨ has some effect on cell ⑤. It can be seen that the voltage effects between cells are strongly related to the distance between cells.

The invention also provides an information storage device of the memory, referring to fig. 6, fig. 6 is a schematic structural diagram of the information storage device of the memory in the hardware running environment according to the embodiment of the invention.

The information storage device of the memory according to the embodiment of the invention can be a computing device such as a desktop computer, a notebook computer, a palm computer, a server and the like. As shown in fig. 6, the information storage of the memory may include a processor 1001 (e.g., CPU), a network interface 1004, a user interface 1003, a memory 1005, and a communication bus 1002. Wherein the communication bus 1002 is used to enable connected communication between these components. The user interface 1003 may include a Display, an input unit such as a Keyboard (Keyboard), and the optional user interface 1003 may also include a standard wired interface, a wireless interface. The network interface 1004 may optionally include a standard wired interface, a wireless interface (e.g., WI-FI interface). The memory 1005 may be a high-speed RAM memory or a stable memory (non-volatile memory), such as a disk memory. The memory 1005 may also optionally be a storage device separate from the processor 1001 described above.

It will be appreciated by those skilled in the art that the information storage device structure of the memory shown in fig. 6 does not constitute a limitation of the information storage device of the memory, and may include more or less components than illustrated, or may combine certain components, or may be arranged in different components.

The invention also provides a memory, which comprises NAND FLASH memories, an information storage device of the memories and a plurality of storage units connected in series, wherein each storage unit corresponds to one word line, and the information storage device of the memory is the information storage device of the memory shown in fig. 6.

As shown in fig. 6, an operating system, a network communication module, a user interface module, and a computer program may be included in the memory 1005, which is a type of computer storage medium.

In the information storage device of the memory shown in fig. 6, the network interface 1004 is mainly used for connecting to a background server and performing data communication with the background server, the user interface 1003 is mainly used for connecting to a client (user side) and performing data communication with the client, and the processor 1001 may be used for calling a computer program stored in the memory 1005, and the computer program is called by the processor 1001 to implement the steps of the information storage method of the memory.

Based on the computer program set forth in the foregoing embodiment, the present invention also provides a storage medium storing the computer program, where the computer program when executed by the controller implements the information storage method of the memory set forth in the foregoing embodiment.

The information storage device, the memory and the storage medium of the memory of the present invention can realize the steps of the information storage method of the memory, so that the information storage device, the memory and the storage medium at least have all the beneficial effects brought by the technical scheme of the information storage method embodiment of the memory, and are not described in detail herein.

In the several embodiments provided in the present application, it should be understood that the disclosed method and apparatus may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, and for example, the division of the modules is merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple modules or components may be combined or integrated into another apparatus, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or modules, which may be in electrical, mechanical, or other forms.

The modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physical modules, i.e., may be located in one place, or may be distributed over a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist alone physically, or two or more modules may be integrated into one module. The integrated modules may be implemented in hardware or in software functional modules.

The integrated modules, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a storage medium, including instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. The storage medium includes a U disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, an optical disk, or other various media capable of storing program codes.

The above description of the preferred embodiments of the present invention should not be taken as limiting the scope of the invention, but rather should be understood to cover all modifications, variations and adaptations of the present invention using its general principles and the following detailed description and the accompanying drawings, or the direct/indirect application of the present invention to other relevant arts and technologies.

Claims

1. A method for storing information in a memory, wherein the memory is NAND FLASH memory, the NAND FLASH memory includes a plurality of memory cells connected in series, each memory cell corresponding to a word line, the method comprising:

Writing target parameter data in a target word line;

each group of adjacent word lines comprises at least one word line, the number of the word lines is determined according to the interference degree between the adjacent word lines, and the greater the interference degree of the adjacent word lines, the more the word lines in each group of adjacent word lines;

writing the target parameter data in the other word lines, wherein the other word lines are word lines except the target word line and the two groups of adjacent word lines;

2. The method of information storage for a memory according to claim 1, wherein after said applying a read voltage to said target word line to obtain read data on said target word line, said method further comprises:

3. The information storage method of a memory according to claim 2, wherein after the verifying the read data, the method further comprises:

4. The information storage method of a memory according to claim 2, wherein after the reading of the target parameter data to a latch, the method further comprises:

reading the target parameter data in the latch to a cache;

5. The method of claim 1, wherein the read voltage is configured to be between a first voltage threshold that is a threshold voltage when electrons are on the floating gate of the memory cell and a second voltage threshold that is a threshold voltage when electrons are not on the floating gate of the memory cell.

6. The method according to any one of claims 1 to 5, wherein the target parameter data includes non-default operation parameter data required for the NAND FLASH memory at the time of reading data.

7. An information storage device of a memory, characterized in that the information storage device of the memory comprises a memory, a processor and a computer program stored on the memory and executable on the processor, which computer program, when being executed by the processor, realizes the steps of the information storage method of the memory according to any one of claims 1 to 6.

8. A memory comprising NAND FLASH memory and an information storage device of the memory, and a plurality of memory cells connected in series, each memory cell corresponding to a word line, wherein the information storage device of the memory is the information storage device of the memory according to claim 7.

9. A storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the information storage method of the memory of any of claims 1 to 7.