CN119806275A

CN119806275A - Current-mode drive circuit

Info

Publication number: CN119806275A
Application number: CN202411845191.1A
Authority: CN
Inventors: 曹建文; 肖浪骐
Original assignee: 3Peak Inc
Current assignee: 3Peak Inc
Priority date: 2024-12-13
Filing date: 2024-12-13
Publication date: 2025-04-11

Abstract

The present disclosure relates to a current-type driving circuit, comprising: an output module (10), comprising a first MOS transistor (M1); a sampling module (20), comprising a second MOS transistor (M2) configured to sample a current flowing through the first MOS transistor (M1); and a loop control module (30), comprising a third MOS transistor (M3) and a comparison module (32), wherein the comparison module is configured to compare the current sampled by the second MOS transistor (M2) with a reference current (Iref1), and output the compared difference to the gate of the third MOS transistor (M3), so that the first MOS transistor (M1) adjusts the output current at an output terminal (OUT) based on the compared difference.

Description

Current type driving circuit

Technical Field

Embodiments of the present disclosure relate generally to driving circuits, and more particularly, to current-mode driving circuits.

Background

Some electronic devices require not only high voltage but also high frequency for driving. In the traditional current type high-voltage driving field, the requirements on speed, precision and large current are difficult to meet at the same time. This is because the output drive current accuracy and speed tend to be incompatible. In terms of frequency, conventional techniques typically employ a current mirror to mirror the current to control the output drive current, but the speed of this drive is relatively slow and there is a large error in high voltage, high current applications. Although the drive output current can be adjusted by providing a loop, this presents a significant challenge for loop stability due to the large parasitic capacitance that the high voltage power transistors present. The loop bandwidth is usually set to a low frequency, which results in a very slow loop response. It is desirable to be able to retrofit conventional current-mode drive circuits.

Disclosure of Invention

Embodiments of the present disclosure provide a current-mode drive circuit that aims to address one or more of the above problems, as well as other potential problems.

According to a first aspect of the present disclosure, a current-mode drive circuit is provided. The current type driving circuit includes an output module including a first MOS transistor and an output terminal, a drain electrode of the first MOS transistor being connected to a power supply node, a source electrode of the first MOS transistor being connected to the output terminal, a sampling module including a second MOS transistor configured to sample a current flowing through the first MOS transistor, a source electrode of the second MOS transistor being connected to the output terminal, a gate electrode of the second MOS transistor being connected to the gate electrode of the first MOS transistor, and a loop control module including a third MOS transistor, a first end of the third MOS transistor being connected to the gate electrode of the second MOS transistor and the gate electrode of the first MOS transistor, and a comparison module configured to compare the current sampled by the second MOS transistor with a reference current, and output a difference value compared to the gate electrode of the third MOS transistor, so that the first MOS transistor adjusts an output current at the output terminal based on the difference value compared.

In some embodiments, the driving circuit further includes a first voltage clamping module configured to clamp a drain voltage of the third MOS transistor, the first voltage clamping module including a first clamping MOS transistor and a second clamping MOS transistor, a source of the first clamping MOS transistor being connected to a first end of the third MOS transistor, a drain of the first clamping MOS transistor being connected to a gate of the second MOS transistor and a gate of the first MOS transistor, a gate of the first clamping MOS transistor being connected to a gate of the second clamping MOS transistor, a source of the second clamping MOS transistor being applied with a first bias current, the first clamping MOS transistor and the second clamping MOS transistor being configured to withstand a first voltage, a source of the first clamping MOS transistor being connected to a first end of the third MOS transistor, a drain of the first clamping MOS transistor being connected to a gate of the second MOS transistor and a gate of the first MOS transistor, the first clamping MOS transistor and the second clamping MOS transistor being configured to operate in a switch mode, the first clamping MOS transistor and the second clamping MOS transistor being configured to operate in a third mode.

In some embodiments, the gate of the first clamp MOS transistor and the gate of the second clamp MOS transistor are connected to a first control node to turn on or off the first clamp MOS transistor and the second clamp MOS transistor based on a potential of the first control node.

In some embodiments, the drive circuit further comprises an impedance attenuation circuit configured to reduce an impedance between the gate of the first MOS transistor and the source of the first MOS transistor.

In some embodiments, the impedance attenuation circuit comprises a first impedance attenuation MOS tube, a second impedance attenuation MOS tube, a resistor, and a resistor, wherein the drain electrode of the first impedance attenuation MOS tube is connected to the grid electrode of the first MOS tube, the source electrode of the first impedance attenuation MOS tube is connected to the output end, the grid electrode of the second impedance attenuation MOS tube is connected to the grid electrode of the first impedance attenuation MOS tube, the source electrode of the second impedance attenuation MOS tube is connected to the output end, the drain electrode of the second impedance attenuation MOS tube is connected to the drain electrode of the second clamp MOS tube, one end of the resistor is connected to the drain electrode of the first impedance attenuation MOS tube, and the other end of the resistor is connected to a first connection node, wherein the grid electrode of the second impedance attenuation MOS tube is connected with the drain electrode of the second impedance attenuation MOS tube.

In some embodiments, the first MOS transistor and the second MOS transistor are laterally diffused metal oxide semiconductor LDMOS.

In some embodiments, the driving circuit further comprises a second voltage clamping module configured to clamp the drain voltage of the first MOS tube and the drain voltage of the second MOS tube, the second voltage clamping module comprising a third clamping MOS tube, a fourth clamping MOS tube, a fifth clamping MOS tube, the source of the third clamping MOS tube being connected to the drain of the second MOS tube, the source of the fourth clamping MOS tube being connected to the drain of the first MOS tube, the drain of the third clamping MOS tube being connected to the gate of the third clamping MOS tube and the gate of the fourth clamping MOS tube, the source of the fifth clamping MOS tube being applied with a second bias current, the third clamping MOS tube, the fourth clamping MOS tube and the fifth clamping MOS tube tolerating the first voltage, the first and the fourth clamping MOS tube being configured to operate in a lower voltage than the first clamping MOS tube, the fourth clamping MOS tube and the fifth clamping MOS tube, wherein the third clamping MOS tube is configured to operate in a higher voltage than the first clamping MOS tube and the fifth clamping MOS tube.

In some embodiments, the drive circuit further includes a current limiting module configured to clamp the gate voltage of the third clamp MOS transistor and the gate voltage of the fourth clamp MOS transistor.

In some embodiments, the current limiting module comprises a zener diode.

In some embodiments, the comparison module includes a first current mirror including a first current mirror MOS transistor configured to convert the sampled current to a first sampled current, a drain of the first current mirror MOS transistor connected to a drain of the second MOS transistor, a source of the first current mirror MOS transistor connected to a source of the second current mirror MOS transistor, and a gate of the first current mirror MOS transistor connected to a gate of the second current mirror MOS transistor.

In some embodiments, the driving circuit further includes a capacitor, one end of the capacitor is connected to a second connection node where the drain of the second current mirror MOS transistor and the gate of the third MOS transistor are connected to each other, the other end of the capacitor is connected to a third connection node where the source of the first current mirror MOS transistor and the source of the first current mirror MOS transistor are connected to each other, and the third connection node is connected to a power supply node.

In some embodiments, the first current mirror further includes a first control MOS transistor, a source of the first control MOS transistor is connected to the third connection node, a drain of the first control MOS transistor is connected to the drains of the two MOS transistors, and a gate of the first control MOS transistor is connected to a second control node to turn on or off the first control MOS transistor based on a potential of the second control node.

In some embodiments, the comparison module further includes a second current mirror that converts a first reference current (Iref 2) to the reference current, the second current mirror including a third current mirror MOS transistor and a fourth current mirror MOS transistor, a gate of the third current mirror MOS transistor being connected to a gate of the fourth current mirror MOS transistor, a source of the third current mirror MOS transistor being connected to a source of the fourth current mirror MOS transistor, a drain of the third current mirror MOS transistor being connected to the second connection node, a drain of the fourth current mirror MOS transistor being configured to receive the first reference current.

In some embodiments, the second current mirror further includes a second control MOS transistor, a gate of the second control MOS transistor is connected to a third control node, and a drain of the second control MOS transistor is connected to a gate of the fourth current mirror MOS transistor and a gate of the third current mirror MOS transistor to turn on or off the second control MOS transistor based on a potential of the third control node.

A loop design according to the present disclosure may be able to achieve accurate sampling and fast response performance.

Drawings

The above, as well as additional purposes, features, and advantages of embodiments of the present disclosure will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown by way of example, and not by way of limitation.

Fig. 1 shows a schematic circuit diagram of a current-mode drive circuit according to a first embodiment of the present disclosure.

Fig. 2 shows a schematic circuit diagram of a current-mode drive circuit according to a second embodiment of the present disclosure.

Fig. 3 shows a schematic circuit diagram of a current-mode drive circuit according to a third embodiment of the present disclosure.

Like or corresponding reference characters indicate like or corresponding parts throughout the several views.

Detailed Description

Preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While the preferred embodiments of the present disclosure are illustrated in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In many electronic apparatuses, it is necessary to realize high-frequency driving in addition to precisely controlling the driving current. As an application example, in a driving application of a light emitting tube or the like, the switching frequency of the apparatus is becoming higher. In addition, these applications are often accompanied by high voltages and high currents.

In the traditional current type high-voltage driving field, the requirements on speed, precision and large current are difficult to meet at the same time. In contrast, the voltage type driving can be rapidly turned on and off by a logic chain, and the current type driving is very difficult. As described in the background section, although the accuracy of the output current for driving can be controlled by a loop, a high-voltage power tube brings a large parasitic capacitance at the time of high-frequency driving, which affects the loop stability. Once the bandwidth of the loop is set to a lower frequency, this results in a very slow loop response speed, which is not suitable for high frequency applications.

According to the present disclosure, a current-type driving circuit, in particular a large driving current, is proposed, which is capable of solving one or more of the above-mentioned technical problems. Specific implementation structures of the current-mode driving circuit according to the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

Fig. 1 shows a schematic circuit diagram of a current-mode drive circuit 100 according to a first embodiment of the present disclosure. As shown in fig. 1, the driving circuit 100 includes an output module 10, a sampling module 20, and a loop control module 30. The output module 10 includes a first MOS transistor M1 and an output terminal OUT. The first MOS transistor M1 is a main power transistor, and a source of the first MOS transistor M1 is connected to the output terminal OUT. The drain of the first MOS transistor M1 is connected to a power supply node VM configured to provide a high voltage, for example, several tens of volts. In some embodiments, the voltage is, for example, 10v to 100 v. The sampling module 20 includes a second MOS transistor M2, where the second MOS transistor M2 is a sampling MOS transistor and is configured to sample a current flowing through the first MOS transistor M1. The source of the second MOS transistor M2 is connected to the output terminal OUT, and the Gate of the second MOS transistor M2 is connected to the Gate (denoted hs_gate in the figure) of the first MOS transistor M1. In the illustrated embodiment, M1, M2 are high voltage N-type LDMOS, it being understood that M1, M2 may also be P-type LDMOS.

The loop control module 30 includes a third MOS transistor M3 and a comparison module 32. The first end of the third MOS transistor M3 is connected to the gate of the second MOS transistor M2 and the gate of the first MOS transistor M1. In the illustrated embodiment, M3 is a PMOS transistor, and the first end corresponds to the drain of the PMOS transistor. It should be appreciated that this is merely exemplary, and that M3 may also be an NMOS transistor, with the first end corresponding to the source of the NMOS transistor. The comparison module 32 may be a differential comparator, and the comparison module 32 is configured to compare the current sampled by the second MOS transistor M2 with the reference current Iref1, and output the difference value generated by the comparison to the gate of the third MOS transistor M3, and amplified by the third MOS transistor M3, and output the gate of the first MOS transistor M1 and the gate of the second MOS transistor M2. Thus, the first MOS transistor M1 adjusts the output current at the output terminal OUT based on the current from the third MOS transistor M3.

According to the present disclosure, the first MOS transistor M1, the second MOS transistor M2, and the third MOS transistor M3 all operate in a proportional mode, i.e., in an analog region, and the output current at the output terminal OUT can be accurately regulated by the loop control module 30 based on the reference current Iref 1. In operation, the comparing module 32 can compare the current sampled by the second MOS transistor M2 with the reference current Iref1, and output the difference value generated by the comparison to the gate of the third MOS transistor M3 for amplification, and the amplified current is further output to the gate of the first MOS transistor M1 and the gate of the second MOS transistor M2, so that the output current at the output terminal OUT can be accurately controlled.

In some embodiments, as shown in fig. 1, the first MOS transistor and the second MOS transistor may be MOS transistors that are subjected to high voltage, for example, may be LDMOS transistors that are laterally diffused, and the third MOS transistor M3 may be a normal MOS transistor (for example, a conventional NMOS transistor or PMOS transistor) and is subjected to low voltage lower than the high voltage to which the first MOS transistor and the second MOS transistor are subjected. This is particularly suitable for application scenarios when the power supply node VM is high voltage (e.g. tens of volts).

In some embodiments, as shown in fig. 1, the driving circuit 100 may further include a first voltage clamping module 40 configured to clamp the drain voltage of the third MOS transistor M3. By clamping the drain voltage of the third MOS transistor M3, the third MOS transistor M3 can be used in high voltage applications.

In some embodiments, as shown in fig. 1, the first voltage clamping module 40 may include a first clamping MOS transistor QM1 and a second clamping MOS transistor QM2. The first clamp MOS transistor QM1 and the second clamp MOS transistor QM2 operate in a switch mode. The first clamp MOS transistor QM1 may be connected in series between the drain of the third MOS transistor M3 and the gate of the first MOS transistor M1, the gate of the first clamp MOS transistor QM1 may be connected to the gate of the second clamp MOS transistor QM2, and the source of the second clamp MOS transistor QM2 may be applied with the first bias current Ib. The drain of the second clamp MOS transistor QM2 may be connected to the drain of the second impedance attenuating MOS transistor ZM 2. In some embodiments, the gate of the first clamp MOS transistor QM1 and the gate of the second clamp MOS transistor QM2 may also be connected to a control node, and the turn-on and turn-off of the first clamp MOS transistor QM1 and the second clamp MOS transistor QM2 may be controlled based on the voltage at the control node. In the illustrated embodiment, QM1 and QM2 employ P-type LDMOS. It should be understood that the illustrated embodiment is merely exemplary, and that QM1 and QM2 may also employ N-type LDMOS.

A loop design according to the present disclosure may be able to achieve accurate sampling and fast response performance. The output current for driving mainly comes from the power tube M1, in some embodiments, the sampling tube M1 will have a detection current of mA level, M3 will also have a regulation current of mA level, and the rest of the MOS tubes are all currents of uA level. The mA level current on M2 flows to the driving output current, which reduces the size of the power tube to a certain extent, and on the other hand, the current on the power supply voltage VM flows into the driving output as much as possible instead of the internal circuit consumption, thereby reducing the energy loss.

In some embodiments, M3 may employ an NMOS structure because the NMOS size is smaller than the PMOS for the same current capability, thus reducing chip area with an NMOS architecture. It should be understood that this is merely exemplary, and that M3 may also take the PMOS structure. In the present disclosure, by using the MOS transistor M3 instead of the charge pump, it is possible to further reduce the chip area.

In addition, in some embodiments, it is also desirable to increase the Headroom (Headroom) of M1 and M2 as much as possible, and in the case of P-type LDMOS for M2, the gate-source voltage Vgs of M2 is fully opened, and the drain-source voltage Vds is small, which is equivalent to outputting the drain terminal of M3 to the gates of M1 and M2. When OUT approaches VM, the headroom of M1 and M2 depends on the sum of the gate-source voltage Vgs of M1 and M2 and the drain-source voltage of M3. As an example, the M3 drain-source voltage may be set to a few hundred mV, in which case the headroom between OUT and VM may be between 1-2V at a minimum, the above-described circuit design meeting the requirements for many applications.

According to the current comparison method, a fast response loop can be realized, the driving output current can be accurately regulated, but a power tube (for M1 and M2 for example) in a driving circuit has large parasitic capacitance, and the loop stability can be influenced. The greater the effect of such parasitic capacitance when the loop control module 30 is operating in the high frequency region. In some embodiments, the drive circuit 100 is also provided with an impedance attenuation circuit 50 to increase the bandwidth of the loop.

As shown in fig. 1, the driving circuit 100 may further include an impedance attenuation circuit 50. The impedance attenuation circuit 50 is configured to reduce the impedance between the gate of the first MOS transistor M1 and the source of the first MOS transistor M1. In some embodiments, as shown in fig. 1, the impedance attenuation circuit 50 may include a first impedance attenuation MOS transistor ZM1, a second impedance attenuation MOS transistor ZM2, and a resistor R1. The drain electrode of the first impedance attenuation MOS tube ZM1 is connected to the grid electrode of the first MOS tube M1, and the source electrode of the first impedance attenuation MOS tube ZM1 is connected to the output end OUT. The gate of the second impedance attenuation MOS transistor ZM2 is connected to the gate of the first impedance attenuation MOS transistor ZM1, and the source of the second impedance attenuation MOS transistor ZM2 is connected to the output terminal OUT. One end of the resistor R1 is connected to the drain electrode of the first impedance attenuation MOS tube ZM1, and the other end of the resistor R1 is connected to a first connection node P1, wherein the grid electrode of the second impedance attenuation MOS tube ZM2 is connected with the drain electrode of the second impedance attenuation MOS tube ZM 2.

According to the present disclosure, as shown in the embodiment of fig. 1, the impedance between hs_gate and the source of the first MOS transistor M1 can be reduced by the low impedance path configured by ZM1, ZM2, and R1. Thus, bias current Ib flows through QM2 into ZM2, thereby establishing a voltage for a bias of the low-resistance path. The bias current Ib is significantly smaller than the current of the loop in which M2 is located. The principle of the low impedance path increasing the loop bandwidth is described in detail below.

After the loop is established, the current M3 flows to ZM2 and Ib is negligible. ZM1 and ZM2 have the same gate-source voltage and may be low voltage MOS transistors. ZM1, ZM2 both operate in a proportional mode. ZM2 is low current, ZM1 is mA class current, and the current of the two currents is mirror proportion N1. In some embodiments, ZM2 is a small current, on the order of uA, and resistor R1 is typically on the order of KΩ in an integrated circuit design. Therefore, the equivalent resistance of the impedance decay circuit can be reduced to:

Therefore, the equivalent resistance Req can be determined by adjusting the resistance value of R1, the mirror ratio between ZM1 and ZM 2. By the selection of the low impedance path and the parameters described above, the bandwidth of the loop can be effectively widened even if there is a high impedance node (e.g. a current mirror) in the comparison module 32 and a large parasitic capacitance node (e.g. an LDMOS tube) in the loop.

Fig. 2 shows a schematic circuit diagram of a current-mode drive circuit 200 according to a second embodiment of the present disclosure. The embodiment shown in fig. 2 is similar to the embodiment shown in fig. 1, and the differences are described with emphasis, and the description of the same parts thereof is omitted.

In some embodiments, as shown in fig. 2, the comparison module 32 may further include a first current mirror and a capacitor C1. The first current mirror comprises a first current mirror MOS tube JM1 and a second current mirror MOS tube JM2. The first current mirror MOS transistor JM1 is configured to convert the sampled current into a first sampled current. The drain of the first current mirror MOS transistor JM1 is connected to the drain of the second MOS transistor M2, the source of the first current mirror MOS transistor JM1 is connected to the source of the second current mirror MOS transistor JM2, and the gate of the first current mirror MOS transistor JM1 is connected to the gate of the second current mirror MOS transistor JM2. One end of the capacitor C1 is connected to the second connection node P2 where the drain of the second current mirror MOS transistor JM2 and the gate of the third MOS transistor M3 are connected to each other, the other end of the capacitor C1 is connected to the third connection node P3 where the source of the first current mirror MOS transistor JM1 and the source of the first current mirror MOS transistor JM1 are connected to each other, and the third connection node P3 is connected to the power supply node VM. By setting the capacitor C1, the bandwidth of the loop can be further adjusted.

In some embodiments, comparison module 32 may also include a second current mirror that converts first reference current Iref2 to reference current Iref 1. The second current mirror includes a third current mirror MOS transistor JM3 and a fourth current mirror MOS transistor JM4, a gate of the third current mirror MOS transistor JM3 is connected to a gate of the fourth current mirror MOS transistor JM4, a source of the third current mirror MOS transistor JM3 is connected to a source of the fourth current mirror MOS transistor JM4, a drain of the third current mirror MOS transistor JM3 is connected to the second connection node P2, and a drain of the fourth current mirror MOS transistor JM4 is configured to receive the first reference current Iref2.

The design of loop stability is primarily concerned with high impedance nodes and large parasitic capacitance nodes, both of which are prone to pole introduction. The outputs of the drain terminals of JM2 and JM3 are high impedance nodes, and the gates HS_Gate of the power transistors M1 and M2 are large capacitance nodes. In some embodiments, considering the low power circuit design, the JM3 and JM2 currents are smaller, the output impedance is larger, the node P2 can be considered to be the main pole of the loop, and the main pole can be set in the mid-band by introducing the capacitor C1 into the node. The gates hs_gate of the power transistors M1 and M2 introduce a large capacitance, and the pole at the node P2 is pushed to a high frequency. The parasitic capacitance of the power tube M1 and the low impedance Req form a high-frequency pole. Therefore, the loop bandwidth is expanded by pushing the pole at the grid electrode HS_gate of the power tube to a high frequency so as to realize quick loop response.

In some embodiments, the drive circuit 100 may also include one or more control nodes to control the activation of the respective modules of the drive circuit 100. In some embodiments, as shown in fig. 2, the gate of the first clamp MOS transistor QM1 and the gate of the second clamp MOS transistor QM2 are connected to the first control node. The first control node may be a logic control node hs_ctrl_b, and the first clamp MOS transistor QM1 and the second clamp MOS transistor QM2 are turned on or off based on a level of the logic control node hs_ctrl_b.

In some embodiments, as shown in fig. 2, the first current mirror may further include a first control MOS transistor CM1, a source of the first control MOS transistor CM1 is connected to the third connection node P3, a drain of the first control MOS transistor CM1 is connected to a drain of the second MOS transistor M2, and a gate of the first control MOS transistor CM1 is connected to the second control node. The second control node is a logic control node hs_ctrl, and the first control MOS transistor CM1 is turned on or off based on the potential of the second control node.

In some embodiments, as shown in fig. 2, the second current mirror may further include a second control MOS transistor CM2, a gate of the second control MOS transistor CM2 is connected to the third control node hs_ctrl_b, a drain of the second control MOS transistor CM2 is connected to a gate of the fourth current mirror MOS transistor JM4 and a gate of the third current mirror MOS transistor JM3, and the second control MOS transistor CM2 is turned on or off based on a potential of the third control node.

In some embodiments, as shown in fig. 2 and 3, the first control node and the third control node are connected to the same logic potential, while the second control node is connected to an opposite logic potential. It should be understood that the illustrated logic is exemplary.

In some embodiments, as shown in fig. 2, hs_ctrl is control logic that turns the drive circuit on and off, when hs_ctrl is high, the drive circuit is on, and when hs_ctrl is low, the drive circuit is off. Iref2 is a driving reference current, which may be generated from the outside or from the inside of the chip, and the driving output current Iout is proportional to Iref 2. VM is a high voltage supply voltage source, FGND is a floating reference potential, and the pressure difference between VM and FGND is low (e.g., no more than 5.5V). OUT is the drive output, which varies from GND to VM. ZM1 and ZM2 float the voltage domain between OUT to the power tube gate.

When hs_ctrl is high, hs_ctrl_b is low, CM1 and CM2 are off, and QM1 and QM2 are on when the driving circuit shown in fig. 2 is in operation. Iref2 is mirrored by JM 1to JM2 as reference current Iref1, and the drive output current Iout is regulated by the loop. M1 and M2 have the same gate-source voltage Vgs, and the drain-source voltages Vds of both differ only by the gate-source voltage JM 1. Considering the channel modulation effect of the high-voltage LDMOS, the drain-source voltages of M1 and M2 have small differences. In high voltage applications of tens of volts, M2 is almost also able to accurately sample the current of M1. It should be understood that the illustrated embodiments are merely exemplary, and that the control logic of each node may take other implementations based on different MOS transistors.

Fig. 3 shows a schematic circuit diagram of a current-mode drive circuit 300 according to a third embodiment of the present disclosure. The embodiment shown in fig. 3 is similar to the embodiment shown in fig. 2, with the difference that the description thereof is focused on, and the description of the same parts thereof is omitted. In the embodiment shown in fig. 2, the power transistors M1 and M2 are MOS transistors (e.g., LDMOS) that are subjected to high voltage. M1, M2 are arranged in the loop and thus their gain has a significant effect on the performance of the loop. In the integrated circuit process, the LDMOS has the minimum channel length, which is mainly convenient for the use of the voltage type driving circuit, but has less attention to the analog characteristic of the LDMOS tube. This can result in the analog (i.e., proportional) characteristics of M1, M2 being unsatisfactory in some cases. In the embodiment shown in fig. 3, the high voltage-bearing power transistors M1, M2 in the loop are replaced with low voltage MOS transistors (e.g., NMOS or PMOS), which has the advantage of further improving the loop performance.

In some embodiments, as shown in fig. 3, M1 and M2 are low-voltage MOS transistors, e.g., NMOS or PMOS. The driving circuit 300 may further include a second voltage clamping module configured to clamp the drain voltage of the first MOS transistor M1 and the drain voltage of the second MOS transistor M2. The second voltage clamping module comprises a third clamping MOS tube QM3, a fourth clamping MOS tube QM4 and a fifth clamping MOS tube QM5. The source of the third clamp MOS transistor QM3 is connected to the drain of the second MOS transistor M2, the source of the fourth clamp MOS transistor QM4 is connected to the drain of the first MOS transistor M1, the gate of the third clamp MOS transistor QM3 is connected to the gate of the fourth clamp MOS transistor QM4, the drain of the fifth clamp MOS transistor QM5 is connected to the gate of the third clamp MOS transistor QM3 and the gate of the fourth clamp MOS transistor QM4, and the source of the fifth clamp MOS transistor QM5 is applied with the second bias current Ib1.

According to the present disclosure, the third clamp MOS transistor QM3, the fourth clamp MOS transistor QM4, and the fifth clamp MOS transistor QM5 are tolerant to the first voltage, and the first MOS transistor M1 and the second MOS transistor M2 are configured as MOS transistors tolerant to the second voltage lower than the first voltage. M1, M2 are low-voltage MOS tubes, have fine analog characteristic. The output current of M3 adjusts the gate potentials of M1 and M2 at the equivalent impedance Req. QM3, QM4, QM5 will not act in the loop gain. Therefore, the MOS tube is low-voltage in loop adjustment, and the performance can be further ensured.

In some embodiments, as shown in fig. 3, the driving circuit 300 further includes a current limiting module configured to clamp the gate voltage of the third clamp MOS transistor QM3 and the gate voltage of the fourth clamp MOS transistor QM 4. In some embodiments, the current limiting module may include a zener diode Z1 to clamp the gate voltages of QM3 and QM4 with Z1 to turn QM3 and QM4 on. Ib1 is the bias current of Z1. QM5 is, for example, a high voltage P-type LDMOS transistor, and is used to clamp a low voltage MOS transistor. When the high-side driving is on, QM5 is on, and when the high-side driving is off, QM5 is off, there is no current on Z1, and the gate voltages of power transistors QM3 and QM4 are pulled low.

According to the method and the device, the high-voltage LDMOS is nested into the low-voltage MOS tube, so that errors caused by inaccurate high-voltage LDMOS tube can be avoided, and the driving output current can be better regulated. On the other hand, the driving circuit has a current limiting function. The gate voltage of QM3 is clamped by Z1, which is a fixed superposition of QM3 gate-source voltage and M1 drain-source voltage. When the OUT or reference current generating circuit is short-circuited, the gate-source voltage Vgs of M1 is rapidly increased, and if the driving output current is to be increased, the gate-source voltage Vgs of QM3 is to be increased, so that the drain-source voltage of M1 is reduced, M1 is caused to enter a linear region, and finally, the currents on QM3 and M1 reach an equilibrium state. Thereby, the current limiting function can be realized. By limiting the maximum current that the drive circuit can output, the drive circuit is protected in a short circuit state, and the reliability of the drive circuit is improved. On the other hand, the low-voltage MOS transistor is used for adjusting the output driving current in the loop, and has smaller area than the high-voltage LDMOS transistor under the same current capacity, so that the parasitic capacitance of the grid electrode of the low-voltage MOS transistor is reduced, the secondary point frequency can be set at a higher frequency, the loop bandwidth is further increased, and the high-speed response is realized more conveniently, so that the high-frequency application is met.

Moreover, although operations are depicted in a particular order, this should be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the present disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are example forms of implementing the claims.

The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the technical improvements in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A current-type driving circuit, comprising:

An output module (10) comprises a first MOS transistor (M1) and an output end (OUT), wherein the drain of the first MOS transistor (M1) is connected to a power supply node (VM), and the source of the first MOS transistor (M1) is connected to the output end (OUT);

a sampling module (20), comprising a second MOS transistor (M2) configured to sample the current flowing through the first MOS transistor (M1), the source of the second MOS transistor (M2) being connected to the output terminal (OUT), and the gate of the second MOS transistor (M2) being connected to the gate of the first MOS transistor (M1); and

The loop control module (30) comprises:

a third MOS transistor (M3), wherein a first end of the third MOS transistor (M3) is connected to a gate of the second MOS transistor (M2) and a gate of the first MOS transistor (M1); and

A comparison module (32) is configured to compare the current sampled by the second MOS transistor (M2) with a reference current (Iref1), and output the compared difference to the gate of the third MOS transistor (M3), so that the first MOS transistor (M1) adjusts the output current at the output terminal (OUT) based on the compared difference.

2. The driving circuit according to claim 1, wherein the driving circuit further comprises a first voltage clamping module (40) configured to clamp the drain voltage of the third MOS tube (M3); the first voltage clamping module (40) comprises a first clamping MOS tube (QM1) and a second clamping MOS tube (QM2);

The source of the first clamping MOS transistor (QM1) is connected to the first end of the third MOS transistor (M3), and the drain of the first clamping MOS transistor (QM1) is connected to the gate of the second MOS transistor (M2) and the gate of the first MOS transistor (M1);

The gate of the first clamping MOS transistor (QM1) is connected to the gate of the second clamping MOS transistor (QM2), and a first bias current (Ib) is applied to the source of the second clamping MOS transistor (QM2);

The first clamping MOS transistor (QM1) and the second clamping MOS transistor (QM2) are configured to withstand a first voltage, and the third MOS transistor (M3) is configured to withstand a second voltage lower than the first voltage;

The first clamping MOS transistor (QM1) and the second clamping MOS transistor (QM2) are configured to operate in a switch mode, and the first MOS transistor (M1), the second MOS transistor (M2) and the third MOS transistor (M3) are configured to operate in a proportional mode.

3. The driving circuit according to claim 2, wherein the gate of the first clamping MOS transistor (QM1) and the gate of the second clamping MOS transistor (QM2) are connected to a first control node so as to turn on or off the first clamping MOS transistor (QM1) and the second clamping MOS transistor (QM2) based on the potential of the first control node.

4. The driving circuit according to any one of claims 2 to 3, further comprising an impedance attenuation circuit (50), wherein the impedance attenuation circuit (50) is configured to reduce the impedance between the gate of the first MOS transistor (M1) and the source of the first MOS transistor (M1).

5. The driving circuit according to claim 4, wherein the impedance attenuation circuit (50) comprises:

a first impedance attenuation MOS transistor (ZM1), wherein the drain of the first impedance attenuation MOS transistor (ZM1) is connected to the gate of the first MOS transistor (M1), and the source of the first impedance attenuation MOS transistor (ZM1) is connected to the output end (OUT);

a second impedance attenuation MOS transistor (ZM2), wherein the gate of the second impedance attenuation MOS transistor (ZM2) is connected to the gate of the first impedance attenuation MOS transistor (ZM1), the source of the second impedance attenuation MOS transistor (ZM2) is connected to the output end (OUT), and the drain of the second impedance attenuation MOS transistor (ZM2) is connected to the drain of the second clamping MOS transistor (QM2); and

A resistor (R1), one end of the resistor (R1) is connected to the drain of the first impedance reduction MOS transistor (ZM1), and the other end of the resistor (R1) is connected to a first connection node (P1) at which the gate of the second impedance reduction MOS transistor (ZM2) is connected to the drain of the second impedance reduction MOS transistor (ZM2).

6. The driving circuit according to any one of claims 2 to 3 and 5, wherein the first MOS transistor (M1) and the second MOS transistor (M2) are laterally diffused metal oxide semiconductors (LDMOS).

7. The driving circuit according to any one of claims 1 to 3 and 5, wherein the driving circuit further comprises a second voltage clamping module configured to clamp the drain voltage of the first MOS tube (M1) and the drain voltage of the second MOS tube (M2),

The second voltage clamping module includes a third clamping MOS transistor (QM3), a fourth clamping MOS transistor (QM4), and a fifth clamping MOS transistor (QM5).

The source of the third clamping MOS transistor (QM3) is connected to the drain of the second MOS transistor (M2), the source of the fourth clamping MOS transistor (QM4) is connected to the drain of the first MOS transistor (M1),

The gate of the third clamping MOS transistor (QM3) is connected to the gate of the fourth clamping MOS transistor (QM4),

The drain of the fifth clamping MOS transistor (QM5) is connected to the gate of the third clamping MOS transistor (QM3) and the gate of the fourth clamping MOS transistor (QM4), and the second bias current (Ib1) is applied to the source of the fifth clamping MOS transistor (QM5);

The third clamping MOS transistor (QM3), the fourth clamping MOS transistor (QM4) and the fifth clamping MOS transistor (QM5) are tolerant to a first voltage, and the first MOS transistor (M1) and the second MOS transistor (M2) are configured as MOS transistors tolerant to a second voltage lower than the first voltage;

The third clamping MOS transistor (QM3), the fourth clamping MOS transistor (QM4) and the fifth clamping MOS transistor (QM5) are configured to operate in a switching mode, and the first MOS transistor (M1), the second MOS transistor (M2) and the third MOS transistor (M3) are configured to operate in a proportional mode.

8. The driving circuit according to claim 7, further comprising a current limiting module, wherein the current limiting module is configured to clamp the gate voltage of the third clamping MOS tube (QM3) and the gate voltage of the fourth clamping MOS tube (QM4).

9 . The driving circuit according to claim 8 , wherein the current limiting module comprises a Zener diode.

10. The driving circuit according to any one of claims 1-3, 5, 8, and 9, wherein the comparison module (32) comprises a first current mirror, the first current mirror comprises a first current mirror MOS tube (JM1) and a second current mirror MOS tube (JM2), the first current mirror MOS tube (JM1) being configured to convert the sampled current into a first sampling current,

The drain of the first current mirror MOS tube (JM1) is connected to the drain of the second MOS tube (M2), the source of the first current mirror MOS tube (JM1) is connected to the source of the second current mirror MOS tube (JM2), and the gate of the first current mirror MOS tube (JM1) is connected to the gate of the second current mirror MOS tube (JM2).

11. The driving circuit according to claim 10, further comprising a capacitor (C1), one end of the capacitor (C1) being connected to a second connection node (P2) at which the drain of the second current mirror MOS tube (JM2) and the gate of the third MOS tube (M3) are interconnected, the other end of the capacitor (C1) being connected to a third connection node (P3) at which the source of the first current mirror MOS tube (JM1) and the source of the first current mirror MOS tube (JM1) are interconnected, and the third connection node (P3) is connected to a power supply node (VM).

12. The driving circuit according to claim 11, wherein the first current mirror further comprises a first control MOS tube (CM1), a source of the first control MOS tube (CM1) being connected to the third connection node (P3), a drain of the first control MOS tube (CM1) being connected to the drain of the second MOS tube (M2), and a gate of the first control MOS tube (CM1) being connected to a second control node so as to turn on or off the first control MOS tube (CM1) based on the potential of the second control node.

13. The driving circuit according to claim 12, wherein the comparison module (32) further comprises a second current mirror for converting the first reference current (Iref2) into the reference current (Iref1), the second current mirror comprising a third current mirror MOS tube (JM3) and a fourth current mirror MOS tube (JM4), the gate of the third current mirror MOS tube (JM3) being connected to the gate of the fourth current mirror MOS tube (JM4), the source of the third current mirror MOS tube (JM3) being connected to the source of the fourth current mirror MOS tube (JM4), the drain of the third current mirror MOS tube (JM3) being connected to the second connection node (P2), and the drain of the fourth current mirror MOS tube (JM4) being configured to receive the first reference current (Iref2).

14. The driving circuit according to claim 13, wherein the second current mirror further comprises a second control MOS tube (CM2), a gate of the second control MOS tube (CM2) being connected to a third control node, a drain of the second control MOS tube (CM2) being connected to a gate of the fourth current mirror MOS tube (JM4) and a gate of the third current mirror MOS tube (JM3), so as to turn on or off the second control MOS tube (CM2) based on the potential of the third control node.