CN119780684A - Scanning chain fault positioning method and system based on special chain diagnosis vector - Google Patents
Scanning chain fault positioning method and system based on special chain diagnosis vector Download PDFInfo
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Abstract
本发明公开了一种基于专用链诊断向量的扫描链故障定位方法及系统，该方法首先通过链测试确定待测的功能电路扫描链中存在的故障类型，然后针对每一位触发器生成对应的专用链诊断向量，其中，该触发器及其下游触发器对应位置，根据所述故障类型设置为故障值；调整功能电路输入值，使得该触发器的上一位触发器捕获到故障值的相反值；最后利用所述专用链诊断向量进行扫描链故障测试，得到发生故障的触发器位置。本发明通过生成针对每一位扫描触发器的专用链诊断向量，并结合电路逻辑分析，能够更加准确地定位扫描链中的故障位置。
The present invention discloses a scan chain fault location method and system based on a dedicated chain diagnostic vector. The method first determines the fault type existing in the scan chain of the functional circuit to be tested through chain testing, and then generates a corresponding dedicated chain diagnostic vector for each bit of trigger, wherein the corresponding position of the trigger and its downstream trigger is set to a fault value according to the fault type; the functional circuit input value is adjusted so that the previous trigger of the trigger captures the opposite value of the fault value; finally, the scan chain fault test is performed using the dedicated chain diagnostic vector to obtain the position of the trigger where the fault occurs. The present invention can more accurately locate the fault position in the scan chain by generating a dedicated chain diagnostic vector for each bit of scan trigger and combining it with circuit logic analysis.
Description
Technical Field
The invention relates to the field of integrated circuit testability design, in particular to a scan chain fault positioning method and system based on a special chain diagnosis vector.
Background
Scan test (SCAN TESTING) is a method of fault detection of digital circuits, particularly Integrated Circuits (ICs), and has been widely used to detect defects generated during integrated circuit fabrication and to achieve high test coverage. The method effectively tests the functions and performances of the complex circuit by utilizing the scanning chain structure through scanning and controlling the internal state of the circuit. The core principle of a scan chain is to connect a plurality of flip-flops in series into a chain by a specific circuit design so that an external test vector can enter the chain in turn, thereby sequentially activating and controlling each flip-flop of the circuit. The design enables test signals to be transmitted through the scan chain, and sets states inside the circuit, so that effective testing of functions inside the circuit is achieved.
However, the integrity of scan chains remains a significant challenge for scan testing. The scan chain is composed of a plurality of flip-flops in series, and in different circuit designs, there is a difference in chip area consumed by the scan element, the chain connection, and the control circuit, in which the scan element and the clock portion may occupy about 30% of the chip area. More importantly, the incidence of scan chain failures varies from design to design, typically between 10% and 30%, while scan chain failures account for almost 50% of chip failures. Thus, accurate diagnosis of faults in the scan chain is critical to ensure the validity of the scan test.
At present, a method for realizing scan chain fault positioning based on simulation and the like generally uses a traditional test vector to process an obtained simulation result to position the position of a scan chain fault, however, the traditional test vector generation mainly aims at fault detection of a functional part of a circuit, and indexes which are generally concerned include fault coverage rate, test vector quantity, test time and the like. Not specifically generated for chain diagnosis, the generation process does not consider the specificity of the chain structure, and the efficiency and the accuracy in the fault positioning of the scanning chain are low.
Disclosure of Invention
The invention aims to provide the scan chain fault positioning method and system based on the special chain diagnosis vector, which have high accuracy and high diagnosis speed.
The technical scheme is that the scan chain fault positioning method based on the special chain diagnosis vector comprises the following steps:
step 1, determining the fault type existing in a functional circuit scanning chain to be tested through chain test, wherein the fault type is stuck-at-1 fault or stuck-at-0 fault, and the corresponding fault value is 1 or 0;
Step 2, generating a corresponding special chain diagnosis vector for each trigger, wherein the corresponding positions of the trigger and the downstream trigger are set as fault values according to the fault types;
and step 3, performing scan chain fault test by using the special chain diagnosis vector to obtain the position of the failed trigger.
In step 1, a circuit netlist file inserted into a scan chain is read in, stuck-at-1 and stuck-at-0 faults are injected into each trigger in the scan chain to obtain a fault circuit netlist, and periodic test vectors are used for carrying out chain test to judge fault types in the functional circuit scan chain.
Further, in step 2, in the dedicated chain diagnostic vector, the corresponding position of the upstream trigger of the trigger is an irrelevant bit, and is randomly set to 0 or 1.
Further, in step 2, the method for adjusting the input value of the functional circuit so that the flip-flop of the previous bit of the flip-flop captures the opposite value of the fault value includes:
And setting constraint conditions, namely setting the corresponding positions of the trigger and the downstream trigger thereof in the special chain diagnosis vector as fault values, and obtaining input combinations meeting the constraint conditions by traversing all possible input combination calculation function circuit outputs.
Further, in step 2, the capture value of the trigger is set to the opposite value of the fault value.
Further, step 3 specifically includes saving the chain diagnostic vector and generating a testbench file corresponding to the chain diagnostic vector, and performing scan chain fault test by using the testbench file to obtain a position of a faulty trigger.
The invention relates to a scan chain fault positioning system based on special chain diagnosis vector, which comprises:
The fault type test unit is used for determining the fault type existing in the functional circuit scanning chain to be tested through chain test, wherein the fault type is stuck-at-1 fault or stuck-at-0 fault, and the corresponding fault value is 1 or 0;
The special chain diagnosis vector generation unit is used for generating a corresponding special chain diagnosis vector for each trigger, wherein the corresponding position of the trigger and the downstream trigger thereof is set as a fault value according to the fault type;
And the scan chain fault test unit is used for performing scan chain fault test by using the special chain diagnosis vector to obtain the position of the failed trigger.
Further, in the fault type test unit, a circuit netlist file inserted into a scan chain is read in, and a stuck-at-1 and stuck-at-0 fault is injected into each trigger in the scan chain to obtain a fault circuit netlist;
in the special chain diagnosis vector generation unit, the corresponding position of the upstream trigger of the trigger is an irrelevant bit, and is randomly set to 0 or 1;
In a dedicated chain diagnostic vector generation unit, a method of adjusting functional circuit input values such that a previous flip-flop of the flip-flop captures an opposite value of a fault value, comprising:
setting constraint conditions, an input port and an output port, wherein the constraint conditions are that the corresponding positions of the trigger and a downstream trigger thereof in a special chain diagnosis vector are fault values, and obtaining input combinations meeting the constraint conditions by traversing all possible input combination calculation function circuit outputs;
in the dedicated chain diagnosis vector generation unit, the capture value of the trigger is set to the opposite value of the fault value;
And in the scan chain fault test unit, a chain diagnosis vector is stored, a testbench file corresponding to the chain diagnosis vector is generated, and the scan chain fault test is carried out by utilizing the testbench file, so that the position of a faulty trigger is obtained.
The electronic equipment comprises a memory, a processor and a computer program which is stored in the memory and can run on the processor, wherein the computer program realizes the scan chain fault positioning method based on the special chain diagnosis vector when being loaded to the processor.
The computer readable storage medium of the present invention stores a computer program which, when executed by a processor, implements the scan chain fault locating method based on a dedicated chain diagnostic vector.
Compared with the prior art, the invention has the advantages that (1) the traditional method is based on the vector generated by ATPG for detecting the fault of the functional circuit, and the invention can more accurately locate the fault position in the scanning chain by generating the special chain diagnosis vector for each bit of scanning trigger and combining with circuit logic analysis. Because each special chain diagnosis vector is carefully designed, accurate excitation can be carried out aiming at different fault types, and therefore the coverage rate and accuracy of diagnosis are improved. (2) The invention firstly determines the fault type existing in the scanning chain through chain diagnosis, and generates a corresponding diagnosis vector aiming at the identified fault type. Unlike traditional method, the invention does not need to introduce various fault type vectors in the test process, thereby effectively reducing the number of required test vectors and obviously shortening the test time. (3) Compared with a hardware-based scan chain diagnosis method, the method has the remarkable advantage that particularly, high-efficiency fault diagnosis can be realized under the condition of not increasing extra hardware cost. Conventional hardware approaches often require the addition of additional diagnostic circuitry or logic to the circuit to facilitate fault detection and localization, which often results in increased chip area and power consumption, and may even affect the performance of the circuit. The invention only depends on the scan chain and the generated diagnosis vector, and completes fault diagnosis through the simulation process, and no hardware structure is changed or additional hardware modules are introduced.
Drawings
FIG. 1 is a flow chart of a scan chain fault locating method of the present invention.
Fig. 2 is a diagram of the S27 circuit structure according to the embodiment of the present invention.
Fig. 3 is a schematic diagram of a stuck-at fault injection circuit in accordance with an embodiment of the present invention.
FIG. 4 is a schematic diagram of calculating a dedicated chain diagnostic vector according to a circuit configuration in accordance with an embodiment of the present invention.
FIG. 5 is a diagram illustrating a format of a dedicated chain diagnostic vector stil according to an embodiment of the present invention.
FIG. 6 is a schematic diagram of waveforms of dedicated chain diagnostic vectors according to an embodiment of the present invention.
FIG. 7 is a schematic diagram of a stuck-at-1 fault diagnosis vector stil according to an example embodiment of the present invention.
FIG. 8 is a schematic diagram of a dedicated chain diagnostic vector simulation waveform in accordance with an embodiment of the present invention.
Detailed Description
First, a process of scan test and a test vector will be briefly described. In scan testing, test vector generation directly determines the validity and efficiency of the test. A test vector is a set of bit vectors used to excite a circuit input signal, each vector corresponding to a certain input configuration of the circuit, in order to verify whether the circuit can output as expected after receiving a particular input signal. Generating high quality test vectors is critical to ensuring circuit reliability, performance, and functional correctness. Typically, test vectors pass through various input states of an analog circuit, excite the circuit and detect its response, thereby evaluating whether the circuit has a manufacturing defect.
In scan testing, test vectors are first input into the circuit through the scan chain, a process known as test vector shifting in. The scan chain is a series of flip-flops in series that allow the test equipment to input test data into the circuit one by one. Next, the circuit performs a stimulus operation based on the input test vector, which is referred to as a capture operation. After the capturing operation, the circuit performs corresponding function calculation or operation according to the signal of the excitation input, and outputs the state of the circuit. Finally, the test vector shift shifts out the output or internal state of the circuit through the scan chain, and judges whether the circuit correctly responds to the input signal through comparison with the expected output. Test vector shifting is the process of inputting the generated test vector into the circuit through the scan chain. The scan chain is a series of flip-flops in series that allow the test device to input test data into the circuit on a flip-flop-by-flip-flop basis, and the capture operation is the process by which the circuit, after shifting into a test vector, fires and performs a calculation or operation in accordance with the test vector. This step typically involves normal functional operation of the circuit, adding a stimulus to the input of the functional circuit, and calculating a corresponding output from the input of the stimulus. Test vector shifting out is the process of shifting out the output or internal state of a circuit from flip-flops in a scan chain. By shifting out the captured state (i.e., circuit response) can be extracted and compared to the expected output to determine if the circuit is correct.
The technical scheme of the invention is further described below with reference to the accompanying drawings.
As shown in fig. 1, the scan chain fault locating method based on the dedicated chain diagnosis vector of the present invention includes the following steps.
S1, reading in a circuit netlist file inserted into a scan chain structure, analyzing the circuit netlist inserted into the scan chain, and determining the length of the scan chain.
S2, injecting stuck-at-1 and stuck-at-0 faults into SI ports of each scan trigger (trigger for short) in the scan chain to obtain a fault circuit netlist.
And S3, determining the fault type of the scanning chain through chain test.
In chain testing, periodic test vector 0011 is first shifted into the scan chain, driving the circuit internal states through flip-flops one by one. Directly moving out of the output state, and performing comparison analysis. If the shift-out values are all 0 or all 1, it can be determined that the circuit has a stuck-at-0 or stuck-at-1 fault.
S4, after determining the fault type of the scanning chain, generating a corresponding special chain diagnosis vector for each bit of trigger, wherein the special chain diagnosis vector needs to be designed for each bit of trigger, and setting a vector at the downstream of the special chain diagnosis vector as a fault value when the trigger is assumed to have faults;
After determining the downstream value of each bit flip-flop, the circuit logic is further analyzed to identify the propagation path of the downstream flip-flop. These propagation paths are analyzed to determine the range of impact of the faulty trigger on the downstream triggers. The corresponding positions of the downstream triggers in the special chain diagnosis vector are set to be fault values, so that the influence of the fault values on the functional circuit is reduced, and the controllability of the capture values is ensured.
S5, generating special chain diagnosis vectors corresponding to different triggers.
To ensure that the effect of the fail-safe is effectively controlled, the circuit logic needs to be analyzed to determine the upstream value of the test vector and the functional circuit input (PI) value. According to the type of the fault trigger, the PI input of the input end of the functional circuit is adjusted, so that the fault trigger and the trigger of the last position can capture the opposite value of the fault trigger (namely the fault reverse value), and a complete scan chain special chain diagnosis vector is determined.
And S6, storing the generated special chain diagnosis vector, and generating a corresponding testbench file for the special chain diagnosis vector to ensure that the diagnosis vector is correctly verified in simulation.
S7, simulating the fault circuit by using the generated testbench file, inputting the generated special chain diagnosis vector through a VCS simulation tool to obtain a simulation result, and observing output of a test_so port.
And S8, analyzing a simulation result to obtain an accurate fault position.
When there is a fault in the scan chain, the faulty flip-flop will change the shift-out value of its upstream flip-flop during the shift-out phase. By designing dedicated chain diagnostic vectors in advance, it is possible to ensure that the captured values are unchanged and to use the characteristics of these vectors to diagnose the location of the faulty trigger.
The present invention will be described in detail in the following in five aspects.
(1) A scan chain fault locating method process based on a dedicated chain diagnostic vector.
The complete scan chain fault locating process includes eight stages, including reading circuit file, fault injection, fault type determination, analysis of circuit structure, generation of chain diagnosis vector, generation testbench, simulation and obtaining fault locating result. Because the traditional scan chain diagnosis process needs to add additional circuits to design, increases the expenditure, has low diagnosis efficiency and has limited fault recognition accuracy, the invention provides a scan chain fault positioning method based on a special chain diagnosis vector for solving the problem, and solves the problems of low accuracy and low diagnosis speed of the traditional method. The method comprises the specific steps of analyzing a circuit netlist, determining the length of a scanning chain, injecting stuck-at-1 and stuck-at-0 faults, exciting the scanning chain triggers through periodic test vectors 0011, judging whether output values are all 0 or all 1 to determine fault types, simulating faults of each trigger to generate corresponding special chain diagnosis vectors, analyzing propagation paths of downstream triggers, reducing influences of fault values on a functional circuit, adjusting the input end of the functional circuit, ensuring capturing of opposite values of the fault triggers, and finally generating and simulating verification diagnosis vectors.
The invention effectively improves the precision and speed of the fault positioning of the scanning chain. Compared with the traditional scan chain diagnosis method based on hardware, the method has the remarkable advantage that the fault diagnosis can be efficiently realized under the condition of not increasing extra hardware cost. Conventional approaches often require the addition of additional diagnostic circuitry or logic cells in the circuit, which not only increases chip area and power consumption, but may also affect circuit performance. The invention only depends on the scan chain and the generated diagnosis vector, and fault location is completed through the simulation process without modifying a hardware structure or introducing an additional hardware module, thereby effectively avoiding related problems.
In addition, the invention designs a special diagnosis vector for each trigger, and can more accurately position the fault position by combining circuit logic analysis. Each test vector is carefully designed, and the corresponding diagnosis vector can be selected to be accurately excited according to different fault types, so that the number of the chain diagnosis vectors is reduced, the diagnosis coverage rate and accuracy are improved, the test period is shortened, and the test time is shortened.
(2) Scan chain fault injection.
After the circuit netlist file inserted into the scan chain is read, an injection link of stuck at fault is added. The stuck at fault is injected at the SI terminal of each flip-flop according to the scan chain structure of the circuit.
Referring to fig. 2, taking the S27 circuit netlist in the standard test circuit ISCAS'85 as an example, ports G0, G1, G2, G3 are functional input ports and G17 is a functional output port, tests_si is a scan input port, tests_so is a scan output port, SE is a scan enable port, se=1 shifts the test vector from tests_si into SFF2, SFF1, SFF0, and shifts the last test vector from test_so port, and se=0 shifts the scan flip-flop D port from the combinational logic to capture data. blif _clk_net is a clock port, provides a clock for the scan flip-flop and is connected with the clk port of the flip-flop, and when rst is a reset port and rst=1, SFF is all set to zero. After analyzing the scan chain structure, the SI ports of the triggers SFF0, SFF1 and SFF2 in each scan chain are respectively injected with stuck at-0 and stuck at-1 faults, and the generated fault netlist is stored to prepare for the follow-up simulation verification of the fault position.
(3) Chain testing determines the type of fault present in the scan chain.
In the chain test process, the periodic test vector 0011 is first shifted into the scan chain, the internal states of the circuit are excited by flip-flops one by one, and the output values are directly shifted out for comparison and analysis. If the shift-out values are all 0 or all 1, it may be determined that the circuit has stuck-at-0 or stuck-at-1.
Referring to fig. 3, the test is performed by the circuit chain test in S27, the test vector sequence is { SFF2, SFF1, SFF0}, the test vector is shifted into the 001 vector from the test_si port, and the output value is directly shifted out for comparison and analysis, when the test_so port output is 111, it indicates that one or several flip-flops in the scan chain have a stuck-at-1 fault, when the test_so port output is SFF2, SFF1, sff0=000, it indicates that one or several flip-flops in the scan chain have a stuck-at-0 fault, and when the test_so port output is 001, it indicates that the scan chain has no fault.
(4) The analysis circuit structure generates a chain diagnostic vector.
After determining the scan chain failure type, a corresponding dedicated chain diagnostic vector is generated for each flip-flop. The trigger connected between the faulty trigger and test_so is his downstream trigger and the trigger connected between the test_si is his upstream trigger.
When a fault occurs, the fault trigger will change its downstream value, resulting in a change in the capture value. By designing the special chain diagnosis vector, when the fault trigger is supposed to be faulty, the value of the downstream trigger is set to be a fault value, so that the shifted special chain diagnosis vector is not influenced, and the stability of the capture value of the scanning chain is ensured.
Further analysis of the circuit logic identifies the propagation path of the downstream flip-flop and masks it to reduce the effects of faults. Meanwhile, during scan-in, the fault trigger affects only the downstream value and does not change the upstream value. By adjusting the value of the functional circuit input (PI), it is ensured that the flip-flop that is one bit above the failed flip-flop captures its failure inverse, thereby generating a complete chain diagnostic vector.
The following description is made by way of a case.
Suppose that the result after the chain test is 111, indicating that there is a stuck-at-1 fault in the scan chain. At this time, it is necessary to generate corresponding chain diagnosis vectors for the three flip-flops, respectively. When the SI end of the SFF1 fails, the value of the SFF0 is changed when the scanning is shifted in, and the SFF0 is blocked as1, so that the capture value of the scanning chain is affected. Therefore, when designing the diagnostic vector corresponding to the stuck-at-1 fault of SFF1, the values of SFF1 and SFF0 need to be set to 1 to ensure that the captured value of the scan chain is not affected regardless of whether the SI port of SFF1 is faulty or not, and thus the test_si port is shifted into the vector of test_si=11x. Wherein X represents an don't care bit.
During a scan out period, the value of the flip-flop upstream of the scan chain may be affected by a failure of the flip-flop downstream. Taking SFF1 as an example of a stuck-at-1 fault, the value of SFF2 will get stuck at 1 when removed, regardless of the value captured by SFF 2. In order to enable visual observation of stuck-at-1 failure of SFF1, the capture value of SFF2 should be set to 0. As shown in fig. 4, analysis of the S27 circuit shows that the capture value of SFF2 is from the nor_1 gate, the signal of which is controlled by n1 and n2, and n2 is connected to the G0 port only through a not gate, which has better controllability. Therefore, the SFF2 trapping value can be ensured to be 0 by setting the G0 end to 0 and n2 to 1.
Meanwhile, the capture value of SFF1 is set to 0. When scanning out, if the value of SFF1 is 0 and can be shifted out normally, and the value of SFF2 is mainly 1, the fault is indicated to occur at the SI end of SFF 1. According to the S27 circuit diagram, the capture value of SFF1 is controlled by a nor_2gate, the nor_n2 gate is controlled by the Q terminal of SFF2, and when the SFF2 output is 1, the D terminal capture value of SFF1 is 0.
Finally, the chain diagnostic vector when SFF1 fails stuck-at-1 is determined to be test_si=111, pi=g0, G1, G2, g3=0x1x.
Based on the above method, two fixed fault types of each trigger are simulated respectively. Firstly, when a stuck-at-0 fault occurs in a scan chain, setting test_si=000 to ensure that the value of the scan shift-in is not affected by the fault, and according to calculation, when input PI is G0, G1, G2, g3=x0x1, the expected capture value test_so=010, if the actual shift-out value test_so=000, 1 captured by SFF1 is stuck to 0, the fault is proved to occur at the SI port of SFF0, if the actual shift-out value test_so=010, 1 captured by SFF1 can be shifted out normally, the fault is demonstrated to occur at the upstream scan unit of SFF0, and when the test_si=000, input PI is G0, G1, G2, g3=1xxx, the expected capture value test_so=101, if the actual shift-out value test_so=101, 1 captured by SFF2 can be shifted out normally, and if the actual shift-out value test_so=001, 1 captured by SFF2, the fault is demonstrated to occur at the SI port of SFF2, and if the actual shift-out value test_so=001, 1 is captured by SFF1, the fault is demonstrated to occur at the downstream of SFF 0;
Similarly, if a stuck-at-1 fault occurs in the scan chain, the test_si=111 is set to ensure that the scan-in process is not affected by the stuck-at-1 fault, and the capture value test_so=000 is calculated when pi=g0, G1, G2, g3=0011. The shift-out value is observed, and if test_so=110, the fault occurs at SFF0, if test_so=100, the fault occurs at SFF1, and if test_so=000, the fault occurs at SFF2.
In summary, for the fault diagnosis of the S27 circuit chain, the following diagnostic vectors are obtained:
at stuck-at-1, pattern0: test_si=111, g0123=0x1x, test_so=000;
At stuck-at-0, pattern0: test_si=000, g0123=x0x1, test_so=010;
pattern1:test_si=000,G0123=1XXX, test_so=101;
For stuck-at-0 faults, only two chain diagnosis vectors are needed, while for stuck-at-1 faults, accurate positioning can be realized by only one chain diagnosis vector. Through the diagnosis vectors, faults can be effectively positioned, and the positions where the faults occur can be accurately identified.
(5) The chain diagnostic vector generation testbench file is saved for simulation.
After the chain diagnosis vector of each trigger is obtained, the irrelevant bit X is randomly filled, fault simulation is executed, and the capture value corresponding to each vector is obtained.
Referring to FIG. 5, the STIL file format for the private chain diagnostic vector is as follows. "Pattern 0" represents the 0 th dedicated chain diagnostic vector, which is the dedicated chain diagnostic vector. In the 'load_unlock' phase, i.e., the move-in phase, the value of 'test_si' is 001. In the 'multiclock _capture' phase, the value of the 'pi' port consists of 11 input ports of the circuit, i.e. `_pi = G0 + G1 + G2 + G3 + blif_clk_net + reset + scan_clk + scan_rst + test_mode + test_se + test_si`., at this stage, by applying one or more clock cycles, the flip-flop is enabled to capture the signal in the functional circuit and to measure the 'po' port value, where H is high 1 and l is low 0. During chain testing, the 'test_se' value is set to 1, meaning that the flip-flop still takes value from the previous bit flip-flop, since the circuit is not captured and only the dedicated chain diagnostic vector is shifted in and out.
After the chain diagnosis vector is organized into stil format files, a corresponding testbench file can be generated, the circuit is simulated through the VCS, and the simulation result is observed through verdi. After the circuit is simulated, the generated 'fsdb' waveform file can be used for observing the simulation result through a Verdi tool. Referring to fig. 6, as a chain test result, after the dedicated chain diagnosis vector '001' is input at the 'test_si' port, the result of the 'test_so' port shift out is '111' at the 'pattern 1' period, which indicates that the scan chain has a stuck-at-1 fault.
Referring to fig. 7, for the STIL file of the chain diagnosis vector corresponding to the stuck-at-1 fault found after the S27 circuit chain test, the value of 'test_si' is 111 in the 'load_unlock' stage, pi=0011P 010100 is set in the 'multiclock _capture' stage, where G0, G1, G2, g3=0011, and blif_clk_net=p indicates that one clock pulse is applied, and testbench file is generated and simulated observation result is performed after saving.
Referring to fig. 8, the value of 'test_si' shift-in is 111, G0, G1, G2, g3=0011 when the capture clock is triggered, the result of 'test_so' port shift-out is 000, no value is stuck 1, but the result of the chain test indicates that stuck-at-1 fault exists in the scan chain, so it can be determined that stuck-at-1 fault occurs at SI port of SFF 0.
The invention relates to a scan chain fault positioning system based on special chain diagnosis vector, which comprises:
The fault type test unit is used for determining the fault type existing in the functional circuit scanning chain to be tested through chain test, wherein the fault type is stuck-at-1 fault or stuck-at-0 fault, and the corresponding fault value is 1 or 0;
The special chain diagnosis vector generation unit is used for generating a corresponding special chain diagnosis vector for each trigger, wherein the corresponding position of the trigger and the downstream trigger thereof is set as a fault value according to the fault type;
And the scan chain fault test unit is used for performing scan chain fault test by using the special chain diagnosis vector to obtain the position of the failed trigger.
The electronic equipment comprises a memory, a processor and a computer program which is stored in the memory and can run on the processor, wherein the computer program realizes the scan chain fault positioning method based on the special chain diagnosis vector when being loaded to the processor.
The computer readable storage medium of the present invention stores a computer program which, when executed by a processor, implements the scan chain fault locating method based on a dedicated chain diagnostic vector.
The computer-readable storage media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage, flash memory or any other medium that can be used to store program code in the form of instructions or data structures and that can be accessed by a computer.
The processor is configured to execute the computer program stored in the memory to implement the steps in the method according to the above-mentioned embodiments.
Claims (10)
1. A scan chain fault positioning method based on a special chain diagnosis vector is characterized by comprising the following steps:
step 1, determining the fault type existing in a functional circuit scanning chain to be tested through chain test, wherein the fault type is stuck-at-1 fault or stuck-at-0 fault, and the corresponding fault value is 1 or 0;
Step 2, generating a corresponding special chain diagnosis vector for each trigger, wherein the corresponding positions of the trigger and the downstream trigger are set as fault values according to the fault types;
and step 3, performing scan chain fault test by using the special chain diagnosis vector to obtain the position of the failed trigger.
2. The scan chain fault location method based on the special chain diagnosis vector according to claim 1, wherein in step 1, a circuit netlist file inserted into the scan chain is read in, a stuck-at-1 and stuck-at-0 fault is injected into each trigger in the scan chain to obtain a fault circuit netlist, and a periodic test vector is used for carrying out a chain test to judge the fault type existing in the functional circuit scan chain.
3. The scan chain fault location method based on a dedicated chain diagnostic vector according to claim 1, wherein in step 2, in the dedicated chain diagnostic vector, the corresponding position of the upstream trigger of the trigger is an irrelevant bit, which is randomly set to 0 or 1.
4. The method for scan chain fault location based on a dedicated chain diagnostic vector according to claim 1, wherein in step 2, the method for adjusting the functional circuit input value such that the previous trigger of the trigger captures the opposite value of the fault value comprises:
And setting constraint conditions, namely setting the corresponding positions of the trigger and the downstream trigger thereof in the special chain diagnosis vector as fault values, and obtaining input combinations meeting the constraint conditions by traversing all possible input combination calculation function circuit outputs.
5. The scan chain fault location method based on a dedicated chain diagnostic vector as recited in claim 1, wherein in step 2, the capture value of the trigger is set to the opposite of the fault value.
6. The scan chain fault locating method based on the dedicated chain diagnostic vector according to claim 1, wherein step 3 specifically comprises the steps of saving the chain diagnostic vector and generating a testbench file corresponding to the chain diagnostic vector, and performing scan chain fault test by using the testbench file to obtain a trigger position where a fault occurs.
7. A scan chain fault location system based on dedicated chain diagnostic vectors, comprising:
The fault type test unit is used for determining the fault type existing in the functional circuit scanning chain to be tested through chain test, wherein the fault type is stuck-at-1 fault or stuck-at-0 fault, and the corresponding fault value is 1 or 0;
The special chain diagnosis vector generation unit is used for generating a corresponding special chain diagnosis vector for each trigger, wherein the corresponding position of the trigger and the downstream trigger thereof is set as a fault value according to the fault type;
And the scan chain fault test unit is used for performing scan chain fault test by using the special chain diagnosis vector to obtain the position of the failed trigger.
8. The scan chain fault location system based on the dedicated chain diagnostic vector according to claim 7, wherein in the fault type test unit, a circuit netlist file inserted into the scan chain is read in, and a stuck-at-1 and stuck-at-0 fault is injected into each trigger in the scan chain to obtain a fault circuit netlist;
in the special chain diagnosis vector generation unit, the corresponding position of the upstream trigger of the trigger is an irrelevant bit, and is randomly set to 0 or 1;
In a dedicated chain diagnostic vector generation unit, a method of adjusting functional circuit input values such that a previous flip-flop of the flip-flop captures an opposite value of a fault value, comprising:
setting constraint conditions, an input port and an output port, wherein the constraint conditions are that the corresponding positions of the trigger and a downstream trigger thereof in a special chain diagnosis vector are fault values, and obtaining input combinations meeting the constraint conditions by traversing all possible input combination calculation function circuit outputs;
in the dedicated chain diagnosis vector generation unit, the capture value of the trigger is set to the opposite value of the fault value;
And in the scan chain fault test unit, a chain diagnosis vector is stored, a testbench file corresponding to the chain diagnosis vector is generated, and the scan chain fault test is carried out by utilizing the testbench file, so that the position of a faulty trigger is obtained.
9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the computer program when loaded to the processor implements the scan chain fault localization method based on dedicated chain diagnostic vectors according to any of claims 1-6.
10. A computer readable storage medium storing a computer program, characterized in that the computer program, when executed by a processor, implements the scan chain fault localization method based on a dedicated chain diagnostic vector according to any one of claims 1-6.
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