CN119743981A

CN119743981A - A SiCVD MOSFET structure with high temperature reliability and its preparation method

Info

Publication number: CN119743981A
Application number: CN202510254586.2A
Authority: CN
Inventors: 许一力; 李鑫; 刘倩倩
Original assignee: Hangzhou Spectro Crystal Semiconductor Technology Co ltd
Current assignee: Hangzhou Spectro Crystal Semiconductor Technology Co ltd
Priority date: 2025-03-05
Filing date: 2025-03-05
Publication date: 2025-04-01

Abstract

The invention relates to the technical field of MOS semiconductors, and discloses a SiCVDMOSFET structure with high-temperature reliability, which comprises a drain electrode, a semiconductor epitaxial layer, a source electrode, a grid electrode and a grid oxide layer covering the surface of the grid electrode, wherein an N substrate layer, an N drift layer, a P well layer I, a heavily doped P layer and an N well layer are arranged in the semiconductor epitaxial layer, a P well layer II and a heavily doped N layer I are arranged at one side of the N well layer and close to the grid electrode, the P well layer II is positioned between the N well layer and the heavily doped N layer I, the cross section profile of the grid electrode is in a T shape, the heavily doped N layer I also comprises a heavily doped N layer III, and the heavily doped N layer III is in contact with the N drift layer. The invention can help the heat of the grid region to be distributed more uniformly through the T-shaped grid structure, avoid heat concentration at a certain point, reduce the device fault or degradation caused by local high temperature, and the T-shaped grid structure can generally optimize the grid resistance and reduce the current required by grid driving.

Description

SiCVDMOSFET structure with high-temperature reliability and preparation method thereof

Technical Field

The invention relates to the technical field of MOS semiconductors, in particular to a SiCVDMOSFET structure with high-temperature reliability and a preparation method thereof.

Background

The preparation method of the high temperature reliability SiC VDMOSFET (vertical bipolar metal oxide semiconductor field effect transistor) involves a plurality of key steps. SiC (silicon carbide) has a high thermal conductivity, a wide forbidden bandwidth and a high breakdown voltage as a material, and is suitable for high-temperature, high-power and high-frequency applications.

The prior patent discloses a SiC VDMOSFET structure (publication No. CN 118969842A) with high power and high temperature reliability, which comprises a drain electrode, wherein an N+ substrate is arranged above the drain electrode, an N-drift region is arranged above the N+ substrate, a SiO2 passivation layer is positioned above a gate oxide layer and a grid electrode, three groups of groove buffer regions are arranged on a P well region and are communicated, and a variable resistor V is arranged in the N-drift region. In the technology disclosed in the prior patent, carriers of the drift layer are insufficient due to more active carriers in a high-temperature environment, so that the resistance of the channel region is increased. Moreover, a simple and clear judgment method for the high-temperature performance of the MOS device is lacking.

Disclosure of Invention

The invention mainly solves the technical problem of providing a SiCVDMOSFET structure with high-temperature reliability and a preparation method thereof, and solves the problems in the background art.

In order to solve the above technical problems, according to one aspect of the present invention, a SiCVDMOSFET structure with high-temperature reliability is provided, which includes a drain electrode, a semiconductor epitaxial layer, a source electrode, a gate electrode, and a gate oxide layer covering the surface of the gate electrode, wherein an N substrate layer, an N drift layer, a P-well layer one, a heavily doped P-layer, and an N-well layer are disposed in the semiconductor epitaxial layer, and a P-well layer two and a heavily doped N-layer one are disposed at a position near the gate electrode on one side of the N-well layer, and the P-well layer two is disposed between the N-well layer and the heavily doped N-layer one;

the cross-sectional profile of the grid is in a T shape.

Further, the first heavily doped N layer further includes a third heavily doped N layer, where the third heavily doped N layer is in contact with the N drift layer.

Further, the bottom of the grid electrode is also etched with a T-shaped groove, wherein the inner part of the T-shaped groove is filled with a filling medium.

Further, the filling medium is one of SiO, P-type polysilicon or N-type polysilicon.

Furthermore, a second heavily doped N layer is formed in the N drift layer through ion implantation, the cross section outline of the second heavily doped N layer is U-shaped, and the cross section thickness of the second heavily doped N layer is the same as that of the first heavily doped N layer.

A preparation method of a structure with high-temperature reliability SiCVDMOSFET comprises the following steps:

S1, preparing a substrate and treating the surface of the substrate;

S2, doping the grid electrode region and forming source electrode/drain electrode regions;

s3, gate metallization and source drain metallization form a SiC VDMOSFET structure;

S4, performing high-temperature stress test on the SiC VDMOSFET structure to verify long-term reliability of the device under high-temperature conditions.

Further, in the step S2, a heavily doped N layer is formed by doping phosphorus impurities by an ion implantation process.

Further, in the step S4, the high temperature reliability of the SiCVDMOSFET structure is determined according to the change amount of the leakage current after the SiCVDMOSFET structure is heated to 60 ℃ in the normal temperature environment, the change amount of the on-resistance after the SiCVDMOSFET structure is heated to 100 ℃ in the normal temperature environment, and the change amount of the temperature after the SiCVDMOSFET structure is continuously operated for 5 hours under the voltage exceeding 20% of the threshold voltage, and the steps include:

in the formula, Representing the high temperature reliability coefficient of the detected SiCVDMOSFET structure,The larger the high temperature performance of SiCVDMOSFET structure; the change amount of leakage current after the temperature is raised by 60 ℃ in a normal temperature environment is shown; The variation of the on-resistance after the temperature is raised by 100 ℃ in the normal temperature environment is shown; The temperature change after continuous operation for 5 hours at 20% voltage exceeding the threshold voltage is shown.

Further, whenAnd when the detected SiCVDMOSFET structure has high-temperature reliability.

The beneficial effects are that:

1. the invention can greatly improve the stability of the device through the design of the serial double channels, and avoid the risk of breakdown of the device in a high-temperature environment.

2. The invention can help the heat of the grid region to be distributed more uniformly through the T-shaped grid structure, avoid heat concentration at a certain point, reduce the device fault or degradation caused by local high temperature, and the T-shaped grid structure can generally optimize the grid resistance and reduce the current required by grid driving.

3. According to the invention, the SiC VDMOSFET can work more effectively under high power density through the filling medium, so that the heat loss is reduced, the power conversion efficiency is improved, and especially under a high-temperature environment, the device can be ensured to stably operate by optimizing the filling medium, and the efficiency of the whole system is improved.

4. According to the invention, the higher carrier concentration is provided by heavily doping the second N layer, so that the resistance of the channel region is reduced, the on-resistance can be obviously reduced when high current passes, and the on-performance of the device is improved.

5. According to the invention, through the change amount of leakage current after the SiCVDMOSFET structure is heated to 60 ℃ in the normal temperature environment, the change amount of on-resistance after the temperature is raised to 100 ℃ in the normal temperature environment and the temperature change amount after the MOS device continuously works for 5 hours under the voltage exceeding the threshold voltage of 20%, the high-temperature performance of the MOS device can be simply and clearly judged.

Drawings

FIG. 1 is a schematic diagram of a first embodiment of the present invention;

FIG. 2 is a schematic diagram of a second embodiment of the present invention;

FIG. 3 is a schematic diagram of a third embodiment of the present invention;

Fig. 4 is a schematic diagram of a fourth embodiment of the present invention.

In the figure, 1, a drain electrode, 2, a source electrode, 3, a gate oxide layer, 4, a gate electrode, 5, an N substrate layer, 6, an N drift layer, 7, a first P well layer, 8, a heavily doped P layer, 9, an N well layer, 10, a second P well layer, 11, a heavily doped first N layer, 12, a filling medium, 13, a heavily doped second N layer, 1101 and a heavily doped third N layer are shown.

Detailed Description

In order to make the technical scheme of the invention clearer, the invention is further described in detail below with reference to the attached drawings and specific embodiments.

As shown in fig. 1 to 4, a method for manufacturing a structure with high-temperature reliability SiCVDMOSFET includes the following steps:

Step one, substrate preparation and substrate surface treatment.

And doping the grid electrode region and forming source electrode/drain electrode regions, and doping phosphorus element impurities by utilizing an ion implantation process to form a heavily doped N layer 11.

And thirdly, gate metallization and source-drain metallization form a SiC VDMOSFET structure.

And fourthly, performing high-temperature stress test on the SiC VDMOSFET structure to verify the long-term reliability of the device under the high-temperature condition.

According to the change amount of leakage current after the SiCVDMOSFET structure is heated to 60 ℃ in a normal temperature environment, the change amount of on-resistance after the temperature is raised to 100 ℃ in the normal temperature environment and the change amount of temperature after the structure continuously works for 5 hours under the voltage exceeding the threshold voltage of 20%, the high-temperature reliability of the SiCVDMOSFET structure is determined, and the high-temperature reliability of the SiCVDMOSFET structure is determined by the following steps:

When (when)And when the detected SiCVDMOSFET structure has high-temperature reliability.

And detecting the high-temperature reliability coefficient of any SiCVDMOSFET structure. The SiCVDMOSFET structure is heated to 60 ℃ in normal temperature environment, and the leakage current is changed(UnitWherein ambient temperature conditions mean that the device is at 25 ℃ conditions).

The change amount of on-resistance of SiCVDMOSFET structure after temperature rise of 100 ℃ in normal temperature environment(Milliohms unit).

The SiCVDMOSFET structure is subjected to temperature change after continuous operation for 5 hours under the voltage exceeding the threshold voltage by 20 percent(Temperature change amount = elevated temperature +.room temperature ambient temperature). Then there are:

From the above calculation, it can be known that the high temperature reliability coefficient of the detected SiCVDMOSFET structure is Then this indicates that the SiCVDMOSFET structure detected has excellent high temperature reliability.

Example 1

As shown in fig. 1, according to one aspect of the present invention, there is provided a SiCVDMOSFET structure with high-temperature reliability, which includes a drain electrode 1, a semiconductor epitaxial layer, a source electrode 2, a gate electrode 4, and a gate oxide layer 3 covering the surface of the gate electrode 4, wherein an N substrate layer 5, an N drift layer 6, a P-well layer 7, a heavily doped P-layer 8, and an N-well layer 9,N are disposed in the semiconductor epitaxial layer, a P-well layer two 10 and a heavily doped N-layer one 11 are disposed on one side of the well layer 9 near the gate electrode 4, and the P-well layer two 10 is disposed between the N-well layer 9 and the heavily doped N-layer one 11. In the gate voltage state where the gate electrode 4 is interposed, charge channels are formed at the position of the first P-well layer 7 close to the gate electrode 4 and above the second P-well layer 10, and the charge channels can communicate the N-drift layer 6 with the N-well layer 9, so that the drain electrode 1 and the source electrode 2 are conducted. The design of the serial double channels can greatly improve the stability of the device and avoid the risk of breakdown of the device in a high-temperature environment.

Example 2

As shown in fig. 2, the heavily doped N layer one 11 further includes a heavily doped N layer three 1101, where the heavily doped N layer three 1101 is in contact with the N drift layer 6, the cross-section profile of the gate 4 is in a T shape, the T-shaped gate 4 structure can help the heat in the gate 4 region to be distributed more uniformly, avoid heat concentration at a certain point, and reduce device failure or degradation caused by local high temperature, and the T-shaped gate 4 structure can generally optimize the resistance of the gate 4, reduce the current required for driving the gate 4, and thus improve the accuracy and response speed of gate control at high temperature due to the reduction of the gate resistance.

Example 3

As shown in fig. 3, the bottom of the gate 4 is also etched by a T-shaped trench, wherein the inside of the T-shaped trench is filled with a filling medium 12. The filling medium 12 is one of SiO2, P-type polysilicon or N-type polysilicon. SiC VDMOSFETs are enabled to operate more efficiently at high power densities by filling medium 12, reducing heat loss and improving power conversion efficiency. The optimization of the fill medium 12 ensures stable operation of the device and improves overall system performance, particularly in high temperature environments.

Example 4

As shown in fig. 4, the heavily doped N layer 13 is formed inside the N drift layer 6 by ion implantation, the cross-sectional profile of the heavily doped N layer 13 is in a shape of a 'U', and the cross-sectional thickness of the heavily doped N layer 13 is the same as the cross-sectional thickness of the heavily doped N layer 11. Heavily doped N layer two 13 reduces the resistance of the channel region by providing a higher carrier concentration. When high current passes through, the on-resistance can be obviously reduced, and the on-performance of the device is improved. This helps to promote the overall efficiency of SiC VDMOSFETs, especially in high power applications. And, heavily doped N layer two 13 can effectively adjust the breakdown voltage of device. The introduction of the N layer with high doping concentration between the gate and the drift layer helps to change the distribution of the electric field, thereby optimizing the breakdown voltage of the device. This design helps to improve the voltage withstand capability of the device, particularly in high voltage and high power applications, ensuring reliable operation of the device at high voltages.

The foregoing examples illustrate only a few embodiments of the invention and are described in detail herein without thereby limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.

Claims

1. A SiCVD MOSFET structure with high temperature reliability, comprising a drain (1), a semiconductor epitaxial layer, a source (2), a gate (4) and a gate oxide layer (3) covering the surface of the gate (4), wherein an N substrate layer (5), an N drift layer (6), a P well layer (7), a heavily doped P layer (8) and an N well layer (9) are provided inside the semiconductor epitaxial layer, characterized in that: a P well layer (10) and a heavily doped N layer (11) are provided on one side of the N well layer (9) and close to the gate (4), and the P well layer (10) is located between the N well layer (9) and the heavily doped N layer (11);

The cross-sectional profile of the gate (4) is in a ‘T’ shape.

2. The SiCVD MOSFET structure with high temperature reliability according to claim 1, characterized in that: the heavily doped N layer one (11) further includes a heavily doped N layer three (1101), wherein the heavily doped N layer three (1101) is in contact with the N drift layer (6).

3. The SiCVD MOSFET structure with high temperature reliability according to claim 1, characterized in that: a T-shaped groove is etched at the bottom of the gate (4), wherein the interior of the T-shaped groove is filled with a filling medium (12).

4. The SiCVD MOSFET structure with high temperature reliability according to claim 3, characterized in that: the filling medium (12) is one of SiO2, P-type polysilicon or N-type polysilicon.

5. The SiCVD MOSFET structure with high temperature reliability according to claim 1 is characterized in that: a heavily doped N layer 2 (13) is formed inside the N drift layer (6) by ion implantation, the cross-sectional profile of the heavily doped N layer 2 (13) is in a ‘U’ shape, and the cross-sectional thickness of the heavily doped N layer 2 (13) is the same as the cross-sectional thickness of the heavily doped N layer 1 (11).

6. A method for preparing a SiCVD MOSFET structure with high temperature reliability, characterized in that the method for preparing a SiCVD MOSFET structure with high temperature reliability is applied to the SiCVD MOSFET structure with high temperature reliability as claimed in any one of claims 2 to 5, and the method for preparing a SiCVD MOSFET structure with high temperature reliability comprises the following steps:

S1, substrate preparation and substrate surface treatment;

S2, gate region doping, and source/drain region formation;

S3, gate metallization and source-drain metallization form a SiC VDMOSFET structure;

S4. Perform high temperature stress test on SiC VDMOSFET structure to verify the long-term reliability of the device under high temperature conditions.

7. The method for preparing a SiCVD MOSFET structure with high temperature reliability according to claim 1, characterized in that: in the step S2, phosphorus impurities are doped by ion implantation to form a heavily doped N layer 1 (11).

8. The method for preparing a SiCVD MOSFET structure with high temperature reliability according to claim 1, characterized in that: in step S4, the high temperature reliability of the SiCVD MOSFET structure is determined according to the change in leakage current after the SiCVD MOSFET structure is heated by 60°C under normal temperature, the change in on-resistance after the SiCVD MOSFET structure is heated by 100°C under normal temperature, and the temperature change after continuous operation for 5 hours at a voltage exceeding the threshold voltage by 20%, wherein:

In the formula, represents the high temperature reliability coefficient of the SiCVDMOSFET structure tested, The larger the value, the better the high temperature performance of the SiCVDMOSFET structure; It indicates the change in leakage current after the temperature rises by 60°C under normal temperature environment; It indicates the change in on-resistance after the temperature rises by 100°C under normal temperature environment; Indicates the temperature change after continuous operation for 5 hours at a voltage 20% higher than the threshold voltage.

9. The method for preparing a SiCVD MOSFET structure with high temperature reliability according to claim 8, characterized in that: When , it means that the SiCVDMOSFET structure tested has excellent high temperature reliability.