CN119727700A - Low voltage differential signal communication system and its driver - Google Patents

Abstract

The present invention discloses a low voltage differential signal device and a driver thereof, wherein the driver comprises an output circuit, a bias circuit and a first clamp circuit; the output circuit comprises a push-pull circuit and a first tail current source arranged between a power supply terminal and the push-pull circuit; the bias circuit comprises a bias current generating unit for providing a first bias current; the first clamp circuit provides a second bias current to the bias circuit; when an enable signal is at a first level, the bias circuit provides a bias voltage of a first preset value to the first tail current source according to the sum of the first bias current and the second bias current, and the driver is in a normal state; when the enable signal is at a second level, the bias circuit provides a bias voltage of a second preset value to the first tail current source according to the second bias current, and the driver is in a high impedance state; the second preset value is less than the voltage value of the power supply terminal and greater than the first preset value, thereby improving the enabling speed when the output state of the LVDS driver is switched from a high impedance state to a normal state.

Description

Low voltage differential signal communication system and driver thereof

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a low-voltage differential signal communication system and a driver thereof.

Background

LVDS (Low Voltage DIFFERENTIAL SIGNALING) is a point-to-point high-speed differential electrical interface designed for applications requiring ultra-Low power consumption, low noise, and high data rates. The low-voltage swing high-speed differential transmission data is adopted, so that the LVDS technology can realize the improvement of low power consumption and anti-interference capability while guaranteeing the data transmission quality.

The transmission medium of the LVDS technology is flexible and various, and can be a copper PCB (Printed Circuit Board ) connecting line or a balanced cable, so that the LVDS has wide application prospect in various electronic devices. Because the LVDS adopts a differential signal transmission mode, namely a pair of signal lines are used for transmitting differential signals, common mode noise and other types of interference are effectively restrained, the signal-to-noise ratio of the signals is obviously improved, and the error rate is reduced. LVDS devices are typically composed of an LVDS driver and a receiver. The main function of the LVDS driver is to convert an input single-ended signal into a differential signal with a low voltage swing and output the signal.

MLVDS (Multi-Point Low Voltage DIFFERENTIAL SIGNALING, multi-drop low voltage differential signal) has all the advantages of LVDS technology and can be applied to Multi-drop bus systems. An LVDS communication system using MLVDS technology includes a plurality of LVDS drivers, and there are typically at least two LVDS drivers on the same cable, so these LVDS drivers need to have an output enable function, so as to ensure that only a selected LVDS driver outputs a signal on the same cable at the same time, and the unselected LVDS drivers output a high-resistance state Hi-z.

Fig. 1 shows a timing diagram of the operation of two LVDS drivers alternately outputting signals. Referring to fig. 1, if two LVDS drivers of the LVDS communication system alternately transmit signals using the same cable, when one of the LVDS drivers is switched from non-selected to selected, it needs to wake up from the high-resistance state Hi-z, so that a period of time T1 is required to enable to stably output a correct signal, which will limit the operating frequency of the LVDS communication system.

Therefore, a new low voltage differential signal communication system and a driver thereof have been proposed to solve the above-mentioned problems.

Disclosure of Invention

In view of the above-described problems, an object of the present invention is to provide a low-voltage differential signal communication system and a driver thereof, whereby the enabling speed when the output of the low-voltage differential signal driver is switched from a high-resistance state to a normal state can be improved.

According to one aspect of the invention, a low voltage differential signal driver is provided, the driver is provided with two output states, namely a high-resistance state and a normal state, the driver comprises an output circuit, a bias circuit and a first clamping circuit, the output circuit comprises a push-pull circuit and a first tail current source arranged between a power end and the push-pull circuit, the push-pull circuit is used for generating a first output signal and a second output signal according to a first input signal and a second input signal, the bias circuit is used for providing a bias voltage for the first tail current source, the bias circuit is provided with a bias current generating unit used for providing a first bias current, the first clamping circuit is connected with the bias circuit and used for providing a second bias current for the bias circuit, when the enabling signal is of a first level, the bias current generating unit is started, the bias circuit is used for providing a first preset voltage for the first tail current according to the sum of the first bias current and the second bias current, the bias circuit is provided with a bias current generating unit used for providing a second bias current for the bias current according to the first level, and when the bias current is of the first level, the bias current generating unit is in the first bias current and the first bias current source is in the normal state, and the bias current is enabled to be in the first bias current and is in the state and is smaller than the first bias current.

Optionally, the output circuit further comprises a second tail current source arranged between the push-pull circuit and the ground terminal, the driver further comprises a common mode feedback circuit for comparing the common mode feedback voltage of the first output signal and the second output signal with a reference voltage to provide bias voltage for the second tail current source according to a comparison result, and a second clamping circuit connected with the common mode feedback circuit and used for providing bias voltage with a third preset value for the second tail current source when the enabling signal is at a second level, wherein the third preset value is larger than the voltage value of the ground terminal and smaller than the range of the bias voltage provided by the common mode feedback circuit when the driver is in a normal state.

Optionally, the bias circuit includes the bias current generating unit and a second transistor, where the bias current generating unit includes a first current source, a first switch, a second switch, a first transistor and a third transistor, where the first current source, the first switch, and the first transistor are sequentially connected between a power supply terminal and a ground terminal, a control terminal of the first switch receives an enable signal, a control terminal of the first transistor is connected to a first terminal of the first transistor, the second switch is connected between the control terminal of the first transistor and the ground terminal, a control terminal of the second switch receives an inverted signal of the enable signal, the second transistor and the third transistor are sequentially connected between the power supply terminal and the ground terminal, a control terminal of the second transistor provides a bias voltage to the first tail current source, a control terminal of the second transistor is connected to a second terminal of the second transistor, and a control terminal of the third transistor is connected to a control terminal of the first transistor.

Optionally, the first clamping circuit includes a second current source and a fourth transistor sequentially connected between a power supply terminal and a ground terminal, a control terminal of the fourth transistor is connected to a first terminal of the fourth transistor, the second current source provides a second bias current, a fifth transistor is connected between an intermediate node of the second transistor and the third transistor and the ground terminal, a control terminal of the fifth transistor is connected to an intermediate node of the second current source and the fourth transistor, and the first terminal of the fifth transistor provides a fourth bias current.

Optionally, the current value of the first bias current is greater than the current value of the second bias current.

Optionally, the common mode feedback circuit comprises a first resistor and a second resistor, which are sequentially connected between a positive differential output end and a negative differential output end, wherein the positive differential output end provides the first output signal, the negative differential output end provides the second output signal, the error amplifier has a positive input end connected with intermediate nodes of the first resistor and the second resistor, a negative input end receives a reference voltage, the output end provides the second bias voltage for the second tail current source, and the intermediate nodes of the first resistor and the second resistor provide the common mode feedback voltage.

Optionally, the second clamping circuit includes a third current source and a sixth transistor sequentially connected between the power supply terminal and the ground terminal, the third current source provides a fifth bias current, a control terminal of the sixth transistor is connected to the first terminal of the sixth transistor, and a third switch connected between the control terminal of the sixth transistor and the output terminal of the error amplifier, wherein a control terminal of the third switch receives an inverted signal of the enable signal.

Optionally, the first tail current source includes a seventh transistor, and the second tail current source includes an eighth transistor.

Optionally, the first tail current source includes a seventh transistor, the second tail current source includes an eighth transistor, the push-pull circuit includes ninth to twelfth transistors, the seventh transistor, the ninth transistor, the tenth transistor, and the eighth transistor are sequentially connected between the power supply terminal and the ground terminal, the control terminal of the seventh transistor receives the first bias voltage, the control terminals of the ninth transistor and the tenth transistor receive the first input signal, the control terminal of the eighth transistor receives the second bias voltage, the intermediate nodes of the ninth transistor and the tenth transistor are the negative differential output terminal, the eleventh transistor and the twelfth transistor are sequentially connected between the intermediate nodes of the seventh transistor and the ninth transistor and the intermediate nodes of the tenth transistor, the control terminals of the eleventh transistor and the twelfth transistor receive the first input signal, the control terminals of the eleventh transistor and the twelfth transistor receive the second bias voltage, the intermediate nodes of the eleventh transistor and the positive differential output terminal are the positive differential input signal.

According to another aspect of the present invention, there is provided a low voltage differential signal communication system comprising at least one set of low voltage differential signal transmission lines, each set of low voltage differential signal transmission lines having one end connected to a low voltage differential signal receiving end and the other end connected to at least two low voltage differential signal drivers as described above.

According to the LVDS communication system and the driver thereof, the LVDS driver has two output states of a high-resistance state and a normal state, when the output is the high-resistance state, the voltage value of the first bias voltage is slightly higher than the voltage value of the first bias voltage in the normal state and is smaller than the voltage value of the power supply end, so that when the output state of the LVDS driver is switched from the high-resistance state to the normal state, the discharge time of the parasitic capacitance of the first grid is reduced, the first bias voltage can be quickly restored to the voltage value in the normal state, the enabling speed of the output of the LVDS driver is improved when the output is switched from the high-resistance state to the normal state, and the working frequency limit of the LVDS communication system applying the LVDS driver is reduced.

In a preferred embodiment, when the output state of the LVDS driver is in the high-resistance state, the voltage value of the second bias voltage is close to the voltage range of the second bias voltage in the normal state and is greater than the ground voltage, so that when the output state of the LVDS driver is switched from the high-resistance state to the normal state, the charging time of the parasitic capacitance of the second gate is reduced, and the second bias voltage can be quickly restored to the voltage value in the normal state, thereby further improving the enabling speed when the output state of the LVDS driver is switched from the high-resistance state to the normal state, and further reducing the operating frequency limitation of the LVDS communication system applying the LVDS driver.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

FIG. 1 shows a timing diagram of the operation of two LVDS drivers alternately outputting signals;

FIG. 2 shows a schematic circuit diagram of an LVDS driver;

FIG. 3 shows a schematic circuit diagram of an LVDS driver according to an embodiment of the invention;

Fig. 4 is a timing diagram illustrating the operation of the LVDS driver according to an embodiment of the invention and the LVDS driver shown in fig. 2.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. The same elements or modules are denoted by the same or similar reference numerals in the various figures. For clarity, the various features of the drawings are not drawn to scale.

It should be appreciated that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and/or elements capable of storing instructions for execution by the programmable circuits. When an element or circuit is referred to as being "connected to" another element or circuit is "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present, the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two.

Also, certain terms are used throughout the description and claims to refer to particular components. It will be appreciated by those of ordinary skill in the art that a hardware manufacturer may refer to the same component by different names. The present patent specification and claims do not take the form of an element or components as a functional element or components as a rule.

Furthermore, it should be noted that relational terms such as first and second are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.

Fig. 2 shows a circuit schematic of an LVDS driver. Referring to fig. 2, the lvds driver 100 includes a bias circuit, an output circuit, and a common mode feedback circuit.

Specifically, the bias circuit includes a current source I1, transistors M1-M3, and switches S1-S3. The transistors M1 and M2 form a current mirror, the current source I1, the switch S1 and the transistor M1 are sequentially connected between the power supply voltage VDD and the ground terminal, the transistors M3 and M2 are sequentially connected between the power supply voltage VDD and the ground terminal, the control terminal of the transistor M1 is connected with the first terminal thereof and the control terminal of the transistor M2, the switch S2 is further connected between the control terminal of the transistor M1 and the ground terminal, the switch S3 is connected between the first terminal and the second terminal of the transistor M3, the control terminal of the transistor M3 is connected with the second terminal thereof, the control terminal of the switch S1 receives the enable signal EN, the control terminals of the switches S2 and S3 receive the enable signal ENB, and the enable signal EN is inverted with the enable signal ENB.

The output circuit comprises transistors M4-M9, transistors M4 and M3 form a current mirror, transistors M4, M6, M8 and M5 are sequentially connected between a power supply voltage VDD and a grounding terminal, transistors M7 and M9 are sequentially connected between intermediate nodes of transistors M4 and M6 and intermediate nodes of transistors M8 and M5, a control terminal of transistor M4 is connected with a control terminal of transistor M3, control terminals of transistors M6 and M8 receive an input signal Vin1, and control terminals of transistors M7 and M9 receive an input signal Vin2. The intermediate nodes of transistors M7 and M9 provide the output signal vout+ as positive differential outputs and the intermediate nodes of transistors M6 and M8 provide the output signal Vout-as negative differential outputs. The input signal Vin1 is inverted from the input signal Vin2.

The common mode feedback circuit includes resistors R1 and R2 and an error amplifier 110. The resistors R1 and R2 are sequentially connected between a positive differential output end and a negative differential output end, the positive input end of the error amplifier 110 is connected with the intermediate node of the resistors R1 and R2, the negative input end receives the reference voltage Vref, and the output end is connected with the control end of the transistor M5.

Further, the positive differential output terminal and the negative differential output terminal of the LVDS driver 100 are also connected to the LVDS receiving terminal. The LVDS receiving end comprises a resistor Rt, a capacitor CL1 and a capacitor CL2, wherein the resistor Rt is connected between the positive differential output end and the negative differential output end, the capacitor CL1 is connected between the positive differential output end and the grounding end, the capacitor CL2 is connected between the negative differential output end and the grounding end, and the current flowing through the resistor Rt is driving current Iout.

The bias circuit turns on the switch S1 and turns off the switches S2 and S3 when the enable signal EN Is at a high level, and provides a bias current to the transistor M3 by the transistor M2, so that the control terminal of the transistor M3 provides a bias voltage Vbp1 having a voltage value equal to VDD- |vgs3| (Vgs 3 represents a voltage difference between the gate terminal and the source terminal of the transistor M3) to turn on the transistor M4 to provide a tail current Is, thereby enabling the output circuit to normally generate the output signals vout+ and Vout-, and turns off the switch S1 and turns on the switches S2 and S3 to turn off the transistors M2 and M3 to completely turn off the bias current path when the enable signal EN Is at a low level, and at this time, the bias voltage Vbp1 Is a power supply voltage VDD and the transistor M4 Is turned off. The common mode feedback circuit generates the bias voltage Vbn1 according to the comparison result of the common mode feedback voltage of the output signals vout+ and Vout-and the reference voltage Vref when the enable signal EN is at a high level so that the common mode feedback voltage is stabilized around the reference voltage Vref. The common mode feedback circuit also turns off the transistor M5 when the enable signal EN is low, and at this time, the bias voltage Vbn1 is equal to the ground voltage GND.

In order to meet the requirements of the output swing and the operating frequency, the tail current Is provided by the transistor M4 as the output current source needs to be very large, and Is generally 3.5mA, so that the width-to-length ratio of the transistor M4 Is very large, the transistor M4 has a very large gate parasitic capacitance Cp1, and the gate parasitic capacitance Cp1 causes that the bias circuit needs a long time to discharge the bias voltage Vbp1, that Is, the control terminal voltage of the transistor M4 from the power supply voltage VDD to the required potential vdd—|vgs3|, thereby greatly delaying the enabling time of the LVDS driver 100. In addition, the transistor M5 as a current source also has the gate parasitic capacitance Cp2, and the gate parasitic capacitance Cp2 may cause the common mode feedback circuit to take a long time to charge the bias voltage Vbn1 to a desired potential from the ground voltage GND during the enabling process, thereby extending the settling time of the common mode feedback loop, resulting in an increase in the enabling time required by the LVDS driver 100.

In view of the above, the present invention provides a new LVDS driver to solve the above problems.

Fig. 3 shows a circuit schematic of an LVDS driver according to an embodiment of the invention.

Referring to fig. 3, the LVDS driver 200 according to the embodiment of the present invention has two output states, namely a high-resistance state and a normal state. The LVDS driver 200 includes an output circuit 210, a bias circuit 220, a first clamp circuit 230, a common mode feedback circuit 240, and a second clamp circuit 250.

The output circuit 210 includes a first tail current source, a push-pull circuit, and a second tail current source sequentially connected between a power supply terminal and a ground terminal. The first tail current source Is used for generating a first tail current Is according to the bias voltage Vbp2, and the second tail current source Is used for generating a second tail current according to the bias voltage Vbn 2. The push-pull circuit is used for generating output signals Vout+ and Vout-according to input signals Vin1 and Vin 2. When the LVDS driver 200 is in a normal state, the input signals Vin1 and Vin2 are inverted signals, and the output signals Vout+ and Vout-are differential output signals.

The bias circuit 220 is configured to provide a bias voltage Vbp2 to the first tail current source. The bias circuit 220 has a bias current generating unit for supplying a bias current I4. The first clamp circuit 230 is connected to the bias circuit 220 for providing a bias current I5 to the bias circuit 220. The enable signal EN controls the bias current generating unit to be turned on and off, when the enable signal EN is at a first level, the bias current generating unit is turned on, so that the bias circuit 220 provides the bias voltage Vbp2 of a first preset value to the first tail current source according to the sum of the bias current I4 and the bias current I5, the LVDS driver 200 is in a normal state, and when the enable signal EN is at a second level, the bias current generating unit is turned off, so that the bias circuit 220 provides the bias voltage Vbp2 of a second preset value to the first tail current source according to the bias current I5, and the LVDS driver 200 is in a high-resistance state. The second preset value is smaller than the voltage value VDD of the power supply terminal and larger than the first preset value.

The common mode feedback circuit 240 is configured to compare the common mode feedback voltages of the output signals vout+ and Vout-with the reference voltage Vref when the LVDS driver 200 is in a normal state, so as to provide the bias voltage Vbn2 to the second tail current source according to the comparison result, and adjust the output signals vout+ and Vout-through the bias voltage Vbn2, so that the common mode feedback voltages of the output signals vout+ and Vout-are stabilized around the reference voltage Vref.

The second clamp circuit 250 is connected to the common mode feedback circuit 240 and is configured to provide the bias voltage Vbn2 of the third preset value to the second tail current source when the enable signal EN is at the second level. The third preset value is greater than the voltage value of the ground terminal and less than the range of the bias voltage Vbn2 provided by the common mode feedback circuit 240 when the LVDS driver 200 is in the normal state.

The push-pull circuit comprises transistors M6-M9, the first tail current source being implemented for example with transistor M4 and the second tail current source being implemented for example with transistor M5. The transistors M3 and M4 form a current mirror, and the mirror ratio of the current mirror formed by the transistors M3 and M4 is 1:M. By way of example, M >10. Transistors M4, M6, M8 and M5 are connected in sequence between the power supply terminal and the ground terminal, transistors M7 and M9 are connected in sequence between the intermediate nodes of transistors M4 and M6 and the intermediate nodes of transistors M8 and M5, the control terminal of transistor M4 is connected to the control terminal of transistor M3, the control terminal of transistor M5 receives the bias voltage Vbn2, the control terminals of transistors M6 and M8 receive the input signal Vin1, the control terminals of transistors M7 and M9 receive the input signal Vin2, the intermediate nodes of transistors M7 and M9 provide the output signal vout+ as a positive differential output terminal, and the intermediate nodes of transistors M6 and M8 provide the output signal Vout-as a negative differential output terminal.

The bias circuit 220 further includes a transistor M2, and the bias current generating unit includes a current source I1, transistors M1, M3, and switches S1-S2. Wherein transistors M1 and M2 constitute a current mirror, current source I1 is used to provide bias current I1. The current source I1, the switch S1 and the transistor M1 are sequentially connected between the power end and the ground end, the transistor M3 and the transistor M2 are sequentially connected between the power end and the ground end, the control end of the transistor M1 is connected with the first end and the control end of the transistor M2, the control end of the transistor M3 is connected with the first end, the control end of the transistor M3 provides bias voltage Vbp2 for the first tail current source, the switch S2 is further connected between the control end of the transistor M1 and the ground end, the control end of the switch S1 receives an enable signal EN, the control end of the switch S2 receives an enable signal ENB, and the second end of the transistor M2 provides bias current 14. Wherein the enable signal ENB is inverted to the enable signal EN, i4=k1×i1 (k1 > 0), and k1 is equal to the mirror ratio of the current mirror formed by the transistors M2 and M1, for example, k1=1.

The first clamp 230 includes transistors M10-M11 and a current source I2, the current source I2 for providing a bias current I2. The current source I2 and the transistor M11 are sequentially connected between the power supply terminal and the ground terminal, the transistor M10 is connected between the intermediate node of the transistors M3 and M2 and the ground terminal, the control terminal of the transistor M10 is connected with the intermediate node of the current source I2 and the transistor M11, the control terminal of the transistor M11 is connected with the first terminal thereof, and the first terminal of the transistor M10 provides the bias current I5. Where i5=k2×i2 (k2 > 0), and k2=1, as an example.

Alternatively, the current value of the bias current I4 is much larger than the current value of the bias current I5, for example, the current value of the bias current I4 may be set to be about ten times the current value of the bias current I5. By setting the current values of I5 and I4 to I5< I4, the LVDS driver 200 does not generate a large power consumption even in the high-resistance state.

When the LVDS driver 200 is in the high-resistance state, the second end of the transistor M3 receives the bias current I5, and at this time, the bias voltage Vbp2 is equal to the first preset value, i.e., VDD- |vgs3_a| (vgs3_a represents the voltage difference between the gate end and the source end of the transistor M3 under the influence of the bias current I5). When the LVDS driver 200 is in a normal state, the second terminal of the transistor M3 receives the bias current I4 and the bias current I5, and at this time, the bias voltage Vbp2 is equal to a second preset value, i.e., VDD- |vgs3_b| (Vgs 3_b represents a voltage difference between the gate terminal and the source terminal of the transistor M3 under the influence of the sum of the bias currents I4 and I5).

The common mode feedback circuit 240 includes resistors R1 and R2 and an error amplifier 231. The resistors R1 and R2 are sequentially connected between the positive differential output end and the negative differential output end, the positive input end of the error amplifier 231 is connected with the intermediate node of the resistors R1 and R2, the negative input end receives the reference voltage Vref, and the output end provides the bias voltage Vbn2 for the second tail current source.

The second clamping circuit 250 includes a current source I3 and a transistor M12 sequentially connected between the power supply terminal VDD and the ground terminal, the current source I3 provides a bias current I3, a control terminal of the transistor M12 is connected to the first terminal thereof, a switch S3 is further connected between the control terminal of the transistor M12 and the output terminal of the error amplifier 231, and a control terminal of the switch S3 receives an enable signal ENB. The third preset value is equal to Vgs12 (Vgs 12 represents the voltage difference between the gate and source terminals of transistor M12 under the influence of bias current I3).

The operating principle of the LVDS driver 200 is that when the enable signal EN is at the second level, the LVDS driver 200 is in a high-resistance state, the switch S2 is turned on, and the transistor M2 is turned off, at this time, although the bias current I4 supplied to the transistor M3 is turned off, the bias current I5 supplied to the transistor M3 is not turned off, but flows to the ground through the transistor M10, and thus the bias voltage Vbp2 is not pulled up to the voltage value VDD of the power supply terminal, but is pulled up to VDD- |vgs3_a| by the influence of the bias current I5 flowing through the transistor M10, and is held by the gate parasitic capacitance Cp1 of the transistor M4, and at the same time, the switch S3 is turned on, clamping the voltage value of the bias voltage Vbn2 to Vgs12, and is held by the gate parasitic capacitance Cp2 of the transistor M5. When the enable signal EN Is switched from the second level to the first level, the transistors M1 and M2 are turned on, the bias voltage Vbp2 Is rapidly pulled down to VDD- |vgs3_b| by the bias current I4 flowing through the transistor M2, the tail current Is of the transistor M4 Is stabilized to a preset value (a preset value Is, for example, 3.5 mA), the output of the LVDS driver 200 Is stabilized in a normal state, and at the same time, the switch S3 Is turned off, the bias voltage Vbn2 Is provided by the error amplifier 231, and the common mode feedback loop rapidly becomes stable. The first level is illustratively a high level and the second level is a low level.

Fig. 4 is a timing diagram illustrating operation of the LVDS driver according to an embodiment of the invention and the LVDS driver shown in fig. 2.

Referring to fig. 4, when the enable signal EN is switched from low level to high level, indicating that the output state of the LVDS driver needs to be switched from high-resistance state to normal state, the bias voltage Vbp2 of the LVDS driver 200 provided by the present application reaches the second voltage value within the first time T3, and the bias voltage Vbp1 of the LVDS driver 100 shown in fig. 2 reaches the second voltage value within the second time T2, and it can be seen that the first time T3 is much smaller than the second time T2, so that the enabling speed of the output state of the LVDS driver 200 provided by the present application is faster when the output state of the LVDS driver 200 is switched from high-resistance state to normal state.

Optionally, the transistors M3-M4 and M6-M7 are P-channel metal Oxide Semiconductor field effect transistors (P-CHANNEL METAL-Oxide-Semiconductor, PMOS for short), the transistors M1-M2, M5 and M8-M12 are N-channel metal Oxide Semiconductor field effect transistors (N-CHANNEL METAL-Oxide-Semiconductor, NMOS for short), the first end of the PMOS is a source end, the second end is a drain end, the control end is a gate end, the first end of the NMOS is a drain end, the second end is a source end, and the control end is a gate end.

The LVDS driver 200 provided in the embodiment of the invention has two output states, namely, a high-resistance state and a normal state, when the output state is the high-resistance state, the voltage value of the bias voltage Vbp2 is slightly higher than the voltage value of the bias voltage Vbp2 in the normal state and is smaller than the voltage value VDD of the power supply terminal, and the voltage value of the bias voltage Vbn2 is close to the voltage range of the bias voltage Vbn2 in the normal state and is larger than the ground voltage GND, so that when the output state of the LVDS driver 200 is switched from the high-resistance state to the normal state, the discharge time of the gate parasitic capacitance Cp1 is reduced, the bias voltage Vbp2 can be quickly recovered to the voltage value in the normal state, and the charging time of the gate parasitic capacitance Cp2 is reduced, so that the enabling speed of the output of the LVDS driver 200 when the output is switched from the high-resistance state to the normal state is improved, and the working frequency limitation of the LVDS communication system applying the LVDS driver 200 is reduced.

Further, the present invention also provides an LVDS communication system, which includes at least one group of low voltage differential signaling lines, one end of each group of low voltage differential signaling lines is connected to an LVDS receiving end, and the other end is connected to at least two LVDS drivers 200, where one group of low voltage differential signaling lines includes two signaling lines to respectively transmit output signals vout+ and Vout-. The LVDS receiving terminal may be, for example, an LVDS receiving terminal as shown in fig. 2.

When a set of low voltage differential signaling lines is transmitting signals, only one of the at least two LVDS drivers 200 is in a normal state and the rest is in a high-impedance state. When the LVDS driver 200 is in the high-impedance state, its connection with the low-voltage differential signal transmission line is broken, and the transistors M6-M9 are turned off under control of their control terminal voltages so that the push-pull circuit has no signal output.

Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The scope of the invention should be determined by the appended claims and their equivalents.

Claims (10)

1. A low voltage differential signal driver having two output states, a high resistance state and a normal state, the driver comprising an output circuit, a bias circuit and a first clamp circuit;

The output circuit comprises a push-pull circuit and a first tail current source arranged between a power end and the push-pull circuit, and the push-pull circuit is used for generating a first output signal and a second output signal according to a first input signal and a second input signal;

The bias circuit is used for providing bias voltage for the first tail current source and is provided with a bias current generating unit used for providing a first bias current;

the first clamping circuit is connected with the bias circuit and is used for providing a second bias current for the bias circuit;

The bias current generation unit is controlled by an enabling signal, when the enabling signal is at a first level, the bias current generation unit is turned on, so that the bias circuit provides a bias voltage with a first preset value for the first tail current source according to the sum of the first bias current and the second bias current, and the driver is in a normal state;

The second preset value is smaller than the voltage value of the power supply end and larger than the first preset value.

2. The driver of claim 1, the output circuit further comprising a second tail current source disposed between the push-pull circuit and ground, the driver further comprising:

A common mode feedback circuit for comparing a common mode feedback voltage of the first output signal and the second output signal with a reference voltage to provide a bias voltage to the second tail current source according to a comparison result;

And the second clamping circuit is connected with the common mode feedback circuit and is used for providing bias voltage with a third preset value for the second tail current source when the enabling signal is at a second level, wherein the third preset value is larger than the voltage value of the grounding end and smaller than the range of the bias voltage provided by the common mode feedback circuit when the driver is in a normal state.

3. The driver of claim 1, wherein the bias circuit comprises the bias current generating unit and a second transistor, the bias current generating unit comprising a first current source, a first switch, a second switch, a first transistor, and a third transistor;

The first current source, the first switch and the first transistor are sequentially connected between a power end and a grounding end, a control end of the first switch receives an enabling signal, and a control end of the first transistor is connected with a first end of the first transistor;

The second switch is connected between the control end of the first transistor and the grounding end, and the control end of the second switch receives the inverted signal of the enabling signal;

the second transistor and the third transistor are sequentially connected between a power end and a ground end, a control end of the second transistor provides bias voltage for the first tail current source, a control end of the second transistor is connected with a second end of the second transistor, and a control end of the third transistor is connected with a control end of the first transistor.

4. The driver of claim 3, wherein the first clamp circuit comprises:

The second current source and the fourth transistor are sequentially connected between the power supply end and the grounding end, and the control end of the fourth transistor is connected with the first end of the fourth transistor;

And a fifth transistor connected between the intermediate nodes of the second transistor and the third transistor and the ground, wherein the control end of the fifth transistor is connected with the intermediate nodes of the second current source and the fourth transistor.

5. The driver of claim 1, wherein a current value of the first bias current is greater than a current value of the second bias current.

6. The driver of claim 2, wherein the common mode feedback circuit comprises:

the first resistor and the second resistor are sequentially connected between a positive differential output end and a negative differential output end, the positive differential output end provides the first output signal, and the negative differential output end provides the second output signal;

And the positive input end of the error amplifier is connected with the intermediate node of the first resistor and the second resistor, the negative input end of the error amplifier receives the reference voltage, the output end of the error amplifier provides bias voltage for the second tail current source, and the intermediate node of the first resistor and the second resistor provides the common mode feedback voltage.

7. The driver of claim 3, wherein the second clamp circuit comprises:

The control end of the sixth transistor is connected with the first end of the sixth transistor;

And the control end of the third switch is connected between the control end of the sixth transistor and the output end of the error amplifier, and receives the inverted signal of the enabling signal.

8. The driver of claim 1, wherein the first tail current source comprises a seventh transistor and the second tail current source comprises an eighth transistor.

9. The driver of claim 8, wherein the push-pull circuit comprises ninth through twelfth transistors,

The seventh transistor, the ninth transistor, the tenth transistor and the eighth transistor are sequentially connected between the power supply terminal and the ground terminal, the control terminals of the ninth transistor and the tenth transistor receive the first input signal, the intermediate nodes of the ninth transistor and the tenth transistor are the negative differential output terminals,

The eleventh transistor and the twelfth transistor are sequentially connected between the intermediate nodes of the seventh transistor and the ninth transistor and the intermediate nodes of the tenth transistor and the eighth transistor, the control ends of the eleventh transistor and the twelfth transistor receive the second input signal, and the intermediate nodes of the eleventh transistor and the twelfth transistor are the positive differential output ends.

10. A low voltage differential signal communication system comprising:

At least one set of low voltage differential signal transmission lines,

One end of each group of low-voltage differential signal transmission lines is connected with a low-voltage differential signal receiving end, and the other end is connected with at least two low-voltage differential signal drivers according to any one of claims 1-9.