CN119677136A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN119677136A CN119677136A CN202411667387.6A CN202411667387A CN119677136A CN 119677136 A CN119677136 A CN 119677136A CN 202411667387 A CN202411667387 A CN 202411667387A CN 119677136 A CN119677136 A CN 119677136A
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Abstract
本公开提供了一种半导体器件及其制造方法，该半导体器件包括半导体层与沟槽栅，半导体层包括：埋层，至少部分埋层位于沟槽栅的底部，并与沟槽栅相连；体区，与沟槽栅的侧壁相连；源区，与沟槽栅的侧壁相连，源区自第一表面朝体区的方向延伸，并与体区相连；以及漂移区，至少部分漂移区位于体区和第二表面之间，并与埋层和体区相连，其中，至少部分埋层的底端还设置有端部掺杂区，端部掺杂区的宽度大于埋层的底端宽度。通过在沟槽栅的底部设置埋层，且在至少部分埋层底端设置端部掺杂区，从而提升了器件的耐压能力。
The present disclosure provides a semiconductor device and a manufacturing method thereof, wherein the semiconductor device comprises a semiconductor layer and a trench gate, wherein the semiconductor layer comprises: a buried layer, at least part of which is located at the bottom of the trench gate and connected to the trench gate; a body region, connected to the sidewall of the trench gate; a source region, connected to the sidewall of the trench gate, the source region extending from a first surface toward the body region and connected to the body region; and a drift region, at least part of which is located between the body region and a second surface and connected to the buried layer and the body region, wherein at least part of the buried layer is further provided with an end doping region at the bottom, and the width of the end doping region is greater than the width of the bottom of the buried layer. By providing a buried layer at the bottom of the trench gate and providing an end doping region at at least part of the bottom of the buried layer, the voltage resistance of the device is improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor device technology, and more particularly, to a semiconductor device having a trench gate structure and a method of manufacturing the same.
Background
In a vertical transistor with a trench gate, the drain of the transistor needs to be able to withstand high voltages. Because PN junction exists between the drain electrode and the source electrode, the high-voltage-resistant power supply has better bearing capacity with high voltage.
However, between the drain and the trench gate, high voltage is not easily sustained due to the gate dielectric layer. Particularly, the high voltage resistance is poor at the bottom of the trench gate, and the overall voltage resistance of the device is reduced. Accordingly, improvements in devices are needed to ameliorate the above problems.
Disclosure of Invention
In view of the foregoing, an object of the present disclosure is to provide a semiconductor device and a method for manufacturing the same, in which a buried layer is provided at a bottom of a trench gate, and an end doping region is provided at a bottom end of at least a portion of the buried layer, thereby improving a withstand voltage capability of the device.
According to an aspect of an embodiment of the present disclosure, there is provided a semiconductor device including a semiconductor layer having opposite first and second surfaces, and a trench gate in a trench of the first surface of the semiconductor layer,
The semiconductor layer includes:
a buried layer, at least part of which is positioned at the bottom of the trench gate and connected with the trench gate;
the body region is connected with the side wall of the trench gate;
A source region connected to the sidewall of the trench gate and extending from the first surface toward the body region and connected to the body region, and
A drift region, at least part of which is located between the body region and the second surface and is connected with the buried layer and the body region,
And the bottom end of at least part of the buried layer is also provided with an end doping region, and the width of the end doping region is larger than that of the bottom end of the buried layer.
Optionally, the source region and the drift region are of a first conductivity type, and the buried layer, the end doped region and the body region are of a second conductivity type, the first conductivity type being opposite to the second conductivity type.
Optionally, at least part of the buried layer is tapered in width from the first surface towards the second surface.
Optionally, the width of the end doped region does not exceed the width of the wide end of the buried layer.
Optionally, the buried layer is in a multi-section inverted boss shape from the first surface toward the second surface.
Optionally, the doping concentration of the buried layer decreases from the first surface toward the second surface.
Optionally, the doping concentration of the buried layer decreases from the middle of the buried layer towards the side edges of the buried layer.
Optionally, an included angle between a bottom surface of the trench gate connected with the buried layer and a side edge of the buried layer is 80 ° to 40 °.
Optionally, the buried layer includes:
a first buried layer positioned at the bottom of the trench gate and connected with the trench gate,
The end doped region is arranged at the bottom end of the first buried layer.
Optionally, the width of the trench gate is greater than the width of the first buried layer.
Optionally, the buried layer includes:
A second buried layer separated from the trench gate, the body region being located between the second buried layer and the first surface and connected to the second buried layer,
The end doped region is arranged at the bottom end of the second buried layer.
Optionally, along the width direction of the trench gate, the body region, the source region and the second buried layer are all located at two sides of the trench gate.
According to another aspect of the embodiments of the present disclosure, there is provided a method of manufacturing a semiconductor device, including:
forming a buried layer in a semiconductor layer, the semiconductor layer having opposite first and second surfaces;
forming a well region in the semiconductor layer, wherein the well region extends from the first surface towards the first buried layer and is connected with the buried layer;
Forming a source region in the well region, the source region extending from the first surface into the well region, and
Forming a groove on the first surface, forming a groove gate in the groove, at least part of the buried layer is positioned at the bottom of the groove gate and connected with the groove gate,
And an end doping region is formed at the bottom end of at least part of the buried layer, and the width of the end doping region is larger than that of the bottom end of the buried layer.
Optionally, the step of forming a buried layer in the semiconductor layer includes:
forming a hard mask on the first surface, performing a first ion implantation to the semiconductor layer through the hard mask, and
Forming at least one side wall on the side wall of the hard mask, carrying out ion implantation once on the semiconductor layer through the hard mask after each side wall is formed once,
Wherein the depth of each ion implantation is greater than the depth of the previous ion implantation.
Optionally, the step of forming the end doped region includes:
performing deep ion implantation to the semiconductor layer through the hard mask to form a deep doped region between the last side wall and the first side wall,
Wherein the deep doped region is unconnected to the first surface of the semiconductor layer and is used for forming the end doped region.
One of the above technical solutions has the following beneficial effects:
Through setting up the buried layer in the semiconductor layer, and at least part buried layer is located the bottom of trench gate, along the direction of the first surface of semiconductor layer towards the second surface, through reducing the width of buried layer gradually, thereby make the flow path of carrier enlarge, and then reduced the hindrance of buried layer to carrier flow, the on-resistance of device has been reduced, through setting up the tip doped region at the narrow end of buried layer, utilize the PN junction that tip doped region and drift formed to further promote the withstand voltage ability of device, thereby compromise the withstand voltage ability that improves the device when being favorable to widening carrier flow path.
In some embodiments, the body region and the source region are disposed on two sides of the trench gate and connected to the sidewalls of the trench gate, so that two sides of the trench gate can be used as a conductive channel (channel), thereby reducing the resistance of the device in the on state.
In some embodiments, the maximum width of the first buried layer is smaller than the width of the bottom of the trench gate, so that the first buried layer can only contact with the bottom of the trench gate, but can not wrap corners of the trench gate, the obstruction of the first buried layer to carrier flow is further reduced, and the on-resistance of the device is reduced.
In some embodiments, the self-aligned process of the hard mask and the side wall is used for performing ion implantation for multiple times, so that the implantation width is gradually reduced, and meanwhile, the implantation depth is gradually deepened, so that a topography that the width of the buried layer is gradually reduced from the first surface of the semiconductor layer to the second surface is realized. In addition, the self-alignment process can save the number of mask plates, and the alignment precision is high.
In some embodiments, the first buried layer and the second buried layer are formed in the semiconductor layer simultaneously by adopting an ion implantation process, so that the number of mask plates is reduced, patterns of the first buried layer and the second buried layer do not need to be additionally aligned, the process difficulty is reduced, and the cost is saved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following brief description of the drawings of the embodiments will make it apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.
Fig. 1 shows a schematic top view of a semiconductor device according to a first embodiment of the present disclosure.
Fig. 2 shows a schematic cross-sectional view taken along line AA in fig. 1.
Fig. 3 shows a schematic structural diagram of a semiconductor device of a second embodiment of the present disclosure.
Fig. 4 shows a schematic structural diagram of a semiconductor device of a third embodiment of the present disclosure.
Fig. 5 to 11 are schematic structural views showing a part of stages in the manufacturing method of the semiconductor device of the first embodiment of the present disclosure.
Detailed Description
The present disclosure will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The semiconductor structure obtained after several steps may be depicted in one figure for simplicity.
It will be understood that when a layer, an area, or a structure of a device is described as being "on" or "over" another layer, another area, it can be referred to as being directly on the other layer, another area, or further layers or areas can be included between the other layer, another area, etc. And if the device is flipped, the one layer, one region, will be "under" or "beneath" the other layer, another region.
If, for the purposes of describing a situation directly on top of another layer, another area, expressions such as "directly on top of" or "on top of and adjacent to" will be used herein.
Power devices typically include an active element region, an edge termination region, and a crack-stop (or shield) region. The active element region includes an active element array. The present disclosure relates to active element structures. The dimensions of the active elements may vary depending on the product requirements and there may be body regions between the active elements in the active element region.
Numerous specific details of the present disclosure, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a more thorough understanding of the present disclosure. However, as will be understood by those skilled in the art, the present disclosure may be practiced without these specific details.
In a vertical transistor, such as a SiC MOSFET, it is necessary to be able to withstand a high voltage applied to the drain. Because PN junction exists between the drain electrode and the source electrode, the high-voltage-resistant power supply has better bearing capacity with high voltage. However, between the drain and the trench gate, high voltage is not easily sustained due to the gate dielectric layer. Particularly, the high voltage resistance of the gate dielectric layer at the bottom of the trench gate is poor, and a gate shielding structure is required to be designed separately. In order to improve the above-mentioned problem, an object of the present disclosure is to provide a semiconductor device, in which the entire withstand voltage capability of the device is improved by a first buried layer provided at the bottom of a trench gate, and in which the on-resistance is reduced by gradually reducing the width of the first buried layer, thereby reducing the obstruction of the buried layer to carrier flow.
Fig. 1 shows a schematic top view of a semiconductor device according to a first embodiment of the present disclosure, and fig. 2 shows a schematic cross-sectional view taken along the line AA in fig. 1, wherein fig. 1 shows only a buried layer and a trench gate, and other structures are omitted to more clearly express the positional relationship between the respective structures.
As shown in fig. 1 and 2, the semiconductor device of the first embodiment of the present disclosure includes a semiconductor layer 100, a plurality of trench gates 150, an interlayer dielectric layer 160, a first conductive layer 171, and a second conductive layer 172. The semiconductor layer 100 has opposing first and second surfaces 101 and 102 and a plurality of trenches in the first surface 101 extending into the semiconductor layer 100 from the first surface 101 toward the second surface 102. A plurality of trench gates 150 are located in the corresponding trenches. The semiconductor layer 100 is, for example, a SiC, gaN, ga 2O3、Al2O3 substrate or a stacked structure of a substrate and an epitaxial layer. However, the embodiments of the present disclosure are not limited thereto, and those skilled in the art may perform other settings on the material of the semiconductor layer, the number of layers, such as other wide bandgap semiconductor materials, etc., as required.
The semiconductor layer 100 includes a drift region 110, a buried layer 120, end doped regions 121a and 122a, a body region 131, a source region 141, and a body contact region 142. The buried layer 120 includes a first buried layer 121 and a second buried layer 122, the source region 141 and the drift region 110 are of a first conductivity type, the first buried layer 121, the second buried layer 122, the end doped regions 121a and 121b, the body region 131 and the body contact region 142 are of a second conductivity type, and the doping concentration of the body contact region 142 is greater than that of the body region 131. The first conductivity type is opposite to the second conductivity type. The first conductivity type is one of P-type and N-type, and the second conductivity type is the other of P-type and N-type.
The semiconductor device of the present embodiment may be used as a Metal-Oxide-semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT), for example, a drain contact region is provided on the second surface 102 of the semiconductor layer 100, and the conductivity type of the drain contact region is set to be the first conductivity type or the second conductivity type, respectively. However, the embodiments of the present disclosure are not limited thereto, and those skilled in the art may make other settings of the conductivity type of each region in the semiconductor layer as needed to make the semiconductor device a MOSFET or an IGBT.
Trench gate 150 includes a gate dielectric layer 151 and a gate conductor 152. A gate dielectric layer 151 covers the inner surface of the trench in which the gate conductor 152 is located. A gate dielectric layer 151 is located between the semiconductor layer 100 and the gate conductor 152 for separating the semiconductor layer 100 from the gate conductor 152. The width direction of the trench gate 150 is the X-axis direction, the depth direction is the Z-axis direction, and the length direction is the Y-axis direction, and optionally, the X-axis, Y-axis, and Z-axis directions are perpendicular to each other.
The first buried layer 121 is located at the bottom of the trench gate 150. The second buried layer 122, the body region 131, the source region 141, and the body contact region 142 are located at both sides of the trench gate 150 in the X-axis direction.
The first buried layer 121 is connected to the trench gate 150, wherein the width of the first buried layer 121 is smaller than the width of the trench gate 150, so that the first buried layer 121 is located only at the bottom of the trench gate 150 and does not wrap around corners of the trench gate 150.
The first buried layer 121 and the second buried layer 122 each extend in the Y-axis direction and are separated from each other. The second buried layer 122 is not connected to the trench gate 150. Alternatively, the doping concentration of the first buried layer 121 decreases from the first surface 101 toward the second surface 102 of the semiconductor layer 100, and the doping concentration of the first buried layer 121 decreases from the middle of the first buried layer 121 toward the side edge of the first buried layer 121. Optionally, the second buried layer 122 has a similar doping concentration profile as the first buried layer 121.
The width of the first buried layer 121 gradually narrows from the bottom of the trench gate 150 toward the second surface 102. The second buried layer 122 has a similar morphology to the first buried layer 121, and the width of the second buried layer 122 gradually narrows from the bottom of the body region 131 toward the second surface 102, and accordingly, the drift region 100 between the first buried layer 121 and the second buried layer 122 gradually widens.
Alternatively, the inclination angle α between the first buried layer 121 and the bottom of the trench gate 150 is 80 ° to 40 °, that is, the bottom surface of the trench gate 150 connected to the first buried layer 121 and the side edge of the first buried layer 121 have an angle α of 80 ° to 40 °. In some embodiments, the tilt angle α may be a range of angles of 80 °, 75 °, 70 °, 65 °, 60 °, 55 °, 50 °, 45 °, 40 °, etc., or other angles.
The tilt angle between the second buried layer 122 and the bottom of the body region 131 is 80 ° to 40 °, and in some embodiments, the tilt angle α may be a series of angles of 80 °, 75 °, 70 °,65 °, 60 °, 55 °, 50 °, 45 °, 40 °, or other angles.
In this embodiment, the end doped region 121a is disposed at the bottom end (narrow end) of the first buried layer 121 and is connected to the bottom end of the first buried layer 121, and the width of the end doped region 121a is greater than the bottom end width of the first buried layer 121. The end doped region 122a is disposed at a bottom end (narrow end) of the second buried layer 122 and is connected to the bottom end of the second buried layer 122, and the width of the end doped region 122a is greater than the bottom end width of the second buried layer 122.
The body region 131 is connected to both sidewalls of the trench gate 150 and the second buried layer 122, respectively, along the X-axis direction. The source region 141 extends from the first surface 101 of the semiconductor layer 100 toward the body region 131 and is connected to the body region 131. The body contact region 142 extends from the first surface 101 of the semiconductor layer 100 toward the body region 131 and is connected to the body region 131. Alternatively, the source region 141 and the body contact region 142 may be connected or may be separated by the body region 131. At least a portion of the drift region 110 is located between the body region 131 and the second surface 102 of the semiconductor layer 100 and is connected to the first buried layer 121, the second buried layer 122 and the body region 131.
An interlayer dielectric layer 160 is located on the first surface 101 of the semiconductor layer 100 and covers the trench gate 150. The first conductive layer 171 serves as a source electrode and covers the first surface 101 of the semiconductor layer 100 and the interlayer dielectric layer 160. The second conductive layer 172 serves as a drain electrode covering the second surface 102 of the semiconductor layer 100.
In the present embodiment, the plurality of trench gates 150 are spaced apart in the Y-axis direction, and the body region 131 and the source region 141 are further located between adjacent trench gates 150 in the Y-axis direction. In some other embodiments, trench gate 150 extends continuously along the Y-axis direction.
In this embodiment, when the device is turned on, the portion of the body region 131 adjacent to the sidewall of the trench gate 150 is inverted to form a channel, and carriers flow from the source (the first conductive layer 171) and then flow to the drift region 110 via the source region 141 and the channel, and finally flow out from the drain (the second conductive layer 172), see a carrier flow path shown by a dotted line in fig. 2.
By arranging the first buried layer 121 and the second buried layer 122 in a direction from the first surface 101 toward the second surface 102 of the semiconductor layer 100, the widths of the first buried layer 121 and the second buried layer 122 are gradually reduced, so that the flow channel of carriers is enlarged, the obstruction of the first buried layer 121 and the second buried layer 122 to the flow of carriers is greatly reduced, and the on-resistance of the device is reduced. By arranging the end doped regions 121a and 122a at the narrow ends of the first buried layer and the second buried layer, the voltage withstand capability of the device is further improved by utilizing PN junctions formed by the end doped regions 121a and 122a and the drift region 110, and along with the continuous reduction of the size of the device, the scheme is more beneficial to widening the carrier flow channel and simultaneously improving the voltage withstand capability of the device.
Further, by disposing the body region 131 and the source region 141 on both sides of the trench gate 150 and connecting the body region and the walls of the trench gate 150, both sides of the trench gate 150 can be used as conductive channels (channels), so that the resistance of the device in the on state is reduced.
Fig. 3 shows a schematic structural diagram of a semiconductor device of a second embodiment of the present disclosure.
As shown in fig. 3, the semiconductor device of the second embodiment of the present disclosure is the same as that of the first embodiment and will not be described again here, and reference is made to the description about fig. 1 and 2. The difference is that in the present embodiment, the end doped region 121a is provided only at the narrow end of the first buried layer 121, and the narrow end of the second buried layer 122 is not provided with the end doped region 122a. In some alternative embodiments, the second buried layer 122 may not be provided.
Fig. 4 shows a schematic structural diagram of a semiconductor device of a third embodiment of the present disclosure.
As shown in fig. 4, the semiconductor device of the third embodiment of the present disclosure is the same as that of the first embodiment and will not be described again here, and reference is made to the description about fig. 1 and 2. The difference is that in the present embodiment, the end doped region 122a is provided only at the narrow end of the second buried layer 122, and the narrow end of the first buried layer 121 is not provided with the end doped region 121a.
Fig. 5 to 11 are schematic structural views showing a part of stages in the manufacturing method of the semiconductor device of the first embodiment of the present disclosure.
Referring to fig. 5, a hard mask 200 is formed on the first surface 101 of the semiconductor layer 100, wherein a space between adjacent hard masks 200 corresponds to the first buried layer 121 and the second buried layer 122 formed in the subsequent steps.
In this step, a hard mask layer is formed on the first surface 101 of the semiconductor layer 100, for example, using a deposition process, and the material of the hard mask layer includes silicon oxide, silicon nitride, and the like, for example. The hard mask layer is then patterned using a photolithography, etching process to form the hard mask 200.
Further, a first ion implantation is performed to the semiconductor layer 100 through the hard mask 200 to form a first doped region 210.
In this step, the hard mask 200 blocks the impurity doping while performing the first ion implantation to form the first doped region 210, and allows only the impurity doping to enter the semiconductor layer 100 from the interval between the adjacent hard masks 200.
Further, a first sidewall 201 is formed on the sidewall of the hard mask 200, as shown in fig. 6.
In this step, for example, a deposition process is first used to cover the hard mask 200 and the first surface 101 of the semiconductor layer 100 to form a sidewall deposition layer, then, without performing a photolithography step, an etching process is directly used to remove the first surface 101 and the sidewall deposition layer on top of the hard mask 200, and the sidewall deposition layer remaining on the sidewall of the hard mask 200 is used as the first sidewall 201.
Further, a second ion implantation is performed to the semiconductor layer 100 through the hard mask 200 to form a second doped region 220.
In this step, since the hard mask 200 and the first sidewall 201 block the impurity doping, the width of the second doped region 220 is smaller than that of the first doped region 210. And the second ion implantation depth is greater than the implantation depth of the first ion implantation, and thus the depth of the second doped region 220 is greater than the depth of the first doped region 210.
Further, a second sidewall 202 is formed on the sidewall of the hard mask 200, and the second sidewall 202 is connected to the first sidewall 201, as shown in fig. 7, where a method for forming the second sidewall 202 is similar to that of the first sidewall 201, and will not be described herein.
Further, a third ion implantation is performed to the semiconductor layer 100 through the hard mask 200 to form a third doped region 230.
In this step, since the hard mask 200, the first sidewall 201 and the second sidewall 202 each block the impurity, the width of the third doped region 230 is smaller than that of the second doped region 220. And the third ion implantation depth is greater than the second ion implantation depth, and thus the third doped region 230 is greater than the second doped region 220.
Further, deep ion implantation is performed to the semiconductor layer 100 through the hard mask 200 to form a deep doped region 231, wherein the deep doped region 231 is not connected to the first surface 101 of the semiconductor layer 100.
In this step, the hard mask 200, the first sidewall 201 and the second sidewall 202 are still used to block the doped impurities, so that the width of the deep doped region 231 is the same as that of the third doped region 230. The ion implantation energy for forming the deep doped region 231 is greater than the energy for forming the third doped region 230, and thus the depth of the deep doped region 231 is greater than the depth of the third doped region 230 and is not connected to the third doped region 230.
Further, a third sidewall 203 is formed on the sidewall of the hard mask 200, and the third sidewall 203 is connected to the second sidewall 202, as shown in fig. 8, where a method for forming the third sidewall 203 is similar to that of the first sidewall 201, and will not be described herein.
Further, a fourth ion implantation is performed into the semiconductor layer 100 through the hard mask 200 to form a fourth doped region 240.
In this step, since the hard mask 200, the first sidewall 201, the second sidewall 202 and the third sidewall 203 each block the doping impurities, the width of the fourth doping region 240 is smaller than that of the third doping region 230. And the fourth ion implantation depth is greater than the third ion implantation depth, and thus, the fourth doped region 240 has a depth greater than the third doped region 230 and is connected to the deep doped region 231. Optionally, the bottom of the fourth doped region 240 is the same depth as the bottom of the deep doped region 231, or the bottom of the fourth doped region 240 is the same depth as the top of the deep doped region 231.
In this embodiment, the first doped region 210, the second doped region 220, the third doped region 230, and the fourth doped region 240 formed by four ion implantations together form the first buried layer 121 and the second buried layer 122 having inclined sidewalls. Wherein the deep doped region 231 is used to constitute end doped regions 121a, 122a respectively connected to the first buried layer 121 and the second buried layer 122. Referring to fig. 7, in this cross section, the pattern formed by the first, second, third and fourth doped regions 210, 220, 230 and 240 together is formed of a plurality of rectangles, the widths of which decrease from top to bottom, thereby forming the first and second buried layers 121 and 122 having inclined sidewalls. After the trench gate 150 is formed in the subsequent step, the first buried layer 121 is in a multi-segment inverted boss shape from the bottom of the trench gate 150 toward the second surface 102 of the semiconductor layer 100, the multi-segment inverted boss shape forms the first buried layer 121 having inclined sidewalls with gradually decreasing widths, the inclined sidewalls of the first buried layer 121 are smoother as the number of the boss-shaped segments is greater, and the second buried layer 122 has a similar morphology to the first buried layer 121.
In this embodiment, the deep doped region 231 is formed after the second sidewall 202 is formed, and the width is the same as that of the third doped region 230. In some other embodiments, the deep doped region 231 is formed after the first sidewall 201 is formed, and at this time, the width of the deep doped region 231 should be the same as the width of the second doped region 220.
In this embodiment, in the middle portion of the first buried layer 121, there is a region where ion implantation is performed multiple times, so that the doping concentration from the middle portion to the side edge portion of the first buried layer 121 has a gradient change, and the doping concentration in the middle portion is greater than that in the side edge portion. The electric field at the bottom of the trench gate formed later is more uniform. Similarly, the doping concentration of the first buried layer 121 from shallow to deep also has a gradient change, that is, in the portion of the first buried layer 121 closer to the first surface 101 of the semiconductor layer 101, the greater the doping concentration, and the portion farther from the first surface 101, the lesser the doping concentration, because of the overlapping region having multiple ion implantation. While the second buried layer 122 has a similar doping concentration profile as the first buried layer 121.
In this embodiment, the first sidewall 201, the second sidewall 202 and the third sidewall 203 are not patterned by using a photolithography process during formation, but are directly formed by using an etching process after the formation of the sidewall deposition layer, so that the hard mask layer is patterned only before the first ion implantation when the first buried layer 121 and the second buried layer 122 having the inclined sidewalls are formed, and the doping region is formed by using the sidewall process in a self-aligned manner without adding an additional patterning process during the subsequent ion implantation process. And the inclination angles of the first buried layer 121 and the second buried layer 122 may be adjusted by changing the interval between adjacent hard masks 200, the thickness of each sidewall, and the energy at the time of ion implantation.
In this embodiment, the first buried layer 121 and the second buried layer 122 are formed by three times of sidewall process. However, the embodiments of the present disclosure are not limited thereto, and a person skilled in the art may adjust the number of the spacers and the number of times of ion implantation according to need, at least one spacer needs to be formed on the sidewall of the hard mask 200, and after each spacer is formed, ion implantation is performed on the semiconductor layer 100 through the hard mask 200, wherein the depth of each ion implantation is greater than the depth of the previous ion implantation, and between the formation of the last spacer and the first spacer, deep ion implantation is performed on the semiconductor layer 100 through the hard mask 200 to form the deep doped region 231.
In this embodiment, the first buried layer 121 and the second buried layer 122 are formed in the semiconductor layer 100 simultaneously by using the ion implantation process, so that the number of mask plates can be reduced, patterns of the first buried layer 121 and the second buried layer 122 do not need to be additionally aligned, and the process difficulty is reduced, so that the cost is saved.
Further, a well region 130 is formed in the semiconductor layer 100, the well region 130 extending from the first surface 101 of the semiconductor layer 100 toward the first buried layer 121 and the second buried layer 122 and being connected to the first buried layer 121 and the second buried layer 122, respectively, as shown in fig. 9, wherein the undoped semiconductor layer 100 serves as the drift region 110.
Further, a source region 141 and a body contact region 142 are formed in the well region 130, the source region 141 and the body contact region 142 extending from the first surface 101 of the semiconductor layer 100 into the well region 130, as shown in fig. 10, wherein the undoped well region 130 serves as the body region 131.
Further, a trench extending from the first surface 101 of the semiconductor layer 100 to the first buried layer 121 is formed, and a trench gate 150 is formed in the trench, as shown in fig. 11. Wherein the width of the trench gate 150 is greater than the width of the first buried layer 121.
Further, the interlayer dielectric layer 160 and the first conductive layer 171 are formed on the first surface 101 of the semiconductor layer 100, and the second conductive layer 172 is formed on the second surface 102 of the semiconductor layer 100, thereby forming the semiconductor device as shown in fig. 1 and 2.
In some embodiments, the first buried layer 121 and the second buried layer 122 may be formed by using more sidewall processes and ion implantation processes, and the better tilt angle structures of the first buried layer 121 and the second buried layer 122 may be formed by using more sidewall processes and ion implantation processes.
The semiconductor device of the second and third embodiments of the present disclosure is substantially similar to the semiconductor device of the first embodiment, and may be described with reference to the related description of the first embodiment, except that the end doped region 121a is provided only at the narrow end of the first buried layer 121, and the narrow end of the second buried layer 122 is not provided with the end doped region 122a. Or only the end doped region 122a is provided at the narrow end of the second buried layer 122, while the end doped region 121a is not provided at the narrow end of the first buried layer 121.
The embodiments of the present disclosure are described above. These examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.
Claims (14)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411667387.6A CN119677136A (en) | 2024-11-20 | 2024-11-20 | Semiconductor device and method for manufacturing the same |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202411667387.6A CN119677136A (en) | 2024-11-20 | 2024-11-20 | Semiconductor device and method for manufacturing the same |
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| CN119677136A true CN119677136A (en) | 2025-03-21 |
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| CN202411667387.6A Pending CN119677136A (en) | 2024-11-20 | 2024-11-20 | Semiconductor device and method for manufacturing the same |
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