CN119675640A

CN119675640A - Power-on reset detection circuit and chip

Info

Publication number: CN119675640A
Application number: CN202411737624.1A
Authority: CN
Inventors: 祝贺; 黄金煌
Original assignee: Beijing Unigroup Tsingteng Microsystems Co Ltd
Current assignee: Beijing Unigroup Tsingteng Microsystems Co Ltd
Priority date: 2024-11-29
Filing date: 2024-11-29
Publication date: 2025-03-21

Abstract

The present application relates to the technical field of integrated circuits, and discloses a power-on reset detection circuit, including: a bias generation circuit, including a bias resistor and a second MOS tube connected in series, the bias resistor is connected to a power supply voltage to generate a bias voltage; wherein the second MOS tube operates in a subthreshold region; a detection circuit, including a first resistor, a first MOS tube, and a second resistor connected in series in sequence; the gate of the first MOS tube is connected to the bias voltage generated by the bias generation circuit, and the drain voltage of the first MOS tube is used as a detection point voltage of the power supply voltage; a comparison circuit, respectively connected to the bias voltage of the bias generation circuit and the detection point voltage of the detection circuit, for comparing the magnitude of the bias voltage and the detection point voltage. The detection circuit helps to reduce the discrete range of the power supply voltage detection of the power-on reset detection module, so that the reset voltage of the chip does not change with temperature. The present application also discloses a chip.

Description

Power-on reset detection circuit and chip

Technical Field

The application relates to the technical field of integrated circuits, for example to a power-on reset detection circuit and a chip.

Background

The power-on reset detection circuit is used for providing a reset signal for the chip so as to prevent the chip from continuously working in an environment with excessively low (under-voltage) power supply voltage. Since the power-on reset detection circuit has a certain discrete range for detecting the power supply voltage, the highest value of the detection voltage is generally set as the lowest working voltage of the chip. However, for the NVM (Non-Volatile Memory) chip, the operation mode is entered after the reset signal of the power-on reset detection circuit is released. This results in the fact that the actual operating voltage of the internal circuitry of the chip must be able to detect the lowest value of the voltage detected by the reset detection circuit, otherwise it may cause the NVM chip to have a functional abnormality in some operating scenarios.

If the working voltage of the internal circuit of the chip is reduced, the design difficulty and the cost are increased, and the use scene of the chip does not support the raising of the minimum working voltage of the chip.

Disclosure of Invention

The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview, and is intended to neither identify key/critical elements nor delineate the scope of such embodiments, but is intended as a prelude to the more detailed description that follows.

The embodiment of the disclosure provides a power-on reset detection circuit and a chip, so as to reduce the discrete range of power-on reset detection module for detecting power supply voltage, thereby enabling the internal circuit of the chip to work at higher voltage.

In some embodiments, the circuit comprises a bias generation circuit, a detection circuit and a comparison circuit, wherein the bias generation circuit comprises a bias resistor and a second MOS tube which are connected in series, the bias resistor is connected with a power supply voltage to generate bias voltage, the second MOS tube works in a subthreshold region, the detection circuit comprises a first resistor, a first MOS tube and a second resistor which are sequentially connected in series, the grid electrode of the first MOS tube is connected with the bias voltage generated by the bias generation circuit, the drain voltage of the first MOS tube is used as a detection point voltage of the power supply voltage, and the comparison circuit is respectively connected with the bias voltage of the bias generation circuit and the detection point voltage of the detection circuit and is used for comparing the bias voltage and the detection point voltage.

In some embodiments, the chip comprises a chip body and a power-on reset detection circuit connected with the chip body, wherein the chip body enters a working mode when the power-on reset detection circuit outputs a reset signal, and the power-on reset detection circuit outputs the reset signal when the voltage of the detection point is larger than a preset voltage.

The power-on reset detection circuit and the chip provided by the embodiment of the disclosure can realize the following technical effects:

The bias generating circuit and the detection circuit are designed to enable the detection point voltage to have a temperature compensation function. I.e. the detection point voltage does not vary with temperature, and is relatively constant for the supply voltage. The power-on reset detection module is beneficial to reducing the discrete range of power supply voltage detection, so that the reset voltage of the chip does not change along with the temperature. Thereby allowing the internal circuitry of the chip to operate at higher voltages.

The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which like reference numerals refer to similar elements, and in which:

FIG. 1 is a schematic diagram of a power-on reset detection circuit according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of another power-on-reset detection circuit provided in an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of another power-on-reset detection circuit provided by an embodiment of the present disclosure;

Fig. 4 is a schematic diagram of an equivalent circuit structure of fig. 3 provided in an embodiment of the present disclosure.

Reference numerals:

10, a bias generating circuit, 20, a detecting circuit, 30, a comparing circuit, 40, a trigger logic circuit, R1, R2, R3, R1A, M1, M2, M3, M4, M5, M6, and M6.

Detailed Description

So that the manner in which the features and techniques of the disclosed embodiments can be understood in more detail, a more particular description of the embodiments of the disclosure, briefly summarized below, may be had by reference to the appended drawings, which are not intended to be limiting of the embodiments of the disclosure. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may still be practiced without these details. In other instances, well-known structures and devices may be shown simplified in order to simplify the drawing.

The terms first, second and the like in the description and in the claims of the embodiments of the disclosure and in the above-described figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe embodiments of the present disclosure. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.

In the embodiments of the present disclosure, the terms "upper", "lower", "inner", "middle", "outer", "front", "rear", and the like indicate an azimuth or a positional relationship based on that shown in the drawings. These terms are used primarily to better describe embodiments of the present disclosure and embodiments thereof and are not intended to limit the indicated device, element, or component to a particular orientation or to be constructed and operated in a particular orientation. Also, some of the terms described above may be used to indicate other meanings in addition to orientation or positional relationships, for example, the term "upper" may also be used to indicate some sort of attachment or connection in some cases. The specific meaning of these terms in the embodiments of the present disclosure will be understood by those of ordinary skill in the art in view of the specific circumstances.

In addition, the terms "disposed," "connected," "secured" and "affixed" are to be construed broadly. For example, the term "coupled" may be a fixed connection, a removable connection, or a unitary construction, may be a mechanical connection, or an electrical connection, may be a direct connection, or may be an indirect connection via an intermediary, or may be an internal communication between two devices, elements, or components. The specific meaning of the above terms in the embodiments of the present disclosure may be understood by those of ordinary skill in the art according to specific circumstances.

The term "plurality" means two or more, unless otherwise indicated.

In the embodiment of the present disclosure, the character "/" indicates that the front and rear objects are an or relationship. For example, A/B represents A or B.

The term "and/or" is an associative relationship that describes an object, meaning that there may be three relationships. For example, A and/or B, represent A or B, or three relationships of A and B.

It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other.

As shown in conjunction with fig. 1, an embodiment of the present disclosure provides a power-on reset detection circuit including a bias generation circuit 10, a detection circuit 20, and a comparison circuit 30. The bias generation circuit 10 includes a bias resistor Rb and a second MOS transistor M2 connected in series, where the bias resistor Rb is connected to the power supply voltage VCC to generate the bias voltage VBIAS. The detection circuit comprises a first resistor R1, a first MOS tube M1 and a second resistor R2 which are sequentially connected in series, wherein the grid electrode of the first MOS tube M1 is connected with bias voltage VBIAS generated by the bias generating circuit, and the drain voltage of the first MOS tube M1 is used as detection point voltage VDET of power supply voltage VCC. The comparison circuit 30 is connected to the bias voltage VBIAS of the bias generation circuit 10 and the detection point voltage VDET of the detection circuit 20, respectively, and compares the magnitudes of the bias voltage and the detection point voltage.

Here, one end of the bias resistor of the bias generating circuit is connected to the power supply voltage, the other end is connected to the drain electrode and the gate electrode of the second MOS transistor M2, and the source electrode of the second MOS transistor M2 is grounded. Thus, the second MOS transistor M2 operates after power-up, and generates the bias voltage VBIAS. The detection circuit comprises a first resistor R1, a first MOS tube M1 and a second resistor R2 which are sequentially connected in series. One end of the first resistor R1 is connected with the power supply voltage, and the other end of the first resistor R1 is connected with the drain electrode of the first MOS tube M1. The grid electrode of the first MOS tube M1 is connected with bias voltage VBIAS, the source electrode is connected with one end of the second resistor R2, and the other end of the second resistor R2 is grounded. Under the action of the bias voltage, the first MOS transistor M1 works, and the drain voltage of the first MOS transistor M1 is used as a detection point voltage VDET of the power supply voltage. The comparison circuit compares the bias voltage VBIAS with the detection point voltage VDET and outputs a comparison result. As an example, when VBIAS > VDET, the comparison circuit outputs a high level. When VBIAS < VDET, the comparison circuit outputs a low level.

When the bias voltage VBIAS is equal to the detection point voltage VDET, the detection point voltage is known to be related to the bias voltage, the thermoelectric parameter (i.e., the thermal voltage) of the MOS transistor, the first resistor R1 and the second resistor R2 only, based on the MOS transistor sub-threshold region current formula, because the second MOS transistor M2 operates in the sub-threshold region (when the gate-source voltage Vgs is lower than the threshold voltage Vth, the MOS transistor is in a state where the MOS transistor is not fully turned on). The bias voltage is related to the threshold voltage of the second MOS transistor M2, the threshold voltage has a negative temperature coefficient, and the thermoelectric parameter has a positive temperature coefficient. By adjusting the coefficient ratio of the threshold voltage and the thermoelectric parameter, the zero temperature coefficient of the detection point voltage can be realized, namely the detection point voltage keeps constant to the power supply voltage and does not change along with the temperature. Therefore, the discrete range of the power-on reset detection module for detecting the power supply voltage can be reduced, so that the internal circuit of the chip works at higher voltage, and the design difficulty and the chip cost are reduced.

By adopting the design of the power-on reset detection circuit, the bias generation circuit and the detection circuit provided by the embodiment of the disclosure, the detection point voltage has a temperature compensation function. I.e. the detection point voltage does not vary with temperature, and is relatively constant for the supply voltage. The power-on reset detection module is beneficial to reducing the discrete range of power supply voltage detection, so that the reset voltage of the chip does not change along with the temperature.

Optionally, the second MOS tube M2 and the first MOS tube M1 form a current mirror, and the ratio of the channel width to the channel length of the second MOS tube M2 to the channel length of the first MOS tube M1 is 1:N, wherein N is more than or equal to 2.

Here, the first MOS transistor M1 and the second MOS transistor M2 form a current mirror structure, and a ratio of channel widths and lengths of the second MOS transistor M2 and the first MOS transistor M1 is 1:n. Therefore, the first MOS transistor M1 also operates in the subthreshold region. The values of the first resistor R1 and the second resistor R2 can be adjusted, and when the bias voltage VBIAS is equal to the detection voltage VDET, the currents of the first MOS transistor M1 and the second MOS transistor M2 can be the same. And the detection point voltage can be deduced based on the current formula of the MOS tube subthreshold region.

Optionally, the comparison circuit includes a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, and a sixth MOS transistor M6, sources of the fifth MOS transistor M5 and the sixth MOS transistor M6 are connected to a power supply voltage, and gates of the fifth MOS transistor M and the sixth MOS transistor M6 are connected to each other. The drain electrode of the sixth MOS tube M6 is connected with the drain electrode of the fourth MOS tube M4, the drain electrode of the sixth MOS tube M6 is used as the output end of the comparison circuit, the source electrode of the fourth MOS tube M4 is grounded, and the grid electrode is connected with the detection point voltage. The gate and the drain of the fifth MOS tube M5 are connected, and the drain is also connected with the drain of the third MOS tube M3. The gate of the third MOS tube M3 is connected with the bias voltage generated by the bias generating circuit, and the source is grounded. The fifth MOS transistor M5 and the sixth MOS transistor M6 form a current mirror.

Here, each MOS transistor of the comparison circuit operates in an on state. When VBIAS > VDET, the gate-source voltage of the fourth MOS transistor M4 decreases, and when the fourth MOS transistor M4 operates in the constant current region, the drain-source voltage of the fourth MOS transistor M4 increases along with the decrease of the gate-source voltage. In this case, therefore, a high level is output. Similarly, when VBIAS < VDET, the gate-source voltage of the fourth MOS transistor M4 increases, and when the fourth MOS transistor M4 operates in the constant current region, the drain-source voltage of the fourth MOS transistor M4 decreases with the increase of the gate-source voltage. In this case, the comparison circuit outputs a low level.

Optionally, the ratio of the channel width to the channel length of the fifth MOS tube M5 to the channel width to the channel length of the sixth MOS tube M6 is 1:N, wherein N is more than or equal to 1.

When N >1, the ratio of the channel width to the length of the third MOS transistor M3 to the fourth MOS transistor M4 is the same as the ratio of the channel width to the length of the fifth MOS transistor M5 to the sixth MOS transistor M6.

Here, the ratio of the channel widths and lengths of the fifth MOS transistor M5 and the sixth MOS transistor M6, and the third MOS transistor M3 and the fourth MOS transistor M4 may be 1:1, or other ratios. Under the condition that the ratio is 1:1 and no other factors influence, the third MOS tube M3 and the fourth MOS tube M4 have the same current, the fifth MOS tube M5 and the sixth MOS tube M6 have the same current, and the output of the circuit can reflect the relative magnitude between the input voltages (VBIAS and VDET). Further, the 1:1 aspect ratio of M6 and M5 helps ensure that when VBIAS > VDET, the current of M5 is slightly greater than the current of M6 when VBIAS and VDET are compared. While when VBIAS < VDET, the current of M6 is slightly greater than the current of M5. This difference may cause the drain voltage of M6 to vary, thereby producing a high or low level output. Therefore, when the ratio is 1:1, accurate current replication can be realized, and when VBIAS and VDET are different, the two sizes can be accurately compared, namely, the accuracy of current comparison is ensured to be higher.

At other values of the ratio, the accuracy of the current comparison is slightly reduced. This is because the conductivity of the two branches is different, and when there is a small difference in VBIAS and VDET, the currents of the two branches may already have significantly different, resulting in the comparison circuit outputting a corresponding signal earlier. Or when the VBIAS and the VDET have larger difference, the currents of the two branches can be different, and the comparison circuit side outputs corresponding signals.

Optionally, the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are NMOS transistors, and the fifth MOS transistor and the sixth MOS transistor are PMOS transistors.

Optionally, the detection point voltage has a zero temperature coefficient by adjusting the resistance values of the first resistor R1 and the second resistor R2.

Here, based on the circuit diagram and the above principle, the detection points can be derived by calculation as:

As can be seen from the above formula, the temperature coefficient of V _T can be adjusted by the ratio of the first resistor R1 to the second resistor R2, so that the sum of the positive temperature coefficient and the negative temperature coefficient is zero or tends to zero, and the zero temperature coefficient is realized. The specific derivation of the above formula is described in detail below. As an example, in the initial state, the temperature coefficient of V _T is 0.5%/DEGC and the temperature coefficient of V _th is-1%/DEGC, and the resistances of the first resistor R1 and the second resistor R2 are adjusted to increase the temperature coefficient of V _T to 1%/DEGC. Thus, the positive and negative temperature coefficients cancel each other, and the temperature coefficient of the detection point voltage approaches zero.

Optionally, the power-on reset detection circuit further comprises a trigger logic circuit. The trigger logic circuit is connected with the output end of the comparison circuit and is used for outputting a first level signal when the bias voltage is larger than the detection point voltage or outputting a second level signal when the bias voltage is smaller than the detection point voltage.

Here, the first level signal is low level, and the second level signal is high level. Because the gain of the comparison circuit is limited, when the bias voltage VBIAS is almost the same as the detection voltage VDET, the output of the comparison circuit may become unstable because the current difference between the two branch MOS transistors is small at this time, resulting in that the output level may fluctuate around the threshold value. In order to ensure that the output inversion point is accurate and avoid such fluctuation, an upper limit voltage and a lower limit voltage are set by using a trigger logic circuit, so that the relative stability of the output signal is realized. The trigger logic circuit comprises a circuit structure formed by a gate circuit, an MOS tube and the like.

Optionally the trigger logic circuit comprises a schmitt trigger circuit, STM, circuit. The schmitt trigger is connected with the drain electrode of the fifth MOS tube M5 of the comparison circuit and is used for overturning signals reaching the upper limit voltage or the lower limit voltage of the schmitt window.

Here, the schmitt trigger circuit (i.e., STM circuit) is a special inverter circuit that depends on the hysteresis characteristics caused by the positive feedback mechanism, so that the input signal (i.e., the output signal of the comparison circuit) is flipped only within its set SMT window. Specifically, when the input signal reaches the upper limit voltage from low to high, the output signal jumps, and when the input signal reaches the lower limit voltage from high to low, the output signal jumps again. The signal inversion point is relatively stable, and the signal shaping function of current comparison output is achieved.

As shown in connection with fig. 2, another power-on reset detection circuit is provided in an embodiment of the present disclosure, and the circuit further includes a third resistor R3 on the basis of fig. 1. One end of the third resistor R3 is connected with the drain electrode of the first MOS tube M1, and the other end of the third resistor R is grounded. The third resistor R3 and the detection circuit form a detection adjustment circuit, so that the detection point voltage is kept constant with the temperature change of the power supply voltage.

As described above, the embodiment corresponding to fig. 2 has a temperature compensation function, i.e. a zero temperature coefficient of the detection point voltage is realized, so that the detection point voltage does not change with temperature. However, the voltage at the detection point is not adjustable, and Vth has no coefficient in the above formula, so that it cannot adjust the absolute value of the coefficient. The detection point voltage is not adjustable. Here, the third resistor R3 is introduced such that V _th has a coefficient, so that the detection point voltage adjustment is realized by adjustment of the absolute values of the two coefficients of V _T and V _th.

Optionally, the resistance of the bias resistor is greater than the resistance of the first resistor R1.

Here, the ratio of the channel width to the channel length of the second MOS transistor M2 to the first MOS transistor M1 is 1:M, and M is not less than 2. Under the same condition, the current ratio of the two is M:1. When the bias resistance is larger than the first resistance R1, the bias resistance can be used for reducing the current of the branch where the second MOS tube M2 is located. When the bias voltage VBIAS is equal to the detection voltage VDET, the currents of the first MOS transistor M1 and the second MOS transistor M2 are the same. And then the current formula of the two in the subthreshold region is used for calculating and deducing the voltage of the detection point. Therefore, the detection point voltage has a temperature compensation function, namely, the detection point voltage keeps constant with the change of the temperature on the power supply voltage.

Optionally, the detection point voltage has a zero temperature coefficient by adjusting the resistance values of the first resistor R1, the second resistor R2 and the third resistor.

Here, the zero temperature coefficient of the detection point voltage is correlated with the first resistor R1, the second resistor R2, and the third resistor R3. The temperature coefficients of V _T and V _th can be adjusted by adjusting the resistance values of the three resistors, and the sum of the adjusted temperature coefficients is basically zero so as to realize the zero temperature coefficient of the voltage at the detection point.

Optionally, the detection point voltage is adjusted by adjusting the absolute value of the ratio of the first resistor R1 to the second resistor R2 and the absolute value of the ratio of the first resistor R1 to the third resistor R3.

Specifically, the description is made with reference to the equivalent circuit diagram of fig. 3, in which the first resistor R1 may be equivalent to the bias resistor Rb and the resistor R1A connected in parallel. By controlling the resistance values of the resistors Rb, R1, R2, R3, and R1A, when the bias voltage VBIAS is equal to the detection voltage VDET, the current flowing through the resistor R1A and the resistor R3 is the same. From this, according to kirchhoff's law, it can be obtained that the current passing through the first MOS transistor M1 and the second MOS transistor M2 is the same (when the bias voltage VBIAS is equal to the detection voltage VDET, the bias resistor in the equivalent circuit and the equivalent bias resistor have the same voltages at both ends, so the current of the branch where both are located is the same).

Further combined, the bias generating circuit and the detecting circuit are used for generating a bias voltage according to a current formula of a sub-threshold region of the MOS tube,

Wherein, I ₀ is the square drain current of the MOS tube, V _gs is the gate-source voltage of the MOS tube, V _th is the threshold voltage of the MOS tube, V _T is the thermoelectric parameter of the MOS tube, and W/L is the ratio of the channel width and the channel length of the MOS tube.

The currents of the first MOS tube M1 and the second MOS tube M2 are the same, the W/L ratio of the second MOS tube M2 to the first MOS tube M1 is 1 to N, and parameters of the first MOS tube M1 and the second MOS tube M2 are respectively substituted into the formula (1), so that the following steps are obtained:

After the arrangement of the formula (2), V _R2＝lnN×V_T and V _R2＝I×R₂ are obtained, and the currents of the first MOS tube M1 and the second MOS tube M2 can be obtained by combining the two:

knowing the supply voltage VCC, the kirchhoff current formula may be listed for the detected voltage VDET: I _R1＝I_R2+I_R3, further available based on formula (3):

The formula (4) is finished to obtain:

The bias voltage VBIAS is available for vbias=v _th, and is used for conducting the second MOS transistor M2, so that the bias voltage is greater than or equal to the threshold voltage of the second MOS transistor M2, and here, the bias voltage is equal to the threshold voltage of the second MOS transistor M2, namely V _th.

For the comparison circuit, when the detection voltage VDET is greater than the bias voltage VBIAS, then:

after finishing, the method can obtain:

Since V _T has a positive temperature coefficient and V _th has a negative temperature coefficient, the zero temperature coefficient is achieved by scaling and summing the respective temperature coefficients. And the adjustment of the voltage at the detection point can be realized by adjusting the absolute value of each coefficient.

In the circuit diagram in fig. 2, the third resistor R3 is not present, and it can be said that the third resistor R3 has an infinite resistance value, and the formula (7) becomes the formula (8) above.

The embodiment of the disclosure provides a chip, which comprises a chip body and the power-on reset detection circuit, wherein the power-on reset detection circuit is connected with the chip body. The chip body enters a working mode when the power-on reset detection circuit outputs a reset signal, and the power-on reset detection circuit outputs the reset signal when the voltage of the detection point is larger than a preset voltage. The reset signal indicates that the power supply voltage has reached a range in which the chip can operate normally. As one example, the chip is an NVM chip. In GSMC (Global Semiconductor Manufacturing Corporation) and 90nm ULL (Ultra Low Leakage ) technology, after the values of the resistors R1, R2 and R3 are adjusted, the central value of a detection point of a power-on reset module is 1.0V, the precision can reach +/-0.01V if only temperature dispersion is considered, and the precision can reach +/-0.1V if temperature and technology dispersion are considered.

In the foregoing embodiment, the specific process of the chip in the actual operation is as follows:

After the chip is electrified, the power-on reset detection circuit detects the detection point voltage of the power supply voltage. The initial bias voltage is less than the detection point voltage STM (Schmitt Trigger)) the circuit outputs a low level signal. With the continuous increase of the power supply voltage, the voltage at the detection point is larger than the bias voltage, and if the voltage at the detection point is smaller than the preset voltage, the reset signal is kept (namely, the trigger logic circuit outputs a low-level signal). And if the voltage of the detection point is larger than the preset voltage, releasing a reset signal (namely, outputting a high-level signal by the STM circuit), and powering up the chip.

In addition, the mounting relationship between the chip and the power-on reset detection circuit is not limited to being placed in the chip body, but also includes mounting connection with other components of the chip, including but not limited to physical connection, electrical connection, signal transmission connection, etc. The above description and the drawings illustrate embodiments of the disclosure sufficiently to enable those skilled in the art to practice them. Other embodiments may include structural and other modifications. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in, or substituted for, those of others. The embodiments of the present disclosure are not limited to the structures that have been described above and shown in the drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A power-on reset detection circuit, comprising:

The bias generating circuit comprises a bias resistor and a second MOS tube connected in series, wherein the bias resistor is connected to a power supply voltage to generate a bias voltage; wherein the second MOS tube operates in a subthreshold region;

The detection circuit comprises a first resistor, a first MOS tube and a second resistor connected in series in sequence; the gate of the first MOS tube is connected to the bias voltage generated by the bias generation circuit, and the drain voltage of the first MOS tube is used as the detection point voltage of the power supply voltage;

The comparison circuit is connected to the bias voltage of the bias generation circuit and the detection point voltage of the detection circuit respectively, and is used for comparing the magnitudes of the bias voltage and the detection point voltage.

2. The circuit according to claim 1, characterized in that the second MOS tube and the first MOS tube form a current mirror, and the ratio of the channel width and length of the second MOS tube to that of the first MOS tube is 1:M;

Among them, M≥2.

3. The circuit according to claim 1, characterized in that the comparison circuit comprises:

A fifth MOS and a sixth MOS tube forming a current mirror; the gate and the drain of the fifth MOS tube are connected, and the drain of the sixth MOS tube serves as an output end of the comparison circuit;

The third MOS tube is connected in series with the sixth MOS tube; the gate of the third MOS tube is connected to the bias voltage generated by the bias generating circuit,

The fourth MOS tube is connected in series with the fifth MOS tube; the gate of the fourth MOS tube is connected to the drain of the first MOS tube.

4. The circuit according to claim 3, characterized in that the ratio of the channel width to the length of the fifth MOS transistor and the sixth MOS transistor is 1:N; wherein N≥1;

When N>1, the ratio of the channel width to the length of the third MOS tube and the fourth MOS tube is the same as the ratio of the channel width to the length of the fifth MOS tube and the sixth MOS tube.

5 . The circuit according to claim 1 , wherein the detection point voltage has a zero temperature coefficient by adjusting the resistance values of the first resistor and the second resistor.

6. The circuit according to claim 1, further comprising:

The trigger logic circuit is connected to the output end of the comparison circuit, and is used to output a first level signal when the bias voltage is greater than the detection point voltage; or output a second level signal when the bias voltage is less than the detection point voltage.

7. The circuit according to any one of claims 1 to 6, further comprising:

A third resistor, one end of which is connected to the drain of the first MOS tube, and the other end of which is grounded;

The third resistor and the detection circuit constitute a detection point adjustment circuit to adjust the detection point voltage.

8 . The circuit according to claim 7 , wherein the resistance of the bias resistor is greater than the resistance of the first resistor.

9. The circuit according to claim 7, characterized in that the detection point voltage is adjusted by adjusting the absolute value of the ratio of the first resistor to the second resistor and the absolute value of the ratio of the first resistor to the third resistor.

10. A chip, comprising:

Chip body,

The power-on reset detection circuit according to any one of claims 1 to 9, connected to the chip body;

Among them, the chip body enters the working mode when the power-on reset detection circuit outputs a reset signal; when the voltage at the detection point is greater than the preset voltage, the power-on reset detection circuit outputs a reset signal.