CN119653781B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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Abstract
本申请涉及一种半导体器件及其制造方法，半导体器件的制造方法包括：提供衬底，所述衬底上形成有掩膜层，所述掩膜层暴露所述衬底内需要形成高阻结构的区域；采用离子注入工艺于所述区域内注入离子；去除所述掩膜层并进行退火工艺，于所述区域内形成绝缘埋层，并于所述绝缘埋层上形成结晶层，以形成包括所述绝缘埋层和所述结晶层的高阻结构。半导体器件包括衬底和高阻结构，所述高阻结构包括位于所述衬底内的绝缘埋层和位于所述绝缘埋层上的结晶层。本申请通过于衬底内形成高阻结构，提升了高阻结构的阻值统一性，有助于减小后续形成的层间介质层的厚度，降低了半导体器件的寄生电容和器件功耗。
The present application relates to a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device includes: providing a substrate, on which a mask layer is formed, the mask layer exposing an area in the substrate where a high-resistance structure needs to be formed; using an ion implantation process to implant ions in the area; removing the mask layer and performing an annealing process to form an insulating buried layer in the area, and forming a crystalline layer on the insulating buried layer to form a high-resistance structure including the insulating buried layer and the crystalline layer. The semiconductor device includes a substrate and a high-resistance structure, and the high-resistance structure includes an insulating buried layer located in the substrate and a crystalline layer located on the insulating buried layer. The present application improves the uniformity of the resistance value of the high-resistance structure by forming a high-resistance structure in the substrate, helps to reduce the thickness of the interlayer dielectric layer formed subsequently, and reduces the parasitic capacitance and device power consumption of the semiconductor device.
Description
Technical Field
The present application relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor device and a method for manufacturing the same.
Background
In a typical polysilicon gate process, a High resistance (HIR) is a resistor structure formed directly on polysilicon by ion doping the polysilicon. However, the resistance of the high-resistance layer is susceptible to the poly (poly) feature size (Critical Dimension, CD) and the lightly doped drain structure (Lightly Doped Drain, LDD), n+ plasma doping or p+ plasma doping, resulting in a large Variation (Variation) of the resistance of the high-resistance layer.
In the existing process of manufacturing the high-dielectric-constant metal gate, after the high-dielectric-constant metal gate replaces the polysilicon gate, a high-resistance structure formed by combining Oxide (Oxide), titanium nitride (TiN) and silicon nitride (SiN) is formed by deposition (depo), and then an interlayer dielectric layer (Inter-LAYER DIELECTRIC, ILD) is formed by deposition, so that the effect of shunt voltage limitation is achieved. However, the above method may cause an increase in thickness of the interlayer dielectric layer formed, thereby increasing parasitic capacitance and resistance of the semiconductor device.
Disclosure of Invention
Accordingly, it is desirable to provide a semiconductor device and a method for manufacturing the same that improves the uniformity of the resistance of the high-resistance structure and reduces parasitic capacitance and power consumption of the semiconductor device.
In a first aspect, the present application provides a method of manufacturing a semiconductor device, comprising:
Providing a substrate, wherein a mask layer is formed on the substrate, and the mask layer exposes a region in the substrate, which is required to form a high-resistance structure;
implanting ions into the region by an ion implantation process;
And removing the mask layer and performing an annealing process to form an insulating buried layer in the region, and forming a crystallization layer on the insulating buried layer to form a high-resistance structure comprising the insulating buried layer and the crystallization layer.
In one embodiment, the ion implantation process comprises at least one of a first ion implantation process and a second ion implantation process, wherein,
Performing the first ion implantation process by adopting a first implantation angle to form a first ion implantation region in the region;
performing a second ion implantation process by adopting a second implantation angle to form a second ion implantation region in the region;
The first ion implantation process and the second ion implantation process are opposite in inclination direction, the first implantation angle is an angle formed by the implantation direction of the first ion implantation process and the surface direction of the substrate perpendicularly, and the second implantation angle is an angle formed by the implantation direction of the second ion implantation process and the surface direction of the substrate perpendicularly.
In one embodiment, the cross-sectional width of the region along a direction perpendicular to the surface of the substrate is the sum of the width of the first ion implantation region and the width of the second ion implantation region.
In one embodiment, the resistance of the high-resistance structure is adjusted by adjusting an implantation angle of the ion implantation process, the implantation angle including the first implantation angle and the second implantation angle, without changing implantation energy and implantation dose of the ion implantation process.
In one embodiment, the ion implantation process comprises the first ion implantation process with the first implantation angle α being zero;
at the first injection angle alpha satisfies The ion implantation process includes the second ion implantation process;
at the first injection angle alpha satisfies The ion implantation process includes the first ion implantation process and the second ion implantation process, and the second implantation angle β satisfies the following condition:
;
wherein L is the cross-sectional width of the region along the direction perpendicular to the surface of the substrate, H is the thickness of the mask layer, H1 is the implantation depth of the first ion implantation process, and H2 is the implantation depth of the second ion implantation process.
In one embodiment, the resistance of the high-resistance structure decreases with increasing first implantation angle.
In one embodiment, the implantation depth of the ion implantation process is adjusted by adjusting the implantation energy and the implantation dosage of the ion implantation process under the condition that the implantation angle of the ion implantation process is unchanged, and the resistance value of the high-resistance structure is reduced along with the increase of the implantation depth.
In one embodiment, after forming the high-resistance structure, the method for manufacturing the semiconductor device further includes:
forming a grid structure on the substrate at two sides of the high-resistance structure;
Forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer covers the gate structure and the region;
And forming a gate connecting piece and a high-resistance connecting piece in the interlayer dielectric layer, wherein the gate connecting piece penetrates through the interlayer dielectric layer and is connected with the gate structure, and the high-resistance connecting piece penetrates through the interlayer dielectric layer and is connected with the high-resistance structure.
In a second aspect, the present application also provides a semiconductor device including:
A substrate;
The high-resistance structure comprises an insulating buried layer and a crystallization layer, wherein the insulating buried layer is positioned in the substrate, and the crystallization layer is positioned on the insulating buried layer.
In one embodiment, the semiconductor device further includes:
the grid electrode structure is arranged on the substrate at two sides of the high-resistance structure;
the interlayer dielectric layer is arranged on the substrate and the grid structure;
the grid connecting piece penetrates through the interlayer dielectric layer and is connected with the grid structure;
and the high-resistance connecting piece penetrates through the interlayer dielectric layer and is connected with the high-resistance structure.
The application has the unexpected effects that the uniformity of the resistance value of the high-resistance structure is improved by forming the high-resistance structure in the substrate, the thickness of the interlayer dielectric layer formed subsequently is reduced, and the parasitic capacitance and the device power consumption of the semiconductor device are reduced.
Furthermore, the application realizes the resistance value regulation and control of the subsequently formed high-resistance structure by controlling at least one of the implantation angle, implantation energy and implantation dosage of the ion implantation process, and meets the different resistance value requirements of the semiconductor device.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present application, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1 is a schematic diagram of a related art high resistance structure.
Fig. 2 is a flowchart of a method for manufacturing a semiconductor device according to one embodiment of the present application.
Fig. 3 is a schematic structural diagram corresponding to a step of providing a substrate in a method for manufacturing a semiconductor device according to one embodiment of the present application.
Fig. 4 is a schematic structural diagram corresponding to a step of implanting ions into a substrate by an ion implantation process in a method for manufacturing a semiconductor device according to one embodiment of the present application.
Fig. 5 is a schematic structural diagram corresponding to a step of forming a high-resistance structure in a method for manufacturing a semiconductor device according to one embodiment of the present application.
Fig. 6 is a schematic structural diagram corresponding to a step of forming a gate structure in a method for manufacturing a semiconductor device according to one embodiment of the present application.
Fig. 7 is a schematic structural diagram corresponding to a step of forming an interlayer dielectric layer in a method for manufacturing a semiconductor device according to one embodiment of the present application.
The reference numerals illustrate 100-semiconductor substrate, 110-gate, 120-interlayer dielectric structure, 130-high resistance layer, 200-substrate, 201-region where high resistance structure is required to be formed, 210-mask layer, 220-high resistance structure, 221-buried insulating layer, 222-crystallization layer, 230-gate structure, 240-interlayer dielectric layer, 241-gate connector and 242-high resistance connector.
Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Embodiments of the application are illustrated in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section, for example, a first doping type could be termed a second doping type, and, similarly, a second doping type could be termed a first doping type, a doping type different from the second doping type, such as, for example, the first doping type could be P-type and the second doping type could be N-type, or the first doping type could be N-type and the second doping type could be P-type.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.
Referring to fig. 1, in a typical process of forming a High-k metal gate, after forming a gate 110 on a semiconductor substrate 100, an interlayer dielectric structure 120 is formed on the semiconductor substrate 100 and the gate 110, and a High Resistor (High Resistor) 130 is formed in the interlayer dielectric structure 120 to achieve the purpose of shunt voltage limiting.
However, the method of forming the high-resistance layer 130 in the interlayer dielectric structure 120 may result in an increase in the thickness of the interlayer dielectric structure, thereby resulting in an increase in parasitic capacitance and resistance of the semiconductor device.
In order to solve the above problems, the present application provides a semiconductor device and a method for manufacturing the same, so as to improve the uniformity of the resistance of the high-resistance structure and reduce the parasitic capacitance and the power consumption of the semiconductor device.
Fig. 2 is a flowchart of a method for manufacturing a semiconductor device according to one embodiment of the present application. Referring to fig. 2, a method for manufacturing a semiconductor device according to one embodiment of the present application includes steps S01 to S03.
Step S01, providing a substrate, wherein a mask layer is formed on the substrate, and the mask layer exposes a region, which is required to form a high-resistance structure, in the substrate.
And S02, implanting ions into the region by adopting an ion implantation process.
Referring to fig. 4, in one embodiment, the resistance of the subsequently formed high-resistance structure can be adjusted by adjusting the ion implantation conditions of the ion implantation process, so as to meet the resistance requirements under different process conditions.
And S03, removing the mask layer and performing an annealing process to form an insulating buried layer in the region, and forming a crystallization layer on the insulating buried layer to form a high-resistance structure comprising the insulating buried layer and the crystallization layer.
It should be noted that, since the high-resistance structure is formed in the substrate, in the subsequent process, the ion implantation process or other related processes performed on other semiconductor structures on the surface of the substrate have little influence on the resistance value of the high-resistance structure, thereby being beneficial to improving the uniformity of the resistance value of the high-resistance structure in the semiconductor device.
According to the manufacturing method of the semiconductor device, the high-resistance structure is formed in the substrate, so that the uniformity of the resistance value of the high-resistance structure is improved, the thickness of an interlayer dielectric layer formed subsequently is reduced, and the parasitic capacitance and the device power consumption of the semiconductor device are reduced.
Referring to fig. 3, in one embodiment, the material of the substrate 200 comprises a silicon material and the material of the mask layer 210 comprises silicon nitride. In other embodiments of the present application, the material of the substrate 200 and the material of the mask layer 210 may be adjusted according to actual needs, so long as the material selected by the substrate 200 can react with the ions implanted in the step S02 and generate a high-resistance structure, which is not limited in the present application.
Referring to fig. 4, in one embodiment, the ion implantation process includes at least one of a first ion implantation process and a second ion implantation process, wherein the first ion implantation process is performed at a first implantation angle to form a first ion implantation region in the region 201 where the high-resistance structure is required to be formed, and the second ion implantation process is performed at a second implantation angle to form a second ion implantation region in the region 201. Optionally, oxygen ions are implanted in region 201 during the ion implantation process.
The first ion implantation process and the second ion implantation process are inclined in opposite directions so as to form adjacent first ion implantation regions and second ion implantation regions. The first implantation angle is an angle α formed by an implantation direction of the first ion implantation process and a surface direction perpendicular to the substrate 200, and the second implantation angle is an angle β formed by an implantation direction of the second ion implantation process and a surface direction perpendicular to the substrate 200.
With continued reference to fig. 4, in one embodiment, as known from mathematical geometry, the cross-sectional width L of the region 201 where the high-resistance structure needs to be formed along the surface direction of the vertical substrate 200 is the sum of the width L1 of the first ion implantation region and the width L2 of the second ion implantation region, i.e., l=l1+l2.
In one embodiment, the resistance of the subsequently formed high-resistance structure is adjusted by adjusting the implantation angle of the ion implantation process, wherein the implantation angle comprises a first implantation angle and a second implantation angle, while the implantation Energy (Energy) and the implantation dose (Dosage) of the ion implantation process are unchanged.
Referring to fig. 4, in one embodiment, where the first implantation angle α is zero (i.e., α=0), the ion implantation process comprises a first ion implantation process, where the first implantation angle α satisfiesIn the case of (a), the ion implantation process includes a second ion implantation process, and the first implantation angle alpha is satisfiedThe ion implantation process includes a first ion implantation process and a second ion implantation process, and the second implantation angle β satisfies the following condition:
;
Where L is the cross-sectional width of the region 201 along the direction perpendicular to the surface of the substrate 200, H is the thickness of the mask layer 210, H1 is the implantation depth of the first ion implantation process, and H2 is the implantation depth of the second ion implantation process.
With continued reference to fig. 4, in one embodiment, since the implantation depth H1 of the first ion implantation region is smaller than the implantation depth H2 of the second ion implantation region, the resistance of the subsequently formed high-resistance structure decreases with increasing first implantation angle. Exemplary, at the first implantation angle α, increasing from zero to meetThe resistance of the high-resistance structure decreases as the first implantation angle α increases.
In one embodiment, the implantation depth of the ion implantation process is adjusted by adjusting the implantation energy and the implantation dosage of the ion implantation process under the condition that the implantation angle of the ion implantation process is unchanged, and the resistance of the high-resistance structure is reduced along with the increase of the implantation depth. The thickness and depth of the insulating buried layer are inversely related to the resistance value of the high-resistance structure formed subsequently.
It should be noted that, since the resistance of the subsequently formed high-resistance structure is determined by the insulating buried layer and the crystalline layer formed after the first ion implantation process and/or the second ion implantation process, the high-resistance structure is formed by connecting a part of the high-resistance structure formed by the first ion implantation region and a part of the high-resistance structure formed by the second ion implantation region in series, and therefore, the resistance R of the high-resistance structure is the sum of the resistance R1 of a part of the high-resistance structure formed by the first ion implantation region and the resistance R2 of a part of the high-resistance structure formed by the second ion implantation region, i.e., r=r1+r2.
Correspondingly, the resistance value of the high-resistance structure can be adjusted within a certain range by adjusting the implantation angle in the ion implantation process on the premise of not changing other parameters, and the resistance value of the high-resistance structure can be adjusted within a certain range by adjusting the implantation dosage and/or implantation energy of the ion implantation process on the premise of not changing other parameters, so that the different resistance value requirements of the high-resistance structure are met.
Meanwhile, it should be emphasized that the above-mentioned method for adjusting the resistance value of the high-resistance structure is implemented on the premise that the cross-sectional width L of the region 201 where the high-resistance structure needs to be formed is fixed, so as to reduce the negative influence of the variation of the cross-sectional width L of the region 201 on the resistance value Uniformity (Uniformity) of the high-resistance structure in the subsequent process.
Referring to fig. 5, in one embodiment, a wet cleaning process is used to remove the mask layer 210, and then a high temperature annealing process is performed to react oxygen ions implanted in the ion implantation process with silicon in the substrate 200, thereby forming a buried insulating layer 221 and a crystalline layer 222 to form a high resistance structure 220. The depth and thickness of the buried insulating layer 221 are determined by the implantation energy and implantation dose of the ion implantation process, and the crystalline layer 222 is formed in the substrate 200 and over the buried insulating layer 221.
In one embodiment, the buried insulating layer is a silicon dioxide layer, the crystalline layer is a silicon material layer doped with oxygen ions, and the silicon material combines with the oxygen ions to form silicon dioxide in a portion of the crystalline layer. That is, all silicon materials in the region of the buried insulating layer are combined with oxygen ions to form silicon dioxide, so that the silicon dioxide in the buried insulating layer is distributed relatively uniformly, and only part of silicon materials in the region of the crystalline layer are combined with oxygen ions, so that the silicon dioxide in the crystalline layer is distributed unevenly.
Referring to fig. 6 and 7, in one embodiment, after forming the high-resistance structure 220, the method further includes forming a gate structure 230 on the substrate 200 at two sides of the high-resistance structure 220, forming an interlayer dielectric layer 240 on the substrate 200, wherein the interlayer dielectric layer 240 covers the gate structure 230 and the region 201 where the high-resistance structure 220 is located, forming a gate connection 241 and a high-resistance connection 242 in the interlayer dielectric layer 240, wherein the gate connection 241 penetrates through the interlayer dielectric layer 240 and connects the gate structure 230, and the high-resistance connection 242 penetrates through the interlayer dielectric layer 240 and connects the high-resistance structure 220.
In one embodiment, after the formation of the high-resistance structure, during the etching process of the metal silicide blocking layer, an Oxide (Oxide) in the region where the high-resistance structure is located is remained, and no silicide is formed in the region where the high-resistance structure is located during the subsequent silicide (Silicide) formation process.
In one embodiment, the gate structure 230 includes a metal gate (not shown) and a high-k material layer covering sidewalls of the metal gate, so as to reduce or avoid the influence of the gate structure 230 on the uniformity of the resistance of the high-resistance structure 220.
With continued reference to fig. 7, one embodiment of the present application further provides a semiconductor device, which includes a substrate 200 and a high-resistance structure 220, wherein the high-resistance structure 220 includes a buried insulating layer 221 and a crystalline layer 222, the buried insulating layer 221 is located in the substrate 200, and the crystalline layer 222 is located on the buried insulating layer 221. In one embodiment, the buried insulating layer is a silicon dioxide layer, the crystalline layer is a silicon material layer doped with oxygen ions, and silicon dioxide is formed in a partial region of the crystalline layer.
Referring to fig. 7, in one embodiment, the semiconductor device further includes a gate structure 230, an interlayer dielectric layer 240, a gate connection 241, and a high-resistance connection 242, wherein the gate structure 230 is disposed on the substrate 200 at two sides of the high-resistance structure 220, the interlayer dielectric layer 240 is disposed on the substrate 200 and the gate structure 230, the gate connection 241 penetrates the interlayer dielectric layer 240 and connects the gate structure 230, and the high-resistance connection 242 penetrates the interlayer dielectric layer 240 and connects the high-resistance structure 220.
The application has the unexpected effects that the uniformity of the resistance value of the high-resistance structure is improved by forming the high-resistance structure in the substrate, the thickness of the interlayer dielectric layer formed subsequently is reduced, and the parasitic capacitance and the device power consumption of the semiconductor device are reduced. Furthermore, the application realizes the resistance value regulation and control of the subsequently formed high-resistance structure by controlling at least one of the implantation angle, implantation energy and implantation dosage of the ion implantation process, and meets the different resistance value requirements of the semiconductor device.
In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of the application should be assessed as that of the appended claims.
Claims (8)
1. A method of manufacturing a semiconductor device, comprising:
Providing a substrate, wherein a mask layer is formed on the substrate, and the mask layer exposes a region in the substrate, which is required to form a high-resistance structure;
Implanting ions into the region by adopting an ion implantation process, and regulating and controlling the resistance value of the high-resistance structure by adjusting the ion implantation condition of the ion implantation process;
removing the mask layer and performing an annealing process to form an insulating buried layer in the region, and forming a crystallization layer on the insulating buried layer to form a high-resistance structure comprising the insulating buried layer and the crystallization layer;
forming a grid structure on the substrate at two sides of the high-resistance structure;
Forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer covers the gate structure and the region;
And forming a gate connecting piece and a high-resistance connecting piece in the interlayer dielectric layer, wherein the gate connecting piece penetrates through the interlayer dielectric layer and is connected with the gate structure, and the high-resistance connecting piece penetrates through the interlayer dielectric layer and is connected with the high-resistance structure.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the ion implantation process comprises at least one of a first ion implantation process and a second ion implantation process, wherein,
Performing the first ion implantation process by adopting a first implantation angle to form a first ion implantation region in the region;
performing a second ion implantation process by adopting a second implantation angle to form a second ion implantation region in the region;
The first ion implantation process and the second ion implantation process are opposite in inclination direction, the first implantation angle is an angle formed by the implantation direction of the first ion implantation process and the surface direction of the substrate perpendicularly, and the second implantation angle is an angle formed by the implantation direction of the second ion implantation process and the surface direction of the substrate perpendicularly.
3. The method according to claim 2, wherein a cross-sectional width of the region in a direction perpendicular to a surface of the substrate is a sum of a width of the first ion implantation region and a width of the second ion implantation region.
4. The method according to claim 3, wherein a resistance value of the high-resistance structure is adjusted by adjusting an implantation angle of the ion implantation process, the implantation angle including the first implantation angle and the second implantation angle, with implantation energy and implantation dose of the ion implantation process unchanged.
5. The method according to claim 4, wherein the ion implantation process includes the first ion implantation process in the case where the first implantation angle α is zero;
at the first injection angle alpha satisfies The ion implantation process includes the second ion implantation process;
at the first injection angle alpha satisfies The ion implantation process includes the first ion implantation process and the second ion implantation process, and the second implantation angle β satisfies the following condition:
;
wherein L is the cross-sectional width of the region along the direction perpendicular to the surface of the substrate, H is the thickness of the mask layer, H1 is the implantation depth of the first ion implantation process, and H2 is the implantation depth of the second ion implantation process.
6. The method of manufacturing a semiconductor device according to claim 5, wherein a resistance value of the high-resistance structure decreases with an increase in the first implantation angle.
7. The method according to claim 3, wherein an implantation depth of the ion implantation process is adjusted by adjusting an implantation energy and an implantation dose of the ion implantation process with an implantation angle of the ion implantation process unchanged, and wherein a resistance value of the high-resistance structure decreases with an increase in the implantation depth.
8. A semiconductor device, comprising:
A substrate;
The high-resistance structure comprises an insulating buried layer and a crystallization layer, wherein the insulating buried layer is positioned in the substrate, and the crystallization layer is positioned on the insulating buried layer;
the grid electrode structure is arranged on the substrate at two sides of the high-resistance structure;
the interlayer dielectric layer is arranged on the substrate and the grid structure;
the grid connecting piece penetrates through the interlayer dielectric layer and is connected with the grid structure;
and the high-resistance connecting piece penetrates through the interlayer dielectric layer and is connected with the high-resistance structure.
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| KR20220168735A (en) * | 2021-06-17 | 2022-12-26 | 주식회사 키파운드리 | Method for Forming High Resistance Poly Resistor |
| CN115376936A (en) * | 2022-10-26 | 2022-11-22 | 合肥晶合集成电路股份有限公司 | Method for forming semiconductor device |
| CN118116964A (en) * | 2022-11-29 | 2024-05-31 | 苏州晶湛半导体有限公司 | A semiconductor structure and a method for manufacturing the same |
| CN118231239B (en) * | 2024-05-21 | 2024-08-27 | 湖北江城芯片中试服务有限公司 | Semiconductor structure preparation method and semiconductor device |
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| WO2012113170A1 (en) * | 2011-02-25 | 2012-08-30 | 中国科学院微电子研究所 | Manufacturing method for semiconductor device |
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