CN119562636A - Solar cell and method for manufacturing the same, photovoltaic module - Google Patents

Abstract

The present application provides a solar cell and a manufacturing method thereof, and a photovoltaic module, and relates to the field of photovoltaic technology. The present application forms a nano silicon oxide layer on a first tunneling layer on the surface of a silicon substrate, thereby protecting the first tunneling layer from being damaged during high-temperature annealing, increasing the open circuit voltage Voc and the impact factor FF of the battery, and thus improving the battery performance.

Description

Solar cell, manufacturing method thereof and photovoltaic module

Technical Field

The application relates to the technical field of photovoltaics, in particular to a solar cell, a manufacturing method thereof and a photovoltaic module.

Background

In recent years, development and utilization of renewable energy sources are increasingly receiving attention. Solar energy is one of the main supply forms of energy sources due to the characteristics of cleanness, safety, large energy, wide distribution and the like. Solar cells are semiconductor components that can efficiently absorb solar energy and convert it into electrical energy.

The tunneling oxide passivation contact (Tunnel Oxide Passivated Contact, TOPCon) solar cell uses the tunneling oxide passivation structure as a main core, has good passivation performance and is widely applied. Currently, TOPCon solar cells typically employ an n-type silicon wafer, the back side structure of which typically includes a tunnel oxide layer, an n-type doped polysilicon layer, and a passivation layer, through which a back side metal electrode is in contact with the n-type doped polysilicon layer. The tunneling oxide layer prevents the metal electrode from contacting the semiconductor silicon wafer, and reduces the recombination on the surface of the battery. However, during the fabrication of the solar cell, the local tunneling oxide layer may be damaged, thereby reducing the diffusion barrier performance and affecting the performance of the cell.

Disclosure of Invention

In order to alleviate, alleviate or eliminate the above technical problems, the application provides a solar cell, a manufacturing method thereof, a photovoltaic module and a method for improving the performance of the cell.

In a first aspect, the present application provides a method of manufacturing a solar cell, comprising:

filling laughing gas into the process cavity to form a first tunneling layer on the surface of the silicon substrate;

introducing a first working gas into the process cavity, and forming a nano silicon oxide layer on the first tunneling layer, wherein the first working gas comprises one of laughing gas and carbon dioxide, silane and optionally phosphane, and the flow rate of the phosphane in the first working gas is 0-230sccm;

And introducing a second working gas into the process cavity to form a doped layer on the nano silicon oxide layer, wherein the second working gas comprises silane and phosphane.

In a possible implementation manner, the first working gas includes laughing gas, and the flow rate of the laughing gas in the first working gas is 5700-5800sccm.

In one possible implementation, the nano-silicon oxide layer is deposited at a deposition rate of 0.2-0.4nm/s for a deposition time of 10-20s.

In one possible implementation, the nano-silicon oxide layer has a thickness of 2-8nm.

In one possible implementation, the flow rate of the phosphane in the second working gas is 450-950sccm.

In one possible implementation, the second working gas further includes one of laughing gas and carbon dioxide.

In a possible implementation manner, the second working gas includes laughing gas, and the flow rate of the laughing gas in the second working gas is 5700-5800sccm.

In a possible implementation, the thickness of the doped layer is 40-90nm.

In a possible implementation manner, before the second working gas is introduced into the process chamber to form the doped layer on the nano silicon oxide layer, the method further includes:

and introducing laughing gas into the process cavity, and forming a second tunneling layer on the nano silicon oxide layer.

In a possible implementation manner, the switching ratio of the radio frequency power supply in the first tunneling layer deposition process is smaller than the switching ratio of the radio frequency power supply in the second tunneling layer deposition process.

In a possible implementation manner, the on-off ratio of the radio frequency power supply in the first tunneling layer deposition process is 20/2000-20/1500.

In one possible implementation, the power during deposition of the nano-silicon oxide layer is 7800-11400W.

In a possible implementation manner, the method further includes:

and annealing to crystallize the nano silicon oxide layer and the doped layer, wherein the crystallization rate of the nano silicon oxide layer and the doped layer is more than or equal to 70%.

In a possible implementation manner, the method further includes:

forming a passivation layer on the doped layer;

An electrode is formed through the passivation layer in contact with the doped layer.

In a second aspect, the application provides a solar cell, which comprises a silicon substrate, wherein a first tunneling layer, a nano silicon oxide layer and a doped layer are sequentially formed on at least one surface of the silicon substrate from inside to outside, and the doping concentration of phosphorus in the nano silicon oxide layer is 0-8E20 atoms/cm ³.

In one possible implementation, the nano-silicon oxide layer has a thickness of 2-8nm.

In one possible implementation, the doping concentration of phosphorus in the doped layer is 0.9E21-1.3E21atoms/cm ³.

In one possible implementation, the doped layer is a doped nano-silicon oxide layer.

In one possible implementation, the crystallization rate of the nano silicon oxide layer and the doped layer is greater than or equal to 70%.

In one possible implementation manner, the doped layer is further formed with a passivation layer, and the solar cell further includes:

And an electrode passing through the passivation layer and contacting with the doped layer.

In a possible implementation manner, a second tunneling layer is further formed between the nano silicon oxide layer and the doped layer.

In a third aspect, the present application provides a photovoltaic module comprising a plurality of solar cell strings comprising the solar cells of the second aspect.

Compared with the prior art, the application has the following advantages:

The manufacturing method of the solar cell comprises the steps of introducing laughing gas into a process cavity to form a first tunneling layer on the surface of a silicon substrate, introducing first working gas into the process cavity to form a nano silicon oxide layer on the first tunneling layer, wherein the first working gas comprises one of laughing gas and carbon dioxide, silane and optionally phosphane, the flow rate of the phosphane in the first working gas is 0-230sccm, introducing second working gas into the process cavity to form a doped layer on the nano silicon oxide layer, and the second working gas comprises silane and phosphane. According to the application, the nano silicon oxide layer is formed on the first tunneling layer on the surface of the silicon substrate, so that the first tunneling layer can be protected from being damaged in the high-temperature annealing process, and the open-circuit voltage Voc and the influence factor FF of the battery are improved, thereby improving the performance of the battery.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. In the accompanying drawings:

Fig. 1 is a schematic partial cross-sectional view of a solar cell according to an embodiment of the present application;

Fig. 2 is a schematic flow chart of a method for manufacturing a solar cell according to an embodiment of the present application.

Detailed Description

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are used in the description of the embodiments will be briefly described below. It is apparent that the drawings in the following description are only some examples or embodiments of the present application, and it is apparent to those of ordinary skill in the art that the present application may be applied to other similar situations according to the drawings without inventive effort. Unless otherwise apparent from the context of the language or otherwise specified, like reference numerals in the figures refer to like structures or operations.

As used herein, the terms "a," "an," "the," and/or "the" are not specific to the singular, but may include the plural, unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that the steps and elements are explicitly identified, and they do not constitute an exclusive list, as other steps or elements may be included in a method or apparatus.

The relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present application unless it is specifically stated otherwise. Meanwhile, it should be understood that the sizes of the respective parts shown in the drawings are not drawn in actual scale for convenience of description. Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of the exemplary embodiments may have different values. It should be noted that like reference numerals and letters refer to like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.

In the description of the present application, it should be understood that the azimuth or positional relationships indicated by the azimuth terms such as "front, rear, upper, lower, left, right", "lateral, vertical, horizontal", and "top, bottom", etc., are generally based on the azimuth or positional relationships shown in the drawings, and are merely for convenience of describing the present application and simplifying the description, and these azimuth terms do not indicate and imply that the apparatus or elements referred to must have a specific azimuth or be constructed and operated in a specific azimuth, and thus should not be construed as limiting the scope of the present application, and the azimuth terms "inside and outside" refer to inside and outside with respect to the outline of each component itself.

Spatially relative terms, such as "above," "upper" and "upper surface," "above" and the like, may be used herein for ease of description to describe one device or feature's spatial relationship to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" or "over" other devices or structures would then be oriented "below" or "beneath" the other devices or structures. Thus, the process is carried out, the exemplary term "above" may be included. Upper and lower. Two orientations below. The device may also be positioned in other different ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In addition, the terms "first", "second", etc. are used to define the components, and are only for convenience of distinguishing the corresponding components, and the terms have no special meaning unless otherwise stated, and therefore should not be construed as limiting the scope of the present application. Furthermore, although terms used in the present application are selected from publicly known and commonly used terms, some terms mentioned in the present specification may be selected by the applicant at his or her discretion, the detailed meanings of which are described in relevant parts of the description herein. Furthermore, it is required that the present application is understood, not simply by the actual terms used but by the meaning of each term lying within.

It will be understood that when an element is referred to as being "on," "connected to," "coupled to," or "contacting" another element, it can be directly on, connected or coupled to, or contacting the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to," or "directly contacting" another element, there are no intervening elements present.

A flowchart is used in the present application to describe the operations performed by methods according to embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in order precisely. Rather, the various steps may be processed in reverse order or simultaneously. At the same time, other operations are added to or removed from these processes.

Fig. 1 is a schematic partial cross-sectional view of a solar cell according to an embodiment of the present application. As shown in fig. 1, the solar cell 100 includes a silicon substrate 101, and the silicon substrate 101 may be an N-type silicon wafer or a P-type silicon wafer. The silicon substrate 101 has two opposite surfaces, such as a front surface and a back surface in the thickness direction thereof, the front surface facing the sun when the solar cell is in operation. The plurality of solar cells 100 may constitute a solar cell string, which in turn constitutes a photovoltaic module.

The surface (back surface and/or front surface) of the silicon substrate 101 is formed with a first tunneling layer 102, a nano silicon oxide layer 103, a second tunneling layer 104, a doped layer 105 and a passivation layer 106 in order from inside to outside. The crystallization rate of the annealed nano-silicon oxide layer 103 and doped layer 105 is 70% or more. In some embodiments, the surface is also formed with an electrode 107, the electrode 107 being in contact with the doped layer 105 through the passivation layer 106.

The nano-silicon oxide layer 103 may be an intrinsic nano-silicon oxide layer or an N-type or P-type doped nano-silicon oxide layer. Illustratively, the doping concentration of phosphorus in the nano-silicon oxide layer 103 is 0-8e20atoms/cm ³, such as 0、2E19atoms/cm³、5E19atoms/cm³、6E19atoms/cm³、1E20 atoms/cm³、5E20atoms/cm³、8E20 atoms/cm³. in some embodiments, the doping concentration of phosphorus in the nano-silicon oxide layer 103 is 0, i.e., the nano-silicon oxide layer 103 is an intrinsic nano-silicon oxide layer in which no phosphorus is doped. In other embodiments, the doping concentration of phosphorus in the nano-silicon oxide layer 103 is 0.3E20-8E20atoms/cm ³, i.e., the nano-silicon oxide layer 103 is a phosphorus doped nano-silicon oxide layer.

The first tunneling layer 102 and the second tunneling layer 104 may be silicon oxide (SiOx) layers. In some embodiments, the thickness of the first tunneling layer 102 is approximately 0.75-1.15nm, such as 0.75nm, 1nm, or 1.15nm, etc. The thickness of the second tunneling layer 104 is approximately 0.3-0.6nm, such as 0.3nm, 0.4nm, 0.5nm, or 0.6nm, etc.

The solar cell provided by the embodiment of the application comprises two tunneling layers, namely the first tunneling layer 102 and the second tunneling layer 104, and the nano silicon oxide layer 103 is formed between the two tunneling layers, and the nano silicon oxide layer 103 can protect the first tunneling layer 102 from being damaged in the high-temperature annealing process, so that the open-circuit voltage Voc and the influence factor FF of the cell are improved, and the performance of the cell is improved. Meanwhile, the second tunneling layer 104 can improve the diffusion rate of the doped layer 105, so that the doping atoms of the doped layer 105 diffuse more uniformly during high-temperature annealing.

In some embodiments, the thickness of the nano-silicon oxide layer 103 is 2-8nm, such as 4-6nm, and may specifically be 2nm, 4nm, 6nm, or 8nm, etc., while protecting the first tunneling layer 102 from being damaged during the high temperature annealing process, and avoiding blocking carrier transport.

The doped layer 105 may be an N-type or P-type doped layer having a thickness of about 40-90nm, such as 40nm, 60nm, 80nm, 90nm, etc. When the nano-silicon oxide layer 103 is a doped nano-silicon oxide layer, the doping type of the doped layer 105 is the same as that of the nano-silicon oxide layer 103. Further, the doping concentration of the doped layer 105 is greater than that of the nano silicon oxide layer 103, so that the doping gradient difference is formed, the passivation effect is improved, and the influence factor FF is improved, thereby improving the battery performance. Illustratively, the doping concentration of phosphorus in the doped layer 105 is 0.9E21-1.3E21 atoms/cm ³. By high concentration doping of the doped layer 105, the surface concentration is increased, the contact is increased, the influence factor FF is increased, and the thickness is more than 40nm, so that the increase of metal contact recombination caused by burning-through of metal ions can be prevented, and the open-circuit voltage Voc is increased.

In some embodiments, the doped layer 105 may be a doped nano-silicon oxide layer. The doped nano silicon oxide layer has wider forbidden bandwidth compared with the doped polysilicon layer, so that parasitic absorption can be reduced, and meanwhile, the blocking effect of the doped nano silicon oxide layer on metal ions is larger than that of the doped polysilicon layer, so that a sintering window can be increased, and the open-circuit voltage Voc can be improved.

The passivation layer 106 may be composed of one or more passivation layers. In some embodiments, the passivation layer 106 may include only one silicon nitride layer. In other embodiments, the passivation layer 106 may include multiple silicon nitride layers. Further, the passivation layer 106 may also include an aluminum oxide layer. Illustratively, the passivation layer 106 includes one aluminum oxide layer and five silicon nitride layers.

The solar cell 100 may be manufactured using existing equipment, and the manufacturing method of the solar cell 100 is not limited in the embodiments of the present application. The following describes a method for manufacturing the solar cell 100 in detail, taking an example in which the silicon substrate 101 is an n-type silicon wafer and the doped layer 105 is a phosphorus doped layer.

Referring to fig. 1 and 2, the method for manufacturing the solar cell includes the following steps:

In step 210, laughing gas (N ₂ O) is introduced into the process chamber, and a first tunneling layer 102 is formed on the surface of the silicon substrate 101.

The first tunneling layer 102 may be a silicon oxide (SiOx) layer. Illustratively, after cleaning the silicon substrate 101, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process is used to deposit a first tunneling layer 102 having a thickness of about 0.75-1.15nm on the surface of the silicon substrate 101, wherein the process is specifically implemented by a smile flow of 10800-12800sccm, a deposition time of 75-115s, a deposition temperature of 415-450 ℃, a pressure of 1840-2040mtorr, a power of 13000-16000W, and a radio frequency power on/off ratio of 20/2000-20/1500, such as 20/2000, 20/1900, 20/1800, 20/1700, 20/1500, etc. The rf power on/off ratio in this step is smaller, e.g., smaller than the on/off ratio in step 230, which reduces plasma damage and precisely controls the tunneling layer thickness by deposition time.

In some embodiments, the surface of the silicon substrate 101 may also be textured prior to forming the first tunneling layer 102 on the surface of the silicon substrate 101.

Step 220, introducing a first working gas into the process chamber to form a nano silicon oxide layer 103 on the first tunneling layer 102, wherein the first working gas comprises one of laughing gas (N ₂ O) and carbon dioxide (CO ₂), and silane (SiH ₄) and optionally phosphine (PH ₃), and wherein a flow rate of the phosphine in the first working gas is 0-230sccm, such as0, 50sccm, 80sccm, 130sccm, 200sccm, 230sccm, and the like.

Laughing gas and carbon dioxide in the first working gas may be replaced. If laughing gas is used, the gas sources of the steps can be directly used in other steps, such as step 210 and step 230, and no new gas source is required to be additionally added, so that the production cost can be reduced. Optionally, the first working gas further includes hydrogen (H ₂), so that the nano silicon oxide layer 103 is a hydrogenated nano silicon oxide layer, and the passivation effect is improved.

In some embodiments, the flow rate of the phosphane in the first working gas is 0, i.e., no phosphane is in the first working gas, and the nano-silicon oxide layer 103 is an intrinsic nano-silicon oxide layer. Illustratively, a nano-silicon oxide layer 103 having a thickness of approximately 2-8nm (e.g., 2nm, 7nm, 8nm, etc.) may be deposited on the first tunneling layer 102 using a PECVD process. Alternatively, the nano-silicon oxide layer 103 is 4-6nm, such as 4nm, 5nm, 6nm, etc. The specific implementation process comprises the following steps of depositing for 10-20s, depositing at 415-450 ℃, silane flow rate of 1100-1300sccm, hydrogen flow rate of 5700-5800sccm, laughing gas flow rate of 5700-5800sccm, pressure of 2600-2800mtorr, power of 7800-11400W and switching ratio of a radio frequency power supply of 40/520.

In other embodiments, the flow rate of the phosphane in the first working gas is 130-230sccm, i.e., the first working gas contains the phosphane, and the nano-silicon oxide layer 103 is a phosphorus doped nano-silicon oxide layer. Illustratively, a nano-silicon oxide layer 103 having a thickness of approximately 2-8nm (e.g., 2nm, 7nm, 8nm, etc.) may be deposited on the first tunneling layer 102 using a PECVD process. Alternatively, the nano-silicon oxide layer 103 is 4-6nm, such as 4nm, 5nm, 6nm, etc. The specific implementation process comprises the following steps of depositing for 10-20s, depositing at 415-450 ℃, silane flow rate of 1100-1300sccm, hydrogen flow rate of 5700-5800sccm, laughing gas flow rate of 5700-5800sccm, phosphine flow rate of 130-230sccm, pressure of 2600-2800mtorr, power of 7800-11400W, and switching ratio of radio frequency power source of 40/520.

The lower or no flux of phosphane in this step reduces penetration of phosphorus atoms through the first tunneling layer 102 resulting in increased recombination within the silicon matrix 101 while reducing damage to passivation of the first tunneling layer 102. In addition, the power used in this step is relatively small, which also reduces penetration of phosphorus atoms through the first tunneling layer 102, resulting in increased recombination within the silicon matrix 101, while reducing damage to passivation of the first tunneling layer 102.

In an embodiment of the present application, the nano-silicon oxide layer 103 is deposited at a deposition rate of about 0.2-0.4nm/s, and the deposition rate may be specifically 0.2nm/s, 0.26nm/s, 0.3nm/s, 0.36nm/s, 0.4nm/s, etc., for about 10-20s, so as to form the nano-silicon oxide layer 103 having a thickness of about 2-8nm on the first tunneling layer 102. The deposition rate of the material is in linear correlation with time, the thickness of the material can be directly controlled by the deposition time, and the control of the deposition thickness has high accuracy.

Step 230, introducing laughing gas into the process chamber to form a second tunneling layer 104 on the nano-silicon oxide layer 103.

The second tunneling layer 104 may be a silicon oxide (SiOx) layer. The second tunneling layer 104 is deposited on the nano-silicon oxide layer 103 to a thickness of about 0.3-0.6nm using a PECVD process, which is specifically performed with a smile flow of 10800-12800sccm, a deposition time of 30-60s, a deposition temperature of 415-450 ℃, a pressure of 1840-2040mtorr, a power of 13000-16000W, and a switching ratio of 20/600.

Step 240, introducing a second working gas into the process chamber to form a doped layer 105 on the second tunneling layer 104, wherein the second working gas comprises silane and phosphane.

Illustratively, the flow rate of the phosphine in the second working gas is 450-950sccm, such as 450sccm, 600sccm, 750sccm, 800sccm, 950sccm. The flow rate of the phosphane in the second working gas is greater than the flow rate of the phosphane in the first working gas, so that the doping concentration of the doped layer 105 is greater than the nano-silicon oxide layer 103. In some embodiments, the second working gas may further include hydrogen (H ₂), so that the doped layer 105 is a hydrogenated doped layer, and the passivation effect is improved.

For example, a PECVD process may be used to deposit a doped layer 105 having a thickness of about 60-80nm (e.g., 60nm, 70nm, 80nm, etc.) on the second tunneling layer 104, with a deposition time of 480-640s, a deposition temperature of 415-450 ℃, a silane flow of 2800-3000sccm, a hydrogen flow of 8800-10800sccm, a phosphine flow of 750-950sccm, a pressure of 2600-2800mtorr, a power of 8400-12000W, and a switching ratio of the RF power source of 40/520.

In some embodiments, the second working gas further comprises one of laughing gas and carbon dioxide, i.e., doped layer 105 is a doped nano-silicon oxide layer. Illustratively, laughing gas is introduced into the process chamber to deposit the doped nano silicon oxide layer, thereby reducing the cost. Specifically, a PECVD process may be used to deposit a doped layer 105 having a thickness of about 40-90nm (e.g., 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, etc.) on the second tunneling layer 104, with a deposition time of 100-260s, a deposition temperature of 415-450 ℃, a silane flow of 1100-1300sccm, a hydrogen flow of 5700-5800sccm, a laughing gas flow of 5700-5800sccm, a phosphine flow of 450-550sccm, a pressure of 2600-2800mtorr, a power of 8400-12000W, and a radio frequency power on/off ratio of 40/520.

It should be noted that the same process chamber may be used for steps 210-240, or different process chambers may be used.

Step 250, annealing to crystallize the nano silicon oxide layer 103 and the doped layer 105, wherein the crystallization rate of the nano silicon oxide layer 103 and the doped layer 105 is more than or equal to 70%.

Illustratively, the silicon substrate 101 after step 240 is annealed in a diffusion furnace for a time of 1500-3200s at a temperature of 900-920 ℃.

Step 260, a passivation layer 106 is formed on the doped layer 105.

One or more passivation layers may be formed on the doped layer 105, i.e., the passivation layer 106 may be composed of one or more passivation layers. The following is a detailed description taking an example in which the passivation layer 106 includes one aluminum oxide (AlOx) layer and five silicon nitride (SiNx) layers.

(1) An Atomic Layer Deposition (ALD) process is used for depositing an alumina layer with the thickness of about 4.5-6.5nm on the doped layer 105, so that the alumina layer plays a role of a cap layer, hydrogen (H) atoms in the light and heavy doped layers are blocked from overflowing, the probability of passivation of the hydrogen atoms and defects at the tunneling layer 105 is higher, the surface passivation is improved, and the open-circuit voltage Voc is improved. The specific implementation process comprises the following steps of preprocessing water vapor (H ₂ O) at 270-295 ℃, preprocessing for 4-6 circles, setting the water vapor flow at 19-21sccm, setting the AlOx deposition for 30-34 circles, setting the water vapor flow at 21-24sccm, setting the purging time at 11-13s, setting the pulse time at 6-8s, setting the Trimethylaluminum (TMA) flow at 22-24sccm, setting the purging time at 10-12s and setting the pulse time at 5.5-7.5s.

(2) The pre-deposition treatment is performed using a PECVD process to increase the hydrogen (H) content in the stacked passivation film. The specific implementation process comprises the following steps of 50-60s, 480-530 ℃ of temperature, 220-240bar of pressure, 8600-9600sccm of ammonia (NH ₃) flow, 8000-9700W of power and 3/54 of switching ratio of a radio frequency power supply.

(3) A PECVD process is used to deposit a first silicon nitride layer with high refractive index, and the hydrogen content is increased to provide passivation effect. The specific implementation process comprises the following steps of depositing for 90-110s, depositing at 480-530 ℃, under 220-240bar, with ammonia flow of 8600-9600sccm, silane flow of 2200-3200sccm, power of 9500-12000W, and switching ratio of radio frequency power supply of 3/54.

(4) The PECVD process is used to deposit a second silicon nitride layer with higher refractive index, which plays a part of passivation and reduces parasitic absorption caused by high refractive index. The specific implementation process comprises the following steps of depositing for 80-100s, depositing at 480-530 ℃, pressure of 220-240bar, ammonia flow of 9000-11000sccm, silane flow of 1500-2500sccm, power of 10000-14000W, and switching ratio of a radio frequency power supply of 3/54.

(5) And a third silicon nitride layer with lower refractive index is deposited by using a PECVD process, and light absorption is increased and reflectivity is reduced by overlapping the fourth silicon nitride layer and the fifth silicon nitride layer. The specific implementation process comprises the following steps of depositing for 90-110s, depositing at 480-530 ℃, pressure of 220-240bar, ammonia flow of 11000-13000ccm, silane flow of 1000-2000sccm, power of 9500-12000W, and switching ratio of a radio frequency power supply of 3/36.

(6) And a fourth silicon nitride layer with a slightly lower refractive index is deposited by using a PECVD process, and the fourth silicon nitride layer, the third silicon nitride layer and the fifth silicon nitride layer are stacked to increase light absorption and reduce reflectivity. The specific implementation process comprises the following steps of 130-150s of deposition time, 480-530 ℃ of deposition temperature, 220-240bar of pressure, 11000-13000sccm of ammonia flow, 900-1900sccm of silane flow, 11000-14000W of power, and 3/54 of switching ratio of a radio frequency power supply.

(7) And a fifth silicon nitride layer with low refractive index is deposited by using a PECVD process, and the fifth silicon nitride layer, the third silicon nitride layer and the fourth silicon nitride layer are stacked to increase light absorption and reduce reflectivity. The specific implementation process comprises the following steps of 165-185s of deposition time, 480-530 ℃ of deposition temperature, 220-240bar of pressure, 12500-14500sccm of ammonia flow, 850-1850sccm of silane flow, 10000-14000W of power and the on-off ratio of a radio frequency power supply.

Step 270, forming an electrode 107 through the passivation layer 106 in contact with the doped layer 105.

Illustratively, silver paste may be printed on the surface of the silicon substrate 101 after step 260, and the electrode 107 may be formed after sintering.

While the basic concepts have been described above, it will be apparent to those skilled in the art that the foregoing disclosure is by way of example only and is not intended to be limiting. Although not explicitly described herein, various modifications, improvements and adaptations of the application may occur to one skilled in the art. Such modifications, improvements, and modifications are intended to be suggested within the present disclosure, and therefore, such modifications, improvements, and adaptations are intended to be within the spirit and scope of the exemplary embodiments of the present disclosure.

Meanwhile, the present application uses specific words to describe embodiments of the present application. Reference to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic is associated with at least one embodiment of the application. Thus, it should be emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various positions in this specification are not necessarily referring to the same embodiment. Furthermore, certain features, structures, or characteristics of one or more embodiments of the application may be combined as suitable.

Similarly, it should be appreciated that in order to simplify the present disclosure and thereby facilitate an understanding of one or more embodiments, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure. This method of disclosure does not imply that more features than are mentioned are required for the object of the application. Indeed, less than all of the features of a single embodiment disclosed above.

In some embodiments, numbers describing the components, number of attributes are used, it being understood that such numbers being used in the description of embodiments are modified in some examples by the modifier "about," approximately, "or" substantially. Unless otherwise indicated, "about," "approximately," or "substantially" indicate that the number allows for a 20% variation. Accordingly, in some embodiments, the numerical parameters employed in the specification are approximations that may vary depending upon the desired properties sought to be obtained by the individual embodiments. In some embodiments, the numerical parameters should take into account the specified significant digits and employ a method for preserving the general number of digits. Although the numerical ranges and parameters set forth herein are approximations in some embodiments for use in determining the breadth of the range, in particular embodiments, the numerical values set forth herein are as precisely as possible.

While the application has been described with reference to the specific embodiments presently, it will be appreciated by those skilled in the art that the foregoing embodiments are merely illustrative of the application, and various equivalent changes and substitutions may be made without departing from the spirit of the application, and therefore, all changes and modifications that come within the spirit of the application are desired to be protected.

Claims (22)

1.A method for manufacturing a solar cell, comprising:

filling laughing gas into the process cavity to form a first tunneling layer on the surface of the silicon substrate;

introducing a first working gas into the process cavity, and forming a nano silicon oxide layer on the first tunneling layer, wherein the first working gas comprises one of laughing gas and carbon dioxide, silane and optionally phosphane, and the flow rate of the phosphane in the first working gas is 0-230sccm;

And introducing a second working gas into the process cavity to form a doped layer on the nano silicon oxide layer, wherein the second working gas comprises silane and phosphane.

2. The method of manufacturing of claim 1, wherein the first working gas comprises laughing gas and the flow rate of laughing gas in the first working gas is 5700-5800sccm.

3. The method of manufacturing according to claim 1 or 2, wherein the nano-silicon oxide layer is deposited at a deposition rate of 0.2-0.4nm/s for a deposition time of 10-20s.

4. The method of manufacturing according to claim 1 or 2, wherein the nano-silicon oxide layer has a thickness of 2 to 8nm.

5. The method of claim 1, wherein the flow rate of the phosphine in the second working gas is 450-950sccm.

6. The manufacturing method according to claim 1 or 2 or 5, wherein the second working gas further includes one of laughing gas and carbon dioxide.

7. The method of manufacturing of claim 6, wherein the second working gas comprises laughing gas and the flow rate of laughing gas in the second working gas is 5700-5800sccm.

8. The method of manufacturing according to claim 1, wherein the doped layer has a thickness of 40-90nm.

9. The method of manufacturing of claim 1, further comprising, prior to said introducing a second working gas into the process chamber to form a doped layer on the nano-silicon oxide layer:

and introducing laughing gas into the process cavity, and forming a second tunneling layer on the nano silicon oxide layer.

10. The method of manufacturing of claim 9, wherein a switching ratio of the radio frequency power supply during the first tunneling layer deposition is less than a switching ratio of the radio frequency power supply during the second tunneling layer deposition.

11. The method of manufacturing of claim 10, wherein a switching ratio of the rf power source during the first tunneling layer deposition is 20/2000-20/1500.

12. The method of manufacturing of claim 1, wherein the power during deposition of the nano-silicon oxide layer is 7800W to 11400W.

13. The method of manufacturing as set forth in claim 1, further comprising:

and annealing to crystallize the nano silicon oxide layer and the doped layer, wherein the crystallization rate of the nano silicon oxide layer and the doped layer is more than or equal to 70%.

14. The manufacturing method according to claim 1 or 13, characterized by further comprising:

forming a passivation layer on the doped layer;

An electrode is formed through the passivation layer in contact with the doped layer.

15. The solar cell comprises a silicon substrate, and is characterized in that a first tunneling layer, a nano silicon oxide layer and a doping layer are sequentially formed on at least one surface of the silicon substrate from inside to outside, wherein the doping concentration of phosphorus in the nano silicon oxide layer is 0-8E20 atoms/cm ³.

16. The solar cell of claim 15, wherein the nano-silicon oxide layer has a thickness of 2-8nm.

17. The solar cell of claim 15, wherein the doping layer has a phosphorus doping concentration of 0.9E21-1.3e21 atoms/cm ³.

18. The solar cell of any one of claims 15-17, wherein the doped layer is a doped nano-silicon oxide layer.

19. The solar cell of claim 15, wherein the nano-silicon oxide layer and the doped layer have a crystallization rate of 70% or more.

20. The solar cell of claim 15, wherein the doped layer further has a passivation layer formed thereon, the solar cell further comprising:

And an electrode passing through the passivation layer and contacting with the doped layer.

21. The solar cell of claim 15, wherein a second tunneling layer is further formed between the nano-silicon oxide layer and the doped layer.

22. A photovoltaic module comprising a plurality of solar cell strings comprising the solar cell of any one of claims 15-21.