CN119451129A - Memory structure and manufacturing method thereof - Google Patents
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- H—ELECTRICITY
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- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
- H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
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Abstract
本发明提供了一种存储器结构及其制作方法。该存储器结构包括：基底，具有相对的第一表面和第二表面，且基底包括阵列区以及与阵列区邻接的逻辑区，阵列区中具有自第一表面贯穿至第二表面的多个第一导电通路，逻辑区中具有自第一表面贯穿至第二表面的第二导电通路，第一导电通路和第二导电通路的高度相同；多个存储器单元，位于第一表面上，且每个存储器单元覆盖一个第一导电通路，多个存储器单元与多个第一导电通路一一对应；至少一个顶部电极层，位于多个存储器单元远离基底一侧的表面上；顶部金属连线层，位于基底具有顶部电极层的一侧，并以使顶部金属连线层电连接至少一个顶部电极层。通过本申请，降低了存储器结构的制作成本。
The present invention provides a memory structure and a manufacturing method thereof. The memory structure comprises: a substrate having a first surface and a second surface opposite to each other, and the substrate comprises an array area and a logic area adjacent to the array area, the array area has a plurality of first conductive paths extending from the first surface to the second surface, the logic area has a second conductive path extending from the first surface to the second surface, and the first conductive path and the second conductive path have the same height; a plurality of memory cells located on the first surface, and each memory cell covers a first conductive path, and the plurality of memory cells correspond to the plurality of first conductive paths one by one; at least one top electrode layer located on the surface of the plurality of memory cells away from the substrate side; a top metal wiring layer located on the side of the substrate having the top electrode layer, and the top metal wiring layer is electrically connected to at least one top electrode layer. Through the present application, the manufacturing cost of the memory structure is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductor memories, in particular to a memory structure and a manufacturing method of the memory structure.
Background
MRAM memory cells MTJ are typically composed of three basic cells of ferromagnetic layers, an insulating tunneling layer, and a pinned layer. When the magnetic moment directions of the ferromagnetic layer and the fixed layer are opposite, the memory device exhibits a high resistance state Rap, and when the magnetic moment directions of the two layers are the same, it exhibits a low resistance state Rp for the storage of information "1", "0". As a novel memory, the MRAM has great advantages in terms of read-write speed and device reliability compared with the traditional Flash memory;
However, in the prior art, when manufacturing a memory, a general integration scheme is generally to first prepare a bottom via hole of a memory array area and a memory cell, then prepare a bottom via hole of a non-memory array area, further prepare a top metal layer common to the memory area and the non-memory area, and electrically connect the top metal layer with a plurality of memory cells through the top via hole, so that the bottom via hole of the memory array area, the bottom via hole of the non-memory area and the top via hole on the memory cell need to be formed in multiple photolithography steps, and because each photolithography process needs to use a photomask for manufacturing, the number of photomask layers is more, and the manufacturing cost is increased.
Disclosure of Invention
The invention mainly aims to provide a memory structure and a manufacturing method of the memory structure, which are used for solving the problems of complex manufacturing process and high cost in the prior art.
In order to achieve the above object, according to one aspect of the present invention, there is provided a memory structure including a substrate having first and second surfaces opposite to each other, the substrate including an array region having a plurality of first conductive vias penetrating from the first surface to the second surface therein and a logic region adjacent to the array region, the logic region having second conductive vias penetrating from the first surface to the second surface therein, the first and second conductive vias having the same height, a plurality of memory cells on the first surface and each covering one of the first conductive vias, the plurality of memory cells in one-to-one correspondence with the plurality of first conductive vias, at least one top electrode layer on a surface of the plurality of memory cells on a side away from the substrate, and a top metal wiring layer on a side of the substrate having the top electrode layer and electrically connecting the top metal wiring layer to the at least one top electrode layer.
Further, each memory cell has a first projection on the substrate and at least one top electrode layer has a second projection on the substrate, the first projection being located within the second projection.
Further, the top electrode layers comprise a plurality of top electrode layers and a plurality of memory units, the top electrode layers are in one-to-one correspondence, the surface of one side, far away from the first conductive path, of each memory unit is a third surface, each top electrode layer covers the third surface, and the top metal connecting line layer is electrically connected with the plurality of top electrode layers.
Further, the memory structure further includes a protective layer covering at least the sidewalls of the memory cells.
Further, the top metal wiring layer is electrically connected to the second conductive via.
Further, the memory cell includes one or more of a magnetic random access memory cell, a phase change random access memory cell, a resistance change random access memory cell, and a ferroelectric random access memory cell.
Further, in the case where the memory cell is a magnetic random access memory cell, the at least one top electrode layer includes at least one layer.
Further, the at least one top electrode layer comprises a plurality of layers, and a material of at least one layer of the at least one top electrode layer is a ferromagnetic material.
In order to achieve the above object, according to another aspect of the present invention, there is provided a method for fabricating a memory structure, including providing a substrate having a first surface and a second surface opposite to each other, the substrate including an array region and a logic region adjacent to the array region, forming a plurality of first conductive vias and second conductive vias in the substrate by a photolithography process, wherein the plurality of first conductive vias extend from the first surface corresponding to the array region to the second surface, the second conductive vias extend from the first surface corresponding to the logic region to the second surface, the heights of the first conductive vias and the second conductive vias in the extending direction are the same, forming a plurality of memory cells on the first surface such that each memory cell covers one first conductive via, the plurality of memory cells are in one-to-one correspondence with the plurality of first conductive vias, forming at least one top electrode layer on a surface of the plurality of memory cells away from the substrate, and forming a top metal wiring layer on a side of the substrate having the top electrode layer such that the top metal wiring layer electrically connects the at least one top electrode layer.
Further, the step of forming the top electrode layer includes sequentially depositing a first insulating material and a second insulating material on a side of the substrate having the memory cells such that the first insulating material covers the memory cells and the first surface and the second insulating material covers the first insulating material after the step of forming the memory cells, removing a portion of the first insulating material and a portion of the second insulating material by chemical mechanical polishing to form a fourth surface exposing the plurality of memory cells, and forming the top electrode layer on the fourth surface.
The technical scheme of the application provides a memory structure, which comprises a substrate, a plurality of memory units, at least one top electrode layer and a top metal connecting line layer, wherein the substrate comprises a plurality of first conductive paths in an array area and a second conductive path in a logic area, the plurality of memory units are positioned on the plurality of first conductive paths so as to realize the electric connection between each memory unit and each first conductive path, the at least one top electrode layer is positioned on the surface of one side of the plurality of memory units far away from the substrate so as to realize the electric connection between the top electrode layer and each memory unit, the top metal connecting line layer is positioned on the side of the top electrode layer far away from the substrate, and the top metal connecting line layer is electrically connected with the at least one top electrode layer, since the heights of the first conductive vias and the second conductive vias in the substrate of the memory structure provided by the scheme are consistent, the first conductive vias and the second conductive vias can be formed at one time by adopting the same photoetching process, so that the number of photomasks when the first conductive vias and the second conductive vias are formed is reduced, and then after forming a plurality of memory cells and at least one top electrode layer which cover the first conductive vias on the first surface, since the first conductive vias are used as bottom conductive vias in the memory structure, the second conductive vias are used as top conductive vias of the memory, so that the heights of the plurality of memory cells of the array area are higher than the heights of the second conductive vias under the condition that the heights of the first conductive vias and the second conductive vias are consistent, therefore, the top metal connecting line layer electrically connected with at least one top electrode layer can be directly formed on one side of the substrate with the top electrode layer, so that the top metal connecting line layer can be electrically connected with a plurality of memory cells, the total height of the bottom conductive paths corresponding to the array area and the memory cells in the prior art is lower than that of the top conductive paths of the logic area, the top conductive paths need to be formed on one side of the memory cells far away from the bottom conductive paths again, and compared with the top conductive paths of the logic area, the total height of the bottom conductive paths corresponding to the array area and the memory cells is equal to that of the top conductive paths of the logic area.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention. In the drawings:
FIG. 1 is a schematic cross-sectional view of a memory structure according to an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view of a substrate provided in a method for fabricating a memory structure according to an embodiment of the present invention;
FIG. 3 is a schematic diagram showing a cross-sectional structure of a thin film of a memory cell deposited on the substrate shown in FIG. 2;
FIG. 4 is a schematic diagram showing a cross-sectional structure of a memory cell formed by etching the memory cell thin film shown in FIG. 3;
FIG. 5 is a schematic cross-sectional structure of a planarized surface formed after planarizing the upper surface of the memory cell shown in FIG. 4;
FIG. 6 is a schematic cross-sectional view showing the formation of a top electrode layer on the planarized surface shown in FIG. 5;
FIG. 7 is a schematic cross-sectional view showing the deposition of a second insulating material on the side of the top electrode layer away from the substrate shown in FIG. 6;
FIG. 8 is a schematic cross-sectional view showing the formation of a plurality of top electrode layers on the planarized surface shown in FIG. 5;
FIG. 9 is a schematic cross-sectional view showing the structure after depositing a second insulating material on the side of the plurality of top electrode layers shown in FIG. 8 remote from the substrate;
FIG. 10 is a schematic cross-sectional view of the top metal interconnect layer formed after removing a portion of the material in the structure shown in FIG. 9;
FIG. 11 shows a schematic cross-sectional view of depositing a second insulating material over the structure shown in FIG. 4 and forming a fourth planarized surface;
FIG. 12 is a schematic cross-sectional view showing the structure after etching the fourth planarized surface shown in FIG. 11 and depositing a top electrode material;
FIG. 13 is a schematic cross-sectional view showing the structure of FIG. 12 after etching and forming a top electrode layer, and depositing the second insulating material described above;
fig. 14 is a schematic cross-sectional view of the top metal interconnect layer formed after removing a portion of the material in the structure shown in fig. 13.
Wherein the above figures include the following reference numerals:
10. Substrate, 20, first conductive path, 30, second conductive path, 40, memory cell, 401, lower electrode layer, 402, memory layer, 403, upper electrode layer, 50, top electrode layer, 60, top metal wire layer, 70, protective layer, 80, insulating medium layer, 90, first metal wire layer, 100, second metal wire layer, 110, memory cell film, 111, lower electrode material layer, 112, memory material layer, 113, upper electrode material layer, 120, first insulating material, 130, second insulating material, 140, top electrode material, 150, etching stop layer.
Detailed Description
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other. The invention will be described in detail below with reference to the drawings in connection with embodiments.
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As mentioned in the background art, in the prior art, when manufacturing a memory, a general integration scheme is generally to first prepare a bottom via hole of a memory array area and a memory cell, then prepare a bottom via hole of a non-memory array area, further prepare a top metal layer common to the memory area and the non-memory area, and electrically connect the top metal layer with a plurality of memory cells through the top via hole, so that the bottom via hole of the memory array area, the bottom via hole of the non-memory area and the top via hole on the memory cell need to be formed in multiple photolithography steps, and because a photomask needs to be used for manufacturing in each photolithography process, the number of photomask layers is more, and the manufacturing cost is increased. In order to solve the above technical problems, the present inventors provide a memory structure and a method for manufacturing the memory structure.
In some alternative embodiments, as shown in fig. 1, there is provided a memory structure, where the memory structure includes a substrate 10 having a first surface and a second surface opposite to each other, a plurality of memory cells 40 located on the first surface, at least one top electrode layer 50 located on the plurality of memory cells 40, and a top metal wiring layer 60 located on a side of the top electrode layer 50 away from the substrate 10, specifically, the substrate 10 includes an array region having a plurality of first conductive vias 20 extending from the first surface to the second surface through the array region, a second conductive via 30 extending from the first surface to the second surface in the logic region, the first conductive vias 20 and the second conductive vias 30 having the same height, each of the plurality of memory cells 40 respectively covering a different one of the first conductive vias 20, that is, the plurality of memory cells 40 may be in the same number as the plurality of first conductive vias 20 located on the substrate 10, and the plurality of memory cells 40 may be located on the same number of one side of the top electrode layers 60 located on the substrate 10, and the top metal wiring layer 60 may be located on the at least one side of the top electrode layer 50. Optionally, the substrate 10 further includes a first metal wiring layer 90 and a second metal wiring layer 100, wherein the first metal wiring layer 90 is disposed on a side of the first conductive via 20 away from the memory cell 40 in a contact manner, and the second metal wiring layer 100 is disposed on a side of the second conductive via 30 away from the memory cell 40 in a contact manner.
Specifically, the substrate 10 may include, but is not limited to, a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator substrate, etc., and may be appropriately selected according to actual needs by those skilled in the art. The plurality of first conductive vias 20 and the second conductive vias 30 may be conductive vias formed of a metal material, alternatively, the metal material in the first conductive vias 20 and the second conductive vias 30 may include, but is not limited to W, cu, taN, tiN, one metal or a combination of multiple metals, further, any two adjacent first conductive vias 20 are disposed at intervals, alternatively, any one first conductive via 20 and any one second conductive via 30 are disposed at intervals. It should be noted that the plurality of first conductive vias 20 and second conductive vias 30 in the substrate 10 are formed by one photolithography and filling, and each extend from the first surface to the second surface of the substrate 10, and therefore, the first conductive vias 20 and the second conductive vias 30 have the same height in the direction perpendicular to the first surface.
Specifically, as shown in fig. 1, each of the plurality of memory cells 40 may include a lower electrode layer 401, a memory layer 402, and an upper electrode layer 403 that are sequentially stacked, where the lower electrode layer 401 is located between the memory layer 402 and the first surface of the substrate 10, further, the lower electrode layer 401 in each memory cell 40 covers one first conductive via 20, and any adjacent two lower electrode layers 401 in the plurality of memory cells 40 are spaced apart, so that a plurality of lower electrodes in the plurality of memory cells 40 are in one-to-one correspondence with the plurality of first conductive vias 20, and the lower electrode layer 401, the memory layer 402, and the upper electrode layer 403 of each memory cell 40 in the plurality of memory cells 40 are in one-to-one correspondence with the plurality of first conductive vias 20.
Specifically, the top electrode layer 50 may include one or more top electrode layers 50, where the top electrode layer 50 is located on a side of the plurality of memory cells 40 away from the substrate 10, and a surface (i.e., a third surface) of the plurality of memory cells 40 away from the substrate 10 is completely covered by the top electrode layer 50, so that the plurality of memory cells 40 share the top electrode layer 50, where the plurality of top electrode layers 50 are located on a side of each of the plurality of memory cells 40 away from the substrate 10, the plurality of top electrode layers 50 are located on a third surface, and one top electrode layer 50 is located on each of the third surfaces, so that any two adjacent top electrode layers 50 are spaced apart, and optionally, the top metal wiring layer 60 electrically connects the plurality of top electrode layers 50.
Specifically, as shown in fig. 1, the top metal wiring layer 60 is used to electrically connect the plurality of memory cells 40 and interconnect the plurality of memory cells 40. In the case that the plurality of memory cells 40 have one top electrode layer 50 on the side far from the substrate 10, since the plurality of memory cells 40 are electrically connected through one top electrode layer 50, the top metal wiring layer 60 is disposed on the surface of the side far from the substrate 10, that is, the purpose of interconnecting the top metal wiring layer 60 with the plurality of memory cells 40 is achieved, and in the case that the plurality of memory cells 40 have the plurality of top electrode layers 50 on the side far from the substrate 10 and any two adjacent top electrode layers 50 are disposed at a distance, in order to form an interconnection structure between any two adjacent memory cells 40, the top metal wiring layer 60 is disposed on the surface of the side far from the substrate 10, and the top metal wiring layer 60 is electrically connected with the plurality of top electrode layers 50.
Alternatively, the materials of the upper and lower electrodes may include, but are not limited to, one or more of Ti, tiN, ta, taN, W, etc., and the materials of the top metal wiring layer 60 may include, but are not limited to, copper. The materials of the upper electrode and the lower electrode can be flexibly selected according to actual needs by a person skilled in the art.
In the above embodiment, since the heights of the first conductive vias and the second conductive vias in the substrate of the memory structure provided by the present embodiment are identical, the first conductive vias and the second conductive vias may be formed at one time by using the same photolithography process, thereby reducing the number of masks when forming the first conductive vias and the second conductive vias, and then after forming the plurality of memory cells and at least one top electrode layer covering the plurality of first conductive vias on the first surface, since the first conductive vias serve as bottom conductive vias in the memory structure and the second conductive vias serve as top conductive vias in the memory, the heights of the plurality of memory cells in the array region are higher than the heights of the second conductive vias in the case that the heights of the first conductive vias and the second conductive vias are identical, therefore, the top metal wiring layer electrically connected with at least one top electrode layer can be directly formed on the side of the substrate with the top electrode layer, so that the top metal wiring layer can be electrically connected with a plurality of memory cells, the total height of the bottom conductive paths corresponding to the array region and the memory cells in the prior art is lower than that of the top conductive paths of the logic region, the top conductive paths need to be formed on the side of the memory cells away from the bottom conductive paths again, the total height of the bottom conductive paths corresponding to the array region and the memory cells is equal to that of the top conductive paths of the logic region, compared with the top conductive paths of the memory cells, the application does not need to additionally form conductive paths electrically connected with a plurality of memory cells and the top metal wiring layer on the side of the memory cells away from the first conductive paths, thereby further simplifying the process, reducing the photoetching steps and reducing the number of photomask layers, thereby reducing the manufacturing cost of the memory structure.
Wherein in some alternative embodiments, each of said memory cells 40 has a first projection on said substrate 10, at least one of said top electrode layers 50 has a second projection on said substrate 10, said first projection being located within said second projection.
In the above embodiment, since the first projection of the memory cell 40 on the substrate 10 is located in the second projection of the top electrode layer 50 on the substrate 10, the size of the at least one top electrode layer 50 is larger than the size of the memory cell 40, so that the at least one top electrode layer 50 can protect the memory cell 40 in the later process steps of manufacturing the memory structure. Alternatively, the memory cell 40 can be prevented from being over-etched.
Specifically, in the case where the top electrode layer 50 is one, the projection of the top electrode layer 50 onto the substrate 10 is a second projection, the projections of the plurality of memory cells 40 onto the substrate 10 are correspondingly a plurality of first projections, so that the plurality of first projections are all located in the second projection, and specifically, in the case where the top electrode layer 50 is a plurality, the projection of each top electrode layer 50 of the plurality of top electrode layers 50 onto the substrate 10 is a second projection, the projection of each memory cell 40 of the plurality of memory cells 40 onto the substrate 10 is a first projection, the plurality of first projections and the plurality of second projections are in one-to-one correspondence, and each first projection is located in each corresponding second projection.
Since the top electrode layer 50 is disposed on a surface of the plurality of memory cells 40 on a side away from the substrate 10, the top electrode layer 50 is electrically connected to the memory cells 40, but in case the top electrode layer 50 includes a plurality of top electrode layers, since any two adjacent top electrode layers 50 are electrically isolated from each other, any two adjacent memory cells 40 are electrically isolated from each other, in some alternative embodiments, in order to form an electrical connection relationship between any two adjacent memory cells 40 in case the top electrode layer 50 includes a plurality of top electrode layers, each top electrode layer 50 covers a surface of one of the memory cells 40 on a side away from the first conductive via 20, and the top metal wiring layer 60 is electrically connected to a plurality of the top electrode layers 50, the plurality of top electrode layers 50 are in one-to-one correspondence with the plurality of memory cells 40.
In some alternative embodiments, as shown in FIG. 1, the memory structure further includes a protective layer 70, where the protective layer 70 covers at least the sidewalls of the memory cells 40. Further, the first surface corresponding to the array region has an exposed surface covered by a plurality of memory cells 40, and the protective layer 70 also covers the exposed surface, and further, in the case that the protective layer 70 also covers the exposed surface, the memory structure further includes an insulating dielectric layer 80, and in the case that the top electrode layer 50 is one, the insulating dielectric layer 80 is located between the protective layer 70 covering the exposed surface and the top electrode layer 50, and in the case that the top electrode layer 50 is a plurality, the insulating dielectric layer 80 is located between the top metal wiring layer 60 and the protective layer 70.
In the above embodiment, in order to prevent the memory cell 40 in the memory structure from being damaged by water or the like, the protective layer 70 is disposed around the periphery of the memory cell 40, and further, in order to function as an etching barrier in the memory structure, the protective layer 70 is located on a portion of the first surface of the substrate 10 corresponding to the array region (i.e., an exposed surface except for being covered by the plurality of memory cells 40). Alternatively, the material of the protective layer 70 may include, but is not limited to, silicon nitride, aluminum oxide, etc., and further, the material of the insulating dielectric layer 80 may include, but is not limited to, any one or more of silicon dioxide, carbon oxide, fluorosilicate glass, phosphosilicate glass, borophosphosilicate glass, tetraethyl orthosilicate, low-K dielectric, and Ultra-Low-K dielectric. It should be noted that the protective layer 70 and the insulating dielectric layer 80 have a high etching selectivity therebetween.
Further, in order to planarize the surface of the memory cell 40 on the side away from the substrate 10, the protective layer 70 further has an insulating dielectric layer 80 on the side away from the substrate 10, wherein the projection of the top electrode layer 50 on the substrate 10 and the projection of the insulating dielectric layer 80 on the substrate 10 at least partially overlap.
The plurality of first conductive vias 20 in the array region of the memory structure are electrically connected to the plurality of memory cells 40, the plurality of memory cells 40 are electrically connected to one or more top electrode layers 50, and one or more top electrode layers 50 are electrically connected to a top metal wiring layer 60. Further, in order to electrically connect the array region and the logic region of the memory structure, in some alternative embodiments, the top metal wiring layer 60 is also electrically connected to the second conductive vias 30.
Since the memory structures may include magnetic random access memory structures, phase change random access memory structures, resistance change random access memory structures, and ferroelectric random access memory structures, in some alternative embodiments, the memory cell 40 includes one or more of magnetic random access memory cell 40, phase change random access memory cell 40, resistance change random access memory cell 40, and ferroelectric random access memory cell 40.
In some alternative embodiments, where the memory cell 40 is a magnetic random access memory cell 40, at least one of the top electrode layers 50 includes at least one layer. Further, at least one of the top electrode layers 50 includes a plurality of layers, and at least one of the top electrode layers 50 is made of a ferromagnetic material.
Optionally, the material of the at least one top electrode layer 50 may be a metal material, where the metal material may include, but is not limited to, a nonmagnetic material such as TaN, tiN, W, and in the above embodiment, in order to significantly enhance the capability of the mram cell 40 to resist external magnetic field interference, the material of the at least one top electrode layer 50 may be a ferromagnetic material, where the ferromagnetic material may include, but is not limited to, another ferromagnetic material such as NiFe, coFe, feV, or any other metal material capable of being used as the top electrode layer 50 and combinations thereof known to those skilled in the art. Further, at least one top electrode layer 50 may include a plurality of layers, wherein the material of the plurality of top electrode layers 50 may be all non-magnetic materials, or the material of the plurality of top electrode layers 50 may be all ferromagnetic materials, or the material of a portion of the plurality of top electrode layers 50 may be non-magnetic materials, and the material of another portion of the plurality of top electrode layers 50 may be ferromagnetic materials.
It should be noted that, in the above memory structure of the present embodiment, the plurality of mram cells 40 may be arranged side by side along a direction, and in the case that the top electrode layer 50 on the surface of the memory structure on the side of the plurality of mram cells 40 away from the substrate 10 is one layer, the extending direction of the top electrode layer 50 is the direction in which one mram cell 40 points to another mram cell 40, so that the top electrode layer 50 is a stripe structure in the extending direction, and the stripe structure is parallel to the bit line BL running direction in the memory structure, so that the external magnetic field interference resistance of the mram cell 40 may be significantly enhanced.
According to another aspect of the present application, the inventor provides a method for fabricating a memory structure, the method comprising providing a substrate having a first surface and a second surface opposite to each other, the substrate including an array region and a logic region adjacent to the array region, forming a plurality of first conductive vias and second conductive vias in the substrate by a single photolithography process, wherein the plurality of first conductive vias extend from the first surface corresponding to the array region to the second surface, the second conductive vias extend from the first surface corresponding to the logic region to the second surface, the first conductive vias and the second conductive vias have the same height in an extending direction, forming a plurality of memory cells on the first surface such that each memory cell covers one of the first conductive vias, the plurality of memory cells and the plurality of first conductive vias one by one, forming at least one top electrode layer on a surface of the plurality of memory cells away from one side of the substrate, and forming at least one top electrode layer on one side of the substrate having a top electrode layer electrically connected to the top electrode layer, and forming at least one top electrode layer electrically connected to the top electrode layer on one side of the substrate.
In the above embodiment, the substrate having the first conductive via and the second conductive via is provided, and the first conductive via and the second conductive via in the substrate are highly consistent, that is, the first conductive via and the second conductive via are formed at one time by using the same photolithography process, so that the number of masks for forming the first conductive via and the second conductive via is reduced, and further, after forming the plurality of memory cells and the at least one top electrode layer covering the first conductive via on the first surface, the top metal wiring layer electrically connected to the at least one top electrode layer is directly formed on the side of the substrate having the top electrode layer, so that the top metal wiring layer can be electrically connected to the plurality of memory cells.
Exemplary embodiments of a method of fabricating a memory structure provided in accordance with the present application will be described in more detail below. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. It should be appreciated that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art.
As shown in fig. 2, a substrate 10 is provided, the substrate 10 has a first surface and a second surface opposite to each other, and the substrate 10 includes an array region and a logic region adjacent to the array region, first, a first mask covering the first surface is formed on the first surface of the substrate 10, wherein the first mask includes a plurality of first hollowed-out regions corresponding to the array region and a second hollowed-out region corresponding to the logic region, then the plurality of first hollowed-out regions and the second hollowed-out regions are etched to form a plurality of first through holes penetrating from the first surface to the second surface in the array region, a second through hole penetrating from the first surface to the second surface in the logic region is formed, then after the first mask is removed, a conductive material is deposited on the first surface to fill the plurality of first through holes and the second through holes, further, a planarization process may be used to remove the conductive material located on the first surface so that the remaining conductive material located in the plurality of first through holes forms a plurality of first conductive vias 20, and the remaining conductive material located in the second through holes forms a second conductive via 30. Alternatively, the planarization process may include a chemical mechanical polishing process. Alternatively, the conductive material may include, but is not limited to, W, cu, taN, tiN, a metal or a combination of metals. Optionally, the substrate further includes a first metal wiring layer 90 and a second metal wiring layer 100, the first conductive via 20 is located on the first metal wiring layer 90, and the second conductive via 30 is located on the second metal wiring layer 100.
Further, as shown in fig. 3, a memory cell thin film 110 corresponding to the memory cell 40 is deposited on the substrate 10 shown in fig. 2, and in particular, the memory cell thin film 110 may include a lower electrode material layer 111, a memory material layer 112, and an upper electrode material layer 113 formed by sequential deposition. The lower electrode material layer 111 and the upper electrode material layer 113 may include, but are not limited to, metal layers of Ti, tiN, ta, taN, W, etc., and optionally, a hard mask material layer (not shown) may be further included on the upper electrode material layer 113, and the hard mask material layer may include, but is not limited to, metal layers of Ti, tiN, ta, taN, W, etc., or dielectric layers of silicon oxide, silicon nitride, etc. Alternatively, the memory material layer 112 may include a free layer, a barrier layer, and a reference layer stacked in this order, the free layer being disposed in contact with the lower electrode material layer 111, and the reference layer being disposed in contact with the upper electrode material layer 113.
Further, a second mask is first covered on one side of the memory cell film 110 shown in fig. 3, the second mask having thereon a plurality of memory cell patterns corresponding to the plurality of first conductive vias 20 of the array region, and then the memory cell film 110 is etched according to the memory cell patterns (wherein, in the case that a hard mask material layer is further covered on the memory cell film 110, the hard mask material layer and the memory cell film 110 are sequentially etched), thereby removing the memory cell film 110 except for covering the plurality of first conductive vias 20, so that the remaining memory cell film 110 forms the memory cells 40, as shown in fig. 4, and so that part of the first surfaces are exposed, alternatively, the projected shape of the memory cells 40 on the substrate 10 may be circular.
Further, as shown in fig. 4 to 6, a top electrode layer 50 is formed on a side of the plurality of memory cells remote from the substrate 10, wherein in some alternative embodiments, the step of forming the top electrode layer 50 includes sequentially depositing a first insulating material 120 and a second insulating material 130 on a side of the substrate 10 having the memory cells 40 such that the first insulating material 120 covers the memory cells 40 and the first surface and the second insulating material 130 covers the first insulating material 120, removing a portion of the first insulating material 120 and a portion of the second insulating material 130 by chemical mechanical polishing to form a fourth surface exposing the plurality of memory cells 40, and forming the top electrode layer 50 on the fourth surface.
Specifically, as shown in fig. 4, after the memory cell 40 is formed, a first insulating material 120 is deposited on the exposed first surface side such that the first insulating material 120 covers the exposed portion of the first surface and the exposed surface of the memory cell 40. Alternatively, the first insulating material 120 may include, but is not limited to, silicon nitride, aluminum oxide, and the like. The first insulating material 120 used as a protective function in the prior art can be appropriately selected by those skilled in the art according to actual needs.
Further, as shown in fig. 5, in the structure shown in fig. 4, in order to make the plurality of memory cells 40 have a flat upper surface (i.e., a surface of each memory cell 40 on a side far from the substrate 10), a second insulating material 130 is first deposited so that the second insulating material 130 covers the first insulating material 120, and then a part of the second insulating material 130 and the first insulating material 120 may be removed by chemical mechanical polishing so that the upper surfaces of the plurality of memory cells 40 are exposed, so as to form a fourth surface, which is a planarized surface.
Further, as shown in fig. 6, a top electrode material is deposited on the fourth surface (planarized surface) shown in fig. 5, such that the top electrode material covers the fourth surface (optionally, an etching stop material may also be deposited so that the etching stop material covers a side surface of the top electrode material away from the substrate 10), and further, in order to form one top electrode layer 50 on a surface of the plurality of memory cells 40 away from the substrate 10, a third mask is formed on the fourth surface (or on a surface of the etching stop material away from the top electrode material), and covers the top electrode material (or the etching stop material) corresponding to the array region and exposes the top electrode material corresponding to the logic region, so that the top electrode material (and the etching stop material) corresponding to the logic region and a portion of the second insulating material 130 can be removed by etching to form the top electrode layer 50 (and the etching stop layer 150 corresponding to the etching stop material).
Further, as shown in fig. 7, in order to planarize a surface of the top electrode layer 50 on a side away from the plurality of memory cells 40, the second insulating material 130 is deposited again on a side of the top electrode layer 50 (and the etch stop layer 150 corresponding to the etch stop material) and the remaining second insulating material 130 away from the substrate 10 as shown in fig. 6.
Further, a part of the second insulating material 130 (the etching stop layer 150 corresponding to the etching stop material) in the structure shown in fig. 7 is removed by a chemical mechanical polishing process, so that the top electrode layer 50 is exposed, further, a fourth photomask is formed on the planarized surface of the exposed top electrode layer 50, so that the fourth photomask covers the top electrode layer 50 and exposes the second insulating material 130 corresponding to the logic region, then, the second insulating material 130 not covered by the fourth photomask is removed by etching, and in the case that the first insulating material 120 is used as an etching stop layer, the first insulating material 120 located in the logic region is removed, so that the second conductive via 30 is exposed, so that the logic region and the array region form a step structure, so that the remaining first insulating material forms the protective layer 70, the remaining second insulating material forms the insulating medium layer 80, further, the top metal material is deposited on one side of the exposed top electrode layer 50 and the exposed second conductive via 30, so that the top metal material fills the step structure, and the top metal layer 60 is electrically connected to the plurality of connection lines of the logic region 30 by a chemical mechanical polishing process, so that the top metal layer 60 is electrically connected to the plurality of connection lines of the logic region 30.
Or, as illustrated in fig. 8, in other embodiments, a top electrode material is deposited on a fourth surface (planarized surface) illustrated in fig. 5 such that the top electrode material covers the fourth surface (alternatively, an etch stop material may also be deposited such that the etch stop material covers a side surface of the top electrode material away from the substrate 10), and further, in order to form a plurality of top electrode layers 50 on a surface of the plurality of memory cells 40 away from the substrate 10, a fifth mask is formed on the fourth surface (and on a surface of the etch stop material away from the top electrode material), the fifth mask including a plurality of sub-mother boards disposed at intervals, the plurality of sub-mother boards covering portions of the top electrode material (and the etch stop material) corresponding to the plurality of memory cells 40 of the array region and exposing the remaining top electrode material, such that the top electrode material (and the etch stop material) except the portions of the top electrode material (or the etch stop material) corresponding to the plurality of memory cells 40 and portions of the second insulating material 130 are removed by etching to form an etch stop layer 150 of the plurality of top electrode layers 50 and the remaining etch stop material. It will be appreciated that since the top electrode material between any two adjacent sub-mother boards is exposed, after the etching process, portions of the second insulating material 130 between any two adjacent top electrode layers 50 or any two adjacent memory cells 40 are also removed, thereby forming pits between any two adjacent top electrode layers 50 or any two adjacent memory cells 40.
Further, as shown in fig. 9, in order to planarize a side surface of the top electrode layer 50 away from the plurality of memory cells 40, the second insulating material 130 is deposited again on a side of the plurality of top electrode layers 50 (and the etch stop layer 150 formed of the remaining etch stop material) and the remaining second insulating material 130 away from the substrate 10 shown in fig. 8, and optionally, the second insulating material 130 fills the pits.
Further, a part of the second insulating material 130 (and the etching stop layer 150 formed by the remaining etching stop material) in the structure shown in fig. 9 is removed by a chemical mechanical polishing process, so that the top electrode layer 50 is exposed, and then a sixth photomask is formed on the planarized surface of the exposed top electrode layer 50, so that the sixth photomask covers the top electrode layer 50, and exposes the second insulating material 130 except for the top electrode layer 50, then the second insulating material 130 which is not covered by the sixth photomask is removed by etching, and under the condition that the first insulating material 120 is used as an etching stop layer, the first insulating material 120 located in the logic region is removed, so that the second conductive path 30 is exposed, and thus the logic region and the array region form a step structure, and then the sidewalls of any two adjacent top electrode layers 50 are exposed, and then the remaining first insulating material forms 70, and the remaining second insulating material forms an insulating dielectric layer 80, and then the top metal layer 60 is electrically connected to the top electrode layer 50 by the chemical polishing process, and then the metal layer 60 is filled in the metal layer between the top electrode layer 50 and the metal layer 50, and the metal layer 50 is electrically connected to the metal layer 60, and the metal layer is filled in the step structure is formed between the two adjacent top electrode layers, and the metal layer 50 is exposed, and the metal layer is electrically removed to form a groove.
Or, as illustrated in fig. 11, in other embodiments, in order to make the plurality of memory cells 40 have a flat upper surface (i.e., a surface of each memory cell 40 on a side far from the substrate 10) on the structure shown in fig. 4, a second insulating material 130 is first deposited so that the second insulating material 130 covers the first insulating material 120, and then a chemical mechanical polishing may be used to remove a portion of the second insulating material 130, so that the first insulating material 120 on a surface of the plurality of memory cells 40 on a side far from the substrate 10 is exposed, to form a fourth planarized surface.
Further, as shown in fig. 12, a seventh mask is formed on the fourth planarized surface shown in fig. 11, the seventh mask covering a portion of the fourth planarized surface corresponding to the logic region and exposing a portion of the fourth planarized surface corresponding to the array region, and further removing the exposed portion of the second insulating material 130 and the portion of the first insulating material 120 by etching and exposing an upper surface of the plurality of memory cells 40 on a side away from the substrate 10, such that after the seventh mask is removed, there is a step structure (the height of the array region in a direction perpendicular to the first surface is lower than the height of the logic region) between the array region and the logic region, such that after the top electrode material 140 is deposited on the step structure, the array region and the logic region still have a height difference;
Further, the top electrode material 140 in the structure shown in fig. 12 is planarized by chemical mechanical polishing to remove the height difference between the array region and the logic region, so that the entire top electrode material 140 of the logic region is removed after the planarization due to the low height of the array region, and the second insulating material 130 is exposed, so that the remaining top electrode material in the array region forms the top electrode layer 50 of the memory structure as shown in fig. 13. Further, in order to planarize a side surface of the top electrode layer 50 away from the plurality of memory cells 40 as shown in fig. 13, the above-mentioned second insulating material 130 is deposited again on the exposed surface of the top electrode layer 50 and the side of the second insulating material 130 remaining after the planarization away from the substrate 10;
Further, a part of the second insulating material 130 is removed by a chemical mechanical polishing process to expose the top electrode layer 50, and then an eighth mask is formed on the planarized surface of the exposed top electrode layer 50, such that the eighth mask covers the top electrode layer 50 and exposes the second insulating material 130 corresponding to the logic region, then the second insulating material 130 not covered by the eighth mask is removed by etching, and in the case that the first insulating material 120 is used as an etching barrier, the first insulating material 120 located in the logic region is removed, such that the second conductive via 30 is exposed, thereby forming a step structure in the logic region and the array region, such that, as shown in fig. 14, the remaining first insulating material forms the protective layer 70, the remaining second insulating material forms the insulating dielectric layer 80, and then a top metal material is deposited on one side of the exposed top electrode layer 50 and the exposed second conductive via 30, such that the top metal material fills the step structure, and the top metal material is planarized by a chemical mechanical polishing process, thereby forming the top metal wiring layer 60, the top metal wiring layer 60 electrically connecting the logic region and the plurality of conductive via array regions 40 of the logic region.
From the above description, it can be seen that the above embodiments of the present invention achieve the following technical effects:
Because the heights of the first conductive paths and the second conductive paths in the substrate of the memory structure provided by the scheme are consistent, the first conductive paths and the second conductive paths can be formed at one time by adopting the same photoetching process, so that the number of photomasks when the first conductive paths and the second conductive paths are formed is reduced, then after a plurality of memory cells and at least one top electrode layer which cover the first conductive paths are formed on the first surface, the first conductive paths are used as bottom conductive paths in the memory structure, and the second conductive paths are used as top conductive paths of the memory, so that the heights of the memory cells of the array region are higher than the heights of the second conductive paths under the condition that the heights of the first conductive paths and the second conductive paths are consistent, and therefore, the number of top metal wire layers which are electrically connected with at least one top electrode layer can be directly formed on one side of the substrate with the top electrode layer, namely the top metal wire layers can electrically connect the memory cells, the total height of the memory cells and the total height of the memory cells which corresponds to the array region in the prior art is lower than the total height of the memory cells which is required to be formed, the total number of the memory cells which is not required to be further reduced compared with the total number of the memory cells which is required to be formed in the first side of the memory structure, the application, the number of the total number of the conductive paths which is reduced, and the total number of the conductive lines is not required to be further reduced by the steps of the top metal wire layers which is required to be electrically connected with the top metal wire layers of the top metal wire layers which is formed at one side of the substrate, thereby reducing the manufacturing cost of the memory structure.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
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| CN109713006A (en) * | 2017-10-25 | 2019-05-03 | 上海磁宇信息科技有限公司 | A method of making magnetic RAM cell array and its peripheral circuits |
| CN109713121A (en) * | 2017-10-25 | 2019-05-03 | 上海磁宇信息科技有限公司 | A method of making magnetic RAM cell array and its peripheral circuits |
| US20200075857A1 (en) * | 2018-08-30 | 2020-03-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Top electrode last scheme for memory cell to prevent metal redeposit |
| CN113471357A (en) * | 2020-06-16 | 2021-10-01 | 台湾积体电路制造股份有限公司 | Memory array device and method of manufacturing the same |
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| US7186569B2 (en) * | 2002-08-02 | 2007-03-06 | Unity Semiconductor Corporation | Conductive memory stack with sidewall |
| US9893278B1 (en) * | 2016-08-08 | 2018-02-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Embedded memory device between noncontigous interconnect metal layers |
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| CN109713006A (en) * | 2017-10-25 | 2019-05-03 | 上海磁宇信息科技有限公司 | A method of making magnetic RAM cell array and its peripheral circuits |
| CN109713121A (en) * | 2017-10-25 | 2019-05-03 | 上海磁宇信息科技有限公司 | A method of making magnetic RAM cell array and its peripheral circuits |
| US20200075857A1 (en) * | 2018-08-30 | 2020-03-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Top electrode last scheme for memory cell to prevent metal redeposit |
| CN113471357A (en) * | 2020-06-16 | 2021-10-01 | 台湾积体电路制造股份有限公司 | Memory array device and method of manufacturing the same |
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