CN119441134B - Sensing and memory calculation integrated macro unit circuit, system and analog-to-digital conversion method - Google Patents

Abstract

The application discloses a sensing and storing integrated macro unit circuit, a sensing and storing integrated macro unit system and an analog-to-digital conversion method, which comprise the steps that a tag module reads analog signals from a iSC bus; the tag module performs traversal comparison on the read analog signals and a plurality of reference analog signals, obtains corresponding digital signals according to comparison results, and the plurality of reference analog signals are data with gradually increased or decreased random function relations. The method does not need a special ADC circuit, and realizes the conversion function by utilizing the existing circuit of PE.

Description

A sensing-storage-computing integrated macro unit circuit, system and analog-to-digital conversion method

Technical Field

The present invention relates to the field of electronic circuits and signal processing, and in particular to a sensing-storage-computing integrated macro unit circuit, system and analog-to-digital conversion method.

Background Art

With the development of the industrial Internet, higher requirements are placed on video acquisition and processing technologies. In traditional visual application systems, image sensors collect image information, convert optical signals into electrical signals, and convert them into digital signals after digital-to-analog conversion. The image data is then processed by the image signal processing unit and finally output to the processor in the system through a special video interface. The processor then performs data analysis and makes corresponding controls and operations.

In applications such as image processing and laser ranging, as shown in Figure 1, the integrated sensing, storage and computing chip achieves efficient and low-power data processing by integrating sensing, storage and computing functions. Among them, the middle is the processing macro unit (PE) 1 array, which is closely placed together in the form of an array of PEs, such as a 1024*1024 scale. Because each PE includes a sensing, storage and computing basic unit, all PEs in the PE array can simultaneously process the data in each unit in parallel. This method is also often called a single instruction multiple data mode, namely SIMD, which is more common in GPUs. Row control modules 5 and column control modules 6 are designed in the horizontal and vertical directions of the PE array respectively. The row control module 5 is used to select rows and related controls for the PE array, and the corresponding column mode control module is used to select columns and related controls for the PE array, as well as data readout selection. The periphery of the PE array also includes a peripheral digital module 4, an INS bus 41, a peripheral analog module 3, and an interface module 7.

As shown in Figure 2, the PE unit includes a sensing unit (SU), an analog signal operator operation unit (AOP), an analog storage unit (AREG Bank), a digital storage unit (DREG bank), a tag module (TAG), and an adjacent PE communication unit (AdjacentIF). The analog storage unit includes several analog signal memories AREG0, AREG1, etc. The analog signal memory itself is also an operation unit. Similarly, the digital storage unit includes several digital signal memories DREG0, DREG1, etc. In addition to storing digital signals, the digital signal memory can also perform logical operations. The output of the tag unit is used as a judgment signal to control whether the current PE executes the current SIMD instruction.

To convert conventional analog signals to digital signals, a special ADC chip or ADC circuit is needed to realize the conversion. For traditional image sensors, from the early single ADC to the column-level ADC, and then to the latest pixel-level ADC design, the chip area and the energy consumption required for conversion will increase, and the pixel-level ADC requires more advanced process technology, such as stacking process. Because of the ADC design size limitation and the ADC frequency characteristic requirements, the traditional data handling process results in high processing delay and high power consumption.

Especially for the memory and computing chip, the analog memory and computing units and digital memory and computing units in PE face great problems when the signals interact or flow in the analog and digital domains. Either the ADC circuit is designed in PE, but it brings problems of circuit area and power consumption. Or the serial conversion is carried out through a single ADC circuit, which brings efficiency problems, data flow delay and power consumption problems.

Summary of the invention

The present invention proposes a sensing, storage and computing integrated macro unit circuit, system and data processing method, which can realize the conversion function through special modules and PE mode control.

The present invention provides an analog-to-digital conversion method for a sensing-storage-computing integrated macro unit circuit, comprising the steps of:

The tag module reads the analog signal from the iSC bus;

The tag module compares the read analog signal with several reference analog signals;

Obtaining a corresponding digital signal according to the comparison result;

The plurality of reference analog signals are data that gradually increase or decrease along a functional relationship.

Optionally, the reference analog signal gradually increases or decreases with the number of times according to a linear function, exponential function, logarithmic function, power function or trigonometric function relationship.

Optionally, the analog signal gradually increases or decreases with the number of times according to a linear function, exponential function, logarithmic function, power function or trigonometric function relationship.

Optionally, the encoding rule of the digital signal is standard binary code, Gray code, Hamming code or Huffman code.

Optionally, obtaining a corresponding digital signal according to the comparison result further includes the steps of:

The initialization value of the digital storage unit is 0;

When the comparison result of the tag module is that the analog signal is less than the reference analog signal, the digital signal stored in the digital storage unit changes a value according to the encoding rule each time the comparison is performed until the analog signal is greater than or equal to the reference analog signal, and the digital storage unit outputs the stored digital signal.

Optionally, the method further includes the step of: the label module determining whether the current sensing, storage and computing integrated macro unit circuit executes the instruction sent by the INS bus based on the stored identification data.

Optionally, the step is also included: in the digital-to-analog conversion mode, the label module is composed of a comparator circuit and a latch circuit, the comparator circuit is used to compare the analog signal with a number of reference analog signals, and the latch is used to store the comparison result, when the comparison result stored in the label module is a first value, the corresponding processing unit executes the current INS instruction, and when the comparison result stored in the label module is a second value, the corresponding processing unit does not execute the current INS instruction.

Optionally, in the non-digital-to-analog conversion mode, the comparator also compares the identification data and the input reference signal, and then stores the output result of the comparator in a subsequent latch; when the comparison result stored in the label module is a first value, the corresponding processing unit executes the current INS instruction, and when the comparison result stored in the label module is a second value, the corresponding processing unit does not execute the current INS instruction.

Optionally, the digital signal is a 3-bit binary signal.

Optionally, the step is also included: a DAC unit outside the sensing-storage-computing integrated macro unit circuit sends a reference analog signal.

The present invention also provides a sensing-storage-computing integrated macro unit circuit, comprising:

iSC bus is used to connect various modules and transmit perception signals and operation signals between modules;

INS bus, used to connect various modules;

A digital storage and calculation unit, used for simultaneously performing data storage and data calculation, wherein the data includes digital signals;

An analog storage and calculation unit, used for simultaneously performing data storage and data calculation, wherein the data includes analog signals;

The tag module is used to read the analog signal from the iSC bus; compare the read analog signal with several reference analog signals;

An output module, used for obtaining a digital signal according to the comparison result;

The first control module is used to provide reference analog signals to the tag module, wherein the reference analog signals are data that gradually increase or decrease along a functional relationship.

Optionally, the reference analog signal gradually increases or decreases with the number of times according to a linear function, exponential function, logarithmic function, power function or trigonometric function relationship.

Optionally, the encoding module is used to correspond the reference analog signal and the digital signal according to a certain encoding rule, and the encoding rule of the digital signal is standard binary code, Gray code, Hamming code or Huffman code.

Optionally, it further includes: a second control module, configured to initialize the digital storage unit to 0;

When the comparison result of the tag module is that the analog signal is less than the reference analog signal, the digital signal stored in the digital storage unit changes a value according to the encoding rule each time the comparison is performed until the analog signal is greater than or equal to the reference analog signal.

Optionally, the sensing unit, analog storage and computing unit, digital storage and computing unit, iSC bus, INS bus and tag module are integrated on the same chip.

Optionally, the label module determines whether the current sensing-storage-computing-in-one macro unit circuit executes instructions sent by the INS bus based on the stored identification data.

Optional: In the digital-to-analog conversion mode, the label module is composed of a comparator circuit and a latch circuit. The comparator circuit is used to compare the analog signal with several reference analog signals, and the latch is used to store the comparison result. When the comparison result stored in the label module is a first value, the corresponding processing unit executes the current INS instruction. When the comparison result stored in the label module is a second value, the corresponding processing unit does not execute the current INS instruction.

Optional: In the non-digital-to-analog conversion mode, the comparator also compares the identification data and the input reference signal, and then stores the output result of the comparator in the subsequent latch; when the comparison result stored in the label module is a first value, the corresponding processing unit executes the current INS instruction, and when the comparison result stored in the label module is a second value, the corresponding processing unit does not execute the current INS instruction.

Optionally, the analog storage and computing unit includes multiple analog signal memories, which also serve as analog computing units. By connecting the multiple analog storage and computing units to the same iSC bus for read and write operations, analog signals can be directly added, subtracted, multiplied, and divided in the analog signal memories.

Optionally, the digital storage and computing unit includes a plurality of digital signal memories, and the digital signal memories have both storage and logical operation capabilities.

Optionally, a DREG BANK is provided in the digital storage and computing unit, and the DREG BANK includes multiple digital signal memories, and a digital read bus iSC RD DBUS and a digital write bus iSC WR DBUS, and the digital signal memory is a digital register DREG; multiple digital registers DREG are connected in parallel between the digital read bus iSC RD DBUS and the digital write bus iSC WR DBUS, wherein the input end IN of the digital register DREG is connected to the digital write bus iSC WR DBUS, and the output end OUT of the digital register DREG is connected to the digital read bus iSC RD DBUS, and a multiplexer MUX is also connected between the digital read bus iSC RDDBUS and the digital write bus iSC WR DBUS, and the digital read bus iSC RDDBUS of the digital register DREG is also connected to the iSC bus through a switch.

Optionally, the digital signal memory is implemented using 3T DRAM, or 6T DRAM, or SRAM.

Optionally, the digital signal memory is implemented using Flash, which further includes: multiple FLASH memories, and a read-write control circuit, a digital read bus iSC RD DBUS and a multiplexer MUX, wherein the input end IN of the FLASH memory is connected to the read-write control circuit, the output end of the FLASH is connected in parallel to the digital read bus iSC RD DBUS, and a multiplexer MUX is connected between the digital read bus iSC RD DBUS and the read-write control circuit.

The present invention also provides a sensing, storage and computing integrated macro unit system, comprising:

Multiple sensing, storage and computing integrated macro-unit circuits are arranged in an array structure, where:

The sensing, storage and computing integrated macro unit circuit includes:

iSC bus is used to connect various modules and transmit perception signals and operation signals between modules;

INS bus, used to connect various modules;

A digital storage and calculation unit, used for simultaneously performing data storage and data calculation, wherein the data includes digital signals;

An analog storage and calculation unit, used for simultaneously performing data storage and data calculation, wherein the data includes analog signals;

The tag module is used to read the analog signal from the iSC bus; compare the read analog signal with several reference analog signals;

An output module, used for obtaining a digital signal according to the comparison result;

The first control module is used to provide reference analog signals to the tag module. The reference analog signals are data that gradually increase or decrease with a functional relationship. The external DAC unit serves as the first control module.

Optionally, the sensing, storage and computing integrated macro unit circuit array is located on the same chip.

The external DAC is located on-chip or off-chip.

The present invention utilizes existing PE resources and realizes the principle of ADC through a control method, thereby realizing a parallel method of converting analog domain to digital domain signals, which is in line with the characteristics of the SIMD system chip of sensing, storage and computing, and realizes ADC conversion for the entire PE array at the same time, allowing barrier-free conversion of analog domain signals and digital domain signals.

The present invention utilizes existing components in PE, such as comparators, to convert analog signals such as Pixel signals and AREG current signals into digital signals, which are stored in DREG in PE. This method realizes a parallel analog domain to digital domain signal conversion method without adding special conversion circuits. This method does not require a dedicated ADC circuit, but utilizes the existing circuits of PE to realize the conversion function. This parallel conversion is equivalent to pixel-level or PE-level signal conversion, has high efficiency and high bandwidth, and is very suitable for visual signal processing and conversion.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

FIG1 is a schematic diagram of the architecture of a sensing-storage-computing integrated macro unit system;

FIG2 is a schematic diagram of the architecture of a sensing-storage-computing integrated macro unit circuit;

FIG3 is a schematic diagram of a DREG architecture of a sensing-storage-computing integrated macro unit circuit;

FIG4 is a schematic diagram of an SRAM circuit of a sensing-storage-computing integrated macro unit circuit;

FIG5 is a schematic diagram of a TAG circuit of a sensing-storage-computing integrated macro unit circuit;

6 is a schematic diagram of an analog-to-digital conversion method of a sensing-storage-computing integrated macro unit circuit according to an embodiment of the present application;

7 is a flow chart of an analog-to-digital conversion method of a sensing-storage-computing integrated macro unit circuit according to an embodiment of the present application;

8 is a schematic diagram of an analog-to-digital conversion method of a sensing-storage-computing integrated macro unit circuit according to another embodiment of the present application;

9 is a schematic diagram of an analog-to-digital conversion method of a sensing-storage-computing integrated macro unit circuit according to an embodiment of the present application;

FIG. 10 is a schematic diagram of coding of an analog-to-digital conversion method of a sensing-storage-computing integrated macro unit circuit according to another embodiment of the present application.

DETAILED DESCRIPTION

The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more explicit definition of the protection scope of the present invention. Obviously, the embodiments described in the present invention are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

In this application, the use of "or" means "and/or" unless otherwise stated. Furthermore, the use of the term "comprising" and other forms such as "including" and "comprising" are not limiting. In addition, unless specifically stated otherwise, terms such as "element" or "component" encompass both elements and components comprising one unit and elements and components comprising more than one unit.

The present invention provides a sensing-storage-computing integrated macro unit system, comprising a plurality of the sensing-storage-computing integrated macro unit circuits described above, wherein the plurality of sensing-storage-computing integrated macro unit circuits are arranged in an array structure;

The sensing, storage and computing integrated macro unit circuit includes:

iSC bus is used to connect various modules and transmit perception signals and operation signals between modules;

INS bus, used to connect various modules;

A digital storage and calculation unit, used for simultaneously performing data storage and data calculation, wherein the data includes digital signals;

An analog storage and calculation unit, used for simultaneously performing data storage and data calculation, wherein the data includes analog signals;

The tag module is used to read the analog signal from the iSC bus; compare the read analog signal with several reference analog signals;

An output module, used for obtaining a digital signal according to the comparison result;

The first control module is used to provide reference analog signals to the tag module. The reference analog signals are data that gradually increase or decrease with a functional relationship. The external DAC unit serves as the first control module.

In one embodiment, it further includes: a DAC unit arranged outside the array structure, and the external DAC unit serves as a first control module.

In one embodiment, the sensing, storage and computing integrated macro unit circuit array is located on the same chip, and the external DAC is located inside or outside the chip.

As shown in Figure 1, in this embodiment, the sensing-storage-computing integrated macro unit system is specifically designed in a pixel-level sensing-storage-computing integrated chip, with a processing macro unit (PE) array in the middle, which is closely arranged together in the form of an array of PE1, for example, a scale of 1024*1024. The internal structure of PE is described in detail with reference to the specific sensing-storage-computing integrated macro unit circuit and the embodiments of the sensing-storage-computing integrated macro unit circuit later. Here, only the overall architecture of the sensing-storage integrated macro unit system is described.

Because each PE includes a basic sensing, storage and computing unit, all PEs in the PE array can process the data in each unit in parallel at the same time. This method is also often called single instruction multiple data mode, namely SIMD, which is more common in GPUs. Row control modules and column control modules are designed in the horizontal and vertical directions of the PE array respectively. The row control module is used to perform row selection and related control on the PE array, and the corresponding column mode control module is used to perform column selection and related control on the PE array, as well as data readout selection. Therefore, in addition to the PE array, the sensing and storage integrated circuit system also includes an analog-to-digital conversion unit (ADC) 2, a peripheral analog module 3, a peripheral digital module 4, a row control module 5, a column control module 6, an interface module 7, etc., and an INS bus 41 arranged on the periphery of the PE array.

In one embodiment, the sensing, storage and computing integrated macro unit system includes a plurality of sensing, storage and computing integrated macro unit circuits arranged in an array structure, specifically, the sensing, storage and computing integrated macro unit circuit of the distance measurement sensor, as shown in FIG2 , the PE unit includes a sensing unit SU, an analog signal operator operation unit AOP, an analog storage and computing unit AREG bank, a digital storage and computing unit DREGbank, a tag module TAG, an adjacent PE communication unit adjacent IF, an iSC bus, and an INS bus, the above units and modules are connected to the iSC bus and the INS bus, the iSC bus is used to transmit sensing signals and operation signals, and the sensing unit and the storage and computing unit are both connected to the iSC bus; the INS bus is used to transmit instructions. The tag module is used to read an analog signal from the iSC bus; the read analog signal is compared with a plurality of reference analog signals, and the comparison result is output; the output module is used to output a digital signal according to the comparison result and the reference analog signal; the first control module is used to provide a reference analog signal to the tag module, and the plurality of reference analog signals are data that gradually increases or decreases with a function relationship.

In one embodiment, the reference analog signal gradually increases or decreases with the number of times according to a linear function, an exponential function, a logarithmic function, a power function or a trigonometric function relationship.

In one embodiment, the encoding module is used to correspond the reference analog signal and the digital signal according to a certain encoding rule, and the encoding rule of the digital signal is standard binary code, Gray code, Hamming code or Huffman code.

In one embodiment, outputting a corresponding digital signal according to the comparison result and the reference analog signal further comprises the steps of:

The initialization value of the digital storage unit is 0;

When the comparison result of the tag module is that the analog signal is less than the reference analog signal, the digital signal stored in the digital storage unit changes a value according to the encoding rule each time the comparison is performed until the analog signal is greater than or equal to the reference analog signal, and the digital storage unit outputs the stored digital signal.

In one embodiment, the sensing unit, analog storage and computing unit, digital storage and computing unit, iSC bus, INS bus and tag module are integrated on the same chip.

In one embodiment, the analog storage and computing unit includes multiple analog signal memories, which also serve as analog computing units. By connecting the multiple analog storage and computing units to the same iSC bus for read and write operations, analog signals can be directly added, subtracted, multiplied, and divided in the analog signal memories.

In one embodiment, the digital storage and computing unit includes a plurality of digital signal memories, and the digital signal memories have both storage and logic operation capabilities.

In one embodiment, a DREG BANK is provided in the digital storage and computing unit, and the DREG BANK includes multiple digital signal memories, a digital read bus iSC RD data bus and a digital write bus iSC WR data bus, and the digital signal memory is a digital register DREG; multiple digital registers DREG are connected in parallel between the digital read bus iSC RD data bus and the digital write bus iSC WR data bus, wherein the input end IN of the digital register DREG is connected to the iSCWR data bus, and the output end OUT of the digital register DREG is connected to the iSC RD data bus, and a multiplexer MUX is also connected between the digital read bus iSCRD data bus and the digital write bus iSC WR data bus, and the digital read bus iSC RD data bus of the digital register DREG is also connected to the iSC bus through a switch.

In one embodiment, the digital signal memory is implemented using 3T DRAM, or 6T DRAM, or SRAM.

In one embodiment, the digital signal memory is implemented using Flash, which further includes: multiple FLASH memories, and a read-write control circuit, a read data iSC RD data bus and a multiplexer MUX, wherein the input end IN of the FLASH memory is connected to the read-write control circuit, the output end of the FLASH is connected in parallel to the iSC RD data bus, and a multiplexer MUX is connected between the iSC RD data bus and the read-write control circuit.

In one embodiment, it also includes: identification data is stored in the label module, and whether the current sensing, storage and computing integrated macro unit circuit executes the instruction sent by the INS bus is determined based on the stored identification data.

In one embodiment, during operation, one or more digital register DREG signals read out from the digital read bus iSC RD data bus are written back to the digital write bus iSC WR data bus through the multiplexer MUX and then written into the corresponding one or more digital registers DREG to implement the operation.

In one embodiment, each label module corresponds to a processing unit, which is used to determine whether the current processing unit PE executes the current INS instruction based on the comparison result stored in the label module, that is, the identification data; when the comparison result stored in the label module is a first value, the corresponding processing unit executes the current INS instruction, and when the comparison result stored in the label module is a second value, the corresponding processing unit does not execute the current INS instruction.

In one embodiment, the analog storage and calculation unit includes several analog signal memories AREG0, AREG1..., and the analog signal memory itself is also an operation unit. The signal can be added, subtracted, multiplied and divided through the analog memory. For example, 5 registers can be designed to meet basic operation requirements. Similarly, the digital storage and calculation unit is provided with a DREG BANK, and the DREG BANK includes multiple digital signal memories, and the digital signal memory is a digital register DREG; a dedicated digital read bus iSC RD bus and a digital write bus iSC WR bus are designed in the DREGBANK, and multiple DREG read control signals RD are opened to the read bus at the same time, so as to realize the line and operation of storing digital signals. The digital read bus can pass the signal to the iSC bus through the selection tube for further operation. A multiplexer MUX is designed between the two buses to write the read signal of the read bus back to the write bus and then write it to the corresponding DREG. The written signal can be the same as the original signal and can also be written back inversely. This is the role of the multiplexer MUX. Referring to FIG3, multiple digital registers DREG0, DREG1, etc. are connected in parallel between the digital read bus iSC RD DBUS and the digital write bus iSC WR DBUS. In addition to storing digital signals, the digital signal memory can also perform logical operations. Among them, the input terminal IN of the digital register DREG is connected to the iSC WR DBUS, and the output terminal OUT of the digital register DREG is connected to the digital read bus iSC RD DBUS. A multiplexer MUX is also connected between the digital read bus iSCRD DBUS and the digital write bus iSC WR DBUS. The digital read bus iSCRD DBUS of the digital register DREG is also connected to the iSC bus through a switch.

The digital signal memory is implemented by 3T DRAM, or 6T DRAM, or SRAM. 6T SRAM is used as the circuit for digital signal storage DREG in PE. Compared with the previous DRAM, the storage is more stable, but the unit size of DREG will be increased. Data is written through the MWR tube, WR is valid, IN inputs a valid signal, and the write operation is completed. Correspondingly, data is read out through the MRD tube, RD is valid, OUT outputs a valid signal, and the read operation is completed. For the specific RAM in this embodiment, refer to Figure 4.

In one embodiment, in addition to performing conventional operations through analog registers, the analog signal operator operation unit AOP can design efficient special operators to implement special operations, such as square operations, log operations, square root operations, etc., according to the particularity of the application scenario.

During operation, one or more digital register DREG signals read out by the digital read bus iSC RD DBUS are written back to the digital write bus iSC WR DBUS through the multiplexer MUX and then written into the corresponding one or more digital registers DREG to implement the operation.

In one embodiment, the tag module determines whether the current sensing-storage-computing-in-one macro unit circuit executes the instruction sent by the INS bus based on the stored identification data.

In one embodiment, referring to FIG. 5 , the tag unit includes a comparator for reading an analog signal from the iSC bus; performing traversal comparison between the read analog signal and a plurality of reference analog signals, and outputting a digital signal according to the comparison result.

In one embodiment, the output of the tag module is used as a judgment signal or an enable signal to control whether the current PE executes the global SIMD instruction. For a PE designed with a TAG module, when the TAG output state is "invalid", the current PE does not execute the current instruction. On the contrary, when the TAG output state is "valid", the current PE executes the current instruction. The signal affecting the TAG tag module comes from the operation process of the analog register, such as signal overflow after operation, and the numerical judgment of the digital signal "0" and "1", as well as other operation results. The TAG tag module is designed to consist of a comparator circuit and a latch circuit. The comparator circuit is used to compare the signal on the iSC bus with the reference input signal, and then the output result of the comparator is stored in the latch behind. The TAG tag module controls the PE internal perception unit, analog storage unit, digital storage unit, and adjacent PE communication module, and controls the read and write operations or working states of the above unit circuits through the enable circuit. The control range of the TAG tag module is only the current PE. The chip restores the TAG to its initial state through the global TAG reset signal.

In this embodiment, in the digital-to-analog conversion mode, the comparator circuit of the label module is used to compare the analog signal with a number of reference analog signals, and the latch is used to store the comparison result. When the comparison result stored in the label module is a first value, the corresponding processing unit executes the current instruction, and when the comparison result stored in the label module is a second value, the corresponding processing unit does not execute the current instruction.

In the non-digital-to-analog conversion mode, the comparator also compares the identification data and the input reference signal, and then stores the output result of the comparator in the subsequent latch; when the comparison result stored in the label module is a first value, the corresponding processing unit executes the current instruction, and when the comparison result stored in the label module is a second value, the corresponding processing unit does not execute the current instruction.

The PE also designs a communication interface between adjacent PEs, such as the adjacent PE communication unit (Adjacent IF) in Figure 2, which can provide the current PE with information about the eight PEs surrounding the current PE. The above module units are connected together through a specially designed sense-storage-computation bus iSC bus. The analog signal can be a voltage or a current signal. In addition to the iSC bus, the PE also designs a global instruction bus INS bus to perform overall operation control on each functional module in the PE. Because the INS bus of each PE is controlled by the same global signal, storage-computation integration (SIMD) is achieved in this way.

In one embodiment, the original signal may come from the SU unit, or be written into the PE from outside the chip, such as the IO access in the figure, or the signal of the adjacent PE, which is transmitted to the PE bus through the adjacent IF. The SU, IO or adjacent IF transmits the sensing signal to the analog register AREG BANK or the AOP unit through the iSC bus. The AREG can be stored and calculated. The specific implementation method is described in detail below. The analog signal is converted into a digital signal and then stored in the DREGBANK, which can be digitally calculated and stored. The calculation result can be stored in the AREG or DREG of the PE, and then output to the outside of the chip through the iSC bus or other buses and transmission lines to realize a certain type of application function.

In one embodiment, it further includes: a DAC unit arranged outside the array structure, and the external DAC unit serves as a first control module.

In one embodiment, the sensing, storage and computing integrated macro unit circuit array is located on the same chip, and the external DAC is located inside or outside the chip.

In one embodiment, the sensing, storage and computing integrated macro unit circuit also includes: a second control module, which is used to initialize the digital storage and computing unit to 0; when the comparison result of the label module is that the analog signal is less than the reference analog signal, the digital signal stored in the digital storage and computing unit changes a value according to the encoding rule for each comparison until the analog signal is greater than or equal to the reference analog signal, and the digital storage and computing unit obtains a digital signal.

The following is further explained in conjunction with the sensing, storage and computing integrated macro unit circuit and its analog-to-digital conversion method.

6 , the analog-to-digital conversion method of the sensing-storage-computing integrated macro unit circuit in this embodiment includes the following steps:

The tag module reads the analog signal from the iSC bus;

The tag module compares the read analog signal with several reference analog signals;

Obtaining a corresponding digital signal according to the comparison result;

The plurality of reference analog signals are data that gradually increase or decrease along a functional relationship.

Among them, several reference analog signals are data that gradually increase or decrease along with a functional relationship.

In one embodiment, the reference analog signal gradually increases or decreases with the number according to a linear function, an exponential function, a logarithmic function, a power function or a trigonometric function relationship.

In one embodiment, the encoding rule of the digital signal is standard binary code, Gray code, Hamming code or Huffman code.

The present invention realizes the conversion from PE analog domain to digital domain, that is, converting the analog signal in PE into the corresponding digital signal. The following example converts the analog signal of AREG in PE, such as the current signal, into 3-bit precision. In actual use, 5-bit precision or even higher 8-bit digital signal can be used and stored in the digital memory DREG.

In this embodiment, the original signal can come from the SU unit, or be written into the PE outside the chip, or it can come from the analog register AREG BANK, or the AOP unit, and then sent to the iSC bus. The TAG unit receives the analog signal from the iSC bus, and thus can obtain the converted digital signal according to the size of the AREG analog current signal and the size of the voltage input at the negative input terminal, and then store it in the DREG BANK, and digital operations and storage can be performed. The operation result can be stored in the DREG of the PE, and then output to the outside of the chip through the iSC bus to realize a certain type of application function. In the analog-to-digital conversion step, the analog storage unit sends the analog signal to the iSC bus.

All the above data transmission and signal collection require INS command control. The INS bus connects the components in each PE. The INS can come from the system outside the chip, or it can be issued by the MCU module inside the chip, or the chip itself generates an INS for specific applications. The label module determines whether the current sensing, storage and computing macro unit circuit executes the instruction sent by the INS bus based on the stored identification data.

Specifically, in this embodiment, the storage current range of AREG is -8uA to 8uA, and the voltage output to the iSC bus will also change accordingly, from 0.2V to 0.9V.

Specifically, the output of the tag module is used as a judgment signal or an enable signal to control whether the current PE executes the global SIMD instruction. For a PE designed with a TAG module, when the TAG output state is "invalid", the current PE does not execute the current instruction. On the contrary, when the TAG output state is "valid", the current PE executes the current instruction. The signal that affects the TAG tag module comes from the operation process of the analog register, such as signal overflow after operation, and the value judgment of the digital signal "0" and "1", as well as other operation results. The TAG tag module design consists of a comparator circuit as shown in Figure 5 and a latch circuit. The comparator circuit is used to compare the signal on the iSC bus with the reference input signal, and then the output result of the comparator is stored in the latch behind. TAG controls the internal perception unit, analog storage unit, digital storage unit, and adjacent PE communication module of the PE, and controls the read and write operations or working states of the above unit circuits through the enable circuit. The control range of the TAG tag module is only the current PE. The chip restores the TAG to its initial state through the global TAG reset signal.

In one embodiment, the step is further included: the tag module determines whether the current sensing-storage-computing-in-one macro unit circuit executes the instruction sent by the INS bus based on the stored identification data.

In one embodiment, the steps are further included: in the digital-to-analog conversion mode, the comparator circuit is used to compare the analog signal with a plurality of reference analog signals, the latch is used to store the comparison result, when the comparison result stored in the label module is a first value, the corresponding processing unit executes the current instruction, and when the comparison result stored in the label module is a second value, the corresponding processing unit does not execute the current instruction.

In one embodiment, the steps are further included: in a non-digital-to-analog conversion mode, the comparator also compares the identification data and the input reference signal, and then stores the output result of the comparator in a subsequent latch; when the comparison result stored in the label module is a first value, the corresponding processing unit executes the current instruction, and when the comparison result stored in the label module is a second value, the corresponding processing unit does not execute the current instruction.

The specific D/A conversion mode and non-D/A conversion mode can be selected by connecting a multi-way selection switch at the reference signal input terminal of the comparator, for example, selecting to input the reference analog signal in the D/A conversion mode, and selecting to input the comparison reference signal with the identification data in the non-D/A conversion mode. In addition, a multi-way selection switch can be set at the positive input terminal of the comparator to select to read the analog signal from the iSC bus in the corresponding mode.

Because the main circuit of the TAG module is the comparator circuit, the characteristics of the TAG comparator are used to realize the ADC function in the PE, that is, to realize the mutual conversion of analog domain signals in the PE to digital domain signals. Specifically, the iSC bus is connected to the positive end of the comparator in the TAG. The negative end of the comparator in the TAG inputs the reference analog signal.

Specifically, the analog signal can be sent to the iSC bus by AREG or SU. The TAG includes a comparator circuit inside to compare the magnitude of the analog signal obtained from the iSC and the reference analog signal. As shown in FIG5 , the gate input voltage signal A of the MOS tube M171, the gate input voltage signal B of the MOS tube M172, and the drain of the MOS tube M172 are used as the output terminal. The comparator circuit is used to compare the magnitude of the two signals. When A is less than B, the output of the TAG will become 0, or the output terminal of the analog register AREG is input to the B terminal, and the reference analog signal voltage is input to the A terminal to determine whether the value of the AREG exceeds the given reference analog signal voltage. If it exceeds, it is 0, and if it is lower than the threshold, it becomes 1.

For example, in this embodiment, the DAC unit on the periphery of the PE array is connected to the negative end of the comparator in the TAG to provide a reference analog signal. According to Figures 8 and 9, the DAC module on the chip can be used to generate a ramp step voltage and output it to the negative end of the comparator. The output range is equivalent to the signal range stored in the AREG. The change of the ramp step output voltage is related to the quantization accuracy. For example, 8 step voltage values are required for a 3-bit quantization accuracy. This correspondence is a linear relationship, and the size of the code is linearly related to the quantized voltage.

In this embodiment, the coding rule of the digital signal is a standard binary code, and in other embodiments, it can also be based on Gray code, Hamming code or Huffman code, etc., all of which are within the scope of protection of the present invention. The reference analog signal gradually increases or decreases with the number of times according to a linear function, exponential function, logarithmic function, power function or trigonometric function relationship. In another embodiment of this invention, another nonlinear quantization method is used to adjust the output characteristics of the DAC to make it nonlinear output, such as a LOG curve, and corresponding to a linear digital code, which can achieve a quantization conversion method with a higher dynamic range, especially data conversion for optical imaging.

In one embodiment, as shown in FIG7 , the control process is controlled by instructions, the chip performs operations according to the instructions, and the entire PE array operates in a SIMD manner. The analog signal is converted into a digital signal, and the specific operation process and steps are as follows:

S10: The TAG unit is reset and the TAG value becomes "0".

S20: DREGs is initialized to 0, and DREG1, DREG2, and DREG3 are stored as initial values, such as 000.

S30: The TAG unit compares the analog signal with the reference analog signal.

The TAG unit receives an analog signal from the iSC bus, and the external DAC provides an analog reference signal, such as 0.2V, to the TAG unit.

S40: assign a TAG value according to the comparison result; if the TAG unit comparison analog signal is smaller than the reference analog signal, TAG=0, and execute step S50.

Otherwise, TAG=1, and execute step S60.

S50: DREGs changes a value according to the coding rules, for example, adds 1, and the corresponding values of the three bits DREG1, DREG2, and DREG3 change, and the external DAC provides an analog reference signal to the TAG unit that increases by a fixed value, for example, 0.1v, and the reference analog signal increases to 0.3v, and returns to execute step S30.

S60: DREGs are locked and a digital-to-analog conversion is completed.

Therefore, in steps S30 and S40, the loop is continued until one digital-to-analog conversion is completed.

The specific corresponding relationships are as follows:

If the analog signal is less than 0.2V, DREGs is set to 000;

When the analog signal is between 0.2V and 0.3V, DREG is set to 001;

When the analog signal is between 0.3V-0.3V, DREG is set to 010;

When the analog signal is between 0.4V and 0.5V, DREG is set to 011;

When the analog signal is between 0.5V and 0.6V, DREG is set to 100;

When the analog signal is between 0.6V and 0.7V, DREG is set to 101;

When the analog signal is between 0.7V and 0.8V, DREG is set to 110;

When the analog signal is between 0.8V and 0.9V, DREG is set to 111;

The counter function is realized by controlling multiple DREGs through global instructions. For example, 3-bit precision conversion requires 3 DREGs, DREG0/DREG1/DREG2. Let DREG0/DREG1/DREG2 change from "000" to "111". At the same time, each time the value changes, the negative input of the comparator corresponds to the voltage. When the voltage of the negative input of the comparator is equivalent to or greater than the iSC bus voltage, the comparator output in TAG changes from 0 to 1, and the TAG value becomes 1. At this time, the current PE will not respond to the global instruction, and the value in DREG0/DREG1/DREG2 will not be output. The current value is locked and no longer changes with INS control. The value at this time corresponds to the size of the analog signal. DREG locks the current value and no longer responds to the global DREG operation, that is, a digital-to-analog conversion is completed.

In another embodiment, as shown in the figure, the reference analog signal may be gradually increased with the number of times according to a logarithmic function relationship.

In another embodiment, referring to FIG10 , the encoding rule of the digital signal is to use Gray code. The use of Gray code can improve the quantization efficiency, because the change between natural number sequences involves multiple bits changing at the same time, which requires multiple instructions to achieve the corresponding numerical changes. If the Gray code method is used, only one bit needs to change between each number, that is, only one instruction is needed to achieve the change of the corresponding numerical sequence. The following figure shows the change of 3-bit sequence and 4-bit numerical sequence.

The specific corresponding relationships are as follows:

If the analog signal is less than 0.2V, DREG is set to 000;

When the analog signal is between 0.2V and 0.3V, DREG is set to 001;

When the analog signal is between 0.3V-0.3V, DREG is set to 011;

When the analog signal is between 0.4V and 0.5V, DREG is set to 010;

When the analog signal is between 0.5V and 0.6V, DREG is set to 110;

When the analog signal is between 0.6V and 0.7V, DREG is set to 111;

When the analog signal is between 0.7V and 0.8V, DREG is set to 101;

When the analog signal is between 0.8V and 0.9V, DREG is set to 100.

In another embodiment, 4-bit encoding may be used, that is, the accuracy of DREG is 4 bits.

The specific corresponding relationships are as follows:

If the analog signal is less than 0.2V, DREG is set to 0000;

When the analog signal is between 0.2V and 0.25V, DREG is set to 0001;

When the analog signal is between 0.25V and 0.3V, DREG is set to 0011;

When the analog signal is between 0.3V and 0.35V, DREG is set to 0010;

When the analog signal is between 0.35V and 0.4V, DREG is set to 0110;

When the analog signal is between 0.4V and 0.45V, DREG is set to 0111;

When the analog signal is between 0.45V and 0.5V, DREG is set to 0101;

When the analog signal is between 0.5V and 0.55V, DREG is set to 0100;

When the analog signal is between 0.55V and 0.6V, DREG is set to 1100;

When the analog signal is between 0.6V and 0.65V, DREG is set to 1101;

When the analog signal is between 0.65V and 0.7V, DREG is set to 1111;

When the analog signal is between 0.7V and 0.75V, DREG is set to 1010;

When the analog signal is between 0.75V and 0.8V, DREG is set to 1011;

When the analog signal is between 0.8V and 0.85V, DREG is set to 1001;

The analog signal is between 0.85V-0.9V, and DREG is set to 1000.

To convert conventional analog signals to digital signals, a special ADC chip or ADC circuit is needed to realize the conversion. For traditional image sensors, the early single ADC has developed to column-level ADC, and then to the latest pixel-level ADC design, but this requires advanced process requirements. Because of the ADC design size limitation and ADC frequency characteristic requirements, the traditional data handling process results in high processing delay and high power consumption.

Especially for the sensing storage chip, there are analog signal operation and storage units and digital signal operation and storage units in the PE. When the signal interacts or flows in the analog domain and the digital domain, it faces great problems. Either the ADC circuit is designed in the PE, but it brings problems of circuit area and power consumption. Or a single ADC circuit is used for serial conversion, which brings efficiency problems, data flow delay, and power consumption problems.

The present invention utilizes the quantized digital signal and stores it in DREGs, which can be used for digital domain calculations or as the final calculation result. The present invention provides a method for parallelizing analog domain to digital domain signal conversion in PE. This method does not require a dedicated ADC circuit, but uses the existing circuit of PE to realize the conversion function. This parallel conversion is equivalent to pixel-level or PE-level signal conversion, with high efficiency and high bandwidth, and is very suitable for visual signal processing and conversion. Output to the digital system of the chip post-stage, such as MCU.

By utilizing existing components in PE, such as comparators, analog signals such as Pixel signals and AREG current signals are converted into digital signals and stored in DREG in PE. This method realizes parallel analog domain to digital domain signal conversion without adding special conversion circuits. This method does not require a dedicated ADC circuit and utilizes the existing circuits of PE to realize the conversion function. This parallel conversion is equivalent to pixel-level signal conversion, with high efficiency and high bandwidth, and is very suitable for visual signal processing and conversion.

In line with the SIMD execution mode of the memory computing chip, this conversion method only circulates in the PE and does not need to be transmitted outside the PE. This reduces the flow of data and greatly reduces the delay and power consumption caused by data transportation.

The various embodiments of the mechanism disclosed in the present application can be implemented in hardware, software, firmware or a combination of these implementation methods. The embodiments of the present application can be implemented as a computer program or program code executed on a programmable system, which includes at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device and at least one output device.

Program code can be applied to input instructions to perform the functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner.

Program code can be implemented with high-level programming language or object-oriented programming language to communicate with the processing system. When necessary, program code can also be implemented with assembly language or machine language. In fact, the mechanism described in this application is not limited to the scope of any specific programming language. In either case, the language can be a compiled language or an interpreted language.

In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, instructions may be distributed over a network or through other computer-readable media. Therefore, machine-readable media may include any mechanism for storing or transmitting information in a machine (e.g., computer) readable form, including, but not limited to, floppy disks, optical disks, optical disks, read-only memories (CD-ROMs), magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, flash memory, or a tangible machine-readable memory for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) using the Internet in electrical, optical, acoustic, or other forms of propagation signals. Therefore, machine-readable media include any type of machine-readable media suitable for storing or transmitting electronic instructions or information in a machine (e.g., computer) readable form.

In the accompanying drawings, some structural or method features may be shown in a specific arrangement and/or order. However, it should be understood that such a specific arrangement and/or order may not be required. Instead, in some embodiments, these features may be arranged in a manner and/or order different from that shown in the illustrative drawings. In addition, the inclusion of structural or method features in a particular figure does not mean that such features are required in all embodiments, and in some embodiments, these features may not be included or may be combined with other features.

It should be noted that the units/modules mentioned in the various device embodiments of the present application are all logical units/modules. Physically, a logical unit/module can be a physical unit/module, or a part of a physical unit/module, or can be implemented as a combination of multiple physical units/modules. The physical implementation method of these logical units/modules themselves is not the most important. The combination of functions implemented by these logical units/modules is the key to solving the technical problems proposed by the present application. In addition, in order to highlight the innovative part of the present application, the above-mentioned device embodiments of the present application do not introduce units/modules that are not closely related to solving the technical problems proposed by the present application, which does not mean that there are no other units/modules in the above-mentioned device embodiments.

It should be noted that in the examples and description of this patent, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements.

Although the present application has been illustrated and described with reference to certain preferred embodiments thereof, it will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present application.

Claims (23)

1. An analog-to-digital conversion method of a sense and compute integrated macro-unit circuit is characterized by comprising the following steps:

the tag module reads the analog signal from iSC bus;

the tag module performs traversal comparison on the read analog signals and a plurality of reference analog signals;

Obtaining a corresponding digital signal according to the comparison result;

the plurality of reference analog signals are data which gradually increases or decreases with the functional relation;

The step of obtaining the corresponding digital signal according to the comparison result further comprises the steps of:

The initialization value of the digital memory unit is 0;

when the comparison result of the tag module is that the analog signal is smaller than the reference analog signal, the digital signal stored in the digital storage unit changes a numerical value according to the coding rule every 1 time when the comparison result is that the analog signal is smaller than the reference analog signal, the tag state changes until the analog signal is larger than or equal to the reference analog signal, and meanwhile the digital signal in the digital storage unit is locked.

2. The method of claim 1, wherein the reference analog signal gradually increases or decreases with time in accordance with a linear function, an exponential function, a logarithmic function, a power function, or a trigonometric function.

3. The method for analog-to-digital conversion of a sense and compute integrated macrocell circuit according to claim 1, wherein the coding rule of the digital signal is a standard binary code, a gray code, a hamming code, or a huffman code.

4. The method of analog-to-digital conversion of a sense all-in-one macrocell circuit according to claim 1, further comprising the step of the tag module determining whether the present sense all-in-one macrocell circuit executes an instruction transmitted by an INS bus based on the stored identification data.

5. The method of analog-to-digital conversion of a sense and compute integrated macrocell circuit according to claim 4, further comprising the step of the tag module being composed of a comparator circuit for comparing an analog signal with a plurality of reference analog signals and a latch circuit for storing a comparison result in a digital-to-analog conversion mode, the corresponding processing unit executing the current instruction when the comparison result stored in the tag module is a first value, and not executing the current instruction when the comparison result stored in the tag module is a second value.

6. The method of claim 5, wherein in the non-digital-to-analog conversion mode, the comparator further compares the identification data with the input reference signal and stores the output of the comparator in a subsequent latch, and wherein when the comparison result stored in the tag module is a first value, the corresponding processing unit executes the current instruction, and when the comparison result stored in the tag module is a second value, the corresponding processing unit does not execute the current instruction.

7. A method of analog to digital conversion of a sense and compute macrocell circuit according to claim 3, wherein the digital signal is a 3bit binary signal.

8. The method of analog-to-digital conversion of a sense all-in-one macrocell circuit according to claim 1, further comprising the step of transmitting a reference analog signal to a DAC unit external to the sense all-in-one macrocell circuit.

9. A sense and compute integrated macrocell circuit according to claim 1, comprising:

iSC buses used for connecting the modules, and transmitting sensing signals and operation signals between the modules;

an INS bus for connecting the modules;

the digital storage and calculation unit is used for simultaneously storing data and calculating data, wherein the data comprises digital signals;

The analog storage unit is used for simultaneously storing data and operating the data, wherein the data comprises analog signals;

The tag module is used for reading the analog signals from the iSC bus, and performing traversal comparison on the read analog signals and a plurality of reference analog signals;

The output module is used for obtaining a digital signal according to the comparison result;

the first control module is used for providing reference analog signals for the tag module, and the plurality of reference analog signals are data which gradually increase or decrease along with the functional relation.

10. The integrated macrocell circuit according to claim 9, wherein the reference analog signal is gradually increased or decreased with the number of times according to a linear function, an exponential function, a logarithmic function, a power function, or a trigonometric function.

11. The integrated sensing and computing macro-cell circuit of claim 9, wherein the coding module is configured to correspond the reference analog signal and the digital signal according to a coding rule, where the coding rule of the digital signal is a standard binary code, gray code, hamming code, or huffman code.

12. The integrated macro-cell circuit of claim 9, further comprising a second control module for initializing the digital memory cell to a value of 0;

When the comparison result of the tag module is that the analog signal is smaller than the reference analog signal, the digital signal stored by the digital storage unit changes a numerical value according to the coding rule every 1 time of comparison until the analog signal is larger than or equal to the reference analog signal.

13. The integrated macrocell circuit according to claim 9, wherein the analog memory cell, the digital memory cell, the iSC bus, the INS bus, and the tag module are integrated on the same chip.

14. The sense all-in-one macrocell circuit according to claim 9, wherein the tag module determines whether the sense all-in-one macrocell circuit executes an instruction transmitted by the INS bus based on the stored identification data.

15. The integrated macro-cell circuit of claim 14, wherein the tag module comprises a comparator circuit and a latch circuit, the comparator circuit is configured to compare the analog signal with a plurality of reference analog signals in the digital-to-analog conversion mode, the latch is configured to store the comparison result, the corresponding processing unit executes the current INS instruction when the comparison result stored in the tag module is a first value, and the corresponding processing unit does not execute the current INS instruction when the comparison result stored in the tag module is a second value.

16. The integrated macro-cell circuit of claim 15, wherein in the non-digital-to-analog conversion mode, the comparator further compares the identification data with the input reference signal and then stores the output of the comparator into a subsequent latch, and wherein when the comparison stored in the tag module is a first value, the corresponding processing unit executes the current INS instruction, and when the comparison stored in the tag module is a second value, the corresponding processing unit does not execute the current INS instruction.

17. The integrated macro-cell circuit according to claim 9, wherein the analog memory unit includes a plurality of analog signal memories, the analog signal memories are simultaneously used as the analog operation unit, and the analog signal memories of the analog memory unit are connected to the same iSC bus to perform the read-write operation, so that the analog signal directly performs the addition, subtraction, multiplication and division operations in the analog signal memories.

18. The integrated macrocell circuit according to claim 9, wherein the digital storage unit includes a plurality of digital signal memories having both storage and logic operation capabilities.

19. The integrated macro-cell circuit of claim 9, wherein the digital memory unit is provided with a DREG BANK, the DREG BANK includes a plurality of digital signal memories, a digital read bus iSC RD DBUS and a digital write bus iSC WR DBUS, the digital signal memories are digital registers DREG, a plurality of digital registers DREG are connected IN parallel between the digital read bus iSC RD DBUS and the digital write bus iSC WR DBUS, an input terminal IN of the digital registers DREG is connected to iSC WR DBUS, an output terminal OUT of the digital registers DREG is connected to the data read bus iSC RD DBUS, a multiplexer MUX is further connected between the digital read bus iSC RD DBUS and the digital write bus iSC WR DBUS, and a digital read bus iSC RD DBUS of the digital registers DREG is further connected to the iSC bus through a switch.

20. The integrated macro-cell circuit of claim 19, wherein the digital signal memory is implemented with 3T DRAM, or 6T DRAM, SRAM.

21. The integrated macro-cell circuit of claim 19, wherein the digital signal memory is implemented by Flash, and further comprising a plurality of Flash memories, a read-write control circuit, a digital read bus iSC RD DBUS, and a multiplexer MUX, wherein an input IN of the Flash memories is connected to the read-write control circuit, an output of the Flash is connected IN parallel to the digital read bus iSC RD DBUS, and the multiplexer MUX is connected between the digital read bus iSC RD DBUS and the read-write control circuit.

22. A sense all-in-one macrocell system including the sense all-in-one macrocell circuit according to any one of claims 9 to 21, comprising:

the plurality of sense and compute integrated macro-cell circuit layouts are in an array structure, wherein:

the sense and save integrated macro-unit circuit comprises:

iSC buses used for connecting the modules, and transmitting sensing signals and operation signals between the modules;

an INS bus for connecting the modules;

the digital storage and calculation unit is used for simultaneously storing data and calculating data, wherein the data comprises digital signals;

The analog storage unit is used for simultaneously storing data and operating the data, wherein the data comprises analog signals;

The tag module is used for reading the analog signals from the iSC bus, and performing traversal comparison on the read analog signals and a plurality of reference analog signals;

The output module is used for obtaining a digital signal according to the comparison result;

The first control module is used for providing reference analog signals for the tag module, and the plurality of reference analog signals are data with gradually increased or decreased function relations;

an external DAC cell is also included as a first control module.

23. The integrated macro-cell system of claim 22, wherein the integrated macro-cell circuit array is on the same chip,

The external DAC is located either on-chip or off-chip.