CN119400765B - Interface heat dissipation material preform, preparation method thereof and multi-chip packaging structure - Google Patents
Interface heat dissipation material preform, preparation method thereof and multi-chip packaging structureInfo
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- CN119400765B CN119400765B CN202411979194.4A CN202411979194A CN119400765B CN 119400765 B CN119400765 B CN 119400765B CN 202411979194 A CN202411979194 A CN 202411979194A CN 119400765 B CN119400765 B CN 119400765B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3732—Diamonds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
本申请提供一种界面散热材料预成型件、及其制备方法和多芯片封装结构。本申请提供的界面散热材料预成型件、及其制备方法和多芯片封装结构，通过在第二表面上形成多个芯片固定区域，且令多个芯片固定区域中的至少两个芯片固定区域的厚度不同，这样，即可使该界面散热材料预成型件能够同时支持至少两种不同厚度的芯片，能够适应不同的芯片需求，以简化封装过程，减少装配时间，提高生产灵活性，提高生成效率；此外，界面散热材料预成型件的标准化设计有助于确保每个多芯片封装的一致性和可重复性，可以降低生产过程中的变异性。
The present application provides an interface heat dissipation material preform, a preparation method thereof, and a multi-chip packaging structure. The interface heat dissipation material preform, a preparation method thereof, and a multi-chip packaging structure provided by the present application form multiple chip fixing areas on the second surface, and at least two of the multiple chip fixing areas have different thicknesses. In this way, the interface heat dissipation material preform can simultaneously support at least two chips of different thicknesses, adapting to different chip requirements, thereby simplifying the packaging process, reducing assembly time, improving production flexibility, and increasing production efficiency. In addition, the standardized design of the interface heat dissipation material preform helps ensure the consistency and repeatability of each multi-chip package, which can reduce variability in the production process.
Description
Technical Field
The application relates to the technical field of chip packaging, in particular to an interface heat dissipation material preformed piece, a preparation method thereof and a multi-chip packaging structure.
Background
In the multi-chip package, the heights of the chips are different according to different design requirements, so that the distances between the top of the chips and the bottom of the radiator are not uniform due to the change of the heights of the chips, and a plurality of pieces of interface heat radiation material preformed pieces are needed to be used for coping with a plurality of chips with different heights, so that the multi-chip package is realized. When multi-chip packaging is performed by using a plurality of interface heat dissipation material preformed pieces, multiple picking and placing processes exist, and the production period is long.
Disclosure of Invention
In view of the above, the present application provides an interface heat dissipation material preform, a method for manufacturing the same, and a multi-chip package structure for simultaneously packaging chips with different thicknesses by using a piece of interface heat dissipation material preform, so as to improve the efficiency of chip packaging and shorten the cycle of chip packaging.
Specifically, the application is realized by the following technical scheme:
The first aspect of the application provides an interface heat sink material preform for a multi-chip package structure comprising a plurality of chips comprising at least two chips of different thickness, the interface heat sink material preform having a first surface and a second surface disposed opposite each other, wherein,
The first surface is a plane and is used for bonding a heat dissipation cover in the multi-chip packaging structure;
And the total thickness of each chip fixing area and the chips to be fixed on the chip fixing areas is equal to a specified value, and the thicknesses of at least two chip fixing areas in the plurality of chip fixing areas are different so as to fix the chips with at least two different thicknesses simultaneously through the interface heat dissipation material preformed piece.
The second aspect of the application provides a preparation method of the interface heat dissipation material preform, which is used for preparing the interface heat dissipation material preform provided by the first aspect of the application, and comprises the following steps:
Preparing an interface heat dissipation material initial piece, wherein the interface heat dissipation material initial piece is provided with a first surface and a second surface which are arranged in a back-to-back way;
And forming a plurality of chip fixing regions on the second surface, wherein at least two chip fixing regions of the plurality of chip fixing regions have different thicknesses, and the total thickness of each chip fixing region and the chip to be fixed on the chip fixing region is equal to a specified value.
A third aspect of the present application provides a multi-chip package structure comprising a substrate, a plurality of chips, an interfacial heat sink material preform as provided in the first aspect of the present application, and a heat sink cap, wherein,
The plurality of chips are fixed on the substrate and comprise at least two chips with different thicknesses;
The interface heat dissipation material preformed piece is provided with a plurality of chip fixing areas matched with the chips, and is fixed on the chips in a manner that the chip fixing areas are opposite to the chips matched with the chip fixing areas;
The heat dissipation cover is fixed on the first surface of the interface heat dissipation material preformed piece in a mode that the cover surface covers the chips, and the downward protruding surrounding part of the heat dissipation cover is in contact with the substrate.
According to the interface heat dissipation material preformed piece, the preparation method thereof and the multi-chip packaging structure, the plurality of chip fixing areas are formed on the second surface, and the thicknesses of at least two chip fixing areas in the plurality of chip fixing areas are different, so that the interface heat dissipation material preformed piece can simultaneously support at least two chips with different thicknesses, different chip requirements can be met, the packaging process is simplified, the assembly time is shortened, the production flexibility is improved, the production efficiency is improved, and in addition, the standardized design of the interface heat dissipation material preformed piece is beneficial to ensuring the consistency and the repeatability of each multi-chip packaging, and the variability in the production process can be reduced.
Drawings
FIG. 1 is a schematic view of a first embodiment of an interfacial heat sink material preform provided by the present application;
FIG. 2 is a schematic illustration of a multi-chip package structure in which the interfacial heat spreader preform of FIG. 1 is located;
FIG. 3 is a schematic diagram of a second embodiment of an interfacial heat sink material preform provided by the present application;
FIG. 4 is a schematic illustration of a multi-chip package structure in which the interfacial heat spreader material preform of FIG. 3 is located;
FIG. 5 is a schematic view of a third embodiment of an interfacial heat sink material preform provided by the present application;
FIG. 6 is a bottom view of the multi-chip package structure of the interfacial heat sink material preform of FIG. 5;
FIG. 7 is a schematic diagram of a fourth embodiment of an interfacial heat sink material preform provided by the present application;
FIG. 8 is a schematic illustration of an interfacial heat sink material preform according to an exemplary embodiment of the present application;
FIG. 9 is a schematic diagram of a fifth embodiment of an interfacial heat sink material preform provided by the present application;
FIG. 10 is a flowchart of a first embodiment of a method for preparing an interfacial heat sink material preform according to the present application;
fig. 11 is a schematic diagram illustrating an implementation of preparing an interfacial heat sink material preform according to an exemplary embodiment of the present application.
Reference numerals illustrate:
11 a first surface;
A second surface;
121, a chip fixing area;
122, dividing part;
123 melting start control section.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the application. The term "if" as used herein may be interpreted as "at..once" or "when..once" or "in response to a determination", depending on the context.
Specific examples are given below to describe the technical solution of the present application in detail.
Fig. 1 is a schematic view of an interface heat sink material preform according to an embodiment of the present application. Fig. 2 is a schematic view of a multi-chip package structure in which the interfacial heat spreader material preform shown in fig. 1 is located. Referring to fig. 1 and 2, the present embodiment provides an interfacial heat dissipation material preform for a multi-chip package structure, the multi-chip package structure including a plurality of chips, the plurality of chips including at least two chips with different thicknesses, the interfacial heat dissipation material preform having a first surface 11 and a second surface 12 disposed opposite to each other,
The first surface 11 is a plane and is used for bonding a heat dissipation cover in the multi-chip packaging structure;
the second surface 12 is formed with a plurality of chip fixing regions 121 matching the plurality of chips, each chip fixing region 121 is used for fixing a chip matching the chip fixing region 121, the total thickness of each chip fixing region 121 and a chip to be fixed on the chip fixing region 121 is equal to a specified value, and the thicknesses of at least two chip fixing regions 121 in the plurality of chip fixing regions 121 are different to simultaneously fix the chips of the at least two different thicknesses through the interfacial heat dissipation material preform.
Specifically, the multi-chip package structure includes a plurality of chips, and the thickness of the plurality of chips may be different due to different designs, i.e., the plurality of chips include chips of at least two different thicknesses. For example, in the example shown in fig. 2, the multi-chip package structure includes three chips each having a different thickness, i.e., the multi-chip package structure includes three chips having different thicknesses.
Further, referring to fig. 1 and 2, the interface heat dissipation material preform provided in this embodiment has a first surface 11 and a second surface 12, where the first surface 11 and the second surface 12 are disposed opposite to each other, and the first surface 11 is a plane for bonding with a heat dissipation cover in a multi-chip package structure, and the second surface 12 is formed by a plurality of planes with different heights, and a plurality of uneven planes form a plurality of chip fixing areas 121. For example, in the example shown in fig. 1, the second plane 12 has three uneven planes that constitute three chip fixing regions 121.
The manner of bonding the first surface 11 and the heat dissipating cover is set according to actual needs, and is not limited in this embodiment. For example, the bonding between the first surface 11 and the heat dissipating cover may be thermal conductive adhesive bonding, welding, or the like. Further, the number of chip fixing regions 121 included on the second surface 12 matches the number of chips included in the multi-chip package structure, and each chip fixing region 121 is used for fixing the chip matched with the chip fixing region 121. If the sum of the thickness of one chip fixing region 121 and the thickness of one chip (i.e., the total thickness) is equal to a specified value, the chip fixing region 121 is matched with the chip.
Referring to fig. 2, in the example shown in fig. 2, the multi-chip package structure includes three chips, which are respectively referred to as a first chip, a second chip and a third chip in order from left to right for convenience of description. Further, referring to fig. 1 and 2, the interfacial heat dissipation material preform provided in the present embodiment includes three die-fixing regions 121, and for convenience of distinction, the three die-fixing regions 121 are respectively referred to as a first die-fixing region, a second die-fixing region, and a third die-fixing region.
Referring to fig. 2, the total thickness of the first chip and the first chip fixing region is equal to a designated value, the first chip and the first chip fixing region are matched, the first chip fixing region is used for fixing the first chip, the total thickness of the second chip and the second chip fixing region is equal to a designated value, the second chip and the second chip fixing region are matched, the second chip fixing region is used for fixing the second chip, the total thickness of the third chip and the third chip fixing region is equal to a designated value, the third chip and the third chip fixing region are matched, and the third chip fixing region is used for fixing the third chip. The interfacial heat sink material preform includes three die attach regions 121 of different thickness, capable of attaching three die of different thickness simultaneously.
The specified value is set according to actual needs, and in this embodiment, it is not limited.
Alternatively, in one possible implementation, the interfacial heat sink material preform may be made of any of indium, tin, silver, indium alloy, tin alloy, silver alloy, graphite, graphene, and composite materials.
Furthermore, in another possible implementation, the interfacial heat sink material preform is a preform with an external polymer coating or an external flux coating.
Specifically, the external polymer coating and the external soldering flux coating can provide additional mechanical strength and wear resistance for the interface heat dissipation material preform, prevent the interface heat dissipation material preform from being chemically corroded, ensure the heat dissipation performance of the interface heat dissipation material preform, and promote welding so that welding is firmer.
Alternatively, in one possible implementation, the thickness difference between any two die attach regions having different thicknesses is between 20 μm and 700 μm.
Or alternatively
The thickness difference between any two chip fixing areas with different thicknesses is less than or equal to 80% B, wherein B is the thickness value of the chip fixing area with the largest thickness among the plurality of chip fixing areas.
Specifically, referring to the above description, for example, in the example shown in fig. 1, the thickness of the first die-fixing region is 200 μm, the thickness of the second die-fixing region is 130 μm, the thickness of the third die-fixing region is 170 μm, and among the three die-fixing regions 121, the die-fixing region 121 having the largest thickness is the first die-fixing region having a thickness of 200 μm, i.e., B is equal to 200 μm, and 80% B is equal to 160 μm at this time. Further, the difference in thickness between the first chip fixing region and the second chip fixing region is 70 μm, the difference in thickness between the first chip fixing region and the third chip fixing region is 30 μm, and the difference in thickness between the second chip fixing region and the third chip fixing region is 40 μm. I.e., the difference in thickness between any two chip-fixing regions 121 having different thicknesses is 20 μm to 700 μm among the three chip-fixing regions 121, or the difference in thickness between any two chip-fixing regions 121 having different thicknesses is less than or equal to 80% b (160 μm).
Two specific examples are given below for the purpose of detailing the interfacial heat sink material preform provided by the present application.
Fig. 3 is a schematic diagram of a second embodiment of an interfacial heat spreader preform according to the present application, and fig. 4 is a schematic diagram of a multi-chip package structure in which the interfacial heat spreader preform shown in fig. 3 is located.
Referring to fig. 4, in the example shown in fig. 4, the multi-chip package structure includes three chips, which are respectively referred to as a first chip, a second chip, and a third chip in order from left to right for convenience of description. Further, referring to fig. 3 and 4, the interfacial heat dissipation material preform provided in the present embodiment includes three die-fixing regions 121, and for convenience of distinction, the three die-fixing regions 121 are respectively referred to as a first die-fixing region, a second die-fixing region, and a third die-fixing region.
Further, the total thickness of the first chip and the first chip fixing region is equal to a specified value, the first chip and the first chip fixing region are matched, the first chip fixing region is used for fixing the first chip, the total thickness of the second chip and the second chip fixing region is equal to a specified value, the second chip and the second chip fixing region are matched, the second chip fixing region is used for fixing the second chip, the total thickness of the third chip and the third chip fixing region is equal to a specified value, the third chip and the third chip fixing region are matched, and the third chip fixing region is used for fixing the third chip.
Referring to fig. 3 and 4, in the present embodiment, the thickness of the first chip and the thickness of the third chip are the same, and the thickness of the second chip is greater than the thickness of the first chip. Further, the thickness of the first chip fixing region is the same as that of the third chip fixing region, and the thickness of the second chip fixing region is smaller than that of the first chip fixing region.
In other words, the interfacial heat sink material preform includes two die attach regions 121 having different thicknesses, which enable two types of die having different thicknesses to be attached simultaneously.
Further, fig. 5 is a schematic diagram of a third embodiment of an interfacial heat sink material preform (fig. 5 is a bottom view of the interfacial heat sink material preform), and fig. 6 is a partial schematic diagram of a multi-chip package structure of the interfacial heat sink material preform shown in fig. 5. Referring to fig. 5 and 6, in the example shown in fig. 6, the multi-chip package structure includes four chips, namely, a chip a, a chip B, a chip C and a chip D, wherein the thickness of the chip a is the same as that of the chip D, and the thickness of the chip a, the thickness of the chip B and the thickness of the chip C are different, i.e., the multi-chip package structure includes three kinds of chips with different thicknesses.
Further, referring to fig. 5, the interface heat dissipation material preform provided in this embodiment includes four chip fixing regions 121, where the four chip fixing regions 121 are a chip fixing region a, a chip fixing region B, a chip fixing region C, and a chip fixing region D, respectively, and the thicknesses of the chip fixing region a and the chip fixing region D are the same, and the thicknesses of the chip fixing region a, the chip fixing region B, and the chip fixing region C are different.
Further, the total thickness of the chip A and the chip fixing area A is equal to a specified value, the chip A and the chip fixing area A are matched, the chip fixing area A is used for fixing the chip A, the total thickness of the chip B and the chip fixing area B is equal to a specified value, the chip B and the chip fixing area B are matched, the chip fixing area B is used for fixing the chip B, the total thickness of the chip C and the chip fixing area C is equal to a specified value, the chip C and the chip fixing area C are matched, the chip fixing area C is used for fixing the chip C, the total thickness of the chip D and the chip fixing area D is equal to a specified value, the chip D and the chip fixing area D are matched, and the chip fixing area D is used for fixing the chip D.
With reference to the foregoing description, it will be appreciated that the interfacial heat sink material preform includes four die attach regions 121 that are capable of attaching three types of die of different thicknesses simultaneously.
According to the interface heat dissipation material preformed piece, the plurality of chip fixing areas are formed on the second surface, and the thicknesses of at least two chip fixing areas in the plurality of chip fixing areas are different, so that the interface heat dissipation material preformed piece can simultaneously support at least two chips with different thicknesses, different chip requirements can be met, the packaging process is simplified, the assembly time is shortened, the production flexibility is improved, and the generation efficiency is improved; in addition, the standardized design of the interfacial heat sink material preform helps to ensure uniformity and repeatability of each multi-chip package, which can reduce variability in the manufacturing process.
Specifically, fig. 7 is a schematic diagram of a fourth embodiment of an interfacial heat dissipation material preform according to the present application, referring to fig. 7, on the basis of the foregoing embodiment, the interfacial heat dissipation material preform provided in the present application has a dividing portion 122 at the boundary between two adjacent die fixing areas, and the dividing portion 122 divides the two adjacent die fixing areas 121, so that in the reflow process, the melting start point of the interfacial heat dissipation material preform is controlled by the dividing portion 122, and the melted interfacial heat dissipation material is divided by the dividing portion 122, wherein the dividing portion 122 includes at least one dividing portion in the form of a groove, a sink, a through hole array, and a blind hole array.
Specifically, the junction between two adjacent chip fixing regions 121 has a dividing portion 122, where the dividing portion 122 includes at least one dividing portion of a groove, a countersink, a through hole array, and a blind hole array. Thus, in the reflow process, in addition to forming the melting start point around the outside of the interfacial heat sink material preform, the groove, the countersink, the through hole, or the blind hole, etc. can effectively guide the distribution of heat in the interfacial heat sink material preform, and further form the melting start point at the dividing portion 122 to simultaneously melt the interfacial heat sink material preform from the outside and the inside of the interfacial heat sink material preform, thereby accelerating the melting speed of the interfacial heat sink material preform.
Further, the dividing portion 122 may further divide the adjacent chip fixing region 121, so as to divide the melted interface heat dissipation material, ensure reasonable distribution during the reflow soldering process, and prevent the melted interface heat dissipation material from flowing into the chip.
Alternatively, fig. 8 provides a schematic view of an interfacial heat sink material preform according to an exemplary embodiment of the present application, and fig. 8 a to E illustrate different forms of dividing portions. Referring to fig. 8, it can be understood that the interfacial heat dissipation material preform shown in fig. 8 includes three die-fixing areas 121, and for convenience of distinction, the three die-fixing areas 121 are respectively designated as a first die-fixing area, a second die-fixing area, and a third die-fixing area in order from left to right, wherein the first die-fixing area and the second die-fixing area are two adjacent die-fixing areas, and the second die-fixing area and the third die-fixing area are two adjacent die-fixing areas.
Taking the first chip fixing region and the second chip fixing region as examples, the junction of two adjacent chip fixing regions may include a first boundary of the first chip fixing region near the second chip fixing region and/or a second boundary of the second chip fixing region near the first chip fixing region. Thus, the divider 122 may be disposed at the first boundary, and/or at the second boundary. For example, in a diagram a in fig. 8, for the first chip fixing region and the second chip fixing region, the dividing portion 122 is provided at a first boundary on the first chip fixing region. For another example, in the B diagram in fig. 8, for the first chip fixing region and the second chip fixing region, the dividing portion 122 is provided at the second boundary on the second chip fixing region. For another example, in the C diagram in fig. 8, for the first chip fixing region and the second chip fixing region, the dividing portion 122 is provided at both a first boundary on the first chip fixing region and a second boundary on the second chip fixing region.
The dividing portion 122 includes at least one of a groove, a countersink, an array of through holes, and an array of blind holes.
For example, in fig. 8, a, B, and E, each of the partitions 122 includes one form of partition. Further, for another example, in the C and D diagrams in fig. 8, each divided portion includes a plurality of forms of divided portions. For example, in fig. 8C, two types of dividing portions 122 are provided at the boundary between the first chip fixing region and the second chip fixing region and the boundary between the second chip fixing region and the third chip fixing region. In fig. 8D, for example, two types of dividing portions 122 are provided at the boundary between the first chip fixing region and the second chip fixing region, namely, a through hole array and a groove, and three types of dividing portions 122 are provided at the boundary between the second chip fixing region and the third chip fixing region, namely, a through hole array, a groove, and a sink.
Further, referring to fig. 8, in addition to fig. D and E, optionally, in one possible implementation manner, a length direction of the dividing portion 122 is parallel to an intersection line of the two adjacent chip fixing regions 121, or an included angle between the length direction of the dividing portion 122 and the intersection line of the two adjacent chip fixing regions 121 is smaller than 90 °.
With reference to the foregoing description, it will be understood that the dividing portion 1 at the boundary between two adjacent chip fixing regions 121 may be one of a groove, a countersink, a through hole array, and a blind hole array, or may be a combination of any two or more of a groove, a countersink, a through hole array, and a blind hole array, which is not limited in this embodiment. For example, in one embodiment, the dividing portion 122 is in the form of a groove, and in another embodiment, the dividing portion 122 is in the form of a combination of three types, namely a groove, a through hole array and a blind hole array.
Note that, when the dividing portion 122 is in the form of a through hole array or a blind hole array, the number of through holes or blind holes is set according to actual needs, and in this embodiment, the number of through holes or blind holes is not limited.
Alternatively, in one possible implementation, when the dividing portion 122 is a groove or an array of through holes, a width of the groove in an arrangement direction (a left-right direction shown in fig. 8) of the adjacent two chip fixing regions 121 or a diameter of each through hole in the array of through holes is greater than or equal to 20 μm and less than or equal to a pitch between the adjacent two chip fixing regions 121.
The distance between two adjacent chip fixing regions 121 refers to the distance between the positions where the two chip fixing regions 121 actually fix chips (the positions where the chips cover) in the arrangement direction.
In other words, when the dividing portion 122 is in the form of a groove, the width of the groove in the arrangement direction of the adjacent two chip fixing regions 121 is within the range of the spacing between 20 μm and the adjacent two chip fixing regions 121, i.e., the width of the groove is at least 20 μm and at most the spacing between the adjacent two chip fixing regions 121, and similarly, when the dividing portion 122 is in the form of a through-hole array, the diameter of each through-hole in the through-hole array is within the range of the spacing between 20 μm and the adjacent two chip fixing regions 121, i.e., the diameter of the through-hole is at least 20 μm and at most the spacing between the adjacent two chip fixing regions 121.
Alternatively, in another possible implementation manner, when the dividing portion 122 is a countersink or an array of blind holes, a width of the countersink along an arrangement direction of the adjacent two chip fixing regions 121 or a diameter of each blind hole in the array of blind holes is greater than or equal to 10 μm and less than or equal to 2 times a pitch between the adjacent two chip fixing regions 121.
Further, when the dividing portion 122 is in the form of a countersink, the width of the countersink in the arrangement direction of the adjacent two chip fixing regions 121 is within a range of 10 μm and 2 times the pitch between the adjacent two chip fixing regions 121, i.e., the width of the countersink is at least 10 μm and at most 2 times the pitch between the adjacent two chip fixing regions 121, and similarly, when the dividing portion 122 is in the form of a blind hole array, the diameter of each blind hole in the blind hole array is within a range of 10 μm and 2 times the pitch between the adjacent two chip fixing regions 121, i.e., the width of the countersink is at least 10 μm and at most 2 times the pitch between the adjacent two chip fixing regions 121.
Optionally, in another possible implementation, when the dividing portion 122 is a sink groove or an array of blind holes, the depth of the sink groove or the depth of each blind hole in the array of blind holes is 5%A to 95% a, where a is a thickness value of the interfacial heat dissipation material preform at a location of the sink groove or the array of blind holes.
Preferably, in an embodiment, the depth of the sink groove or the depth of each blind hole in the array of blind holes is between 30% a and 60% a.
Further, when the dividing portion 122 is in the form of a countersink or an array of blind holes, the depth of the blind holes in the countersink and the array of blind holes is within 5% to 95% of the thickness of the interfacial heat-dissipating material preform at the location of the countersink or the array of blind holes, i.e., the depth of the blind holes in the countersink and the array of blind holes is at least 5% of the thickness at the location of the countersink and the array of blind holes, and at most 95% of the thickness at the location of the countersink and the array of blind holes. The depth of the blind holes in the countersink and the blind hole array is preferably 30 to 60 percent of the thickness value at the position of the countersink and the blind hole array.
The interface heat dissipation material preform provided in this embodiment is provided by disposing a dividing portion at the junction of two adjacent chip fixing regions, and making the dividing portion divide the two adjacent chip fixing regions. Thus, in the first aspect, in addition to forming a melting start point around the outside of the interfacial heat sink material preform in the reflow process, a melting start point may be formed at a dividing position to melt the interfacial heat sink material preform simultaneously from the outside and the inside of the interfacial heat sink material preform, thereby accelerating the melting speed of the interfacial heat sink material preform, and in the second aspect, the dividing portion may divide the melted interfacial heat sink material, ensure a reasonable distribution thereof during the reflow process, and prevent the melted interfacial heat sink material from flowing into the chip.
Fig. 9 is a schematic diagram of a fifth embodiment of an interfacial heat dissipation material preform according to the present application, referring to fig. 9, in the above embodiment, each die attach area 121 of the interfacial heat dissipation material preform has a melting start point control portion 123 therein, so as to control a melting start point by the melting start point control portion 123 in a reflow process, wherein the melting start point control portion 123 includes at least one control portion in the form of a sink or a blind hole.
Further, as shown in fig. 9, each die attach region has a melting start point control portion 123 therein, and in the reflow process, the melting start point control portion 123 in the form of a sink or blind hole can control the melting start point in the die attach region 121. In this way, at the time of the reflow process, the die-fixing regions 121 can be simultaneously melted from the outside, the dividing portion 122 between the adjacent two die-fixing regions 121, and the melting start point control portion 123 inside each die-fixing region 121, and the melting speed of the interfacial heat-dissipating material preform can be increased.
Further, the form of the melting start point control portion 123 may be a countersink or a blind hole, and the form of the melting start point control portion 123 in each chip fixing area may be the same or different, and meanwhile, the size, depth, number and form of the melting start point control portion 123 in each chip fixing area are set according to actual needs, which is not limited in this embodiment. For example, in one embodiment, two melting start point control portions are provided in a die-attach area, wherein one melting start point control portion is in the form of a sink, and the other melting start point control portion is in the form of a blind hole.
According to the interface heat dissipation material preformed piece provided by the embodiment, the melting starting point control part is arranged in each chip fixing area in the interface heat dissipation material preformed piece, so that the melting starting point is controlled by the melting starting point control part in the reflow soldering process, and the interface heat dissipation material preformed piece can be melted from the outside, the dividing part between two adjacent chip fixing areas and the melting starting point control part in each chip fixing area at the same time, so that the melting speed of the interface heat dissipation material preformed piece is increased.
Corresponding to the embodiment of the interface heat dissipation material preformed piece, the application also provides a preparation method of the interface heat dissipation material preformed piece. Fig. 10 is a flowchart of a first embodiment of a method for preparing an interfacial heat sink material preform according to the present application. Referring to fig. 10, the method for preparing an interfacial heat dissipation material preform according to the present embodiment is used for preparing any interfacial heat dissipation material preform according to the first aspect of the present application, and the method for preparing includes:
S101, preparing an interface heat dissipation material initial piece, wherein the interface heat dissipation material initial piece is provided with a first surface and a second surface which are arranged in a back-to-back mode.
S102, forming a plurality of chip fixing areas on the second surface, wherein the thicknesses of at least two chip fixing areas in the plurality of chip fixing areas are different, and the total thickness of each chip fixing area and the chip to be fixed on the chip fixing area is equal to a specified value.
In particular implementations, for example, in one possible implementation, the plurality of die attach regions may be formed on the second surface by machining.
Alternatively, in one possible implementation, the second surface may be imprinted with a micro-imprint mold having a pattern matching the plurality of chip-securing regions to form a plurality of chip-securing regions on the second surface.
Optionally, in one possible implementation, the imprinting the second surface with a micro-imprint mold includes:
And heating the initial piece of the interface heat dissipation material in the imprinting process to soften the initial piece of the interface heat dissipation material, wherein the heating temperature is less than or equal to 85% C, and C is the melting temperature of the initial piece of the interface heat dissipation material.
Optionally, in one possible implementation manner, the heating the initial piece of the interface heat dissipation material during the embossing process includes:
An inert gas is used to create a protective environment during heating to prevent oxidation of the interfacial heat sink material precursor.
Specifically, fig. 11 is a schematic diagram illustrating an implementation of preparing an interfacial heat sink material preform according to an exemplary embodiment of the present application. Referring to fig. 11, the second surface may be imprinted with a micro-imprint mold having a pattern matching the plurality of chip-securing regions to form a plurality of chip-securing regions on the second surface.
Referring to fig. 11, the micro-embossing mold includes an upper mold and a lower mold, the lower mold has a pattern matching with a plurality of chip fixing areas, the upper mold contacts with a first surface of an interfacial heat dissipation material initial member during embossing, and the lower mold contacts with a second surface, so that a plurality of chip fixing areas meeting requirements can be embossed on the second surface. Further, referring to the foregoing description, while imprinting the second surface, the interfacial heat sink material precursor may be heated in an inert gas atmosphere to soften the interfacial heat sink material precursor and prevent oxidation thereof. Further, the temperature at which the initial piece of the interface heat sink material is heated needs to be less than or equal to 85% of the melting temperature of the initial piece of the interface heat sink material, i.e., the maximum heating temperature is 85% of the melting temperature of the initial piece of the interface heat sink material.
Alternatively, the micro-imprint mold may be a linear press mold or a roll mold, which is not limited in this embodiment.
The method provided by the embodiment provides a method for preparing the interface heat dissipation material preformed piece, through which the interface heat dissipation material preformed piece with different thicknesses can be prepared, so that chips with different thicknesses can be packaged through one piece of the interface heat dissipation material preformed piece at the same time, the efficiency of chip packaging is improved, and the cycle of chip packaging is shortened.
Optionally, after forming a plurality of chip fixing regions on the second surface, the preparation method further includes:
And forming a dividing part at the junction of the two adjacent chip fixing areas, wherein the dividing part divides the two adjacent chip fixing areas so as to control the melting starting point of the interface heat dissipation material preformed piece through the dividing part and divide the melted interface heat dissipation material through the dividing part in the reflow soldering process, and the dividing part comprises at least one of a groove, a sink groove, a through hole array and a blind hole array.
According to the preparation method of the interface heat dissipation material preformed piece, the dividing part is formed at the junction of the two adjacent chip fixing areas, so that in the reflow soldering process, the melting starting point of the interface heat dissipation material preformed piece is controlled by the dividing part to be melted simultaneously from the outside of the interface heat dissipation material preformed piece and the junction of the two adjacent chip fixing areas, the melting speed of the interface heat dissipation material preformed piece is increased, and further, the dividing part can divide the melted interface heat dissipation material to ensure reasonable distribution in the reflow soldering process and prevent the melted interface heat dissipation material from flowing into the chip.
Optionally, after forming a plurality of chip fixing regions on the second surface, the preparation method further includes:
a melting start point control part is formed inside each chip fixing region to control a melting start point by the melting start point control part in a reflow process, wherein the melting start point control part comprises at least one control part in the form of a sink or a blind hole.
In particular, the dividing portion or the melting start point control portion is formed by a micro-imprint mold or a cutting mold.
With continued reference to fig. 1 and 3, the present application further provides a multi-chip package structure, which includes a substrate, a plurality of chips, an interface heat dissipation material preform as provided in the first aspect of the present application, and a heat dissipation cap, wherein,
The plurality of chips are fixed on the substrate and comprise at least two chips with different thicknesses;
The interface heat dissipation material preformed piece is provided with a plurality of chip fixing areas matched with the chips, and is fixed on the chips in a manner that the chip fixing areas are opposite to the chips matched with the chip fixing areas;
The heat dissipation cover is fixed on the first surface of the interface heat dissipation material preformed piece in a mode that the cover surface covers the chips, and the downward protruding surrounding part of the heat dissipation cover is in contact with the substrate.
The multi-chip packaging structure provided by the embodiment can package a plurality of chips with different thicknesses according to different design requirements, so that the picking and placing processes of chip packaging are reduced, the packaging efficiency can be improved, and the production period is shortened.
The application also provides a use of the interfacial heat sink material preform as provided in the first aspect of the application for the field of multi-chip packaging.
The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather to enable any modification, equivalent replacement, improvement or the like to be made within the spirit and principles of the application.
Claims (14)
1. An interface heat sink material preform for a multi-chip package structure comprising a plurality of chips comprising at least two chips of different thickness, the interface heat sink material preform having a first surface and a second surface disposed opposite each other, wherein,
The first surface is a plane and is used for bonding a heat dissipation cover in the multi-chip packaging structure;
A plurality of chip fixing areas matched with the chips are formed on the second surface, each chip fixing area is used for fixing the chip matched with the chip fixing area, the total thickness of each chip fixing area and the chip to be fixed on the chip fixing area is equal to a specified value, and the thicknesses of at least two chip fixing areas in the chip fixing areas are different, so that the chips with at least two different thicknesses are simultaneously fixed through the interface heat dissipation material preformed piece;
The interface heat dissipation material forming device comprises a plurality of chip fixing areas, a plurality of interface heat dissipation material preformed pieces, a plurality of through holes and a plurality of blind holes, wherein the junction of the two adjacent chip fixing areas is provided with a dividing part which divides the two adjacent chip fixing areas so as to control the melting starting point of the interface heat dissipation material preformed pieces and divide the melted interface heat dissipation material through the dividing part in a reflow soldering process;
A melting start point control part is arranged in each chip fixing area so as to control a melting start point through the melting start point control part in a reflow soldering process, wherein the melting start point control part comprises at least one control part in the form of a sink or a blind hole;
when the dividing portion is a groove or a through hole array, a width of the groove in an arrangement direction of the two adjacent chip fixing regions or a diameter of each through hole in the through hole array is greater than or equal to 20 μm and less than or equal to a pitch between the two adjacent chip fixing regions;
When the dividing portion is a blind hole array, the diameter of each blind hole in the blind hole array is larger than or equal to 10 μm and smaller than or equal to 2 times of the spacing between the adjacent two chip fixing areas.
2. The interfacial heat sink material preform as claimed in claim 1, wherein when said dividing portion is an array of blind holes, the depth of each blind hole in said array of blind holes is 5%A to 95% a, wherein said a is the thickness value of said interfacial heat sink material preform at the location of said array of blind holes.
3. The interfacial heat sink material preform as claimed in claim 1, wherein the depth of each blind hole in said array of blind holes is between 30% A and 60% A, wherein A is the thickness value of said interfacial heat sink material preform at the location of said array of blind holes.
4. The interfacial heat sink material preform of claim 1, wherein the length direction of said dividing portion is parallel to the boundary line of said two adjacent die-holding regions, or wherein the angle of the length direction of said dividing portion to the boundary line of said two adjacent die-holding regions is less than 90 °.
5. The interfacial heat sink material preform as defined in claim 1, wherein said interfacial heat sink material preform is made from any one of indium, tin, silver, indium alloy, tin alloy, silver alloy, graphite, graphene, and composite materials.
6. The interfacial heat sink material preform of claim 1, wherein the interfacial heat sink material preform is a preform with an external polymer coating or an external flux coating.
7. The interfacial heat sink material preform of claim 1, wherein the thickness difference between any two die-attach regions having different thicknesses is between 20 μm and 700 μm;
Or alternatively
The thickness difference between any two chip fixing areas with different thicknesses is less than or equal to 80% B, wherein B is the thickness value of the chip fixing area with the largest thickness among the plurality of chip fixing areas.
8. A method for preparing an interfacial heat sink material preform, wherein the method is used for preparing an interfacial heat sink material preform as defined in any one of claims 1 to 7, and the method comprises:
Preparing an interface heat dissipation material initial piece, wherein the interface heat dissipation material initial piece is provided with a first surface and a second surface which are arranged in a back-to-back way;
Forming a plurality of chip fixing regions on the second surface, wherein at least two chip fixing regions of the plurality of chip fixing regions have different thicknesses, and a total thickness of each chip fixing region and a chip to be fixed on the chip fixing region is equal to a specified value;
after forming the plurality of chip fixing regions on the second surface, the manufacturing method further includes:
Forming a dividing part at the junction of two adjacent chip fixing areas, wherein the dividing part divides the two adjacent chip fixing areas so as to control the melting starting point of the interface heat dissipation material preformed piece through the dividing part and divide the melted interface heat dissipation material through the dividing part in the reflow soldering process;
forming a melting start point control part inside each chip fixing region to control a melting start point by the melting start point control part in a reflow process, wherein the melting start point control part comprises at least one control part in the form of a sink or a blind hole;
when the dividing portion is a groove or a through hole array, a width of the groove in an arrangement direction of the two adjacent chip fixing regions or a diameter of each through hole in the through hole array is greater than or equal to 20 μm and less than or equal to a pitch between the two adjacent chip fixing regions;
When the dividing portion is a blind hole array, the diameter of each blind hole in the blind hole array is larger than or equal to 10 μm and smaller than or equal to 2 times of the spacing between the adjacent two chip fixing areas.
9. The method of manufacturing according to claim 8, wherein the forming a plurality of chip attach regions on the second surface comprises:
and imprinting the second surface with a micro-imprint mold having a pattern matching the plurality of chip-securing regions to form a plurality of chip-securing regions on the second surface.
10. The method of preparing according to claim 9, wherein the imprinting the second surface with a micro-imprint mold comprises:
And heating the initial piece of the interface heat dissipation material in the imprinting process to soften the initial piece of the interface heat dissipation material, wherein the heating temperature is less than or equal to 85% C, and C is the melting temperature of the initial piece of the interface heat dissipation material.
11. The method of manufacturing according to claim 10, wherein heating the initial piece of interfacial heat sink material during imprinting comprises:
An inert gas is used to create a protective environment during heating to prevent oxidation of the interfacial heat sink material precursor.
12. The manufacturing method according to claim 8, wherein the dividing portion or the melting start point control portion is formed by a micro-imprint mold or a cutting mold.
13. A multi-chip package structure, comprising a substrate, a plurality of chips, an interfacial heat sink material preform as defined in any one of claims 1-7, and a heat sink cap, wherein,
The plurality of chips are fixed on the substrate and comprise at least two chips with different thicknesses;
The interface heat dissipation material preformed piece is provided with a plurality of chip fixing areas matched with the chips, and is fixed on the chips in a manner that the chip fixing areas are opposite to the chips matched with the chip fixing areas;
The heat dissipation cover is fixed on the first surface of the interface heat dissipation material preformed piece in a mode that the cover surface covers the chips, and the downward protruding surrounding part of the heat dissipation cover is in contact with the substrate.
14. Use of an interfacial heat sink material preform as defined in any one of claims 1-7, wherein said interfacial heat sink material preform is used in the field of multichip packaging.
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| JP2006332126A (en) * | 2005-05-23 | 2006-12-07 | Hitachi Kokusai Electric Inc | Heat dissipation structure |
| CN116435267A (en) * | 2023-04-10 | 2023-07-14 | 宁波施捷电子有限公司 | Semiconductor packaging structure and packaging method |
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| JP2001267485A (en) * | 2000-03-17 | 2001-09-28 | Hitachi Ltd | Multi-chip module |
| JP2002088171A (en) * | 2000-09-13 | 2002-03-27 | Polymatech Co Ltd | Thermal conductive sheet, method for manufacturing the same, and heat dissipation device |
| JP5799565B2 (en) * | 2011-04-22 | 2015-10-28 | 株式会社ソシオネクスト | Semiconductor device and manufacturing method thereof |
| US9576930B2 (en) * | 2013-11-08 | 2017-02-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Thermally conductive structure for heat dissipation in semiconductor packages |
| CN111900142B (en) * | 2020-09-04 | 2024-12-06 | 星科金朋半导体（江阴）有限公司 | A chip packaging structure and packaging method thereof |
| CN118800739A (en) * | 2024-07-01 | 2024-10-18 | 展讯通信（上海）有限公司 | Chip packaging and manufacturing method thereof, circuit board |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006332126A (en) * | 2005-05-23 | 2006-12-07 | Hitachi Kokusai Electric Inc | Heat dissipation structure |
| CN116435267A (en) * | 2023-04-10 | 2023-07-14 | 宁波施捷电子有限公司 | Semiconductor packaging structure and packaging method |
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