CN119361435A - A FCBGA packaging substrate and manufacturing method thereof - Google Patents

Abstract

The present invention discloses an FCBGA package substrate and a manufacturing method thereof, the method comprising: providing two core boards, making interconnected inner-layer circuits on the first and second surfaces of each core board relative to each other; temporarily bonding the first surfaces of the two core boards together, the two bonded core boards being symmetrical with the first surface as the central axis; wiring the second surfaces of the two bonded core boards to form a first redistribution structure on the second surface of each core board, the dielectric layer of each first redistribution structure being an ABF film; debonding the two bonded core boards, and covering each first redistribution structure with protective glue; wiring the first surfaces of each core board respectively to form a second redistribution structure on the first surface of each core board, the dielectric layer of each second redistribution structure being a PI film; separating the protective glue from the first redistribution structure. The method has simple steps, high efficiency, good yield, and low cost, and can manufacture a package substrate that can better realize the connection between a chip and a PCB.

Description

FCBGA packaging substrate and manufacturing method thereof

Technical Field

The invention relates to the technical field of advanced packaging of semiconductors, in particular to an FCBGA packaging substrate and a manufacturing method thereof.

Background

"Moore's law" (Moore) is slow to develop and the difficulty of improving the computational power of chips by means of conventional methods is increased. The difficulty of process development is continually increasing as the physical limits are increasingly approached. This has forced the search for More cost-effective technology routes to meet the increasing demands of the industry for chip performance, with the "over-the-mole" (More than mole) approach represented by the chip technology being a powerful candidate.

Chiplet is a design concept of a chip, and it is critical to see whether packaging technology can be supported or not to assemble individual core grains together. In order to interconnect different die, a piece of silicon interposer (Silicon Interposer) with higher fine pitch I/O density is added between the lower PCB and the upper die. However Silicon Interposer itself is very expensive and the product area increases and the yield decreases resulting in further increases in production costs. In addition, the manufacturing steps of the package substrate in the related art are complex, and the yield efficiency is limited.

Disclosure of Invention

The present invention aims to solve at least to some extent one of the technical problems in the above-described technology. Therefore, the invention aims to provide the FCBGA packaging substrate and the manufacturing method thereof, wherein the manufacturing method of the FCBGA packaging substrate has the advantages of simple steps, high efficiency, good yield and low cost, and can manufacture the packaging substrate capable of better realizing the connection between the chip and the PCB.

In order to achieve the above object, a first aspect of the present invention provides a method for manufacturing an FCBGA package substrate, comprising the steps of:

providing two core boards, and manufacturing an interconnected inner-layer circuit on a first surface and a second surface which are opposite to each other;

temporarily bonding the first surfaces of the two core plates together, wherein the two core plates after bonding are symmetrical by taking the first surfaces as central axes;

wiring the second surfaces of the two core boards after bonding to form first rerouting structures electrically connected with the inner layer circuits of the core boards on the second surfaces of the core boards, wherein a dielectric layer of each first rerouting structure is an ABF film;

de-bonding the two core boards bonded together, and covering the first rewiring structures with protective glue;

Wiring the first surface of each core board respectively to form a second re-wiring structure electrically connected with the inner layer circuit of each core board on the first surface of each core board, wherein a dielectric layer of each second re-wiring structure is a PI film;

And separating the protective glue from the first rerouting structure.

According to the manufacturing method of the FCBGA packaging substrate, the first surfaces (tops) of the two core boards are bonded with each other, then the two second surfaces (bottoms) of the two core boards are manufactured, then the two core boards are unbonded, and finally the single core board is manufactured into the first surface of the two core boards, so that the manufacturing method of the whole FCBGA packaging substrate is simple in steps, high in efficiency (the two core boards with low requirements on the bottoms can be manufactured synchronously), good in yield (the two core boards can be temporarily bonded to prevent warping), low in cost, in addition, the second redistribution structure at the tops is formed by adopting PI film build-up for connecting chips, finer circuits can be manufactured, better copper thickness uniformity can be achieved, the first redistribution structure at the bottoms is formed by adopting ABF film build-up for connecting with a PCB, and the requirements on line width spacing can be met well, and the asymmetric packaging structure formed in this way replaces expensive Silicon Interposer to realize electrical vertical interconnection of core particles and the PCB.

In addition, according to the manufacturing method of the FCBGA package substrate provided by the invention, the manufacturing method further has the following additional technical characteristics:

Optionally, a first solder mask layer is fabricated on each of the first redistribution structures, and a surface treatment is performed on the first solder mask layer for implanting solder balls, a second solder mask layer is fabricated on each of the second redistribution structures, and a window is opened on the second solder mask layer and plated to fabricate plated pillars connecting the second redistribution structures, the plated pillars being adapted for bonding micro bumps of a connection chip.

Optionally, wiring is performed on each of the second surfaces of the two bonded core boards simultaneously.

Optionally, the core plate is a glass core plate, a ceramic core plate or an organic core plate.

Further, the step of fabricating an interconnect inner layer of circuitry on the opposed first and second surfaces of the glass core panel includes:

fabricating a glass through hole on the glass core plate to form one or more TGV holes;

filling conductive materials in the TGV holes to form conductive through holes;

and manufacturing the inner layer circuits on the first surface and the second surface, wherein the inner layer circuits on the first surface and the inner layer circuits on the second surface are electrically interconnected through the conductive through holes.

And further, carrying out laser induction and deep etching on the glass core plate to manufacture the glass through hole.

Further, the step of filling the TGV holes with a conductive material includes:

forming a seed layer on the first surface, the second surface and the inner wall of the TGV cell;

Forming a conductive layer on the surface of the seed layer, wherein the conductive layer fills the TGV holes and covers the seed layer on the first surface and the second surface;

the conductive layers on the first surface and the second surface are thinned.

Further, the step of fabricating the inner layer wiring on both the first surface and the second surface includes:

forming a resist layer on each thinned conductive layer;

patterning the resist layer to form an inner layer wiring pattern penetrating the resist layer;

Forming the inner layer circuit on the inner layer circuit pattern by adopting an electroplating process;

And removing the resist layer, and etching away the conductive layer and the seed layer exposed after the resist layer is removed.

Optionally, the first re-wiring structure is provided with one or more first metal wiring layers, the second re-wiring structure is provided with one or more second metal wiring layers, the line width spacing of the second metal wiring layers is less than or equal to 2/2 mu m, and the disc diameter is less than or equal to 10 mu m.

In order to achieve the above object, a second aspect of the present invention provides an FCBGA package substrate manufactured by the above manufacturing method, where the FCBGA package substrate includes:

A glass core plate having opposed first and second surfaces;

one or more conductive vias extending through the glass core plate and exposed to the first surface and the second surface;

Two inner layer lines formed on the first surface and the second surface in one-to-one correspondence and electrically connected with the conductive through holes;

the first rewiring structure is formed on the second surface and is electrically connected with the inner-layer circuit on the second surface, and the dielectric layer of the first rewiring structure is an ABF film;

the second redistribution structure is formed on the first surface and is electrically connected with the inner-layer circuit on the first surface, and a dielectric layer of the second redistribution structure is a PI film;

The first solder mask layer is formed on the first rewiring structure and exposes an outer layer bonding pad of the first rewiring structure;

And a second solder resist layer formed on the second redistribution structure and having a plating post electrically connected to the second redistribution structure.

Drawings

FIG. 1 is a process flow diagram of a method for fabricating a FCBGA package substrate in accordance with an embodiment of the present invention;

FIGS. 2-6 are schematic cross-sectional views of intermediate structures of steps in a method for fabricating a FCBGA package substrate in accordance with one embodiment of the present invention;

FIG. 7 is a schematic diagram of a FCBGA package substrate in accordance with one embodiment of the present invention;

FIGS. 8-15 are schematic cross-sectional views of intermediate structures of steps in the fabrication of inner layer wires of a core in accordance with embodiments of the present invention;

FIGS. 16-22 are schematic cross-sectional views of intermediate structures of various steps in the fabrication of a first re-wiring structure in accordance with embodiments of the present invention;

FIGS. 23-30 are schematic cross-sectional views of intermediate structures at various steps in the fabrication of a second redistribution structure in accordance with embodiments of the present invention;

FIGS. 31-35 are schematic cross-sectional views of intermediate structures of various steps of a solder mask process in accordance with embodiments of the present invention;

description of the reference numerals:

A glass core plate 100, a first surface 100a, a second surface 100b, TGV aperture 110;

an inner layer wiring 200;

a conductive material 300, a seed layer 310, a conductive layer 320;

a first rewiring structure 400;

a second rewiring structure 500;

A first solder resist layer 600;

A second solder mask 700, and plated pillars 710.

Detailed Description

Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.

In order that the above-described aspects may be better understood, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

Referring to fig. 1 to 35, an embodiment of the present application provides a technology for manufacturing an FCBGA package substrate, which has an asymmetric structure, wherein the top is used for connecting a core particle, and the bottom is used for connecting a PCB board, so as to realize electrical vertical interconnection between the core particle and the PCB board.

Referring to fig. 1, the method for manufacturing the FCBGA package substrate is shown as a process flow chart of the manufacturing method, and includes the following steps:

s1, providing two core boards, and manufacturing an interconnected inner-layer circuit on a first surface and a second surface which are opposite to each other of the core boards;

s2, temporarily bonding the first surfaces of the two core plates together, wherein the two bonded core plates are symmetrical by taking the first surfaces as central axes;

S3, wiring the second surfaces of the two core boards after bonding to form first rerouting structures electrically connected with the inner layer circuits of the core boards on the second surfaces of the core boards, wherein a dielectric layer of each first rerouting structure is an ABF film;

s4, performing de-bonding on the two core boards bonded together, and covering protection glue on each first rewiring structure;

s5, wiring the first surface of each core board respectively to form second re-wiring structures electrically connected with the inner layer circuits of the core boards on the first surface of each core board, wherein the dielectric layers of each second re-wiring structures are PI films;

And S6, separating the protective glue from the first rewiring structure.

The manufacturing method of the FCBGA packaging substrate is simple in steps, high in efficiency (the two core plates can be synchronously manufactured in the low-bottom-requirement re-wiring structure), good in yield (the two core plates can be temporarily bonded to prevent warping), low in cost, in addition, the second re-wiring structure at the top adopts PI film build-up layers for connecting chips, finer circuits can be manufactured, better copper thickness uniformity is achieved, the first re-wiring structure at the bottom adopts ABF film build-up layers for connection with a PCB, the requirement of line width spacing can be well met, and the formed asymmetric packaging structure replaces expensive Silicon Interposer to achieve electrical vertical interconnection of core particles and the PCB.

That is, the method adopts the manufacturing process of an asymmetric packaging structure, the top of the core plate adopts PID/PSPI as a dielectric layer, and the method can be used for connecting chips to manufacture finer circuits and has better copper thickness uniformity. The bottom of the core plate adopts an ABF film lamination, and the surface is connected with the PCB, so that the requirement of line width and distance can be well met. The manufacturing process is simple, firstly, the tops of the two core plates are mutually bonded (the two core plates are piled and weighed by taking the first surface as a central axis, the warping problem can be prevented), then, two-sided ABF layering is carried out (the two core plates can be simultaneously subjected to ABF layering, namely, the bonded two core plates are subjected to one-time double-sided manufacturing, so that the efficiency is improved), then, the two core plates are de-bonded, and finally, the single substrate is subjected to PID layering manufacturing (the fineness of a top circuit is ensured). The manufacturing method has the advantages of simple steps, high efficiency, good yield and low cost, and the FCBGA packaging substrate replaces an expensive Silicon Interposer technology to realize the connection of the chip and the PCB, and is not limited by technical bottlenecks.

Specifically, please refer to fig. 2-6, which illustrate schematic cross-sectional views of intermediate structures of steps in the method for manufacturing the FCBGA package substrate.

The manufacturing method of the FCBGA packaging substrate comprises the following steps:

As shown in fig. 2, two core plates 100 are provided. Wherein the core 100 may be a glass, ceramic or organic substrate. In this embodiment, a glass core is taken as an example.

By way of example, the glass core sheet 100 has a thickness of 0.2mm to 1.6mm and the glass core sheet 100 has dimensions greater than 70X 70mm. The glass core plate has high heat resistance, extremely low Df (Dissipation factor) and high Young's modulus. The breadth is not limited, the cost is low, the mechanical stability is strong, and the high-frequency electric performance is excellent.

Thereafter, an interconnect inner layer wire 200 is fabricated on the first surface 100a and the second surface 100b of each core board 100 opposite thereto, as shown in particular with reference to fig. 8 to 15.

First, as shown in fig. 9, glass through holes are made on a glass core plate 100 to form one or more TGV holes 110. Wherein the TGV holes 110 are obtained by performing laser induction and deep etching on the glass core plate 100, and the aperture of the TGV holes 110 is >10 μm. The laser induction is to use pulse laser to act on glass to generate continuous deformation area, compared with glass in undenatured area, the etching rate of the modified glass in hydrofluoric acid system or alkaline system is faster, based on which through holes and blind holes can be made on the glass. Specifically, a denatured area is generated on glass by using one of nanosecond laser, picosecond laser and femtosecond laser, and then the glass after laser treatment is put into hydrofluoric acid solution or alkaline solution for etching. And obtaining the glass through holes and blind holes with high uniformity. The technology has the advantages of uniform pore-forming quality, good consistency, no crack, high pore-forming speed and adjustable morphology, and the perpendicularity and morphology of the through hole can be controlled by adjusting laser parameters due to anisotropism of etching.

Next, as shown in fig. 10-12, a conductive material 300 is filled in the TGV holes 110 to form conductive vias. That is, the glass via is metallized using a metal plating or deposition process to form a conductive via.

As an example, the step of filling the conductive material 300 in the TGV holes 110 includes forming a seed layer 310 on the first surface 100a, the second surface 100b and the inner wall of the TGV holes 110 as shown in fig. 10. That is, the seed layer 310 is formed inside the glass through hole and on the surface of the glass core plate 100. The seed layer 310 may be formed by metal sintering, polymer (Polymer) + copper, PVD (Physical Vapor Deposition) sputtering, or the like, and PVD is taken as an example in this embodiment. The glass core plate 100 completed with the glass through hole is subjected to double-sided PVD seed layer sputtering. The surface of the material is gasified into gaseous atoms or molecules or partially ionized into ions by a physical method under vacuum conditions, and a Ti/Cu layer (seed layer) is deposited on the surface of the substrate by plasma. Wherein the thickness of the copper layer is larger than that of the titanium layer, the thickness of the titanium layer is more than 50nm, and the thickness deviation is less than 5%. The vacuum coating equipment is one of a vacuum evaporation coating machine, a vacuum sputtering coating machine or a vacuum ion coating machine, and the deposition method is one of vacuum evaporation coating, sputtering coating, arc plasma coating, ion coating, molecular beam epitaxy and the like. The process may include degassing, plasma etching, sputtering titanium, sputtering copper. The degassing temperature is 60-150 ℃, the time is 30-3000s, the gas used in the plasma etching is one or more of oxygen, carbon tetrafluoride and argon, the power is 500-5000w, and the treatment time is 1-8min. Subsequently, as shown in fig. 11, a conductive layer 320 is formed on the surface of the seed layer 310, the conductive layer 320 filling the TGV holes 110 and covering the seed layer 310 on the first surface 100a and the second surface 100 b. The conductive layer 320 may be formed by electroplating, filling holes with metal conductive paste, and the like. In this embodiment, the conductive layer 320 is formed to fill the TGV holes 110 and cover the first surface 100a and the second surface 100b when electroplating to fill the holes. The plating solution contains an accelerator, an inhibitor, a leveler, a sulfuric acid solution, and the like. Wherein the conductive layer 320 may be a copper layer having a certain thickness. In other examples, the seed layer and the conductive layer may also be other suitable conductive materials, such as tin, nickel, and the like. Next, as shown in fig. 12, the conductive layer 320 on the first surface 100a and the second surface 100b is thinned. Specifically, after the electroplating is finished, the copper thickness is thinned by adopting a CMP (CHEMICAL MECHANICAL Polishing) chemical mechanical Polishing mode or chemical liquid, and the thinned copper thickness is smaller than 15 mu m. CMP can planarize the surface more by organically combining the physical grinding action of nano-sized particles with the chemical etching action of the polishing liquid. This step is performed using a CMP process and polishing is performed using a polishing machine suitable for board-level carrier processing, and the process of plating, adding polishing liquid, mechanical polishing, and thickness monitoring is repeated multiple times until the excess copper plating is completely removed. The final copper thickness was <15 μm. And ensures the surface level of the core plate without protruding points or grooves. The polishing liquid generally includes abrasive grains, an oxidizing agent, a complexing agent, a surfactant, an abrasive, a pH adjuster, a corrosion inhibitor, and the like. The chemical thinning adopts a copper reducing agent to chemically thin the copper surface, and the main components of the chemical thinning agent are sulfuric acid, hydrogen peroxide, additives and the like.

Subsequently, as shown in fig. 13 to 15 and fig. 2, the inner layer wiring 200 is formed on both the first surface 100a and the second surface 100b, and the inner layer wiring 200a on the first surface 100a and the inner layer wiring 200b on the second surface 100b are electrically interconnected by conductive vias. Specifically, the step of forming the inner layer wiring 200 on both the first surface 100a and the second surface 100b includes, as shown in fig. 13, forming a resist layer on each thinned conductive layer 320, that is, double-sided dry film (resist layer) lamination on both sides of the glass core board 100. The dry film consists of a polyethylene film (PE), a photoresist film and a polyester film (PET), is a high polymer material capable of blocking electroplating and etching functions, and is subjected to polymerization reaction through ultraviolet irradiation. Thereafter, as shown in fig. 14, the resist layer is patterned to form an inner layer wiring pattern penetrating the resist layer. The patterning of the resist layer may be performed by exposure and development. After the dry film is applied, the glass core plate 100 is exposed to light and developed. As an example, the exposure machine is one or a combination of g-line, i-line, h-line. The light source adopts one of a pick lamp, a high-pressure mercury lamp and an iodine gallium lamp. The development is to remove the unexposed dry film to expose the circuit pattern, and the developing solution adopts one of sodium hydroxide, sodium carbonate and sodium bicarbonate. Next, as shown in fig. 15, an inner layer wiring 200 is formed on the inner layer wiring pattern by an electroplating process, that is, an electroplating process is performed on the developed region (i.e., the cavity of the inner layer wiring pattern) by an electroplating process. Finally, as shown in fig. 2, the resist layer is removed, and the conductive layer and the seed layer exposed after the removal of the resist layer are etched away, so that an inner layer line 200 including an inner layer metal pad and an inner layer metal trace is formed on the first surface 100a and the second surface 100b, wherein the inner layer metal pad is electrically connected with the conductive via. That is, the steps are performed by removing the film and etching. The dry film for plating resistance is removed from the copper surface by stripping, and a strong alkali solution is used. And etching the seed layer to complete the manufacture of the inner layer circuit 200 of the core plate 100. The line width spacing of the inner layer 200 can reach 8/8 μm. The etching liquid medicine is one or more of NaOH and NaHCO ₃、Na₂CO₃、HCl、H₃PO₄、H₂O₂.

Next, as shown in fig. 7, the first surfaces 100a of the two glass core plates 100 are temporarily bonded together, and the bonded two glass core plates 100 are symmetrical with the first surfaces 100a as a central axis. That is, the tops of the two glass core boards 100, on which the inner layer wire 200 is fabricated, are bonded to each other, thus being combined into one body. The two core plates are directly bonded together through the temporary bonding scheme, so that the warping problem in the sheet flowing process can be avoided, and the whole double sides can be manufactured simultaneously when the ABF lamination is carried out subsequently. The temporary bonding mode can be thermal bonding, UV bonding and the like, and the thermal bonding and the UV bonding are carried out by adopting the existing technology in the field.

Subsequently, as shown in fig. 4, the second surfaces 100b of the two bonded glass core boards 100 are each routed to form first rerouting structures 400 electrically connected to the inner layer wiring 200 thereof on the second surface 100b of each glass core board 100, and the dielectric layer of each first rerouting structure 400 is an ABF film.

As an example, the first re-wiring structure 400 may be manufactured by an additive/semi-additive method, and the first re-wiring structure 400 may be manufactured on the second surfaces 100b of the two glass core plates 100 at the same time, or may be manufactured on one side and then on the other side after the manufacturing is completed.

Specifically, as shown in fig. 16 to 22 and fig. 4, the first layer of the redistribution layer of the first redistribution structure 400 is fabricated on the Bottom surface (the second surface 100b of the glass core plate 100) by pasting an ABF film, laser drilling, removing the desmear+copper PTH by chemical Desmear, pasting a dry film, exposing, developing, electroplating, stripping, and etching on the second surface 100b of the glass core plate 100. Wherein, the laser drilling, chemical Desmear glue residue removal, copper PTH melting, dry film pasting, exposure, development, VCP, film removal, flash etching and the like are carried out by adopting the prior art. Specifically, as shown in fig. 16, ABF films are laminated on both the upper and lower surfaces of the glass core plate 100. The ABF material has low thermal expansion coefficient, low dielectric loss, easy processing of fine circuits, good mechanical property and good durability. As shown in FIG. 17, laser drilling is performed on the ABF film to obtain blind holes, wherein the aperture of the blind holes is less than or equal to 60 mu m, and the diameter of the disc is less than or equal to 80 mu m. One of a UV laser drilling machine, a CO ₂ laser drilling machine and an ultrafast laser drilling machine is used. The laser is one of continuous laser, quasi-continuous laser, nanosecond laser, picosecond laser and femtosecond laser. As shown in FIG. 18, after the copper melting is completed, electroless copper plating is adopted to form a conductive metal layer, the thickness of the metal layer is 5-15 mu m, and the plating solution mainly comprises copper sulfate, potassium sodium tartrate, sodium hydroxide, formaldehyde, ethylenediamine tetraacetic acid, triethanolamine, sodium carbonate, deionized water and the like. The backlight grade is more than or equal to 9, the surface of the board cannot be seriously oxidized, fiber, finger print and the like, and the copper layer is required to be glossy, uniform and orange-red. As shown in fig. 19-22, after copper is melted, a dry film is attached to the conductive metal layer formed by electroless copper plating, exposure, development, electroplating, film removal and etching are performed, and after the series of processes are completed, a layer of pattern circuit on the ABF film (i.e., the first layer of rerouting layer of the first rerouting structure 400) is completed. Subsequently, as shown in fig. 4, a second redistribution layer may be built up on the first redistribution layer of the first redistribution structure 400, to form the first redistribution structure 400 having two redistribution layers as illustrated in the drawing. The specific number of the redistribution layers of the first redistribution structure 400 may be designed according to practical application requirements, and is not limited to two layers illustrated in the drawings. The build-up process, for example, the second redistribution layer in the figures, is manufactured by repeating the processes described above with reference to fig. 16-22.

Next, as shown in fig. 5, the two glass core boards 100 bonded together are debonded, and a protective paste is applied to each of the first rewiring structures 400. After the two glass core plates 100 are unbuckled, the second surface 100b of each glass core plate 100 is fabricated with the first redistribution structure 400, and when the subsequent fabrication is performed, the first redistribution structure 400 needs to be protected by using the BG pinning process. The bonding can be performed by thermal decomposition or UV decomposition, which is performed by the existing technology in the field. BG taping mainly plays a role in protecting circuits, and can be thermal viscosity reduction or UV viscosity reduction.

Subsequently, as shown in fig. 6, the first surfaces 100a of the respective glass core boards 100 are respectively wired to form second re-wiring structures 500 electrically connected to the inner layer wires 200 thereof on the first surfaces 100a of the respective glass core boards 100, and the dielectric layers of the respective second re-wiring structures 500 are PI films.

Specifically, as shown in fig. 23 to 30 and 6, the step of wiring on the first surface 100a of each glass core plate 100 includes:

As shown in fig. 23, a PI film is formed on the first surface 100a of the glass core plate 100 such that the first surface 100a is upward. The PI film may be formed on the first surface 100a by coating/vacuum lamination. When PID or PSPI is used for layering, the aperture is more than or equal to 5 mu m, the disk diameter is more than or equal to 10 mu m, and the line width spacing is less than or equal to 2/2 mu m. The PID as a dielectric layer has good dielectric constant as low as 2.5, dielectric strength of 200-300KV/mm, good electrical insulation, excellent mechanical property and good chemical stability. The PSPI is used as an insulating layer and a dielectric layer to prevent electric crosstalk between different layers in the chip, and is used as a protective layer to protect the surface of the core plate from being damaged in the working procedures of etching or ion implantation and the like. In this step, the PID film pressing temperature is set at 70-150deg.C, the pressing time is 30-210s, and the pressure is 1-9Kgf/cm ². When PSPI is used for layering, the coating speed of wet coating is 1-12mm/s, the vacuum time is 800-1200s, the pressure is 8-22Pa, the baking temperature is 90-120 ℃, and the baking time is 200-300s.

After that, as shown in fig. 24 to 29, after the PI film layer is completed, wiring is performed on the dielectric layer. The method comprises the steps of photoetching development, solidification, PVD, dry film pasting, exposure development, electroplating and film removing flash etching. Specifically, as shown in fig. 24, the PI film layer is exposed, developed, and post-cured to make a first layer wiring pattern. Wherein, the exposure, development and post-curing are carried out by adopting the prior art. As shown in fig. 25, a conductive metal layer is formed on the first layer wiring pattern by sputtering/deposition. As shown in fig. 26 to 29, a dry film is formed on the conductive metal layer, and then the dry film is exposed, developed, electroplated, and flash etched to obtain the first wiring layer of the second re-wiring structure 500. The steps of photoetching, post-development curing, PVD, dry film pasting, exposure, development, electroplating, film removal, flash etching and the like are carried out by adopting the prior art.

Next, as shown in fig. 30, a second wiring layer may be built up on the first wiring layer of the second wiring structure 500 to form the second wiring structure 500 having two wiring layers as illustrated in the drawing. The specific number of the wiring layers of the second redistribution structure 500 may be designed according to practical application requirements, and is not limited to two layers illustrated in the drawings. The build-up pattern, for example, the second wiring layer in the figure, is produced by repeating the processes described above with reference to fig. 23-29. Thus, an RDL high definition wiring layer (i.e., the second redistribution structure 500) may be fabricated on the Top surface of each glass core panel 100.

Subsequently, as shown in fig. 6, the protective paste is separated from the first re-wiring structure 400. The protective adhesive tape at the bottom is removed, so that the subsequent solder resist process is conveniently carried out.

Finally, based on the above-described fabrication of the glass core board having the first and second re-wiring structures 400 and 500, as shown in fig. 3, a first solder resist layer 600 may be fabricated on each of the first re-wiring structures 400 and surface-treated on the first solder resist layer 600 for implanting solder balls to connect to a PCB board, a second solder resist layer 700 may be fabricated on each of the second re-wiring structures 500 and windowed and plated on the second solder resist layer 700 to fabricate plated pillars 710 connecting to the second re-wiring structures 500, the plated pillars 710 being adapted for bonding micro bumps of a connection chip.

The first solder mask layer 600 and the second solder mask layer 700 may be manufactured simultaneously or sequentially, and the first solder mask layer 600 and the second solder mask layer 700 may be manufactured in different manners, the first solder mask layer 600 is manufactured by surface treatment, and then the bottom ball is implanted, and the second solder mask layer 700 is manufactured by exposure and development, and copper column electroplating, and the like.

For example, as shown in fig. 31 to 35 and fig. 7, the second solder mask 700 and the plating post 710 are formed on the second redistribution structure 500 by the steps of green oil coating, green oil (blanket exposure), green oil (development), solder mask opening (UV drilling of holes), solder mask copper, film pasting, exposure development, copper post/nickel/tin plating, film removal, flash etching, reflow, and the like on the second redistribution structure 500. The first solder resist layer 700 is formed on the first rerouting structure 400 by a process such as green oil coating, green oil (exposure), green oil (development), and surface treatment (ENEPIG/OSP/ENIG) on the first rerouting structure 400. The green oil coating, green oil (exposure), green oil (development), surface treatment (ENEPIG/OSP/eneig), solder mask windowing, copper column/nickel/tin electroplating, copper solder mask, film pasting, film removing, flash etching, reflow and the like are performed by adopting the prior art.

Thus, the FCBGA package substrate with the asymmetric structure is manufactured.

Referring to fig. 7, the FCBGA package substrate includes a glass core board 100, the glass core board 100 having opposite first and second surfaces 100a and 100b, one or more conductive vias penetrating the glass core board 100 and exposed to the first and second surfaces 100a and 100b, two inner-layer wires 200 formed on the first and second surfaces 100a and 100b in one-to-one correspondence and electrically connected to the conductive vias, a first re-wiring structure 400 formed on the second surface 100b and electrically connected to the inner-layer wires 200b on the second surface 100b, a dielectric layer of the first re-wiring structure 400 being ABF film, a second re-wiring structure 500 formed on the first surface 100a and electrically connected to the inner-layer wires 200a on the first surface 100a, the dielectric layer of the second re-wiring structure 500 being PI film, a first solder resist layer 600 formed on the first re-wiring structure 400 and exposing the outer-layer pads of the first re-wiring structure 400, and a second solder resist layer 700 formed on the second re-wiring structure 500 and having plated pillars 710 electrically connected to the second re-wiring structure 500.

Therefore, according to the FCBGA packaging substrate, the connection between the chip and the PCB can be well realized in the packaging structure.

In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed, mechanically connected, electrically connected, directly connected, indirectly connected via an intervening medium, or in communication between two elements or in an interaction relationship between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.

In the present invention, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other through additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms should not be understood as necessarily being directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Further, one skilled in the art can engage and combine the different embodiments or examples described in this specification.

While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.

Claims (10)

1. The manufacturing method of the FCBGA packaging substrate is characterized by comprising the following steps of:

providing two core boards, and manufacturing an interconnected inner-layer circuit on a first surface and a second surface which are opposite to each other;

temporarily bonding the first surfaces of the two core plates together, wherein the two core plates after bonding are symmetrical by taking the first surfaces as central axes;

wiring the second surfaces of the two core boards after bonding to form first rerouting structures electrically connected with the inner layer circuits of the core boards on the second surfaces of the core boards, wherein a dielectric layer of each first rerouting structure is an ABF film;

de-bonding the two core boards bonded together, and covering the first rewiring structures with protective glue;

Wiring the first surface of each core board respectively to form a second re-wiring structure electrically connected with the inner layer circuit of each core board on the first surface of each core board, wherein a dielectric layer of each second re-wiring structure is a PI film;

And separating the protective glue from the first rerouting structure.

2. The method of manufacturing a FCBGA package substrate as set forth in claim 1, wherein a first solder mask layer is formed on each of the first redistribution structures, and a surface treatment is performed on the first solder mask layer for implanting solder balls, and a second solder mask layer is formed on each of the second redistribution structures, and a plated post is formed by windowing and plating the second solder mask layer to connect the second redistribution structures.

3. The method of manufacturing a FCBGA package substrate of claim 1, wherein each of the second surfaces of the two bonded core boards is routed simultaneously.

4. The method of manufacturing a FCBGA package substrate of claim 1, wherein the core is a glass core, a ceramic core or an organic core.

5. The method of manufacturing a FCBGA package substrate of claim 4, wherein the step of forming the interconnect inner traces on the first and second opposite surfaces of the glass core board comprises:

fabricating a glass through hole on the glass core plate to form one or more TGV holes;

filling conductive materials in the TGV holes to form conductive through holes;

and manufacturing the inner layer circuits on the first surface and the second surface, wherein the inner layer circuits on the first surface and the inner layer circuits on the second surface are electrically interconnected through the conductive through holes.

6. The method of manufacturing a FCBGA package substrate of claim 5, wherein the glass core is laser-induced, deep etched to form glass vias.

7. The FCBGA package substrate manufacturing method of claim 5, wherein the step of filling the TGV holes with conductive material comprises:

forming a seed layer on the first surface, the second surface and the inner wall of the TGV cell;

Forming a conductive layer on the surface of the seed layer, wherein the conductive layer fills the TGV holes and covers the seed layer on the first surface and the second surface;

the conductive layers on the first surface and the second surface are thinned.

8. The FCBGA package substrate manufacturing method of claim 7, wherein the step of manufacturing the inner layer wiring on both the first and second surfaces comprises:

forming a resist layer on each thinned conductive layer;

patterning the resist layer to form an inner layer wiring pattern penetrating the resist layer;

Forming the inner layer circuit on the inner layer circuit pattern by adopting an electroplating process;

And removing the resist layer, and etching away the conductive layer and the seed layer exposed after the resist layer is removed.

9. The method of manufacturing a FCBGA package substrate of claim 1, wherein the first redistribution structure has one or more first metal wiring layers, the second redistribution structure has one or more second metal wiring layers, and the line width spacing of the second metal wiring layers is less than or equal to 2/2 μm and the disk diameter is less than or equal to 10 μm.

10. An FCBGA package substrate manufactured by the manufacturing method according to any one of claims 1 to 9, comprising:

A glass core plate having opposed first and second surfaces;

one or more conductive vias extending through the glass core plate and exposed to the first surface and the second surface;

Two inner layer lines formed on the first surface and the second surface in one-to-one correspondence and electrically connected with the conductive through holes;

the first rewiring structure is formed on the second surface and is electrically connected with the inner-layer circuit on the second surface, and the dielectric layer of the first rewiring structure is an ABF film;

the second redistribution structure is formed on the first surface and is electrically connected with the inner-layer circuit on the first surface, and a dielectric layer of the second redistribution structure is a PI film;

The first solder mask layer is formed on the first rewiring structure and exposes an outer layer bonding pad of the first rewiring structure;

And a second solder resist layer formed on the second redistribution structure and having a plating post electrically connected to the second redistribution structure.