CN119317098B

CN119317098B - Semiconductor structure and preparation method thereof

Info

Publication number: CN119317098B
Application number: CN202310828709.XA
Authority: CN
Inventors: 林超
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-07-06
Filing date: 2023-07-06
Publication date: 2025-10-21
Anticipated expiration: 2043-07-06
Also published as: CN119317098A

Abstract

Embodiments of the present disclosure relate to a semiconductor structure and a method for fabricating the same. The semiconductor structure includes: a substrate; a semiconductor pillar located on a surface of the substrate, the semiconductor pillar having a channel region, the semiconductor pillar having a first side surface, at least a portion of the first side surface corresponding to the channel region being recessed toward the center of the semiconductor pillar; and a word line, the word line at least covering the first side surface corresponding to the channel region. The semiconductor structure provided by the embodiments of the present disclosure can at least improve the performance of the semiconductor structure.

Description

Semiconductor structure and preparation method thereof

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof.

Background

Memory is a common semiconductor structure that, as the size of semiconductor structures continues to shrink, allows a greater number of memories to be incorporated on a chip, contributing to an increase in product capacity. Within the semiconductor structure are a number of tiny conductive structure elements, such as channels and source and drain electrodes. Wherein the channel is used to form a conductive channel between the source and the drain. The semiconductor mechanism also has a word line in electrical contact with the channel region for providing a control voltage to the channel region sufficient to turn on the channel, thereby controlling conduction between the source and drain. The control capability of the word line to the channel has an important effect on the performance of the semiconductor structure, and the stronger the control capability of the word line to the channel is, the faster the response speed of the transistor in the semiconductor structure is, and the better the performance of the semiconductor structure is.

However, the performance of current semiconductor structures is still further improved.

Disclosure of Invention

The embodiment of the disclosure provides a semiconductor structure and a preparation method thereof, which are at least beneficial to improving the performance of the semiconductor structure.

The embodiment of the disclosure provides a semiconductor structure, which comprises a substrate, a semiconductor column and a word line, wherein the semiconductor column is positioned on the surface of the substrate and is provided with a channel region, the semiconductor column is provided with a first side surface, at least part of the first side surface corresponding to the channel region is sunken towards the center of the semiconductor column, and the word line at least covers the first side surface corresponding to the channel region.

In some embodiments, the semiconductor column further comprises doped regions located at two sides of the channel region, the arrangement direction of the channel region and the doped regions is perpendicular to the surface of the substrate, a part of the first side surface corresponding to the channel region is recessed towards the center of the semiconductor column to form a first groove, the first groove extends in a direction away from the surface of the substrate, and the first groove spans the doped regions and the channel region.

In some embodiments, a portion of the first side surface corresponding to the channel region is recessed toward the center of the semiconductor pillar to form a first groove, and the number of the first grooves is a plurality of the first grooves which are arranged at intervals.

In some embodiments, the semiconductor pillar has a second side opposite the first side, a portion of the second side corresponding to the channel region is recessed toward a center of the semiconductor pillar, and the word line also covers the second side corresponding to the channel region.

In some embodiments, the number of the semiconductor pillars is a plurality, and the semiconductor pillars are arranged at intervals along a first direction, wherein each row of the semiconductor pillars comprises a plurality of the semiconductor pillars arranged at intervals along a second direction, the number of the word lines is a plurality, each word line extends along the second direction, and one word line covers a first side surface corresponding to a channel region of each semiconductor pillar in one row of the semiconductor pillars.

In some embodiments, a word line surrounds the entire side of the semiconductor pillar of the channel region.

In some embodiments, the number of semiconductor pillars is a plurality, and the plurality of semiconductor pillars includes first sub-semiconductor pillars and second sub-semiconductor pillars alternately arranged along a first direction, wherein a first side of the first sub-semiconductor pillars is opposite to a first side of the second sub-semiconductor pillars along the first direction.

In some embodiments, a first side of the channel region of a first sub-semiconductor pillar and a first side of the channel region of a second sub-semiconductor pillar of a corresponding arrangement are covered by a word line.

In some embodiments, the first sub-semiconductor pillars and the second sub-semiconductor each include a second side opposite the first side, the second side being exposed outside the word line.

In some embodiments, the first and second sub-semiconductor pillars each include a third side contiguous with the first side and a fourth side disposed opposite the third side, the word line also covering at least a portion of the third and fourth sides of the first sub-semiconductor pillar and covering at least a portion of the third and fourth sides of the second sub-semiconductor pillar.

In some embodiments, the semiconductor structure comprises a plurality of rows of first sub-semiconductor pillars arranged at intervals along a first direction, each row of the first sub-semiconductor pillars comprises a plurality of first sub-semiconductor pillars arranged at intervals along the second direction, a plurality of rows of second sub-semiconductor pillars arranged at intervals along the second direction, each row of the second sub-semiconductor pillars comprises a plurality of second sub-semiconductor pillars arranged at intervals along the second direction, each row of the first sub-semiconductor pillars and each row of the second sub-semiconductor pillars are alternately arranged along the first direction, the number of word lines is a plurality of, and each word line covers one row of the first sub-semiconductor pillars and the first side surface corresponding to a channel region in one row of the second sub-semiconductor pillars which are alternately arranged.

In some embodiments, the semiconductor device further comprises a gate dielectric layer, wherein the gate dielectric layer is positioned between the word line and the semiconductor column.

In some embodiments, the number of semiconductor pillars is a plurality, and the plurality of semiconductor pillars includes first sub-semiconductor pillars and second sub-semiconductor pillars alternately arranged along a first direction, wherein a first side surface of a channel region of one of the first sub-semiconductor pillars and a first side surface of a channel region of one of the second sub-semiconductor pillars, which are relatively arranged, are covered by one of the word lines, and the gate dielectric layer covers an entire side surface of a channel region of the first sub-semiconductor pillar corresponding to one of the word lines and an entire side surface of a channel region of the second sub-semiconductor pillar corresponding to an adjacent other of the word lines.

Correspondingly, the embodiment of the disclosure also provides a preparation method of the semiconductor structure, which comprises the steps of providing a substrate, forming a semiconductor column on the surface of the substrate, wherein the semiconductor column is provided with a channel region, the semiconductor column is provided with a first side surface, at least part of the first side surface corresponding to the channel region is recessed towards the center of the semiconductor column, and forming a word line, and the word line at least covers the first side surface corresponding to the channel region.

In some embodiments, the method for forming the semiconductor column comprises the steps of providing an initial substrate, etching part of the initial substrate to form semiconductor layers which are arranged at intervals along a second direction, forming a first pattern layer on part of the surface of the semiconductor layers, wherein the first pattern layer is used for defining the cross-sectional shape of the semiconductor column along the direction parallel to the surface of the substrate, etching the semiconductor layers which are not covered by the first pattern layer, and forming the semiconductor column by the rest of the semiconductor layers.

In some embodiments, the plurality of semiconductor pillars comprises first sub-semiconductor pillars and second sub-semiconductor pillars alternately arranged along a first direction, wherein a first side of the first sub-semiconductor pillars is opposite to a first side of the second sub-semiconductor pillars along the first direction, a first side of a channel region of the first sub-semiconductor pillars and a first side of a channel region of the second sub-semiconductor pillars are opposite to each other by a word line, the method of forming the semiconductor pillars comprises forming a first pattern layer on a part of a surface of the semiconductor layer, the first pattern layer comprises a first sub-pattern layer and a second sub-pattern layer alternately arranged along the first direction, the first sub-pattern layer comprises a first concave side with a first concave, the second sub-pattern layer comprises a second concave side with a second concave, the first concave side is opposite to the second side along the first direction, and the first concave side and the second sub-pattern layer is etched to cover the first sub-pattern layer and the remaining semiconductor layer.

In some embodiments, the front projection shape of the first sub-graphic layer on the surface of the substrate is a "concave" shape, and the front projection shape of the second sub-graphic layer on the surface of the substrate is a "concave" shape.

In some embodiments, the first sub-pattern layer comprises a first non-concave side opposite to the first concave side, the second sub-pattern layer comprises a second non-concave side opposite to the second concave side, the method for forming the word line comprises the steps of forming isolation layers between adjacent semiconductor layers, wherein the isolation layers are in contact with the side walls of the semiconductor layers, the top surfaces of the isolation layers are flush with the top surfaces of the semiconductor layers, forming a plurality of second pattern layers which are arranged at intervals along a first direction on the top surfaces of the isolation layers, the gaps between the second pattern layers and the first non-concave side and the second non-concave side are opposite to each other, etching a semiconductor layer with a second preset thickness along the surfaces of the semiconductor layers which are not covered by the first pattern layers to form first grooves, etching isolation layers with a first preset thickness along the surfaces of the isolation layers which are not covered by the second pattern layers to form second grooves, the first grooves are communicated with the second grooves, forming a plurality of second pattern layers which are in a first direction and are in a first direction opposite to the second grooves, and filling gaps between the first grooves and the second grooves are filled with the second grooves, and the non-concave medium layer is filled with the word line.

The technical scheme provided by the embodiment of the disclosure has at least the following advantages:

In the semiconductor structure provided by the embodiment of the disclosure, the first side surface corresponding to the channel region of the semiconductor pillar has the recess, so that the surface area of the first side surface is increased compared with the case without the recess. The word line covers the first side surface corresponding to the channel region, and the contact area between the word line and the channel region is increased due to the increase of the surface area of the first side surface, so that the channel length of the transistor can be increased, the control capability of the word line on the transistor is enhanced, and the electrical property of the semiconductor structure is improved.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically claimed, and in order to more clearly illustrate the embodiments of the present disclosure or the concepts of the conventional art, the drawings that are required to be utilized in the embodiments will be briefly described below, it will be apparent that the drawings in the following description are merely some embodiments of the present disclosure and that other drawings may be derived from these drawings by one of ordinary skill in the art without undue effort.

FIG. 1 is a schematic top view of a semiconductor structure;

Fig. 2 is a schematic top view of a semiconductor structure according to an embodiment of the disclosure;

FIG. 3 is a schematic view of a partial cross-sectional structure in the aa' direction of FIG. 2;

FIG. 4 is a schematic top view of another semiconductor structure according to an embodiment of the present disclosure;

Fig. 5 is a schematic top view of another semiconductor structure according to an embodiment of the disclosure;

fig. 6 to 22 are schematic top view structures corresponding to steps of a method for manufacturing a semiconductor structure according to another embodiment of the disclosure.

Detailed Description

As known from the background art, the performance of the current semiconductor structure needs to be further improved. Analysis of one of the reasons for poor performance of semiconductor structures in connection with fig. 1 has now found that current semiconductor structures include a semiconductor pillar 1 and a word line 2 disposed around a channel region of the semiconductor pillar 1. As semiconductor structures become smaller in size, the contact area between the word line and the channel region in the semiconductor pillar becomes smaller, so that the length of the channel of the transistor is smaller, the control capability of the word line on the channel is weaker, and the electrical performance of the semiconductor structure is further poorer.

The embodiment of the disclosure provides a semiconductor structure, wherein a first side surface corresponding to a channel region of a semiconductor column is provided with a recess, so that the surface area of the first side surface is increased compared with the situation without the recess. The word line covers the first side surface corresponding to the channel region, and the contact area between the word line and the channel region is increased due to the increase of the surface area of the first side surface, so that the channel length of the transistor can be increased, the control capability of the word line on the transistor is enhanced, and the electrical property of the semiconductor structure is improved.

Embodiments of the present disclosure will be described in detail below with reference to the attached drawings. However, those of ordinary skill in the art will understand that in the various embodiments of the present disclosure, numerous technical details have been set forth in order to provide a better understanding of the present disclosure. The technical solutions claimed in the present disclosure can be implemented without these technical details and with various changes and modifications based on the following embodiments.

Fig. 2 is a schematic top view of a semiconductor structure according to an embodiment of the disclosure, fig. 3 is a schematic partial structure of a cross-sectional structure along aa' direction in fig. 2, fig. 4 is another schematic top view of a semiconductor structure according to an embodiment of the disclosure, and fig. 5 is a schematic top view of yet another semiconductor structure according to an embodiment of the disclosure.

Referring to fig. 2 through 5, a semiconductor structure includes a substrate. The semiconductor structure further comprises a semiconductor column 101 located on the surface of the substrate, wherein the semiconductor column 101 is provided with a channel region 111, the semiconductor column 101 is provided with a first side 11, and at least part of the first side 11 corresponding to the channel region 111 is recessed towards the center of the semiconductor column 101. The semiconductor structure further comprises a word line 102, wherein the word line 102 at least covers the first side 11 corresponding to the channel region 111.

In some embodiments, the material of the substrate may be a semiconductor material. In some embodiments, the material of the substrate may be silicon. In some embodiments, the substrate may also be germanium, silicon germanium, or silicon on insulator.

In some embodiments, the material of the semiconductor pillars 101 may be the same as the material of the substrate. In some implementations, the material of the semiconductor pillars 101 can be silicon. In some embodiments, the material of semiconductor pillars 101 may also be germanium, silicon germanium, or silicon on insulator.

Referring to fig. 3, in some embodiments, the semiconductor pillar 101 further includes doped regions on both sides of the channel region 111, which may include a first doped region 112 and a second doped region 113. The first doped region 112 is located on a side of the channel region 111 facing the substrate, and the second doped region 113 is located on a side of the channel region 111 remote from the substrate. The first doped region 112, the second doped region 113, and the channel region 111 are used to form a transistor. In some embodiments, the first doped region 112 is used to form the source of the transistor, the second doped region 113 is used to form the drain of the transistor, and the channel region 111 is used to form the channel of the transistor.

In some embodiments, the doping ion type of the first doping region 112 is the same as the doping ion type of the second doping region 113, and the doping ion type of the first doping region 112 is different from the doping ion type of the channel region 111.

In some embodiments, the doping ion type of the first doping region 112 is P-type, the doping ion type of the second doping region 113 is N-type, and the doping ion type of the channel region 111 is P-type.

In some embodiments, the doping ion type of the first doping region 112 is N-type, the doping ion type of the second doping region 113 is P-type, and the doping ion type of the channel region 111 is N-type.

In some embodiments, the doping ion type of the first doping region 112 is the same as the doping ion type of the second doping region 113 and the doping ion type of the channel region 111, and the doping ion concentration of the channel region 111 is smaller than the doping ion concentrations of the first doping region 112 and the second doping region 113.

In some embodiments, the P-type dopant ions may include any of boron ions, aluminum ions, gallium ions, or indium ions. In some embodiments, the N-type dopant ions may include any of phosphorus ions, bismuth ions, antimony ions, or arsenic ions.

In some embodiments, the semiconductor structure further includes a bit line 104, where the bit line 104 is located on a side of the first doped region 112 facing the substrate and is in electrical contact with a surface of the first doped region 112 facing the substrate.

In some embodiments, the bit line 104 may be doped into the substrate corresponding to the semiconductor pillar 101, so that a portion of the substrate corresponding to the bottom surface of the semiconductor pillar 101 may be conductive.

In some embodiments, the substrate corresponding to the semiconductor pillar 101 may also be etched, a recess is formed in the substrate corresponding to the bottom of the semiconductor pillar 101, the recess exposes the bottom of the semiconductor pillar 101, and then the bit line 104 is deposited in the recess. In one embodiment, the material of the bit line 104 may include a metallic material, such as at least one of aluminum, tungsten, silver, copper, gold, cobalt, nickel, or staples.

In some embodiments, the number of semiconductor pillars 101 is plural, and the plural semiconductor pillars 101 are arranged at intervals along the first direction X and the second direction Y. The number of the bit lines 104 is plural, each bit line 104 extends along the first direction X, and the plurality of bit lines 104 are arranged at intervals along the second direction Y, and the bit lines 104 are in electrical contact with the first doped regions 112 of each semiconductor pillar 101 of the plurality of semiconductor pillars 101 arranged at intervals along the first direction X.

The first side 11 of the semiconductor pillar 101 has a recess, so that the surface area of the first side 11 is increased compared with the first side 11 without the recess, and then the contact area between the word line 102 and the channel region 111 of the first side 11 covering the channel region 111 is increased, so that the channel length of the transistor is increased, and further the control capability of the word line 102 to the channel is enhanced, the response rate of the transistor is improved, and the electrical performance of the semiconductor structure is improved.

It is noted that the semiconductor pillar 101 has a top surface and a bottom surface parallel to the substrate surface, and has side surfaces connected to the top surface and the bottom surface. The first side 11 referred to herein is a side of the semiconductor pillar 101.

In some embodiments, the front projection of the semiconductor pillar 101 on the substrate surface is circular or elliptical, i.e. the semiconductor pillar 101 has no ridge, the first side 11 may be any part of the side of the semiconductor. In some embodiments, the semiconductor pillar 101 has a ridge, i.e., the semiconductor pillar 101 has multiple sides in different directions that are separated by the ridge, then the first side 11 may be one of the sides of the semiconductor pillar 101.

Referring to fig. 2, only a portion of the first side 11 is recessed toward the center of the semiconductor pillar 101, and in some embodiments, the semiconductor pillar further includes doped regions on both sides of the channel region 111, the channel region 111 and the doped regions being aligned in a direction perpendicular to the surface of the substrate, and a corresponding portion of the first side 11 of the channel region 111 is recessed toward the center of the semiconductor pillar 101 to form a first recess extending in a direction away from the surface of the substrate and crossing the doped region and the channel region 111.

In some embodiments, the orthographic projection of the first recess on the substrate surface may be "concave" shaped.

In some embodiments, the doped regions include a first doped region 112 and a second doped region 113, the first doped region 112 is located on a side of the channel region 111 facing the substrate, and the second doped region 113 is located on a side of the channel region 111 away from the substrate, so that the first recess may only span the channel region 111 and the second doped region 113. That is, the first side 11 corresponding to the first doped region 112 does not have a recess toward the center of the semiconductor pillar 101. In this way, the semiconductor column 101 corresponding to the first doped region 112 can be ensured to have a larger area, so that the contact area between the bit line 104 and the bottom surface of the semiconductor column 101 corresponding to the first doped region 112 can be increased, and the electrical connection performance between the bit line 104 and the first doped region 112 can be improved. The second doped region 113 and the first side 11 of the channel region 111 have a recess towards the center of the semiconductor pillar 101, so that in the step of actually forming the recess, the second doped region 113 may be etched from the top of the second doped region 113, and the second doped region 113 is located on the top of the semiconductor pillar 101, i.e. the semiconductor pillar 101 may be etched from the top of the semiconductor pillar 101 to form the first recess, which is beneficial to simplifying the process of forming the first recess.

In some embodiments, the first recess may also span the first doped region 112, the second doped region 113 and the channel region 111, that is, the first sides 11 corresponding to the first doped region 112, the second doped region 113 and the channel region 111 each have a recess toward the center of the semiconductor pillar 101.

In some embodiments, a portion of the first side 11 corresponding to the channel region 111 is recessed toward the center of the semiconductor pillar 101 to form a first groove, where the number of the first grooves is plural, and the plural first grooves are arranged at intervals. That is, the plurality of first grooves may be distributed on the first side 11. In some embodiments, the plurality of first grooves may be spaced apart in a direction perpendicular to the surface of the substrate.

In some embodiments, the orthographic projection of the first groove on the first side 11 may be at least one of circular, rectangular, or polygonal.

In some embodiments, the semiconductor pillar 101 has a second side 12 opposite the first side 11, the distance between the first side 11 and the second side 12 being a first distance. The first groove is recessed from the first side 11 toward the second side 12, and a ratio of a recessed depth of the first groove to the first distance is less than or equal to 0.7. Within this range, on the one hand, the recess depth of the first groove is larger, and thus the first side 11 has a larger surface area, which is beneficial to increasing the contact area between the word line 102 and the first side 11. On the other hand, in the above range, the recess depth of the first groove is not too large, so that the problem that the electrical performance of the semiconductor pillar 101 is deteriorated due to the too small first distance, i.e., the distance between the first side 11 and the second side 12, caused by the too large recess depth of the first groove is prevented.

Referring to fig. 4, in some embodiments, a portion of the second side 12 corresponding to the channel region is recessed toward the center of the semiconductor pillar 101, and the word line 102 also covers the second side 12 corresponding to the channel region 111. That is, both the first side 11 and the second side 12 are recessed toward the center of the semiconductor pillar 101. Wherein part of the first side 11 is recessed in the direction of the second side 12 and part of the second side 12 is recessed in the direction of the first side 11. In this way, the surface area of the side surface of the semiconductor pillar 101 of the channel region 111 can be further increased. The word line 102 covers the first side 11 of the channel region 111 and the second side 12 of the channel region 111, so that the contact area between the word line 102 and the channel region 111 is further increased, the length of the channel can be further increased, the control capability of the word line 102 on the channel is enhanced, and the electrical performance of the semiconductor structure is further improved.

In some embodiments, a portion of the second side 12 is recessed toward the center of the semiconductor pillar 101 to form a second recess.

In some embodiments, the second recess spans the large second doped region 113 and the channel region 111.

In some embodiments, the second recess is very fast in the first doped region 112, the channel region 111, and the second doped region 113.

In some embodiments, the number of second grooves is a plurality, and the plurality of second grooves are arranged at intervals. In a specific example, the plurality of second grooves are arranged at intervals in a direction perpendicular to the surface of the substrate.

In some embodiments, a portion of the first side 11 is recessed toward the center of the semiconductor pillar 101 to form a first recess, and a portion of the second side 12 is recessed toward the center of the semiconductor pillar 101 to form a second recess, wherein a ratio of a sum of a recess depth of the first recess and a recess depth of the second recess to the first distance is less than or equal to 0.7. Within this range, the first distance can be ensured not to be too small, so that the thickness of the semiconductor pillar 101 in the direction of the first side 11 pointing to the first side 11 is not too small, and further, the electrical performance of the semiconductor pillar 101 is ensured to be better.

Referring to fig. 4, in some embodiments, a portion of the second side 12 is recessed toward the center of the semiconductor pillar 101, and the word line 102 surrounds the entire side of the channel region 111 corresponding to the semiconductor pillar 101. That is, the word line 102 entirely surrounds the entire side surface of the semiconductor pillar 101 of the channel region 111, and thus, it is possible to secure the word line 102 in the first groove and the first groove, and thus, it is possible to increase the contact area of the word line 102 and the channel region 111.

Specifically, in some embodiments, the sides of the semiconductor pillar 101 further include a third side and a fourth side, the third side is thick, the fourth side is opposite to the first side 11, the second side 12, the third side and the fourth side are sequentially connected to form the semiconductor pillar 101. The entire side of the semiconductor pillar 101 referred to herein includes the first side 11, the second side 12, the third side, and the fourth side.

It is noted that in some embodiments, a portion of the first side 11 is recessed toward the center of the semiconductor pillar 101, a portion of the second side 12 is recessed toward the center of the semiconductor pillar 101, and the number of semiconductor pillars is plural, including plural rows of semiconductor pillars 101 arranged at intervals along the first direction X, wherein each row of semiconductor pillars 101 includes plural semiconductor pillars 101 arranged at intervals along the second direction Y, the number of word lines 102 is plural, each word line 102 extends along the second direction Y, and one word line 102 covers the first side 11 corresponding to the channel region 111 of each semiconductor pillar 101 in one row of semiconductor pillars 101.

That is, one word line 102 corresponds to one row of semiconductor pillars 101, one word line 102 covers only the channel region 111 side of one row of semiconductor pillars 101, and one word line 102 covers the semiconductor pillar 101 side of the entire channel region 111 in one row of semiconductor pillars 101.

In some embodiments, there is an isolation layer 105 between adjacent word lines 102, with the sides of the isolation layer 105 contacting the sides of the word lines 102. The isolation layer 105 is used to isolate adjacent word lines 102, and prevent signal crosstalk between adjacent word lines 102. In some embodiments, the material of the isolation layer 105 may be an insulating material such as silicon nitride, silicon oxynitride, or silicon oxide. In some embodiments, the material of the word line 102 may be a metallic material, such as at least one of aluminum, tungsten, silver, copper, gold, cobalt, nickel, or staples.

Referring to fig. 5, in some embodiments, the number of semiconductor pillars is plural, and the plurality of semiconductor pillars 101 includes first sub-semiconductor pillars 101 and second sub-semiconductor pillars 101 alternately arranged along a first direction X, wherein a first side 11 of the first sub-semiconductor pillars 101 is disposed opposite to a first side 11 of the second sub-semiconductor pillars 101 along the first direction X.

Specifically, a portion of the first side 11 of the first sub-semiconductor pillar 101 is recessed toward the center of the first sub-semiconductor pillar 101 to form a first sub-groove, and a portion of the first side 11 of the second sub-semiconductor pillar 101 is recessed toward the center of the second sub-semiconductor pillar 101 to form a second sub-groove, the first sub-groove being disposed face-to-face with the second sub-groove.

In some embodiments, the front projection of the first sub-groove on the substrate surface is "concave" shaped, and the front projection of the second sub-groove on the substrate surface is "concave" shaped.

In some embodiments, a word line 102 is wrapped around the first side 11 of the channel region 111 of a first sub-semiconductor pillar 101 and the first side 11 of the channel region 111 of a second sub-semiconductor pillar 101 that are disposed opposite to each other. That is, the word line 102 is located between the first side 11 and the second side 12 of the first sub-semiconductor pillar 101, and the word line 102 is also located in the first sub-groove and the second sub-groove, and the word line 102 is electrically contacted with both the first sub-semiconductor pillar 101 and the second sub-semiconductor pillar 101, i.e. one word line 102 controls the first sub-semiconductor pillar 101 and the second sub-semiconductor pillar 101.

The channel region 111 of the first sub-semiconductor pillar 101 and the channel region 111 of the second sub-semiconductor pillar 101 are commonly used to form the channel region 111 of a transistor, so that the contact area between the word line 102 and the channel region 111 is further increased, and the channel length of the transistor formed by the first sub-semiconductor pillar 101 and the second sub-semiconductor pillar 101 is increased, thereby facilitating the enhancement of the transistor control capability of the word line 102, compared to the case that the word line 102 only covers the first side 11 of the semiconductor pillar 101.

In some embodiments, the first sub-semiconductor pillar 101 and the second sub-semiconductor pillar 101 each include a second side 12 opposite the first side 11, the second side 12 being exposed outside the word line 102. That is, the word line 102 does not cover the second side 12. It will be appreciated that the same word line 102 covers the first side 11 of the first sub-semiconductor pillar 101 and covers the first side 11 of the second sub-semiconductor pillar 101, and if the word line 102 also covers the second side 12 of the first sub-semiconductor pillar 101 and the second side 12 of the second sub-semiconductor pillar 101, the thickness of the word line 102 in the direction along the first side 11 toward the second side 12 increases compared to the case where the word line 102 only surrounds one side of the semiconductor pillar 101, so that the number of word lines 102 in the same area is reduced, which is disadvantageous for improving the integration of the semiconductor structure.

Therefore, the provision of the word line 102 not covering the second side 12 can ensure that the contact area between the word line 102 and the channel region 111 is increased without increasing the thickness of the word line 102 in the direction from the first side 11 to the second side 12, thereby enhancing the controllability of the word line 102 to the channel.

In a specific example, the first sub-semiconductor pillar 101 and the second sub-semiconductor pillar 101 each include a third side surface connected to the first side surface 11 and a fourth side surface disposed opposite to the third side surface, and the word line 102 also covers at least a portion of the third side surface and at least a portion of the fourth side surface of the first sub-semiconductor pillar 101 and at least a portion of the third side surface and at least a portion of the fourth side surface of the second sub-semiconductor pillar 101.

That is, the first and second sub-semiconductor pillars 101 and 101 disposed opposite each other are surrounded by three sides of the same word line 102, so that the contact area between the word line 102 and the sides of the channel region 111 of the first sub-semiconductor pillar 101 and the sides of the channel region 111 of the second sub-semiconductor pillar 101 is further increased.

In some embodiments, the word line 102 surrounds a portion of the third side of the channel region 111 and a portion of the fourth side of the channel region 111 of the first sub-semiconductor pillar 101. In some embodiments, the word line 102 surrounds a portion of the third side of the channel region 111 and a portion of the fourth side of the channel region 111 of the second sub-semiconductor pillar 101. In some embodiments, the word line 102 surrounds the entire third side of the channel region 111 and the entire fourth side of the channel region 111 of the first sub-semiconductor pillar 101.

In some embodiments, the first sub-semiconductor pillar 101 and the second sub-semiconductor pillar 101 each include a third side surface that interfaces with the first side surface 11, and a fourth side surface that is disposed opposite the third side surface. In a specific example, the word line 102 may cover at least part of the third side, at least part of the fourth side, and the first side 11 of the first sub-semiconductor pillar 101, and cover only the first side 11 of the second sub-semiconductor pillar 101. In another specific example, the word line 102 may cover only the first side 11 of the first sub-semiconductor pillar 101, and cover at least part of the third side, at least part of the fourth side, and the first side 11 of the second sub-semiconductor pillar 101.

Referring to fig. 5, in some embodiments, the semiconductor structure includes a plurality of rows of first sub-semiconductor pillars 101 spaced apart along a first direction X, each row of the first sub-semiconductor pillars 101 including a plurality of first sub-semiconductor pillars 101 spaced apart along a second direction Y, a plurality of rows of second sub-semiconductor pillars 101 spaced apart along the second direction Y, each row of second sub-semiconductor pillars 101 including a plurality of second sub-semiconductor pillars 101 spaced apart along the second direction Y, each row of first sub-semiconductor pillars 101 alternating with each row of second sub-semiconductor pillars along the first direction X, a plurality of word lines 102, each word line 102 encasing a corresponding first side 11 of the channel regions 111 in the alternating rows of first sub-semiconductor pillars 101 and the rows of second sub-semiconductor.

Specifically, a row of first sub-semiconductor pillars 101 and a row of second sub-semiconductor pillars 101 that are disposed opposite to each other are denoted as a semiconductor pillar 101 group. In each semiconductor pillar 101 group, a first sub-groove of the first side 11 of the first sub-semiconductor pillar 101 is disposed opposite a second sub-groove of the first side 11 of the second sub-semiconductor pillar 101. One word line 102 corresponds to one semiconductor pillar 101 group, and is located between a row of first sub-semiconductor pillars 101 and a row of second sub-semiconductor pillars 101 belonging to the same semiconductor pillar 101 group.

In some embodiments, referring to fig. 2-5, further comprising a gate dielectric layer 103, the gate dielectric layer 103 being located between the word line 102 and the semiconductor pillar 101. The gate dielectric layer 103 is located on the side of the semiconductor pillar 101 in the channel region 111, and the word line 102 covers the surface of the gate dielectric layer 103. In some embodiments, the material of gate dielectric layer 103 may be silicon oxide.

Referring to fig. 2 to 4, in some embodiments, a word line 102 wraps a row of channel regions 111 of semiconductor pillars 101 spaced apart along a second direction Y, and then a gate dielectric layer 103 is located on the side of the channel region 111 of each semiconductor pillar 101.

Referring to fig. 5, in some embodiments, the number of semiconductor pillars is plural, and the plurality of semiconductor pillars 101 includes first sub-semiconductor pillars 114 and second sub-semiconductor pillars 115 alternately arranged along a first direction X, and one word line 102 wraps the first side 11 of the channel region 111 of the first sub-semiconductor pillar 114 and the first side 11 of the channel region 111 of the second sub-semiconductor pillar 115, which are disposed opposite to each other, and the gate dielectric layer 103 wraps the entire side of the channel region 111 of the first sub-semiconductor pillar 114 corresponding to one word line 102 and the entire side of the channel region 111 of the second sub-semiconductor pillar 115 corresponding to another adjacent word line 102.

Specifically, the semiconductor pillars arranged at intervals along the first direction X are divided into first sub-semiconductor pillar groups 14 and second sub-semiconductor pillar groups 15 alternately arranged, and the second sub-semiconductor pillars 115 in the first sub-semiconductor pillar groups 14 are adjacent to the first sub-semiconductor pillars 114 in the second sub-semiconductor pillar groups 15.

The word lines 102 include a first sub-word line 102 located between adjacent first sub-semiconductor pillars 114 and adjacent second sub-semiconductor pillars 115 in the first sub-semiconductor pillar group 14, and a second sub-word line 102 located between adjacent first sub-semiconductor pillars 114 and adjacent second sub-semiconductor pillars 115 in the second sub-semiconductor pillar group 15. That is, the first sub-word line 102 corresponds to the first sub-semiconductor pillar set 14, and the second sub-word line 102 corresponds to the second sub-semiconductor pillar set 15. An isolation layer 105 is provided between the first sub-word line 102 and the second sub-word line 102 to isolate the first sub-word line 102 from the second sub-word line 102.

The gate dielectric layer 103 covers the channel region 111 side of the second sub-semiconductor pillars 115 belonging to the first sub-semiconductor pillar group 14 and the channel region 111 side of the first sub-semiconductor pillars 114 belonging to the second sub-semiconductor pillar group 15. And the gate dielectric layer 103 is further located in the gap between the second sub-semiconductor pillars 115 belonging to the first sub-semiconductor pillar group 14 and the first sub-semiconductor pillars 114 belonging to the second sub-semiconductor pillar group 15, for isolating the first sub-semiconductor pillars 114 and the second sub-semiconductor pillars 115 not belonging to the same semiconductor pillar 101 group.

In the semiconductor structure provided in the above embodiment, the first side 11 corresponding to the channel region 111 of the semiconductor pillar 101 has a recess, so that the surface area of the first side 11 is increased compared to the case without the recess. The word line 102 covers the first side 11 corresponding to the channel region 111, and as the surface area of the first side 11 increases, the contact area between the word line 102 and the channel region 111 increases, so that the channel length of the transistor can be increased, the control capability of the word line 102 on the transistor is enhanced, and the electrical performance of the semiconductor structure is improved.

Accordingly, the embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure, which may be used to manufacture the semiconductor structure provided in the foregoing embodiment, and the semiconductor structure provided in one embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

Fig. 7 is a schematic cross-sectional view along the AA ' direction in fig. 6, fig. 9 is a schematic cross-sectional view along the AA ' direction in fig. 8, fig. 11 is a schematic cross-sectional view along the AA ' direction in fig. 10, fig. 13 is a schematic cross-sectional view along the AA ' direction in fig. 12, and fig. 15 is a schematic cross-sectional view along the AA ' direction in fig. 14.

Referring to fig. 6 to 15, the method of fabricating a semiconductor structure includes:

Providing a substrate 100, forming a semiconductor column 101 on the surface of the substrate 100, wherein the semiconductor column 101 is provided with a channel region 111, the semiconductor column 101 is provided with a first side surface 11, and at least part of the first side surface 11 corresponding to the channel region 111 is recessed towards the center of the semiconductor column 101.

In some embodiments, a method of forming semiconductor pillars 101 includes:

Referring to fig. 6 and 7, an initial substrate (not shown) is provided. In some embodiments, the material of the initial substrate may be a semiconductor material. In some embodiments, the material of the initial substrate may be silicon. In some embodiments, the initial substrate may also be germanium, silicon germanium, or silicon on insulator.

Thereafter, a portion of the initial substrate is etched to form semiconductor layers 20 spaced apart in the second direction Y, and the remaining portion of the initial substrate serves as the substrate 100. Each semiconductor layer 20 extends along a first direction X.

In some embodiments, the method of etching a portion of the initial substrate to form the semiconductor layer 20 includes patterning the initial substrate surface to define the location of the initial semiconductor portion, and in some embodiments, patterning the initial substrate surface using any one of SADP (Self-aligned Double Patterning, self-aligned dual imaging) process or SAQP (Self-Aligned Quadruple Patterning, self-aligned multiple exposure) process may be used. Thereafter, an etching process is performed on the patterned initial substrate surface to etch a portion of the thickness of the initial substrate to form the semiconductor layers 20 that are discrete from each other. In some embodiments, the etching process may be any one of a dry etching process or a wet etching process.

Referring to fig. 8 and 9, in some embodiments, the bit lines 104 are formed after forming the semiconductor layers 20 that are discrete from each other. Adjacent semiconductor layers 20 expose a portion of the surface of the substrate 100, and a doping process is performed on the substrate 100 from the gap between the adjacent semiconductor layers 20 to convert a portion of the thickness of the substrate 100 opposite the semiconductor layers 20 into a bit line 104 having conductivity. In some embodiments, the substrate 100 may be doped using an ion implantation process. The implantation angle of the ion implantation process may be controlled to convert the substrate 100 facing the semiconductor layer 20 into the bit line 104 such that the formed bit line 104 is aligned with the extension direction of the semiconductor layer 20, i.e., extends in the first direction X. In this way, after the semiconductor layer 20 is subsequently subjected to the etching process to form the semiconductor pillars 101 arranged at intervals in the first direction X, the semiconductor pillars 101 extending in the first direction X may be electrically contacted with each of the plurality of semiconductor pillars 101 arranged at intervals in the first direction X.

Referring to fig. 12 and 13, a first pattern layer 30 is formed on a portion of the surface of the semiconductor layer 20, the first pattern layer 30 defining a cross-sectional shape of the semiconductor pillar 101 along a plane parallel to the surface of the substrate 100. In some embodiments, the first pattern layer 30 may be formed on the surface of the semiconductor layer 20 using either of the SADP process or SAQP process. In some embodiments, the first pattern layer 30 may be any of photoresist, spin-on hard mask, or silicon oxide.

Referring to fig. 14 and 15, after the first pattern layer 30 is formed, the semiconductor layer 20 not covered by the first pattern layer 30 is etched, and the semiconductor pillars 101 are formed in the remaining semiconductor layer 20. The semiconductor layer 20 other than the first pattern layer 30 is etched, the semiconductor layer 20 covered by the first pattern layer 30 remains, and the semiconductor layer 20 not etched has the same shape as the first pattern layer 30 in a cross-sectional shape in a direction parallel to the surface of the substrate 100. The shape of the first pattern layer 30 is set to have a concave shape so that the semiconductor pillar 101 formed also has a concave shape.

In some embodiments, the semiconductor pillar 101 has a channel region 111 and first doped regions 113 on both sides of the channel region 111, the first doped regions 112 are located on a side of the channel region 111 facing the substrate 100, and the second doped regions 113 are located on a side of the channel region 111 facing away from the substrate 100.

In some embodiments, doping processes may be performed on different portions of the same semiconductor pillar 101 to form the first doped region 112, the second doped region 113, and the channel region 111, respectively.

In some embodiments, after the semiconductor pillar 101 is etched, different portions of the semiconductor pillar 101 may be doped to form the first doped region 112, the second doped region 113, and the channel region 111, respectively. Specifically, the semiconductor pillar 101 includes a first region, a second region, and a third region sequentially arranged in a direction perpendicular to a surface of the substrate 100, and a method of forming the semiconductor pillar 101 includes:

The first region, the second region and the third region are respectively subjected to a doping process to convert the first region into a first doped region 112, the second region into a channel region 111 and the third region into a second doped region 113, wherein the doping ion type of the first doped region 112 is the same as the doping ion type of the second doped region 113, and the doping ion type of the second doped region 113 is different from the doping ion type of the channel region 111. In some embodiments, the doping process may be an ion implantation process.

Since the doping ion type of the first doping region 112 is the same as the doping ion type of the second doping region 113, the first region and the third region may be doped in the same process step to form the second doping region 113 and the first doping region 112, respectively. In the step of doping the first region and the third region, a mask layer is formed on the side surface of the semiconductor part of the second region, and is used for protecting the second region and preventing doped ions from diffusing into the second region.

It is understood that, in the step of doping the second region, a mask layer may be formed on the semiconductor portion side surfaces of the first region and the third region, so as to protect the first region and the third region from diffusion of the dopant ions into the first region and the third region. In some embodiments, the mask layer may be silicon oxide, which may be formed using a thermal oxidation process.

In some embodiments, P-type dopant ions may be implanted into the first region and the third region, and N-type dopant ions may be implanted into the second region. In some embodiments, N-type dopant ions may also be implanted into the first region and the third region, and P-type dopant ions may also be implanted into the second region.

In some embodiments, the first doped region 112, the second doped region 113, and the channel region 111 may also be formed by doping different portions of the semiconductor layer 20 before forming the semiconductor pillar 101. Thus, only a few semiconductor layers 20 need to be doped, simplifying the process.

In some embodiments, the plurality of semiconductor pillars 101 includes first sub-semiconductor pillars 114 (refer to fig. 5) and second sub-semiconductor pillars 115 (refer to fig. 5) alternately arranged along a first direction X, wherein a first side 11 of the first sub-semiconductor pillars 114 is disposed opposite to a first side 11 of the second sub-semiconductor pillars 115 along the first direction X, a word line 102 is disposed opposite to the first side 11 of a channel region 111 of the first sub-semiconductor pillars 114 and the first side 11 of the channel region 111 of the second sub-semiconductor pillars 115, and a method of forming the semiconductor pillars 101 includes:

Referring to fig. 12 and 13, a first pattern layer 30 is formed on a portion of the surface of the semiconductor layer 20, the first pattern layer 30 including first sub-pattern layers and second sub-pattern layers alternately arranged in a first direction X, the first sub-pattern layers including a first recess side having a first recess, the second sub-pattern layers including a second recess side having a second recess, the first recess side being disposed opposite to the second recess side in the first direction X.

The first sub-pattern layer is used to define the cross-sectional shape of the first sub-semiconductor pillars 114 along a surface parallel to the substrate 100, and the second sub-pattern layer is used to define the cross-sectional shape of the second sub-semiconductor pillars 115 along a surface parallel to the substrate 100.

The first recess is used to define the orthographic projection shape of the first recess of the first side 11 of the first sub-semiconductor pillar 114 on the surface of the substrate 100, and the second recess is used to define the orthographic projection shape of the first recess of the first side 11 of the second sub-semiconductor pillar 115 on the surface of the substrate 100.

The first concave side and the second concave side are disposed opposite to each other along the first direction X, and in the first sub-semiconductor pillars 114 and the second sub-semiconductor pillars 115 formed later, the first side surfaces 11 of the first sub-semiconductor pillars 114 and the first side surfaces 11 of the second sub-semiconductor pillars 115 face each other.

In some embodiments, the first pattern layer 30 and the second pattern layer may be formed using any one of the SADP process or SAQP process, the material of the first pattern layer 30 may be any one of photoresist, spin-on hard mask, or silicon oxide, and the material of the second pattern layer may be any one of photoresist, spin-on hard mask, or silicon oxide.

In some embodiments, the front projection of the first sub-graphic layer 30 onto the surface of the substrate 100 is "concave" shaped, and the front projection of the second sub-graphic layer onto the surface of the substrate 100 is "concave" shaped. The concave side of the first sub-graph layer is the first concave side, and the concave side of the second sub-graph layer is the second concave side.

Referring to fig. 14 and 15, the semiconductor layer 20 not covered with the first sub-pattern layer and the semiconductor layer 20 not covered with the second sub-pattern layer are etched, and the remaining semiconductor layer 20 forms the semiconductor pillars 101. In some embodiments, only a portion of the thickness of the semiconductor layer 20 is etched, for example, only the second doped region 113 and the semiconductor layer 20 corresponding to the channel region 111 may be etched, so that the first recess formed only spans the second doped region 113 and the channel region 111, i.e. the first side 11 corresponding to the first doped region 112 has no recess.

In some embodiments, the semiconductor layer 20 corresponding to the first doped region 112, the second doped region 113 and the channel region 111 may also be etched, so that a first recess is formed across the first doped region 112, the second doped region 113 and the channel region 111.

Fig. 17 is a schematic cross-sectional view along AA 'in fig. 16, and fig. 19 is a schematic cross-sectional view along AA' in fig. 18.

Referring to fig. 16 to 19, the word line 102 is formed, and the word line 102 covers at least the first side 11 corresponding to the channel region 111. Since the first side 11 has the recess, the surface area of the first side 11 is greatly increased, that is, the area of the channel region 111 is greatly increased, so that the contact area between the formed word line 102 and the channel region 111 is increased, the channel length of the transistor is increased, and the control capability of the word line 102 on the channel region 111 of the transistor is increased as compared with the case that the first side 11 does not have the recess.

In some embodiments, the first sub-pattern layer includes a first non-recessed side opposite the first recessed side, the second sub-pattern layer includes a second non-recessed side opposite the second recessed side, the first non-recessed side being a side of the first sub-pattern layer that does not have a recess, and the second non-recessed side being a side of the second sub-pattern layer that does not have a recess. In some embodiments, the front projection of the first sub-graphic layer onto the surface of the substrate 100 is "concave" shaped, and the front projection of the second sub-graphic layer onto the surface of the substrate 100 is "concave" shaped. One side of the concave shape of the first sub-graph layer is a first concave side, and the non-concave side opposite to the concave side is a first non-concave side; the second sub-pattern layer has a concave side of the concave shape being a second concave side and a non-concave side opposite to the concave side being a second non-concave side, and the method for forming the word line 102 includes:

an isolation layer 105 is formed between adjacent semiconductor layers 20, the isolation layer 105 being in contact with the sidewalls of the semiconductor layers 20, and the top surface of the isolation layer 105 being flush with the top surface of the semiconductor layers 20.

In some embodiments, referring to fig. 10 and 11, an isolation layer 105 may be formed between adjacent semiconductor layers 20 after forming the bit line 104, and in some embodiments, the isolation layer 105 may be formed between adjacent semiconductor layers 20 using a deposition process, such as an atomic layer deposition process or a chemical vapor deposition process. In some embodiments, the material of the isolation layer 105 may be either silicon nitride or silicon oxynitride.

Referring to fig. 12 and 13, a plurality of second pattern layers 31 are formed on the top surface of the isolation layer 105 at intervals along the first direction X, and a second pattern layer 31 is opposite to the gaps between the first non-concave side and the second non-concave side. The second pattern layer 31 is used to define the shape of the isolation layer 105 that needs to be preserved, and after the plurality of word lines 102 are formed later, the isolation layer 105 defined by the second pattern layer 31 may be used to isolate the adjacent word lines 102.

Since each word line 102 is subsequently formed to cover the first side 11 of the first sub-semiconductor pillar 114 and the first side 11 of the second sub-semiconductor pillar 115, the first recess side is used to define the first side 11 of the first sub-semiconductor pillar 114 and the second recess side is used to define the first side 11 of the second semiconductor pillar 101. That is, the subsequently formed word line 102 is located in the area between the first concave side and the second concave side, and therefore, the second pattern layer 31 is disposed opposite to the gap between the first non-concave side and the second non-concave side, so that the subsequently formed isolation layer 105 and the formed word line 102 can be staggered, and further, the function of isolating the adjacent word lines 102 can be achieved.

In some embodiments, the second pattern layer 31 may be formed using any one of the SADP process or SAQP process. In some embodiments, the material of the second pattern layer 31 may be any one of photoresist, spin-on hard mask, or silicon oxide.

Referring to fig. 14 and 15, the semiconductor layer 20 of a second preset thickness is etched along the surface of the semiconductor layer 20 not covered by the first pattern layer 30 to form a first trench 40, and the isolation layer 105 of a first preset thickness is etched along the surface of the isolation layer 105 not covered by the second pattern layer 31 to form a second trench (not shown), the first trench 40 being in communication with the second trench. The first trench 40 is in communication with the second trench, such that the subsequently formed word line 102 may be located in the first trench 40 and the second trench, and the word lines 102 located in the first trench 40 and the second trench are in communication, forming the word line 102 extending along the second direction Y, so that the same word line 102 can cover the first side 11 of the channel regions 111 of the plurality of first sub-semiconductor pillars 114 arranged at intervals along the second direction Y and cover the first side 11 of the channel regions 111 of the plurality of second sub-semiconductor pillars 115 arranged at intervals along the second direction Y.

In some embodiments, semiconductor layer 20 and isolation layer 105 may be etched using either a dry etching process or a wet etching process.

Referring to fig. 16 and 17, in some embodiments, prior to forming the word line 102, forming a gate dielectric layer 103 on the sidewalls of the semiconductor pillar 101 is further included, wherein the gate dielectric layer 103 also fills the gap between the first non-recessed side and the second non-recessed side.

In some embodiments, a deposition process may be used to form gate dielectric layer 103 on the surface of semiconductor pillars 101 in channel region 111. In some embodiments, the material of the gate dielectric layer 103 may be silicon oxide, and then a thermal oxidation process may be used to form the gate dielectric layer 103 on the surface of the semiconductor pillar 101. In some embodiments, the gate dielectric layer 103 on the non-concave side of the first sub-semiconductor layer 20 is further connected to the gate dielectric layer 103 on the non-concave side of the second sub-semiconductor pillar 115, and the gate dielectric layer 103 between the first sub-semiconductor pillar 114 and the second sub-semiconductor pillar 115 is opposite to the isolation layer 105, so that the gate dielectric layer 103 between the first sub-semiconductor pillar 114 and the second sub-semiconductor pillar 115 functions to isolate the adjacent first sub-semiconductor pillar 114 from the adjacent second sub-semiconductor pillar 115.

Referring to fig. 16 to 19, a word line 102 filling the first trench 40 and the second trench is formed, and the word line 102 covers the gate dielectric layer 103.

Referring to fig. 16 to 17, an initial word line 22 is formed on top of the semiconductor pillar 101, top of the isolation layer 105 and top of the gate dielectric layer 103, and the entire surface of the initial word line 22 covers the top of the semiconductor pillar 101, top of the isolation layer 105 and top of the gate dielectric layer 103. The initial word line 22 is located on the surface of the gate dielectric layer 103 of the channel region 111 and on the surface of the gate dielectric layer 103 of the second doped region 113.

In some embodiments, the initial word line 22 may be formed using a deposition process, such as an atomic layer deposition process or a chemical vapor deposition process. In some embodiments, the material of the initial word line 22 may be a metallic material, such as at least one of aluminum, tungsten, silver, copper, gold, cobalt, nickel, or staples.

Referring to fig. 18 to 19, fig. 19 is a schematic cross-sectional structure along the AA' direction in fig. 18, a patterning process is performed on the initial word line 22 to form a plurality of word lines 102 arranged at intervals along the first direction X, each word line 102 extends along the second direction Y, and each word line 102 covers the first side 11 of the channel region 111 of each of the plurality of first sub-semiconductor pillars 114 arranged at intervals along the second direction Y and covers the first side 11 of the channel region 111 of each of the plurality of second sub-semiconductor pillars 115 arranged at intervals along the second direction Y.

In some embodiments, the word line 102 also covers at least a portion of the third side of the channel region 111 and at least a portion of the fourth side of the channel region 111 of the first sub-semiconductor pillar 114, and the word line 102 also covers at least a portion of the third side of the channel region 111 and at least a portion of the fourth side of the channel region 111 of the second sub-semiconductor pillar 115.

In some embodiments, the word line 102 covers a portion of the third side of the channel region 111 and a portion of the fourth side of the channel region 111 of the first sub-semiconductor pillar 114, and the word line 102 covers a portion of the third side of the channel region 111 and a portion of the fourth side of the channel region 111 of the second sub-semiconductor. Then referring to fig. 12, the width of the second pattern layer 31 in the first direction X may be controlled to be greater than the spacing between the first non-concave side and the second non-concave side, so that, referring to fig. 14, a part of the third side and a part of the fourth side of the subsequently formed first sub-semiconductor pillars 114 are opposite to the isolation layer 105, so that the word lines 102 located at both sides of the isolation layer 105 cannot cover the third side and the fourth side opposite to the isolation layer 105, and the word lines 102 are formed to cover only a part of the third side and a part of the fourth side.

In some embodiments, the word line 102 covers the entire third side of the channel region 111 and the entire fourth side of the channel region 111 of the first sub-semiconductor pillar 114, and the word line 102 covers the entire third side of the channel region 111 and the entire fourth side of the channel region 111 of the second sub-semiconductor. Then referring to fig. 12, the spacing of the second pattern layer 31 in the first direction X may be controlled to be equal to that between the first non-concave side and the second non-concave side, so that, referring to fig. 14, a part of the third side surface and a part of the fourth side surface of the subsequently formed first sub-semiconductor pillars 114 are offset from the isolation layer 105, so that the word lines 102 located at both sides of the isolation layer 105 cover the entire third side surface of the channel region 111 and the entire fourth side surface of the channel region 111.

In some embodiments, a method of patterning the initial word line 22 may include patterning a top surface of the initial word line 22 to define the location of the word line 102. In some embodiments, the initial word line 22 may be etched by using either a SADP process or SAQP process, after which the patterned initial word line 22 is etched to remove the gate dielectric layer 103 and the initial word line 22 on the side of the first sub-semiconductor pillar 114 in the second doped region 113, and to remove the gate dielectric layer 103 and the initial word line 22 on the side of the second sub-semiconductor pillar 115 in the second doped region 113, and the remaining portion of the initial word line 22 forms a plurality of word lines 102 arranged at intervals along the first direction X, each word line 102 extending along the second direction Y. In some embodiments, the etching process may be any one of a dry etching process or a wet etching process.

Referring to fig. 20-22, isolation structures 106 are formed. The isolation structure 106 is used for isolating the adjacent semiconductor pillars 101 corresponding to the second doped region 113.

In some embodiments, a method of forming the isolation structure 106 may include:

Referring to fig. 20 to 21, an initial isolation structure 23 is formed, and the top surface of the word line 102, the top surface of the gate dielectric layer 103, and the top surface of the second doped region 113 of the initial isolation structure 23 are also located between the adjacent semiconductor pillars 101 corresponding to the second doped region 113. In some embodiments, the initial isolation structures 23 may be formed using a deposition process, such as an atomic layer deposition process, and the material of the initial isolation structures 23 may be silicon nitride.

Referring to fig. 22, an etching process is performed on the initial isolation structure 23 to expose the top surface of the semiconductor pillar 101 of the second doped region 113, and the remaining initial isolation structure 23 forms an isolation structure 106. In this way, other conductive structures, such as a capacitor structure, may be formed on the top surface of the semiconductor pillar 101 corresponding to the second doped region 113.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the disclosure, and the scope of the disclosure should be assessed accordingly to that of the appended claims.

Claims

1. A semiconductor structure, comprising:

A substrate;

The semiconductor column is positioned on the surface of the substrate and provided with a channel region, the semiconductor column is provided with a first side surface, and at least part of the first side surface corresponding to the channel region is recessed towards the center of the semiconductor column;

a word line covering at least the first side corresponding to the channel region;

The semiconductor column further comprises doped regions positioned at two sides of the channel region, the arrangement directions of the channel region and the doped regions are perpendicular to the surface of the substrate, a part of the first side surface corresponding to the channel region is recessed towards the center of the semiconductor column to form a first groove, the first groove extends along the direction away from the surface of the substrate, and the first groove spans the doped region and the channel region.

2. The semiconductor structure of claim 1, wherein a portion of the first side surface corresponding to the channel region is recessed toward a center of the semiconductor pillar to form a first groove, the number of the first grooves is plural, and the plural first grooves are arranged at intervals.

3. The semiconductor structure of claim 1, wherein the semiconductor pillar has a second side opposite the first side, a portion of the second side corresponding to the channel region is recessed toward a center of the semiconductor pillar, and the word line also covers the second side corresponding to the channel region.

4. The semiconductor structure of claim 1, wherein the number of semiconductor pillars is a plurality, the plurality of semiconductor pillars comprising first and second sub-semiconductor pillars alternately arranged along a first direction, wherein a first side of the first sub-semiconductor pillar is disposed opposite a first side of the second sub-semiconductor pillar along the first direction.

5. The semiconductor structure of claim 4, wherein a first side of a channel region of a first sub-semiconductor pillar and a first side of a channel region of a second sub-semiconductor pillar of a relative arrangement of one of the word lines is covered.

6. The semiconductor structure of claim 5, wherein the first and second sub-semiconductor pillars each comprise a second side opposite the first side, the second side being exposed outside the word line.

7. The semiconductor structure of claim 6, wherein the first and second sub-semiconductor pillars each comprise a third side contiguous with the first side and a fourth side disposed opposite the third side, the word line further covering at least a portion of the third and fourth sides of the first sub-semiconductor pillar and at least a portion of the third and fourth sides of the second sub-semiconductor pillar.

8. The semiconductor structure of any one of claims 5-7, wherein the semiconductor structure comprises:

A plurality of rows of first sub-semiconductor pillars arranged at intervals along a first direction, each row of the first sub-semiconductor pillars including a plurality of first sub-semiconductor pillars arranged at intervals along a second direction;

the semiconductor device comprises a plurality of rows of second sub-semiconductor columns which are arranged at intervals along a second direction, wherein each row of second sub-semiconductor columns comprises a plurality of second sub-semiconductor columns which are arranged at intervals along the second direction, each row of first sub-semiconductor columns and each row of second sub-semiconductors are alternately arranged along the first direction, the number of word lines is a plurality, and each word line covers one row of first sub-semiconductor columns which are alternately arranged and the first side corresponding to a channel region in one row of second sub-semiconductors.

9. The semiconductor structure of claim 1 or 5, further comprising a gate dielectric layer between the word line and the semiconductor pillar;

The plurality of semiconductor columns comprises first sub-semiconductor columns and second sub-semiconductor columns which are alternately arranged along a first direction, a first side face of a channel region of one first sub-semiconductor column and a first side face of a channel region of one second sub-semiconductor column which are oppositely arranged are covered by one word line, and the whole side face of the channel region of the first sub-semiconductor column corresponding to one word line and the whole side face of the channel region of the second sub-semiconductor column corresponding to the other adjacent word line are covered by the gate dielectric layer.

10. A method of fabricating a semiconductor structure, comprising:

Providing a substrate;

Forming a semiconductor column on the surface of the substrate, wherein the semiconductor column is provided with a channel region, the semiconductor column is provided with a first side surface, at least part of the first side surface corresponding to the channel region is recessed towards the center of the semiconductor column, the semiconductor column is also provided with doped regions formed on two sides of the channel region, the arrangement directions of the channel region and the doped regions are perpendicular to the surface of the substrate, the first side surface corresponding to the channel region is recessed towards the center of the semiconductor column to form a first groove, the first groove extends along the direction away from the surface of the substrate, and the first groove spans the doped regions and the channel region;

And forming a word line, wherein the word line at least covers the first side surface corresponding to the channel region.

11. The method of fabricating a semiconductor structure of claim 10, wherein the method of forming the semiconductor pillars comprises:

providing an initial substrate;

Etching part of the initial substrate to form semiconductor layers which are arranged at intervals along a second direction, and taking the rest of the initial substrate as the substrate;

Forming a first pattern layer on a part of the surface of the semiconductor layer, wherein the first pattern layer is used for defining the cross-sectional shape of the semiconductor column along the direction parallel to the surface of the substrate;

and etching the semiconductor layer which is not covered by the first pattern layer, and forming the semiconductor column by the rest part of the semiconductor layer.

12. The method of manufacturing a semiconductor structure according to claim 11, wherein the plurality of semiconductor pillars includes first sub-semiconductor pillars and second sub-semiconductor pillars alternately arranged along a first direction, wherein a first side of the first sub-semiconductor pillars is opposite to a first side of the second sub-semiconductor pillars along the first direction, wherein a first side of a channel region of the first sub-semiconductor pillars and a first side of a channel region of the second sub-semiconductor pillars are opposite to each other, wherein the forming the semiconductor pillars includes:

Forming a first pattern layer on a part of the surface of the semiconductor layer, wherein the first pattern layer comprises first sub-pattern layers and second sub-pattern layers which are alternately arranged along the first direction, the first sub-pattern layer comprises a first concave side with a first concave, and the second sub-pattern layer comprises a second concave side with a second concave, and the first concave side and the second concave side are oppositely arranged along the first direction;

And etching the semiconductor layer which is not covered by the first sub-pattern layer and the semiconductor layer which is not covered by the second sub-pattern layer, wherein the rest part of the semiconductor layer forms the semiconductor column.

13. The method of claim 12, wherein the front projection of the first sub-pattern layer on the substrate surface is concave, and the front projection of the second sub-pattern layer on the substrate surface is concave.

14. The method of manufacturing a semiconductor structure of claim 12 or 13, wherein the first sub-pattern layer includes a first non-recessed side opposite the first recessed side, the second sub-pattern layer includes a second non-recessed side opposite the second recessed side, the method of forming the word line comprising:

Forming an isolation layer between adjacent semiconductor layers, wherein the isolation layer is in contact with the side wall of the semiconductor layer, and the top surface of the isolation layer is flush with the top surface of the semiconductor layer;

forming a plurality of second pattern layers which are arranged at intervals along a first direction on the top surface of the isolation layer, wherein the second pattern layers are opposite to gaps between the first non-concave side and the second non-concave side;

Etching a semiconductor layer with a second preset thickness along the surface of the semiconductor layer which is not covered by the first pattern layer to form a first groove, and etching an isolation layer with a first preset thickness along the surface of the isolation layer which is not covered by the second pattern layer to form a second groove, wherein the first groove is communicated with the second groove;

forming a gate dielectric layer on the side wall of the semiconductor column, wherein the gate dielectric layer also fills a gap between the first non-concave side and the second non-concave side;

and forming the word lines filled in the first grooves and the second grooves, wherein the word lines cover the gate dielectric layer.