CN119275213B - Semiconductor detection structure, semiconductor device manufacturing method and semiconductor device - Google Patents
Semiconductor detection structure, semiconductor device manufacturing method and semiconductor deviceInfo
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- CN119275213B CN119275213B CN202411389986.6A CN202411389986A CN119275213B CN 119275213 B CN119275213 B CN 119275213B CN 202411389986 A CN202411389986 A CN 202411389986A CN 119275213 B CN119275213 B CN 119275213B
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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Abstract
本发明的半导体检测结构、半导体器件的制备方法及半导体器件，半导体检测结构设置于晶圆的切割道内，该结构包括：基准单元及至少四组检测模块，且每个检测模块的偏移距离均不同。并设置每个检测模块中检测单元内的多晶硅子单元以基准单元中的多晶硅子单元为基准，按照对应偏移距离朝着不同方向进行偏移。后续通过对检测单元内的多晶硅子单元入射电子束，以检测出呈第一状态且偏移距离最大的多晶硅子单元，并将该多晶硅子单元相对于对应有源区子单元的偏移参数作为后续制作共享接触孔的工艺窗口。通过本发明提供半导体检测结构，能避免绝缘层的影响，对共享接触孔的工艺窗口进行高精度的检测，并提前判断是否能够制作共享接触孔，以避免资源浪费。
The semiconductor detection structure, the method for preparing a semiconductor device, and the semiconductor device of the present invention, the semiconductor detection structure is arranged in the cutting path of the wafer, and the structure includes: a reference unit and at least four groups of detection modules, and the offset distance of each detection module is different. The polysilicon subunit in the detection unit of each detection module is set to the polysilicon subunit in the reference unit as a reference, and is offset in different directions according to the corresponding offset distance. Subsequently, an electron beam is incident on the polysilicon subunit in the detection unit to detect the polysilicon subunit in the first state and with the largest offset distance, and the offset parameter of the polysilicon subunit relative to the corresponding active area subunit is used as the process window for the subsequent production of shared contact holes. The semiconductor detection structure provided by the present invention can avoid the influence of the insulating layer, perform high-precision detection of the process window of the shared contact hole, and judge in advance whether the shared contact hole can be produced to avoid waste of resources.
Description
Technical Field
The present invention relates to the field of semiconductor inspection, and in particular, to a semiconductor inspection structure, a method for manufacturing a semiconductor device, and a semiconductor device.
Background
As a semiconductor memory, a Static Random Access Memory (SRAM) has a shared contact hole that falls on an Active Area (AA) and a polysilicon (Poly Silicon) at the same time to form a pull-up transistor and a pull-down transistor at the same time. As process nodes become more advanced, process windows shrink, and the shared contact Kong Meineng falls on both AA and Poly, causing an increasing risk of open circuit.
In the prior art, when preparing the shared contact hole, the relative positions of AA and Poly are usually represented by measured overlay accuracy parameters. After the relative positions of AA and Poly are measured, the shared contact holes are aligned to the common area of AA and Poly by photolithography of the shared contact holes. However, the prior art has the problem that on one hand, the alignment of the shared contact hole is completely dependent on the lithography of the contact hole, so that the correction and adjustment capability is limited. On the other hand, the relative positions of AA and Poly are only represented by the overlay accuracy parameter, so that the process window size of the shared contact hole at different positions of the wafer cannot be completely and accurately reflected, and the alignment accuracy of the shared contact hole cannot be ensured.
Therefore, providing a method for accurately detecting the offset parameters of the active region and the polysilicon before the preparation of the shared contact hole has become a technical problem to be solved in the industry.
Disclosure of Invention
The invention solves the technical problem of providing a semiconductor detection structure, a preparation method of a semiconductor device and the semiconductor device, wherein the offset parameters of an active region and polysilicon are detected before a shared contact hole is prepared.
In order to solve the above technical problems, the present invention provides a semiconductor inspection structure, which is disposed in a scribe line of a wafer, and includes:
The device comprises a reference unit A1, a first detection module, a second detection module, a third detection module, a fourth detection module, a fifth detection module and a sixth detection module, wherein each detection module comprises a first detection unit, a second detection unit, a third detection unit, a fourth detection unit, a fifth detection unit, a sixth detection unit and a fourth detection unit, each reference unit A1 and each detection unit respectively comprises an active area subunit and a polysilicon subunit, the polysilicon subunits are vertically arranged above the active area subunits, and one end of each polysilicon subunit is in physical contact with one end of each active area subunit; wherein, N and N are positive integers, and N is more than or equal to 4;
The polycrystalline silicon subunits in the detection units in each detection module are respectively offset towards different quadrants by first distances compared with the corresponding active region subunits by taking the polycrystalline silicon subunits in the reference unit as an origin, and the first distances of the different detection units in the same detection module are different from the origin in the different detection modules.
Optionally, each of the polysilicon subunits includes two first polysilicon structures and second polysilicon structures which are relatively parallel and are arranged along the first direction;
Each of the active region subunits includes two first and second active region structures that are relatively parallel and are each disposed along the second direction.
Optionally, the second end of the first polysilicon structure is physically connected to the first end of the first active region structure, and the first end of the second polysilicon structure is physically connected to the second end of the second active region structure.
Optionally, the first direction and the second direction are perpendicular to each other.
Correspondingly, the technical scheme of the invention also provides a preparation method of the semiconductor device, which is used for preparing the static random access memory structure and comprises the following steps:
providing a substrate;
Sequentially forming an active region layer and an insulating layer on the substrate along a direction deviating from the substrate;
Forming a patterned first mask layer on the insulating layer, wherein the patterned first mask layer comprises a first window region and a blocking region;
etching the insulating layer in the first window area by taking the patterned first mask layer as a mask, wherein an etching end point stays on the surface of the active area layer, and the first window area is used for representing the area where the cutting channel is located;
depositing a polysilicon layer;
Forming a patterned second mask layer on the polysilicon layer, wherein the patterned second mask layer comprises a first pattern area, a second pattern area and a blocking area;
Etching the polysilicon layer in the first pattern region and the second pattern region by taking the patterned second mask layer as a mask to form a polysilicon gate in the static random access memory structure and the polysilicon subunit in the semiconductor detection structure, wherein the first pattern region is used for representing the pattern of the polysilicon gate in the static random access memory structure, and the second pattern region is used for representing the pattern of the polysilicon subunit in the semiconductor detection structure;
Incident electron beams to all the polysilicon subunits in the semiconductor detection structure;
Judging whether a target polycrystalline silicon subunit exists, wherein the target polycrystalline silicon subunit is a polycrystalline silicon subunit in a first state and is the largest in a first distance which is offset compared with an active region subunit, and the first state is used for representing that the target polycrystalline silicon subunit is in physical contact with a corresponding active region subunit;
If the target polysilicon subunit is present, a process window of the polysilicon gate is obtained according to the offset distance and the offset direction of the target polysilicon subunit compared with the active region subunit;
And preparing a shared contact hole in the region where the static random access memory structure is located, and correcting offset of photoetching of the shared contact hole through the process window.
Optionally, the insulating layer includes an oxide layer.
Optionally, the insulating layer includes an oxide layer and a high-k dielectric layer.
Optionally, the pattern size of the polysilicon in the first pattern area and the pattern size of the polysilicon subunit are consistent, and the pattern shape of the polysilicon in the first pattern area and the pattern shape of the polysilicon subunit are consistent.
Optionally, preparing a shared contact hole in the area where the static random access memory structure is located, and performing offset correction on lithography of the shared contact hole through the process window, which specifically includes:
performing overlay accuracy measurement on the polycrystalline silicon grid electrode and the active region layer to obtain an overlay error of the polycrystalline silicon grid electrode and the active region layer;
Forming a conductive contact layer, wherein the conductive contact layer is respectively formed on the surfaces of the polysilicon, the source drain region and the active region corresponding to the shared contact hole in the region where the static random access memory structure is located;
Forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the surface of the substrate and the surface of the polysilicon gate;
Depositing a photoresist layer on the interlayer dielectric layer;
Taking the polysilicon gate as a reference layer, taking the process window as compensation, aligning the photoresist layer before exposure, and photoetching to form the shared contact hole patterning mask layer;
etching the interlayer dielectric layer to the surfaces of the substrate and the polysilicon gate by taking the patterned photoresist layer as a mask to form a shared contact hole, wherein the shared contact hole penetrates through the interlayer dielectric layer;
depositing metal in the shared contact hole to form a shared plug.
Correspondingly, the technical scheme of the invention provides a semiconductor device which comprises a static random access memory structure, and the semiconductor device is prepared by a preparation method of the semiconductor device.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
In the semiconductor detection structure of the technical scheme of the invention, through setting the reference unit and at least four groups of detection modules with different offset distances, each detection module comprises a plurality of detection units, and the polysilicon subunits in the detection units are offset towards different directions according to the corresponding offset distances by the reference unit. The electron beam can be incident to the polysilicon sub-unit in the detection unit to detect the polysilicon sub-unit in the first state with the largest offset distance, and the offset parameter of the polysilicon sub-unit relative to the corresponding active region sub-unit is used as the shared contact hole for the subsequent manufacture to provide photoetching alignment correction. The semiconductor detection structure provided by the invention can detect the process window of the shared contact hole in advance with high precision, and judge whether the shared contact hole can be manufactured in advance so as to avoid waste of resources.
In the preparation method of the semiconductor device, before the polysilicon layer is deposited, the insulation layer with the designed structure is etched, so that the polysilicon layer deposited subsequently can be in direct physical contact with the active area layer. After the preparation of the semiconductor detection structure is completed, the process window of the polysilicon grid in the static random access memory structure can be obtained through the electron beam incidence polysilicon subunit, so that correction is provided for photoetching of the shared contact hole when the shared contact hole of the static random access memory structure is prepared subsequently, and the accurate preparation of the shared contact hole is realized. If the deviation of the polysilicon gate is too large, the process window of the polysilicon gate cannot be detected, and the polysilicon gate can be removed in advance, so that the waste of resources is reduced.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to the present invention;
Fig. 2 to 8 are simplified cross-sectional structure diagrams of the method for manufacturing a semiconductor device according to the present invention under different process flows;
FIG. 9 is a block diagram of a semiconductor inspection structure according to the present invention;
fig. 10 is a flowchart of implementing step S12 in an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As described in the background art, in the process of preparing the shared contact hole, the existing technology has the problem of detecting the offset parameters of the active region and the polysilicon. The problems of the prior art will be described in detail below.
In a semiconductor device such as a Static Random Access Memory (SRAM), a shared contact hole is generally provided. Wherein a portion of the shared contact hole is in contact with the previously prepared drain active region to form a pull-up transistor. And another portion of the shared contact hole may be contacted with the previously prepared gate polysilicon to form a pull-down transistor.
It is important whether the shared contact hole contacts the active region and the polysilicon at the same time. In the prior art, in the early stage of the semiconductor device, the relative position of the active region and the polysilicon is measured, and the overlay error of the active region and the polysilicon is used as a process window of the shared contact hole. And subsequently, when photoetching is carried out on the shared contact hole, compensating the photoetching of the shared contact hole through a process window of the shared contact hole. And finally, after the preparation of the shared contact hole is finished, detecting whether the shared contact hole contacts the active region and the polysilicon at the same time.
It should be noted that, the process window of the shared contact hole may be understood as an offset parameter between the active region and the polysilicon in a semiconductor device such as a static random access memory. If the offset parameter between the active region and the polysilicon is too large, the shared contact hole cannot fall on the active region and the polysilicon at the same time.
The prior art has the problems that on one hand, the process window confirmation of the prior art about the shared contact hole only depends on the alignment of the relative positions between the active region and the polysilicon in the previous process, but the alignment of the active region and the polysilicon cannot completely and accurately reflect the process windows of the shared contact hole at different positions of the wafer, so that the problem that the shared contact hole cannot simultaneously contact the active region and the polysilicon due to inaccurate process windows exists. On the other hand, in the prior art, only after the preparation of the shared contact hole is completed, whether the shared contact hole contacts the active region and the polysilicon at the same time can be detected. If the shared contact hole is found not to contact the active region and the polysilicon at the same time, the semiconductor device is disabled, so that the problem of resource waste caused by too late detection period exists.
In view of the above, the technical scheme of the invention provides a novel preparation method of a semiconductor device, which is used for preparing a static random access memory structure and a semiconductor detection structure. Wherein the static random access memory structure is prepared in the device region, and the semiconductor detection structure is prepared in the scribe line.
Fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to the present invention. Fig. 2 to 8 are simplified cross-sectional structure diagrams of the method for manufacturing a semiconductor device according to the present invention under different process flows. Fig. 9 is a structural diagram of a semiconductor inspection structure provided in the technical scheme of the present invention.
Before explaining the preparation method of the semiconductor device provided by the technical scheme of the invention, explaining a semiconductor detection structure prepared by the preparation method:
Referring to fig. 9, the semiconductor inspection structure specifically includes a reference unit A1 and first to nth inspection modules A2 to AN, each of the inspection modules includes first to nth inspection units B1 to Bn, each of the reference unit A1 and each of the inspection units includes AN active region subunit 20 and a polysilicon subunit 50, the polysilicon subunit 50 is vertically disposed above the active region subunit 20, and one end of the polysilicon subunit 50 is in physical contact with one end of the active region subunit 20, where N, N are positive integers, and N, N is greater than or equal to 4.
The polysilicon subunits 50 in the detection units in each detection module are respectively offset towards different quadrants by a first distance compared with the corresponding active region subunits 20 by taking the polysilicon subunits 50 in the reference unit A1 as an origin, and the first distances of the different detection units in the same detection module are different from the origin in the different detection modules.
Since the semiconductor detection structure is provided with the plurality of detection modules which are offset by different distances, and each detection module is provided with the detection units which are offset by different directions, the offset condition of the polysilicon gate 50 and the active region layer 20 in the device region i1 can be simulated by the detection units which are offset by different directions in the detection modules which are offset by different distances. Referring to fig. 1 to 9, the method for manufacturing a semiconductor device according to the present invention includes the following steps:
s1, providing a substrate 10, corresponding to FIG. 2.
The substrate 200 provides an operation platform for subsequent processes, and may be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components, such as a die, a wafer processed by an epitaxial growth process, or a circuit layer on which devices are formed. Alternatively, the substrate 200 may include a silicon-on-insulator (SOI) substrate, a bulk silicon (bulk) substrate, a germanium silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate, etc.
And S2, sequentially forming an active region layer 20 and an insulating layer 30 on the substrate 10 along a direction away from the substrate 10, corresponding to FIG. 3.
Specifically, a shallow trench isolation structure STI is formed in the substrate 10 to divide the active region layer 20 in the device region i1 into active regions of a static random access memory structure, and the shallow trench isolation structure STI is also used to electrically isolate the active regions.
Then, ion implantation is carried out on the region to be doped in the active region so as to form a plurality of well regions in the active region. And if the NMOS tube is formed, the well region is doped with P-type ions, and if the PMOS tube is formed, the well region is doped with N-type ions.
It should be noted that, the active region and the polysilicon in the semiconductor detection structure designed in this patent are not ion-implanted.
Finally, an insulating layer 30 is formed on the surface of the substrate 200. Optionally, the insulating layer 30 is formed by a thermal oxidation process, and materials of the oxide layer 30 include silicon dioxide, a high dielectric constant dielectric layer, and the like, so as to be used as a gate dielectric of the static random access memory structure.
And S3, forming a patterned first mask layer 40 on the insulating layer 30, wherein the patterned first mask layer comprises a first window area and a blocking area, and corresponds to FIG. 4. Specifically, the patterned first mask layer 40 is a patterned photoresist layer.
And S4, etching the insulating layer 30 in the first window area by taking the patterned first mask layer 40 as a mask, wherein an etching end point stays on the surface of the active area layer 20, and the first window area is used for representing the area where the cutting channel i2 is located, corresponding to FIG. 5.
And S5, depositing a polysilicon layer 50, which corresponds to FIG. 6. The polysilicon layer 50 is used as the gate of the semiconductor device, and optionally, a low pressure chemical vapor deposition process is used to form polysilicon.
And S6, forming a patterned second mask layer 60 on the polysilicon layer 50, wherein the patterned second mask layer comprises a first pattern area, a second pattern area and a blocking area, and corresponds to FIG. 7.
Specifically, the patterned second mask layer 60 is a patterned photoresist layer.
And S7, etching the polysilicon layer 50 in the first pattern area and the second pattern area by taking the patterned second mask layer 60 as a mask to form the polysilicon grid in the static random access memory structure and the polysilicon subunit in the semiconductor detection structure, wherein the first pattern area is used for representing the pattern of the polysilicon grid in the static random access memory structure, and the second pattern area is used for representing the pattern of the polysilicon subunit in the semiconductor detection structure, and corresponds to FIG. 8.
Specifically, the polysilicon gate comprises polysilicon and an insulating layer between the polysilicon and a substrate, and the polysilicon subunit comprises polysilicon only. Wherein the second graphic region corresponds to the position of the dicing street i 2.
S8, incidence electron beams to all the polysilicon subunits in the semiconductor detection structure.
And S9, judging whether a target polycrystalline silicon subunit exists, wherein the target polycrystalline silicon subunit is a polycrystalline silicon subunit in a first state and is the largest in a first distance which is offset compared with the active region subunit, and the first state is used for representing that the target polycrystalline silicon subunit is in physical contact with the corresponding active region subunit. If the target polysilicon subunit is not present, the process goes to S10, and if the target polysilicon subunit is present, the process goes to S11.
S10, removing the polysilicon gate 50;
S11, obtaining a process window of the polysilicon gate 50 according to the offset distance and the offset direction of the target polysilicon subunit compared with the active region subunit;
And S12, preparing a shared contact hole in the area where the static random access memory structure is located, and performing offset correction on photoetching of the shared contact hole through the process window.
By the technical means, compared with the prior art, the technical scheme of the invention can detect the process window of the shared contact hole in advance with high precision, and judge whether the shared contact hole can be made in advance, thereby avoiding wasting resources. The specific reasons are as follows:
After depositing the polysilicon, etching the polysilicon at the dicing street i2 according to the second pattern area to form the semiconductor detecting structure. Since the insulating layer 30 at the dicing street i2 is etched before the polysilicon is deposited. Thus, the polysilicon subcell in the semiconductor detection structure can be in direct physical contact with the active region subcell.
After the semiconductor inspection structure is manufactured, if the polysilicon gate 50 and the active region layer 20 are offset, so that the active region sub-unit 20 of the polysilicon sub-unit 50 in the reference unit A1 is no longer in physical contact, the polysilicon sub-unit 50 and the active region sub-unit 20 that are originally offset in the inspection unit may be in physical contact due to the offset.
At this time, electron beams are incident to all the polysilicon subunits 50 in the semiconductor inspection structure. For example, the incident electron beam is positively charged. All polysilicon subcells 50 in physical contact with the active region subcell 20 will assume a bright state, i.e., the first state, due to leakage of positive carriers and capturing fewer secondary electrons. All polysilicon subcells 50 that are not in physical contact with the active region subcell 20 will be in a dark state because positive carriers are retained and more secondary electrons are captured. The bright and dark states can be observed by naked eyes, so that the arrangement of an additional machine can be omitted, and the process cost is saved.
Among all the polysilicon subunits 50 exhibiting a bright state, the polysilicon subunit 50 having the largest initial setting offset is selected as the target polysilicon subunit 50. At this time, the original offset parameter of the target polysilicon subunit 50 compared to the corresponding active region subunit 20 may be used as the offset parameter of the polysilicon subunit 50 and the active region subunit 20 in the reference unit A1. Because the positional relationship between the polysilicon sub-unit 50 and the active region sub-unit 20 in the reference unit A1 is the same as the positional relationship between the polysilicon gate 50 and the active region layer 20 in the device region i1, the offset parameters of the polysilicon sub-unit 50 and the active region sub-unit 20 in the reference unit A1, including the offset distance and the offset direction, can be corrected for the photolithography of the shared contact hole when the shared contact hole of the static random access memory structure is subsequently prepared, so as to realize the accurate preparation of the shared contact hole.
If there is no polysilicon subunit 50 in a bright state, which means that the offset between the polysilicon gate 50 and the active region layer 20 exceeds the acceptable maximum range, the polysilicon gate 50 is removed, and the polysilicon gate is manufactured again, thereby realizing advanced determination of whether the shared contact can be manufactured, and avoiding waste of resources.
Of course, the incident electron beam may also be negative, and the polysilicon subunit in physical contact with the active region subunit may be in a dark state due to the outflow of the negative carriers and capturing excessive secondary electrons. The charge of the electron beam may be selected according to the need, and is not limited herein.
It should be noted that the polysilicon subunit is essentially the polysilicon gate 50 disposed in the semiconductor inspection structure in the region of the scribe line i 2. The active area subunit is essentially an active area layer 20 arranged in the semiconductor detection structure in the region of the scribe line i 2.
It should be noted that, the upper and lower limits of the offset distances corresponding to the different detection modules are required to be consistent with the upper limit of the overlay deviation of the polysilicon gate with respect to the active region layer. For example, if the upper limit of the overlay deviation of the polysilicon gate electrode with respect to the active region layer is 20nm, the upper limit of the offset distance of the polysilicon subunit with respect to the active region subunit in the detection unit is also set to 20nm. In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
As a specific embodiment, the insulating layer 30 includes an oxide layer. Of course, under the advanced process node. For example, below 28nm, the insulating layer 30 may include a high-k dielectric layer in addition to the oxide layer. Specific materials of the high-dielectric constant dielectric layer can be set according to requirements, and are not limited herein.
As a specific embodiment, the pattern size of the polysilicon in the first pattern area and the pattern size of the polysilicon subunit are consistent, and the pattern shape of the polysilicon in the first pattern area and the pattern shape of the polysilicon subunit are consistent.
Fig. 10 is a flowchart of implementing step S12 in an embodiment of the present invention.
Referring to fig. 10, as a specific embodiment, in S12, a shared contact hole is prepared in a region where the static random access memory structure is located, and offset correction is performed on lithography of the shared contact hole through the process window, which specifically includes the following steps:
and S121, performing overlay accuracy measurement on the polysilicon gate and the active region layer to obtain an overlay error between the polysilicon gate and the active region layer.
And S122, forming a conductive contact layer, wherein the conductive contact layer is respectively formed on the surfaces of the polysilicon, the source drain region and the active region corresponding to the shared contact hole in the region where the static random access memory structure is located.
In a specific example, the conductive contact layer 103 is made of metal silicide. Specifically, the metal silicide may be cobalt silicide or titanium silicide.
And S123, forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the surface of the substrate and the surface of the polysilicon gate.
And S124, depositing a photoresist layer on the interlayer dielectric layer.
And S125, taking the polysilicon gate as a reference layer, taking the process window as compensation, aligning the photoresist layer before exposure, and carrying out photoetching to form the shared contact hole patterning mask layer.
Specifically, the polysilicon gate is used as a reference layer, the process window is combined as compensation, alignment is performed before exposure is performed on the photoresist layer, alignment marks of the polysilicon gate of the front layer are required to be aligned before the photolithography process is performed on the photoresist, the process window is used as compensation for compensation in the alignment process, alignment is completed, and then photolithography is performed to form the photoresist layer with patterns.
And S126, etching the interlayer dielectric layer to the surfaces of the substrate and the polysilicon gate by taking the patterned photoresist layer as a mask to form a shared contact hole, wherein the shared contact hole penetrates through the interlayer dielectric layer.
Optionally, the etching of the shared contact hole may be completed by using different etching rates or selective ratios, or the etching of the interlayer dielectric layer corresponding to the polysilicon gate electrode is performed first and then the interlayer dielectric layer corresponding to the active region is performed to complete the etching of the shared contact hole, where the etching process of the shared contact hole is not limited, and a person skilled in the art may select a suitable process according to practical situations.
And S127, depositing metal in the shared contact hole to form a shared plug.
Specifically, after the patterned photoresist is removed, the shared contact hole and other contact holes are filled with a metal tungsten material. And (3) covering the surface of the interlayer dielectric layer with a metal tungsten material, and then grinding the metal tungsten material by adopting a chemical mechanical grinding process until the interlayer dielectric 209 is exposed, so that the shared plug and other metal plugs are formed.
As a supplementary explanation, theoretically, the finer the offset distance is divided, the more the detection modules are arranged, the finer the offset direction of the polysilicon subunits is divided, and the more the detection units are arranged in each detection module, the more accurate the process window of the obtained shared contact hole is. However, in consideration of the limited area of the scribe line i2 and the working time of the incident electron beam, it is necessary to divide a certain number of offset distances and offset directions according to actual conditions and sequentially set the corresponding detection units.
The number of electron beam incident polysilicon subunits, i.e. the number of detection units required to be detected, can be adjusted according to different stages. For example, in the early stages of process development, it is necessary to confirm the process window of the shared contact hole, and thus it is necessary to inject electron beams to the polysilicon subcells in all the detection cells. After the process is stable, the offset between the polysilicon gate and the active region layer is basically the same in each process of preparing the static random access memory structure, so that a process window obtained in the initial stage of process development can be directly applied to the preparation of the shared contact hole. However, the actual process window may be changed due to unexpected situations or process errors, so that the detection range may be reduced, that is, the number of electron beams incident on the polysilicon subunits may be reduced, and the specific detection range may be adjusted according to the actual situation, which is not limited herein.
The following describes a specific method for detecting a process window of a shared contact hole by taking an example in which five detection modules are provided and four detection units are provided in each detection module, wherein the offset distances of the detection modules are respectively 12nm, 14nm, 16nm, 18nm and 20 nm.
And setting a conventional XY axis in the direction, and enabling the polycrystalline silicon subunit of the detection unit in each detection module to deviate towards the first quadrant, the second quadrant, the third quadrant and the fourth quadrant respectively relative to the corresponding active region subunit. The specific angles of the offsets toward the first, second, third, and fourth quadrants may be set to 45 °. Of course, more detection units may be provided to increase the deflectable angle.
The electron beam of positive charge is incident on the polysilicon subunits in each detection cell in each detection module.
And finding out each polycrystalline silicon subunit presenting a bright state, and taking the polycrystalline silicon subunit presenting the largest offset distance in the bright state as a target polycrystalline silicon subunit. For example, if the offset distance in the polysilicon sub-unit in the bright state is 18nm at the maximum and is offset by 45 ° toward the third quadrant, the offset parameters of the polysilicon sub-unit and the corresponding active region sub-unit are used as the process window of the shared contact hole.
And if the polycrystalline silicon subunit in the bright state is not found, the polycrystalline silicon grid electrode is removed if the deviation of the polycrystalline silicon grid electrode is excessively large.
In summary, in the method for manufacturing a semiconductor device provided by the embodiment of the invention, an insulation layer on an active region of a designed detection structure is removed, so that a polysilicon subunit in the structure and the active region subunit can be in physical contact. And setting a reference unit A1 and at least four groups of detection modules with different offset distances, wherein each detection module comprises a plurality of detection units, and the polysilicon subunits in the detection units are offset towards different directions by the reference unit A1 according to the corresponding offset distances to serve as reference groups of the polysilicon grid electrode and the active region layer in the device region. And then, the electron beam is incident into the polysilicon subunit, the polysilicon subunit which is in the first state and has the largest offset distance is used as a target polysilicon subunit, and the offset parameter of the target polysilicon subunit relative to the corresponding active region subunit is used as a process window for manufacturing the shared contact hole subsequently. If the target polysilicon subunit is not found, the deviation of the polysilicon gate is too large to prepare the shared contact hole, the polysilicon gate is removed and manufactured again, and the advanced judgment of whether the shared contact hole can be prepared is realized, so that the waste of resources is avoided.
Referring to fig. 9, the technical scheme of the present invention further provides a semiconductor inspection structure, the semiconductor inspection structure is disposed in a scribe line of a wafer, the semiconductor inspection structure includes:
The detection device comprises a reference unit A1 and first detection modules A2 to N detection modules AN, wherein each detection module comprises a first detection unit B1 to AN N detection unit Bn, each reference unit A1 and each detection unit respectively comprises AN active region subunit 20 and a polysilicon subunit 50, the polysilicon subunits 50 are vertically arranged above the active region subunits 20, and one end of each polysilicon subunit 50 is in physical contact with one end of each active region subunit 20, wherein N and N are positive integers, and N and N are more than or equal to 4;
The polysilicon subunits 50 in the detection units in each detection module are respectively offset towards different quadrants by a first distance compared with the corresponding active region subunits 20 by taking the polysilicon subunits 50 in the reference unit A1 as an origin, and the first distances of the different detection units in the same detection module are different from the origin in the different detection modules.
Wherein each of the polysilicon subunits 50 comprises two first polysilicon structures and second polysilicon structures which are relatively parallel and are arranged along the first direction;
each of the active region subunits 20 includes two first and second active region structures that are relatively parallel and each disposed along the second direction.
The second end of the first polysilicon structure is physically connected with the first end of the first active area structure, and the first end of the second polysilicon structure is physically connected with the second end of the second active area structure.
Wherein the first direction and the second direction are perpendicular to each other. Specifically, the first direction may be an X-axis direction, and the second direction may be a Y-axis direction.
The technical scheme of the invention also provides a semiconductor device which comprises the static random access memory structure, and the semiconductor device is prepared by the preparation method of the semiconductor device.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (10)
1. A semiconductor inspection structure disposed within a scribe line of a wafer, the semiconductor inspection structure comprising:
The device comprises a reference unit A1, a first detection module, a second detection module, a third detection module, a fourth detection module, a fifth detection module and a sixth detection module, wherein each detection module comprises a first detection unit, a second detection unit, a third detection unit, a fourth detection unit, a fifth detection unit, a sixth detection unit and a fourth detection unit, each reference unit A1 and each detection unit respectively comprises an active area subunit and a polysilicon subunit, the polysilicon subunits are vertically arranged above the active area subunits, and one end of each polysilicon subunit is in physical contact with one end of each active area subunit; wherein, N and N are positive integers, and N is more than or equal to 4;
The polycrystalline silicon subunits in the detection units in each detection module are respectively offset towards different quadrants by a first distance compared with the corresponding active region subunits by taking the polycrystalline silicon subunits in the reference unit as an origin, and the first distances of the different detection units in the same detection module are different from the origin in the different detection modules;
Each polycrystalline silicon subunit comprises two first polycrystalline silicon structures and second polycrystalline silicon structures which are relatively parallel and are arranged along a first direction;
each active region subunit comprises two first active region structures and second active region structures which are relatively parallel and are arranged along the second direction;
the second end of the first polysilicon structure is physically connected with the first end of the first active area structure, and the first end of the second polysilicon structure is physically connected with the second end of the second active area structure;
the first direction and the second direction are perpendicular to each other.
2. A method for manufacturing a semiconductor device is characterized in that, a method for fabricating a static random access memory structure and the semiconductor test structure of claim 1, the method comprising:
providing a substrate;
Sequentially forming an active region layer and an insulating layer on the substrate along a direction deviating from the substrate;
Forming a patterned first mask layer on the insulating layer, wherein the patterned first mask layer comprises a first window region and a blocking region;
etching the insulating layer in the first window area by taking the patterned first mask layer as a mask, wherein an etching end point stays on the surface of the active area layer, and the first window area is used for representing the area where the cutting channel is located;
depositing a polysilicon layer;
Forming a patterned second mask layer on the polysilicon layer, wherein the patterned second mask layer comprises a first pattern area, a second pattern area and a blocking area;
Etching the polysilicon layer in the first pattern region and the second pattern region by taking the patterned second mask layer as a mask to form a polysilicon gate in the static random access memory structure and the polysilicon subunit in the semiconductor detection structure, wherein the first pattern region is used for representing the pattern of the polysilicon gate in the static random access memory structure, the second pattern region is used for representing the pattern of the polysilicon subunit in the semiconductor detection structure, and the position relationship between the polysilicon gate in the first pattern region and the active region layer is equal to the position relationship between the polysilicon subunit in the reference unit and the active region subunit;
Incident electron beams to all the polysilicon subunits in the semiconductor detection structure;
Judging whether a target polycrystalline silicon subunit exists, wherein the target polycrystalline silicon subunit is a polycrystalline silicon subunit in a first state and is the largest in a first distance which is offset compared with an active region subunit, and the first state is used for representing that the target polycrystalline silicon subunit is in physical contact with a corresponding active region subunit;
If the target polysilicon subunit is present, a process window of the polysilicon gate is obtained according to the offset distance and the offset direction of the target polysilicon subunit compared with the active region subunit;
And preparing a shared contact hole in the region where the static random access memory structure is located, and correcting offset of photoetching of the shared contact hole through the process window.
3. The method of manufacturing a semiconductor device according to claim 2, wherein the insulating layer comprises an oxide layer.
4. The method of manufacturing a semiconductor device according to claim 2, wherein the insulating layer comprises an oxide layer and a high-permittivity dielectric layer.
5. The method of manufacturing a semiconductor device according to claim 2, wherein a pattern size of the polysilicon gate and a pattern size of the polysilicon sub-unit in the first pattern region are both identical, and a pattern shape of the polysilicon gate and a pattern shape of the polysilicon sub-unit in the first pattern region are both identical.
6. The method for manufacturing a semiconductor device according to claim 2, wherein the step of manufacturing a shared contact hole in the region where the static random access memory structure is located and performing offset correction on lithography of the shared contact hole through the process window comprises:
performing overlay accuracy measurement on the polycrystalline silicon grid electrode and the active region layer to obtain an overlay error of the polycrystalline silicon grid electrode and the active region layer;
Forming a conductive contact layer, wherein the conductive contact layer is respectively formed on the surfaces of the polysilicon, the source drain region and the active region corresponding to the shared contact hole in the region where the static random access memory structure is located;
Forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the surface of the substrate and the surface of the polysilicon gate;
Depositing a photoresist layer on the interlayer dielectric layer;
Taking the polysilicon gate as a reference layer, taking the process window as compensation, aligning the photoresist layer before exposure, and carrying out photoetching to form a patterned photoresist layer;
etching the interlayer dielectric layer to the surfaces of the substrate and the polysilicon gate by taking the patterned photoresist layer as a mask to form a shared contact hole, wherein the shared contact hole penetrates through the interlayer dielectric layer;
and filling metal into the shared contact hole to form a shared plug.
7. The method of claim 5, wherein sequentially forming an active region layer and an insulating layer on the substrate in a direction away from the substrate comprises:
Forming a shallow trench isolation structure in the substrate to divide an active region layer in the device region into active regions of a static random access memory structure;
ion implantation is carried out on the region to be doped in the active region so as to form a plurality of well regions in the active region;
and forming an insulating layer on the surface of the substrate.
8. The method of claim 5, wherein the insulating layer is formed using a thermal oxidation process.
9. The method of claim 5, wherein the polysilicon gate comprises polysilicon and an insulating layer between the polysilicon and the substrate, and wherein the polysilicon subunit comprises polysilicon.
10. A semiconductor device comprising a static random access memory structure, the semiconductor device being manufactured by the method of manufacturing a semiconductor device according to any one of claims 2 to 9.
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| CN102376601A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Detection method and structure for deviation of contact hole |
| CN104134619A (en) * | 2014-08-08 | 2014-11-05 | 上海华力微电子有限公司 | Method for detecting alignment degree between polycrystalline silicon and connecting hole through insufficient etching defect |
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| US6855568B2 (en) * | 2001-06-29 | 2005-02-15 | Kla-Tencor Corporation | Apparatus and methods for monitoring self-aligned contact arrays using voltage contrast inspection |
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| CN102376601A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Detection method and structure for deviation of contact hole |
| CN104134619A (en) * | 2014-08-08 | 2014-11-05 | 上海华力微电子有限公司 | Method for detecting alignment degree between polycrystalline silicon and connecting hole through insufficient etching defect |
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