CN119170505A - Semiconductor structure and method of forming the same - Google Patents
Semiconductor structure and method of forming the same Download PDFInfo
- Publication number
- CN119170505A CN119170505A CN202411281671.XA CN202411281671A CN119170505A CN 119170505 A CN119170505 A CN 119170505A CN 202411281671 A CN202411281671 A CN 202411281671A CN 119170505 A CN119170505 A CN 119170505A
- Authority
- CN
- China
- Prior art keywords
- drift region
- shallow trench
- trench isolation
- isolation structure
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a semiconductor structure and a forming method, wherein the forming method of the semiconductor structure comprises the steps of providing a substrate, forming a first shallow trench isolation structure in the substrate, forming a drift region in the substrate, wherein the first shallow trench isolation structure is positioned in the drift region, the drift region comprises a first drift region and a second drift region adjacent to the first drift region, the ion concentration in the first drift region is larger than that in the second drift region, one side and part of the bottom of the first shallow trench isolation structure are positioned in the second drift region, forming a grid structure on the surface of the substrate, wherein the grid structure covers the surface of the second drift region and extends to the surface of part of the first shallow trench isolation structure in the first drift region, expanding the depletion region, enabling an electric field to be distributed evenly as much as possible, improving difficulty of occurrence of avalanche breakdown, greatly improving breakdown voltage, improving quality of the semiconductor structure and having wider application range.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
The lateral diffusion metal oxide semiconductor device (LDMOS, LATERALLY DIFFUSEDMETAL OXIDE SEMICONDUCTOR) is a high-voltage semiconductor device widely applied to the fields of radio frequency base stations, display driving of a plasma display panel (PLASMA DISPLAY PANEL, PDP), power management, automobile electronics and the like. Compared with a conventional insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT), it has a higher response speed and lower leakage current, and has a greater advantage in terms of process integration as a planar device. A shallow trench isolation (shallow trench isolation, STI) region is added in a drift region of a traditional LDMOS device, so that the breakdown voltage of the high-voltage device can be effectively improved, the on-state resistance of the device is improved, and the STI type LDMOS device is widely applied. Because in most applications the drain terminal often needs to be connected to a high voltage, the effect of hot carrier effects is very pronounced. In the field of device reliability, the density and location information of interface traps plays an important role in device reliability.
The drain-source breakdown voltage BVDS (Drain to Source Breakdown Voltage, BV) is an important parameter of the LDMOS and is also an important aspect of the reliability of the LDMOS device. Although LDMOS has a drift region with low doping, which makes it have a higher breakdown voltage than other MOS devices, with the social development of high voltage and high power, it is necessary to increase the breakdown voltage of LDMOS devices.
STI is added in the drift region of the traditional LDMOS device, so that the breakdown voltage of the LDMOS device can be effectively improved, and therefore the LDMOS device with the STI is widely applied. However, the power LDMOS device has a limitation relationship of "silicon limit". The on-resistance increases while the LDMOS device is being improved. The on-resistance of the LDMOS device is greatly increased while the breakdown voltage is improved by using the STI type LDMOS device.
The performance of the current LDMOS device needs to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which aims to improve the performance of the semiconductor structure.
In order to solve the problems, the invention provides a method for forming a semiconductor structure, which comprises the steps of providing a substrate, forming a first shallow trench isolation structure in the substrate, forming a drift region in the substrate, wherein the first shallow trench isolation structure is positioned in the drift region, the drift region comprises a first drift region and a second drift region adjacent to the first drift region, the ion concentration in the first drift region is larger than that in the second drift region, one side and part of the bottom of the first shallow trench isolation structure are positioned in the second drift region, and forming a grid structure on the surface of the substrate, wherein the grid structure covers the surface of the second drift region and extends to the surface of part of the first shallow trench isolation structure in the first drift region.
Optionally, the ion type in the first drift region is the same as the ion type in the second drift region, and the width of the first drift region in the first direction is greater than the width of the second drift region in the first direction, and the first direction is parallel to the channel direction.
Optionally, a width of the first shallow trench isolation structure in the second drift region is smaller than a width of the first shallow trench isolation structure in the first drift region, and a direction of the width is parallel to a channel direction.
Optionally, a ratio of a width of the first shallow trench isolation structure in the second drift region to a width of the first shallow trench isolation structure in the first drift region ranges from 0.2:1 to 0.4:1, and a direction of the width is parallel to a channel direction.
Optionally, the method for forming the drift region comprises the steps of forming a first mask layer on the surface of a substrate, forming a first mask layer opening in the first mask layer, exposing part of the top surface of the first shallow trench isolation structure and part of the surface of the substrate on one side of the first shallow trench isolation structure at the bottom of the first mask layer opening, performing first ion implantation on the exposed surface of the substrate and the exposed substrate on the bottom of the first shallow trench isolation structure to form the first drift region, removing the first mask layer, forming a second mask layer on the surface of the substrate, forming a second mask layer opening in the second mask layer, exposing the top surface of the first shallow trench isolation structure outside the first drift region and the surface of the substrate on one side of the first shallow trench isolation structure and adjacent to the first drift region at the bottom of the first shallow trench isolation structure at the bottom of the second mask layer opening, performing second ion implantation on the exposed surface of the substrate and the first shallow trench isolation structure and the substrate on the bottom of the first shallow trench isolation structure, forming the second drift region and the second drift region adjacent to the first drift region, and forming the first drift region and the second drift region adjacent to the first drift region.
Optionally, the process parameters of the first ion implantation include that the element of ion implantation is phosphorus, the doping amount of ion implantation is about 4E12 atoms/cm 2-5E12atom/cm2, and the energy of ion implantation is about 100Kev-200Kev.
Optionally, the process parameters of the second ion implantation include that the ion implanted element is phosphorus, the ion implanted dopant amount is about 2E12 atoms/cm 2-3E12atom/cm2, and the ion implanted energy is about 100Kev-200Kev.
Optionally, after the gate structure is formed, a body doped region is formed in the substrate at one side of the gate structure, and the body doped region and the first drift region are located at two sides of the second drift region.
Optionally, the ion type in the drift region is opposite to the ion type of the bulk doped region.
Optionally, the method further comprises the steps of forming first source-drain doped regions in the drift region and the body doped regions at two sides of the gate structure, and forming second source-drain doped regions in the body doped regions between adjacent first source-drain doped regions.
Correspondingly, the invention further provides a semiconductor structure, which comprises a substrate, a first shallow trench isolation structure located in the substrate, a drift region located in the substrate, wherein the first shallow trench isolation structure is located in the drift region, the drift region comprises a first drift region and a second drift region adjacent to the first drift region, the ion concentration in the first drift region is larger than that in the second drift region, one side and part of the bottom of the first shallow trench isolation structure are located in the second drift region, and a grid structure located on the surface of the substrate covers the surface of the second drift region and extends to the surface of part of the first shallow trench isolation structure in the first drift region.
Optionally, a width of the first drift region in a first direction is greater than a width of the second drift region in the first direction, and the first direction is parallel to a channel direction.
Optionally, the width of the first shallow trench isolation structure in the second drift region is smaller than the width of the first shallow trench isolation structure in the first drift region, the ratio of the width of the first shallow trench isolation structure in the second drift region to the width of the first shallow trench isolation structure in the first drift region ranges from 0.2:1 to 0.4:1, and the direction of the width is parallel to the channel direction.
Compared with the prior art, the technical scheme of the invention has the following advantages:
In the method for forming the semiconductor structure, a substrate is provided, a first shallow trench isolation structure is formed in the substrate, a drift region is formed in the substrate, the first shallow trench isolation structure is positioned in the drift region, the drift region comprises a first drift region and a second drift region, the ion concentration in the first drift region is larger than that in the second drift region, one side wall and part of the bottom of the shallow first trench isolation structure are positioned in the second drift region, a grid structure is formed on the surface of the substrate of the part of the drift region, the grid structure covers the second drift region and extends to the surface of the part of the first shallow trench isolation structure in the first drift region, the concentration of injected ions in the second drift region is reduced, the bearing voltage of a contact region between the first shallow trench isolation structure at the bottom of the grid structure and the second drift region is reduced, the broadening of a depletion region is increased, an electric field is distributed as evenly as possible, the difficulty of avalanche breakdown is increased, the breakdown voltage is greatly increased, the quality of the semiconductor structure is improved, and the semiconductor structure is wide in application range.
Drawings
FIG. 1 is a cross-sectional view of a semiconductor structure in one embodiment;
FIG. 2 shows an electric field distribution of a semiconductor structure according to an embodiment;
FIGS. 3-9 are schematic views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention;
Fig. 10 is an electric field distribution diagram of a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As described in the background, the performance of the existing semiconductor structure is poor, and the detailed description is given with reference to fig. 1 and 2.
Referring to fig. 1, the semiconductor structure includes a substrate 100, shallow trench isolation structures 101 located in the substrate 100, a drift region 102 located in the substrate 100, at least one shallow trench isolation structure 101 located in the drift region 102 and extending to a portion of the bottom of an adjacent shallow trench isolation structure, a body doped region 104 formed in the substrate 100, a gate structure 103 formed on the substrate 100, the gate structure 103 located on a top surface of the shallow trench isolation structure of the portion of the drift region and the gate structure 103 also located on a surface of the substrate 100 between the body doped region 104 and the drift region 102, and source/drain doped regions 105 formed by doping the substrate 100 on both sides of the gate structure 103.
The inventors found that in such a semiconductor structure, the contact region between the shallow trench isolation structure at the bottom of the gate structure and the drift region is a region where the electric field is concentrated (dotted circle in the figure), and impact ionization easily occurs, so that avalanche breakdown occurs, and the quality of the semiconductor structure is reduced, and the breakdown voltage BV is 55v and rsp is 37 according to fig. 2.
The inventor finds that, through researches, a substrate is provided, a first shallow trench isolation structure is formed in the substrate, a drift region is formed in the substrate, the first shallow trench isolation structure is located in the drift region, the drift region comprises a first drift region and a second drift region, the ion concentration in the first drift region is larger than that in the second drift region, one side wall and part of the bottom of the shallow first trench isolation structure are located in the second drift region, a grid structure is formed on the surface of the substrate of the part of the drift region, the grid structure covers the second drift region and extends to the surface of the part of the first shallow isolation trench structure in the first drift region, the means of reducing the concentration of injected ions in the second drift region is adopted, the bearing voltage of a contact region between the first shallow trench isolation structure at the bottom of the grid structure and the second drift region is reduced, the broadening of a depletion region is increased, an electric field is distributed as evenly as possible, the difficulty of avalanche breakdown is increased, the breakdown voltage is greatly increased, the quality of the semiconductor structure is improved, and the semiconductor structure is wide in application range.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 3 to 9 are schematic views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Referring to fig. 3, a substrate 200 is provided.
In this embodiment, the material of the substrate 200 is silicon.
In other embodiments, the material of the substrate 200 may further include semiconductor materials such as single crystal silicon, polycrystalline silicon, amorphous silicon, germanium, silicon germanium, gallium arsenide, and the like.
In this embodiment, the substrate 200 is a P-type substrate 200.
With continued reference to fig. 3, the substrate 200 is etched to form a first shallow trench 201 in the substrate 200.
In this embodiment, in addition to forming the first shallow trench 201, a plurality of shallow trenches, for example, fig. 3, are formed in the process of etching the substrate 200, and a second shallow trench 202 is also formed in the substrate 200.
In the present embodiment, the formation of two shallow trenches is shown.
Referring to fig. 4, an isolation layer is filled in the first shallow trench 201 to form a first shallow trench isolation structure 203.
In this embodiment, the second shallow trench 202 is filled simultaneously with the first shallow trench 201, and a second shallow trench isolation structure 204 is formed in the second shallow trench 202.
In this embodiment, the method of forming the first and second shallow trench isolation structures 203 and 204 includes forming an isolation structure film (not shown) on the substrate 200, etching back the isolation structure film, and forming the first and second shallow trench isolation structures 203 and 204.
The process of forming the isolation structure film is a deposition process, such as a fluid chemical vapor deposition process. The isolation structure film is formed by adopting a fluid chemical vapor deposition process, so that the filling performance of the isolation structure film is better.
In this embodiment, the material of the isolation layer includes silicon oxide.
In this embodiment, after the shallow trench is filled with the isolation layer, the isolation layer is planarized until the surface is flush with the surface of the substrate 200.
The process of forming the drift region in the substrate 200 is illustrated in fig. 5-6.
Referring to fig. 5, a first mask layer (not shown) is formed on the surface of the substrate 200, and a first mask layer opening (not shown) is formed in the first mask layer, wherein a bottom of the first mask layer opening exposes a portion of a top surface of the first shallow trench isolation structure 203 and a portion of a surface of the substrate 200 on one side of the first shallow trench isolation structure 203.
Specifically, the first mask layer opening exposes a portion of the top surface of the first shallow trench isolation structure 203, a portion of the top surface of the second shallow trench isolation structure 204, and a surface of the substrate 200 between the first shallow trench isolation structure 203 and the second shallow trench isolation structure 204, and a size of the first shallow trench isolation structure 203 exposed by the first mask layer opening is larger than a size of the second shallow trench isolation structure 204 exposed by the first mask layer opening.
In this embodiment, the first drift region 205 is formed by performing a first ion implantation on the exposed surface of the substrate 200 and the exposed bottom of the first shallow trench isolation structure 203.
In this embodiment, after the first drift region 205 is formed, the first mask layer is removed.
In this embodiment, the material of the first mask layer is photoresist.
In other embodiments, the material of the first mask layer may also be a hard mask layer of silicon oxide, silicon nitride, or the like.
In this embodiment, the ion type of the first ion implantation is N-type ion.
In other embodiments, the ion type of the first ion implantation may also be P-type ions.
In this embodiment, the process parameters of the first ion implantation include that the ion implanted element is phosphorus, the ion implanted dopant amount is about 4E12 atoms/cm 2 to 5E12 atoms/cm 2, and the ion implanted energy is about 100Kev to 200Kev.
In this embodiment, the process of removing the first mask layer is an ashing process.
In other embodiments, the process of removing the first mask layer may be a wet etching process or the like.
Referring to fig. 6, a second mask layer (not shown) is formed on the surface of the substrate 200, and a second mask layer opening (not shown) is formed in the second mask layer, wherein the bottom of the second mask layer opening exposes the top surface of the first shallow trench isolation structure 203 outside the first drift region 205 and a portion of the surface of the substrate 200 located on one side of the first shallow trench isolation structure 203 and adjacent to the first drift region 205.
In this embodiment, the material of the second mask layer is photoresist.
In this embodiment, a second ion implantation is performed on the exposed surface of the substrate 200 and the substrate 200 at the bottom of the first shallow trench isolation structure 203 to form the second drift region 206, where the first drift region 205 and the second drift region 206 form the drift region, the first drift region 205 and the second drift region 206 are adjacent, and the first shallow trench isolation structure 203 is located in the drift region.
In this embodiment, the ion type of the second ion implantation is N-type.
In other embodiments, the ion type of the second ion implantation may also be P-type.
In this embodiment, the ion type of the first ion implantation is the same as the ion type of the second ion implantation.
In this embodiment, the width (a 2) of the first shallow trench isolation structure 203 in the first direction in the second drift region 206 is smaller than the width (a 1) of the first shallow trench isolation structure 203 in the first direction in the first drift region 205, which is designed to relieve the density of potential lines at the junction between the right side of the first shallow trench isolation structure 203 and the gate and at the lower right corner of the first shallow trench isolation structure 203, so as to relieve the peak electric field strength at these positions and improve the breakdown voltage of the device.
In this embodiment, the ratio of the width (a 2) of the first shallow trench isolation structure 203 in the first direction in the second drift region 206 to the width (a 1) of the first shallow trench isolation structure 203 in the first direction in the first drift region 205 is in the range of 0.2:1-0.4:1, and the first direction is parallel to the channel direction.
In this embodiment, the process parameters of the second ion implantation include that the ion implanted element is phosphorus, the ion implanted dopant amount is about 2E12 atoms/cm 2-3E12atom/cm2, and the ion implanted energy is about 100Kev-200Kev.
In this embodiment, the ion concentration of the first drift region 205 is greater than the ion concentration in the second drift region 206.
Referring to fig. 7, a gate structure 207 is formed on the substrate 200, wherein the gate structure 207 covers the surface of the second drift region 206 and extends to a portion of the surface of the first shallow trench isolation structure 203 in the first drift region 205.
In this embodiment, the concentration of ions in the second drift region 206 is smaller than that in the first drift region 205, so as to reduce the bearing voltage in the contact region between the shallow trench isolation structure at the bottom of the gate structure 207 and the second drift region 206, increase the broadening of the depletion region, make the electric field be distributed as evenly as possible, and increase the difficulty of avalanche breakdown, thereby greatly increasing the breakdown voltage, improving the quality of the semiconductor structure, and having a wider application range.
In this embodiment, the gate structure 207 includes a gate oxide layer 207b formed on the surface of the substrate 200 and a gate layer 207a formed on the surface of the gate oxide layer 207b, where the material of the gate layer 207a is polysilicon.
In an embodiment, a sidewall 207c is further formed on the sidewall of the gate structure 207.
Referring to fig. 8, a body doped region 208 is formed in the substrate 200 at one side of the gate structure 207, and the body doped region 208 and the first drift region 205 are located at two sides of the second drift region 206.
In this embodiment, the type of ions doped in the bulk doped region 208 is opposite to the type of ions doped in the drift region.
In this embodiment, the ion type in the drift region is N-type, and the ion type in the body doped region 208 is P-type.
In this embodiment, the doping depth of the drift region and the bulk doping region 208 is the same.
Referring to fig. 9, the method further includes forming a first source-drain doped region 209 in the drift region and the body doped region 208 at both sides of the gate structure 207, and forming a second source-drain doped region 210 in the body doped region 208 between adjacent first source-drain doped regions 209.
In this embodiment, the ion type in the first source-drain doped region 209 is the same as the ion type in the first drift region 205.
In this embodiment, the ion type in the second source-drain doped region 210 is opposite to the ion type in the first source-drain doped region 209.
In this embodiment, please refer to fig. 10, after an electric field is applied to the semiconductor structure formed by the method, the breakdown voltage BV is 69v, rsp is 39, the difficulty of avalanche breakdown of the semiconductor structure is greatly improved, the BVDS of the LDMOS is greatly improved under the condition that the Rsp change is very small, the depletion region of the LDMOS is widened and greatly improved through optimized IMP injection, the electric field distribution is more even, the optimized electric field is more beneficial to the reliability of the device of the LDMOS, and no new process step is introduced, but the original photomask for forming the drift region is split into 2 photomasks for separate injection, so that the cost change is not great, and the method has a wider application range.
Rsp means specific on-resistance, which relates resistance to area, and is a normalized quantity used to eliminate the effect of the difference in area between resistance on performance, and represents the relationship between resistance and area in on state in mohm mm 2.
Referring to fig. 9, the present invention further provides a semiconductor structure, which includes a substrate 200, a first shallow trench isolation structure 203 located in the substrate 200, a drift region located in the substrate 200, wherein the first shallow trench isolation structure 203 is located in the drift region, the drift region includes a first drift region 205 and a second drift region 206 adjacent to the first drift region 205, an ion concentration in the first drift region 205 is greater than an ion concentration in the second drift region 206, one side and a part of a bottom of the first shallow trench isolation structure 203 are located in the second drift region 206, and a gate structure 207 located on a surface of the substrate 200, wherein the gate structure 207 covers a surface of the second drift region 206 and extends to a surface of the first shallow trench isolation structure 203 in the first drift region 205.
In this embodiment, the width of the first drift region 205 in the first direction is greater than the width of the second drift region 206 in the first direction, and the first direction is parallel to the channel direction.
In this embodiment, the width of the first shallow trench isolation structure 203 in the first direction in the second drift region 206 is smaller than the width of the first shallow trench isolation structure 203 in the first direction in the first drift region 205.
In this embodiment, the ratio of the width of the first shallow trench isolation structure 203 in the first direction in the second drift region 206 to the width of the first shallow trench isolation structure 203 in the first direction in the first drift region 205 is in the range of 0.2:1-0.4:1, and the first direction is parallel to the channel direction.
In this embodiment, the method further includes a sidewall on the sidewall of the gate structure 207.
In this embodiment, the body doped region 208 is located in the substrate 200 at one side of the gate structure 207, and the body doped region 208 and the first drift region 205 are located at two sides of the second drift region 206.
In this embodiment, the type of ions doped in the bulk doped region 208 is opposite to the type of ions doped in the drift region.
In this embodiment, the ion type in the drift region is N-type, and the ion type in the body doped region 208 is P-type.
In this embodiment, the doping depth of the drift region and the bulk doping region 208 is the same.
In this embodiment, the device further includes a first source-drain doped region 209 located in the drift region and the body doped region 208 at two sides of the gate structure 207, and a second source-drain doped region 210 located between adjacent first source-drain doped regions 209 and located in the body doped region 208.
In this embodiment, the type of ion doping in the first source-drain doped region 209 is opposite to the type of ion doping in the second source-drain doped region 210.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (13)
1. A method of forming a semiconductor structure, comprising:
providing a substrate;
Forming a first shallow trench isolation structure in the substrate;
Forming a drift region in the substrate, wherein the first shallow trench isolation structure is positioned in the drift region, the drift region comprises a first drift region and a second drift region adjacent to the first drift region, the ion concentration in the first drift region is larger than that in the second drift region, and one side and part of the bottom of the first shallow trench isolation structure are positioned in the second drift region;
And forming a gate structure on the surface of the substrate, wherein the gate structure covers the surface of the second drift region and extends to the surface of a part of the first shallow trench isolation structure in the first drift region.
2. The method of forming a semiconductor structure of claim 1, wherein a type of ions in the first drift region is the same as a type of ions in the second drift region, a width of the first drift region in a first direction being greater than a width of the second drift region in the first direction, the first direction being parallel to a channel direction.
3. The method of claim 1, wherein a width of the first shallow trench isolation structure in the second drift region is smaller than a width of the first shallow trench isolation structure in the first drift region, the width being parallel to a channel direction.
4. The method of claim 1, wherein a ratio of a width of the first shallow trench isolation structure in the second drift region to a width of the first shallow trench isolation structure in the first drift region is in a range of 0.2:1-0.4:1, the direction of the width being parallel to a channel direction.
5. The method of forming a semiconductor structure of claim 1, wherein the method of forming the drift region comprises:
forming a first mask layer on the surface of the substrate, wherein a first mask layer opening is formed in the first mask layer, and the bottom of the first mask layer opening exposes part of the top surface of the first shallow trench isolation structure and part of the surface of the substrate on one side of the first shallow trench isolation structure;
performing first ion implantation on the exposed surface of the substrate and the exposed substrate at the bottom of the first shallow trench isolation structure to form the first drift region;
Removing the first mask layer;
Forming a second mask layer on the surface of the substrate, wherein a second mask layer opening is formed in the second mask layer, and the bottom of the second mask layer opening exposes the top surface of the first shallow trench isolation structure outside the first drift region and the surface of a part of the substrate which is positioned on one side of the first shallow trench isolation structure and adjacent to the first drift region;
and performing second ion implantation on the exposed surface of the substrate and the substrate at the bottom of the first shallow trench isolation structure to form a second drift region, wherein the first drift region and the second drift region form the drift region, the first drift region and the second drift region are adjacent, and the first shallow trench isolation structure is positioned in the drift region.
6. The method of claim 5, wherein the first ion implantation process parameters include that the ion implanted element is phosphorus, the ion implantation dopant amount is about 4E12 atoms/cm 2-5E12atom/cm2, and the ion implantation energy is about 100Kev to 200Kev.
7. The method of claim 5, wherein the process parameters of the second ion implantation include that the ion implanted element is phosphorus, the ion implanted dopant amount is about 2E12 atoms/cm 2-3E12atom/cm2, and the ion implantation energy is about 100Kev to 200Kev.
8. The method of forming a semiconductor structure of claim 1, further comprising, after forming the gate structure:
And forming a body doping region in the substrate at one side of the gate structure, wherein the body doping region and the first drift region are positioned at two sides of the second drift region.
9. The method of forming a semiconductor structure of claim 8, wherein an ion type within the drift region is opposite to an ion type of the bulk doped region.
10. The method of forming a semiconductor structure of claim 8, further comprising forming first source drain doped regions in said drift region and said body doped regions on opposite sides of said gate structure, and forming second source drain doped regions in said body doped regions between adjacent said first source drain doped regions.
11. A semiconductor structure, comprising:
A substrate;
a first shallow trench isolation structure located within the substrate;
The first shallow trench isolation structure is positioned in the drift region, the drift region comprises a first drift region and a second drift region adjacent to the first drift region, the ion concentration in the first drift region is larger than that in the second drift region, and one side and part of the bottom of the first shallow trench isolation structure are positioned in the second drift region;
and the grid structure is positioned on the surface of the substrate, covers the surface of the second drift region and extends to the surface of part of the first shallow trench isolation structure in the first drift region.
12. The semiconductor structure of claim 11, wherein a width of the first drift region in a first direction is greater than a width of the second drift region in the first direction, the first direction being parallel to a channel direction.
13. The semiconductor structure of claim 11, wherein a width of the first shallow trench isolation structure within the second drift region is less than a width of the first shallow trench isolation structure within the first drift region, a ratio of the width of the first shallow trench isolation structure within the second drift region to the width of the first shallow trench isolation structure within the first drift region ranges from 0.2:1 to 0.4:1, the direction of the width being parallel to a channel direction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411281671.XA CN119170505B (en) | 2024-09-12 | 2024-09-12 | Semiconductor structure and forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411281671.XA CN119170505B (en) | 2024-09-12 | 2024-09-12 | Semiconductor structure and forming method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN119170505A true CN119170505A (en) | 2024-12-20 |
| CN119170505B CN119170505B (en) | 2025-10-17 |
Family
ID=93886849
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202411281671.XA Active CN119170505B (en) | 2024-09-12 | 2024-09-12 | Semiconductor structure and forming method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN119170505B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101777582A (en) * | 2010-01-12 | 2010-07-14 | 上海宏力半导体制造有限公司 | LDMOS device capable of improving grid oxygen reliability and manufacture method thereof |
| CN107731918A (en) * | 2016-08-12 | 2018-02-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and its manufacture method |
| CN111509044A (en) * | 2019-01-31 | 2020-08-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and method of forming the same |
| CN113517338A (en) * | 2020-04-10 | 2021-10-19 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor structure and method of forming the same |
| CN116137292A (en) * | 2021-11-17 | 2023-05-19 | 无锡华润上华科技有限公司 | LDMOS device and its manufacturing method |
| US20240222501A1 (en) * | 2022-12-28 | 2024-07-04 | United Microelectronics Corp. | Semiconductor Device and Fabricating Method Thereof |
-
2024
- 2024-09-12 CN CN202411281671.XA patent/CN119170505B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101777582A (en) * | 2010-01-12 | 2010-07-14 | 上海宏力半导体制造有限公司 | LDMOS device capable of improving grid oxygen reliability and manufacture method thereof |
| CN107731918A (en) * | 2016-08-12 | 2018-02-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and its manufacture method |
| CN111509044A (en) * | 2019-01-31 | 2020-08-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and method of forming the same |
| CN113517338A (en) * | 2020-04-10 | 2021-10-19 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor structure and method of forming the same |
| CN116137292A (en) * | 2021-11-17 | 2023-05-19 | 无锡华润上华科技有限公司 | LDMOS device and its manufacturing method |
| US20240222501A1 (en) * | 2022-12-28 | 2024-07-04 | United Microelectronics Corp. | Semiconductor Device and Fabricating Method Thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN119170505B (en) | 2025-10-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7033891B2 (en) | Trench gate laterally diffused MOSFET devices and methods for making such devices | |
| JP3954493B2 (en) | A method of manufacturing a power MOSFET using a power MOSFET and a self-aligned body injection process. | |
| US6316806B1 (en) | Trench transistor with a self-aligned source | |
| TWI475614B (en) | Ditch installation structure and manufacturing | |
| US7928508B2 (en) | Disconnected DPW structures for improving on-state performance of MOS devices | |
| CN102751195A (en) | Lateral transistor and manufacturing method thereof | |
| US8067289B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN113206145A (en) | Power semiconductor device with improved hot carrier injection | |
| CN103035730A (en) | Radio frequency laterally diffused metal oxide semiconductor (LDMOS) device and manufacturing method thereof | |
| WO2003003452A2 (en) | Field-effect transistor and method of making the same | |
| US10217828B1 (en) | Transistors with field plates on fully depleted silicon-on-insulator platform and method of making the same | |
| KR20060006171A (en) | High frequency MOS transistor, method for forming same and method for manufacturing semiconductor device | |
| US6762458B2 (en) | High voltage transistor and method for fabricating the same | |
| US8575688B2 (en) | Trench device structure and fabrication | |
| KR101530579B1 (en) | Semiconductor device and manufacturing method thereof | |
| CN103311272A (en) | Lateral mosfet with dielectric isolation trench | |
| US11652170B2 (en) | Trench field effect transistor structure free from contact hole | |
| CN119170505B (en) | Semiconductor structure and forming method | |
| CN112054061B (en) | Body contact structure of partially depleted silicon on insulator and manufacturing method thereof | |
| US11545396B2 (en) | Semiconductor structure and method for forming the same | |
| KR100300189B1 (en) | Horizontal type silicon on insulator bipolar mode field effect transistor and method for forming the same | |
| KR102456758B1 (en) | High voltage semiconductor device and manufacturing method thereof | |
| KR100464535B1 (en) | A method for forming a transistor of a semiconductor device | |
| KR20050104163A (en) | High voltage transistor and method of fabricating the same | |
| KR100521994B1 (en) | Trench gate type MOS transistor and its manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |