CN119136650A

CN119136650A - A superconducting quantum chip, quantum computer and manufacturing method

Info

Publication number: CN119136650A
Application number: CN202411249894.8A
Authority: CN
Inventors: 俞杰勋; 方君鹏; 胡杨; 王谦; 蔡坚
Original assignee: Tsinghua University
Current assignee: Tsinghua University
Priority date: 2024-09-06
Filing date: 2024-09-06
Publication date: 2024-12-13

Abstract

The invention provides a superconducting quantum chip, a quantum computer and a manufacturing method of the superconducting quantum chip, wherein the superconducting quantum chip comprises a chip module and a first heat dissipation layer, the chip module comprises a core particle layer and a substrate, and the substrate is connected with the core particle layer through convex points; the core particle layer is connected with the first heat dissipation layer through a first bonding layer. According to the superconducting quantum chip, the quantum computer and the manufacturing method of the superconducting quantum chip, the first heat dissipation layer is arranged on the core particle layer, so that the effective heat exchange area is increased, and the heat dissipation efficiency of the superconducting quantum chip is improved.

Description

Superconducting quantum chip, quantum computer and manufacturing method

Technical Field

The invention relates to the technical field of semiconductors, in particular to a superconducting quantum chip, a quantum computer and a manufacturing method of the superconducting quantum chip.

Background

At present, quantum computing schemes with high low temperature requirements comprise superconducting, topological and semiconductor quantum computing. Taking superconducting quantum computation as an example, the energy level difference of the quantum bit from the ground state to the first excited state is small, and in order to keep the stability of the quantum state, the noise fluctuation amplitude in the environment is required to be far lower than the energy level difference, and further the superconducting quantum chip is required to be in service in an mK-level extremely low-temperature environment.

For the quantum computing schemes described above, the operation of the quantum computer needs to be performed in very low temperature environments, typically using a dilution refrigerator to achieve low temperature conditions. The cooling process of the dilution refrigerator is very slow, often needs to last for a plurality of days, part of joule heat continuously generated by an electrical structure which does not enter a superconducting state or has no superconducting characteristic can further prolong the cooling time and influence the stability of the electrical structure which enters the superconducting state, so that the superconducting quantum chip in the quantum computer is rapidly cooled, the dilution refrigerator can reach the mK-level working temperature more rapidly, and the quantum computer can be stably and reliably operated.

Therefore, how to solve the heat dissipation problem of superconducting quantum chips, especially complex quantum chips adopting three-dimensional integrated architecture, is an important issue in the art.

Disclosure of Invention

Aiming at the problems in the prior art, the embodiment of the invention provides a superconducting quantum chip, a quantum computer and a manufacturing method of the superconducting quantum chip, which can at least partially solve the problems in the prior art.

In a first aspect, the present invention provides a superconducting quantum chip, including a chip module and a first heat dissipation layer, wherein:

the chip module comprises a core particle layer and a substrate, wherein the substrate is connected with the core particle layer through bumps;

The core particle layer is connected with the first heat dissipation layer through a first bonding layer.

Further, the superconducting quantum chip provided by the embodiment of the invention further comprises a crystal back layer, wherein the crystal back layer is connected with the substrate, and the thermal expansion coefficient of the substrate is larger than that of the crystal back layer and that of the first heat dissipation layer.

Further, the superconducting quantum chip provided by the embodiment of the invention further comprises a second heat dissipation layer, and the second heat dissipation layer is connected with the crystal back layer through a second bonding layer.

Further, the superconducting quantum chip provided by the embodiment of the invention further comprises a base, and the base is connected with the second heat dissipation layer.

Further, a second transition layer is disposed between the base and the second heat sink layer.

Further, the base wraps at least a portion of the structure from the substrate to the base.

Further, a thermoelectric region is disposed between the base and the wrapped structure.

Further, the crystal back layer comprises an optical waveguide area, the optical waveguide area is connected with the off-chip optical fiber through a first coupler, a photonic integrated chip bridging structure is arranged on the substrate and connected with the corresponding convex points, a second coupler corresponding to the photonic integrated chip bridging structure is arranged in the optical waveguide area, and the second coupler is used for realizing optical signal transmission of the photonic integrated chip bridging structure and the optical waveguide area.

Further, the superconducting quantum chip provided by the embodiment of the invention further comprises a first transition layer, and the first transition layer is connected with the first heat dissipation layer.

Further, the core particle layer is provided with a plurality of heat dissipation parts, each heat dissipation part is in contact with the first bonding layer, and the heat dissipation parts are filled with heat conducting materials.

Further, an electrical interconnection line is provided on the substrate, a first end of the electrical interconnection line is connected to the bump, and a second end of the electrical interconnection line is connected to the coaxial line through a lead.

In a second aspect, the present invention provides a quantum computer, including the superconducting quantum chip and the dilution refrigerator according to any one of the embodiments, where the dilution refrigerator includes a first cold plate and a second cold plate, and the superconducting quantum chip is disposed between the first cold plate and the second cold plate and is in contact with the first cold plate and the second cold plate, respectively.

In a third aspect, the present invention provides a method of manufacturing a superconducting quantum chip, comprising:

Manufacturing each core particle;

Obtaining a first assembly based on each core particle and a first heat dissipation layer, wherein the first assembly comprises the first heat dissipation layer and a core particle layer formed by each core particle;

obtaining a second component based on the substrate material, the second component comprising a substrate;

Preparing salient points on each core particle of the core particle layer, and manufacturing salient points corresponding to the salient points of each core particle on the substrate;

and integrating the first component and the second component based on the salient points on the core grains of the core grain layer and the salient points on the substrate to obtain the superconducting quantum chip.

Further, the making each core particle includes:

And punching holes at a preset position on the side of the core particle opposite to the first heat dissipation layer, and filling a heat conduction material to form the heat dissipation part.

Further, the obtaining a first component based on each core particle and the first heat dissipation layer material includes:

sputtering metal nano particles on one side surface of the first heat dissipation layer, and sputtering metal nano particles on one side surface of each core particle;

And bonding the surface of the first heat dissipation layer with the metal nano particles with the surface of each core particle with the metal nano particles at a preset temperature to obtain the first component.

Further, the manufacturing method of the superconducting quantum chip provided by the embodiment of the invention further comprises the following steps:

And manufacturing a first transition layer on the first heat dissipation layer.

Further, the second component further comprises a crystalline back layer, and correspondingly, the obtaining the second component based on the substrate material comprises:

Manufacturing a substrate based on the substrate-based material;

and manufacturing a crystal back layer on the substrate, wherein the thermal expansion coefficient of the substrate is larger than that of the crystal back layer and that of the first heat dissipation layer.

Further, the second component further comprises a second heat dissipation layer, and correspondingly, the obtaining the second component further comprises:

Sputtering metal nano-particles on the surface of the nonfunctional area of the crystal back layer, and sputtering metal nano-particles on the surface of the corresponding area on one side of the second heat dissipation layer;

And bonding the surface of the second heat dissipation layer with the metal nano particles with the surface of the non-functional area of the crystal back layer with the metal nano particles.

and manufacturing a second transition layer on the surface of the second heat dissipation layer.

Further, the fabricating a crystalline back layer on the substrate includes:

And manufacturing an optical waveguide area on the crystal back layer.

An integral structure comprising the first component and the second component is disposed onto a base.

The superconducting quantum chip, the quantum computer and the manufacturing method of the superconducting quantum chip provided by the embodiment of the invention comprise a chip module and a first heat dissipation layer, wherein the chip module comprises a core particle layer and a substrate, the substrate is connected with the core particle layer through convex points, the core particle layer is connected with the first heat dissipation layer through a first bonding layer, and the first heat dissipation layer is arranged on the core particle layer, so that the effective heat exchange area is increased, and the heat dissipation efficiency of the superconducting quantum chip is improved.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. In the drawings:

Fig. 1 is a schematic structural diagram of a superconducting quantum chip according to a first embodiment of the present invention.

Fig. 2 is a schematic structural diagram of a superconducting quantum chip according to a second embodiment of the present invention.

Fig. 3 is a schematic structural diagram of a superconducting quantum chip according to a third embodiment of the present invention.

Fig. 4 is a schematic structural diagram of a superconducting quantum chip according to a fourth embodiment of the present invention.

Fig. 5 is a schematic structural diagram of a superconducting quantum chip according to a fifth embodiment of the present invention.

Fig. 6 is a schematic structural diagram of a superconducting quantum chip according to a sixth embodiment of the present invention.

Fig. 7 is a schematic structural diagram of a superconducting quantum chip according to a seventh embodiment of the present invention.

Fig. 8 is a schematic structural diagram of a superconducting quantum chip according to an eighth embodiment of the present invention.

Fig. 9 is a schematic structural view of a superconducting quantum chip according to a ninth embodiment of the present invention.

Fig. 10 is a schematic structural view of a superconducting quantum chip according to a tenth embodiment of the present invention.

Fig. 11 is a schematic structural view of a superconducting quantum chip according to an eleventh embodiment of the present invention.

Fig. 12 is a schematic structural diagram of a quantum computer according to a twelfth embodiment of the present invention.

Fig. 13 is a schematic structural diagram of a quantum computer according to a thirteenth embodiment of the present invention.

Fig. 14 is a flow chart of a method for manufacturing a superconducting quantum chip according to a fourteenth embodiment of the present invention.

Fig. 15 is a flow chart of a method for manufacturing a superconducting quantum chip according to a fifteenth embodiment of the present invention.

Fig. 16 is a flow chart of a method for manufacturing a superconducting quantum chip according to a sixteenth embodiment of the present invention.

Fig. 17 is a schematic flow chart of a method for manufacturing a superconducting quantum chip according to a seventeenth embodiment of the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the embodiments of the present application will be described in further detail with reference to the accompanying drawings. The exemplary embodiments of the present application and their descriptions herein are for the purpose of explaining the present application, but are not to be construed as limiting the application. It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be arbitrarily combined with each other. In the technical scheme of the application, the acquisition, storage, use, processing and the like of the data all accord with the relevant regulations of laws and regulations. The user information in the embodiment of the application is obtained through legal compliance approaches, and the user information is obtained, stored, used, processed and the like through the approval of the client.

In order to facilitate understanding of the technical scheme provided by the application, the following description will explain relevant contents of the technical scheme of the application.

The cooling difficulty of the dilution refrigerator is high, the cooling speed is low, and for superconducting quantum calculation, the cooling to the mK magnitude by using the dilution refrigerator often needs days. The problem is more obvious in a complex chip structure of a three-dimensional integrated architecture because of different superconducting transition temperatures required by different materials entering a superconducting state, uneven temperature distribution of different parts of a superconducting quantum chip, possibility of existence of some non-superconducting components in a quantum computer, and the like, so that cooling time is further prolonged by part of joule heat continuously generated by an electrical structure which does not enter the superconducting state or has no superconducting characteristic, and stability of the electrical structure which enters the superconducting state is influenced. Therefore, it is necessary to explore an effective conduction and heat dissipation mechanism to optimize the heat dissipation path of the superconducting quantum chip in the process of cooling, especially the heat dissipation problem of the complex superconducting quantum chip adopting the three-dimensional integrated architecture.

Fig. 1 is a schematic structural diagram of a superconducting quantum chip provided in a first embodiment of the present invention, and as shown in fig. 1, the superconducting quantum chip provided in the embodiment of the present invention includes a chip module 1 and a first heat dissipation layer 2, where:

The chip module 1 comprises a core particle layer 1-1 and a substrate 1-2, wherein the substrate 1-2 is connected with the core particle layer 1-1 through a bump 1-3;

the core layer 1-1 is connected with the first heat dissipation layer 2 through the first bonding layer 3.

Specifically, the core particle layer 1-1 includes a quantum integrated chip (Quantum Integrated Circuit, abbreviated as QIC) and an electronic integrated chip (ELECTRICAL INTEGRATED Circuit, abbreviated as EIC), and the QIC and the EIC may be integrated on the same slide, or may be integrated on different slides respectively. The substrate 1-2 is used for carrying the core particle layer 1-1, the substrate 1-2 can be made of materials such as sapphire, and the like, and is selected according to actual needs, and the embodiment of the invention is not limited. The substrate 1-2 and the core particle layer 1-1 are connected through the convex points 1-3, the convex points 1-3 can be solder convex points, nail head convex points and the like, and the convex points can be selected according to actual needs, and the embodiment of the invention is not limited. The specific number of the bumps 1-3 is set according to actual needs, and the embodiment of the invention is not limited. The substrate 1-2 can support the core layer 1-1 by the bumps 1-3, and the bumps 1-3 can also realize inter-chip electrical interconnection.

The first heat dissipation layer 2 is used for dissipating heat of the chip module 1, heat generated by the chip module 1 can be transferred to the first heat dissipation layer 2 through the first bonding layer 3, and the heat can be laterally diffused in the first heat dissipation layer 2, so that the effective heat exchange area of a heat source and the outside is increased, and the heat dissipation efficiency of the superconducting quantum chip is improved. The first heat dissipation layer 2 may be made of a material having a high thermal conductivity, such as diamond. The diamond has excellent insulativity and ultrahigh heat conductivity, the heat conductivity coefficient of the single crystal diamond at room temperature is as high as 2400W/(m.K), and the heat conductivity coefficient of the polycrystalline diamond at room temperature is close to 2000W/(m.K), so that the diamond is an ideal heat dissipation material. After the core particle layer 1-1 is integrated with the diamond, the heat generated by the core particle layer 1-1 can be rapidly and transversely diffused in the first heat dissipation layer 2 by virtue of the ultra-high heat conductivity of the diamond, so that the effective heat exchange area of the first heat dissipation layer 2 and the outside is increased, and the heat exchange capacity of the superconducting quantum chip can be greatly improved.

The first bonding layer 3 may adopt a metal nano structure, the core particle layer 1-1 and the first heat dissipation layer 2 are sputtered with metal nano particles on the surface, and then bonding is performed to form the first bonding layer 3. Because the qubits in the core layer 1-1 are very fragile and cannot withstand long-term high temperature treatment, the temperature at the time of bonding needs to be lower than a preset temperature, such as 150 ℃. The metal nano particles are adopted for bonding, and the melting point of the metal nano structure is greatly reduced due to the existence of a nano effect, and in addition, the surface energy of the metal nano structure is relatively high and is easy to combine with other atoms, so that the bonding of the first heat dissipation layer and the core particle layer 1-1 is realized at a relatively low temperature. Because the metal nano particles can fill the concave and micro holes on the surface after low-temperature sintering, the surface of the bonding pad to be bonded is flattened, the requirement on flattening (such as chemical mechanical polishing process) before the bonding process of the first heat dissipation layer 2 and the core particle layer 1-1 is reduced, adverse effects caused by the fact that the surface of the chip is still uneven after the flattening process are relieved, and adverse mechanical damage possibly caused to Josephson junctions in the high-precision flattening process are relieved. The first bonding layer 3 has good heat conduction performance due to the adoption of a metal nano structure, and can ensure heat conduction between the core particle layer 1-1 and the first heat dissipation layer 2.

The superconducting quantum chip comprises a chip module and a first heat dissipation layer, wherein the chip module comprises a core particle layer and a substrate, the substrate is connected with the core particle layer through convex points, the core particle layer is connected with the first heat dissipation layer through a first bonding layer, and the first heat dissipation layer is arranged on the core particle layer, so that the effective heat exchange area is increased, and the heat dissipation efficiency of the superconducting quantum chip is improved. In addition, the first bonding layer is used for connecting the core particle layer and the first heat dissipation layer, so that the difficulty of the manufacturing process is reduced.

Fig. 2 is a schematic structural diagram of a superconducting quantum chip according to a second embodiment of the present invention, as shown in fig. 2, further, the superconducting quantum chip according to the embodiments of the present invention further includes a crystal back layer 4, where the crystal back layer 4 is connected to the substrate 1-2, and a thermal expansion coefficient of the substrate 1-2 is greater than a thermal expansion coefficient of the crystal back layer 4 and a thermal expansion coefficient of the first heat dissipation layer 2. The substrate 1-2 and the core particle layer 1-1 can be made of the same substrate material, such as sapphire, which is beneficial to improving the preparation quality of the qubit, so that larger mechanical stress can not be generated between the substrate 1-2 and the core particle layer due to the difference of thermal expansion coefficients.

Specifically, the crystalline back layer 4 may be made of a silicon nitride material. The coefficient of thermal expansion of the substrate 1-2 is larger than that of the crystal back layer 4, and the coefficient of thermal expansion of the substrate 1-2 is larger than that of the first heat dissipation layer 2. Because the superconducting quantum chip needs a very low temperature service environment, the superconducting quantum chip can bear heat load in a temperature range from room temperature to mK magnitude, and at the moment, warping and thermal stress caused by mismatching of the thermal expansion coefficients of the substrate 1-2 and the first heat dissipation layer 2 have great adverse effects. By adding the crystal back layer 4, the application realizes the first heat dissipation layer-chip module-crystal back layer structure, the thermal expansion coefficient of the substrate 1-2 is larger than that of the crystal back layer 4 and that of the first heat dissipation layer 2, and in the thermal cycle process, the stress directions of the first heat dissipation layer 2 and the crystal back layer 4 to the intermediate substrate 1-2 are opposite, and the existence of the crystal back layer 4 can release the warping degree of the first heat dissipation layer-chip module structure to a certain extent, so that the risk of mechanical failure is reduced. Specifically, according to the physical characteristics of the first heat dissipation layer 2, such as size and thermal conductivity, the degree of warpage of the overall structure of the first heat dissipation layer-chip module can be reduced by adjusting the shape, size, position distribution, etc. of the crystalline back layer 4.

For example, the first heat dissipation layer 2 is made of a diamond material, the substrate 1-2 is made of a sapphire material, and the crystal back layer 4 is made of a silicon nitride material. The thermal expansion coefficient of diamond is about 0.8X10 ^-6/K, the thermal expansion coefficient of sapphire is about 7.5X10 ^-6/K, and the thermal expansion coefficient of silicon nitride is about 2.35X10 ^-6/K. It is ensured that the resulting substrate 1-2 has a thermal expansion coefficient greater than that of the first heat sink layer 2 and greater than that of the crystalline back layer 4.

Fig. 3 is a schematic structural diagram of a superconducting quantum chip according to a third embodiment of the present invention, as shown in fig. 3, further, on the basis of the foregoing embodiments, the superconducting quantum chip according to the embodiment of the present invention further includes a second heat dissipation layer 5, where the second heat dissipation layer 5 is connected to the crystal back layer 4 through a second bonding layer 6.

Specifically, the second heat dissipation layer 5 is used for dissipating heat from the chip module 1. The heat generated by the chip module 1 can be transferred to the second heat sink layer 5 through the die attach layer 4 and the second bonding layer 6. The heat can be transversely diffused in the second heat dissipation layer 5, so that the effective heat exchange area of the heat source and the outside is increased, and the heat dissipation efficiency of the superconducting quantum chip is improved. The second heat dissipation layer 5 may be made of a material having a high thermal conductivity, such as diamond. The diamond may be a single crystal diamond piece, or may be a polycrystalline diamond piece, preferably a single crystal diamond piece.

The second bonding layer 6 may be a metal nano structure, and the second heat dissipation layer 5 and the crystal back layer 4 are sputtered with metal nano particles on the surface, and then bonded to form the second bonding layer 6. The metal nano particles are adopted for bonding, and the melting point of the metal nano structure is greatly reduced due to the existence of the nano effect, and in addition, the surface energy of the metal nano structure is relatively high, so that the metal nano structure is easily combined with other atoms, and the bonding of the second heat dissipation layer and the crystal back layer 4 is facilitated to be realized at a relatively low temperature.

Fig. 4 is a schematic structural diagram of a superconducting quantum chip according to a fourth embodiment of the present invention, as shown in fig. 4, further, the superconducting quantum chip according to the embodiment of the present invention further includes a base 7, where the base 7 is connected to the second heat dissipation layer 5.

Specifically, the base 7 may be made of a material having a good heat dissipation property. For example, copper is adopted, and copper still has higher heat conductivity at low temperature, so that the copper can play a role in rapid heat dissipation. The base is used for bearing the superconducting quantum chip and provides a close contact thermal interface, thereby being beneficial to accelerating the heat dissipation of the superconducting quantum chip.

Fig. 5 is a schematic structural diagram of a superconducting quantum chip according to a fifth embodiment of the present invention, and as shown in fig. 5, a second transition layer 8 is further disposed between the base 7 and the second heat dissipation layer 5 on the basis of the above embodiments.

In particular, the second transition layer 8 may be made of a thermal interface material (THERMAL INTERFACE MATERIALS, abbreviated as TIM). The second transition layer 8 is used for filling micro-voids and rugged holes on the surface generated when the base 7 is contacted with the second heat dissipation layer 5, reducing contact thermal resistance and improving heat dissipation performance of the device. The thermal interface material is selected according to actual needs, and the embodiment of the invention is not limited.

Fig. 6 is a schematic structural diagram of a superconducting quantum chip according to a sixth embodiment of the present invention, as shown in fig. 6. Further, on the basis of the above embodiments, the susceptor 7 wraps at least a part of the structure from the substrate 1-2 to the susceptor 7. The substrate 1-2 is wrapped by the base 7 to form a part of structure in the base 7, so that the effective heat dissipation area and the heat dissipation path are increased, and the heat dissipation efficiency of the superconducting quantum chip is further improved.

For example, the base 7 may encapsulate the substrate 1-2, the die backing layer 4, the second bonding layer 6, and the second heat sink layer 5.

For example, the submount 7 may wrap the die backing layer 4, the second bonding layer 6, and the second heat sink layer 5.

For example, the base 7 may encapsulate the second bonding layer 6, the second heat dissipation layer 5, and the second transition layer 8.

Fig. 7 is a schematic structural diagram of a superconducting quantum chip according to a seventh embodiment of the present invention, and as shown in fig. 7, a thermoelectric region 9 is disposed between a susceptor 7 and a wrapped structure. The thermoelectric region 9 is provided with a thermoelectric conversion device, the thermoelectric conversion device is a functional device capable of converting heat energy and electric energy into each other, thermoelectric refrigeration is application of Peltier effect, and unlike traditional compressor refrigeration, the thermoelectric refrigeration device has no moving parts and no refrigerant, and has the advantages of simple structure, small volume, light weight, no noise, no pollution, rapid refrigeration and the like, and the switching between refrigeration and heating can be easily realized by changing the direction of current. The thermoelectric conversion device may be made of Bi ₂Te₃、SiGe、PbTe、clathrate、skutterudite、Half-Heusler、SnSe、Zn₄Sb₄, in ₄Se₃, or the like.

Fig. 8 is a schematic structural diagram of a superconducting quantum chip according to an eighth embodiment of the present invention, as shown in fig. 8, further, based on the above embodiments, the crystal back layer 4 includes an optical waveguide area 4-1, the optical waveguide area 4-1 is connected to an off-chip optical fiber 10 through a first coupler 15, a photonic integrated chip (Photonic Integrated Circuit, abbreviated as PIC) bridge structure 1-21 is disposed on the substrate 1-2, the PIC bridge structure 1-21 is connected to a corresponding bump 1-3, a second coupler 4-2 corresponding to the PIC bridge structure 1-21 is disposed on the optical waveguide area 4-1, and the second coupler 4-2 is used to implement optical signal transmission between the PIC bridge structure 1-21 and the optical waveguide area 4-1.

Specifically, the wafer back layer 4 includes an optical waveguide region 4-1, and the optical waveguide region 4-1 is connected to the off-chip optical fiber 10 through a first coupler 15, and can receive an optical signal from the outside through the off-chip optical fiber 10. It is understood that the optical waveguide region 4-1 may be part of the wafer back layer 4. The substrate 1-2 may be provided with a PIC bridge structure 1-21, where the PIC bridge structure 1-21 can convert an electrical signal into an optical signal, and also can convert an optical signal into an electrical signal, and has ports for inputting and outputting electrical signals and ports for inputting and outputting optical signals. The PIC bridging structure is selected as a bridging structure embedded in the substrate 1-2, so that an input optical signal from the off-chip optical fiber 10 can be converted into an electric signal and transmitted to the core particle layer 1-1 through the corresponding salient points 1-3. The PIC bridging structure 1-21 can also convert the electrical signals from the core particle layer 1-1 into optical signals which are finally output through the off-chip optical fiber 10, so that the flexibility and the multiplexing degree of the design are improved. The first coupler 15 may be an end-face coupler.

In order to realize the optical signal transmission between the PIC bridge connecting structure 1-21 and the optical waveguide area 4-1, a through hole may be provided in the substrate 1-2, and a second coupler 4-2 may be provided at a position of the optical waveguide area 4-1 corresponding to the through hole, where the second coupler 4-2 is used to change the transmission direction of the optical signal. The second coupler 4-2 may transfer the optical signal from the optical waveguide region 4-1 to the PIC bridging structure 1-21, or may transfer the optical signal from the PIC bridging structure 1-21 to the optical waveguide region 4-1. The second coupler 4-2 is selected according to actual needs, and the embodiment of the present invention is not limited.

Further, a ball lens may be disposed in the through hole provided in the substrate 1-2, and the second coupler 4-2 transmits the optical signal from the optical waveguide region 4-1 to the ball lens, and transmits the optical signal to the PIC bridge structure 1-21 through the ball lens. The optical signal from the PIC bridge structure 1-21 is transferred through the ball lens to the second coupler 4-2, and the second coupler 4-2 transfers the optical signal to the optical waveguide region 4-1. In order to ensure the stability of the ball lens, the through holes provided in the substrate 1-2 are inclined, the diameter of the hole near the optical waveguide region 4-1 is smaller, and the diameter of the hole near the PIC bridge structure 1-21 is larger.

Fig. 9 is a schematic structural diagram of a superconducting quantum chip according to a ninth embodiment of the present invention, as shown in fig. 9, further, on the basis of the foregoing embodiments, the superconducting quantum chip according to the embodiment of the present invention further includes a first transition layer 11, where the first transition layer 11 is connected to the first heat dissipation layer 2.

Specifically, the first transition layer 11 may be made of TIM. The first transition layer 11 is used for filling micro-voids and rugged holes on the surface generated when the first heat dissipation layer 2 is contacted with a cold plate of a dilution refrigerator, reducing heat transfer contact resistance and improving heat dissipation performance of the device. The thermal interface material is selected according to actual needs, and the embodiment of the invention is not limited.

Fig. 10 is a schematic structural diagram of a superconducting quantum chip according to a tenth embodiment of the present invention, as shown in fig. 10, further, based on the above embodiments, a plurality of heat dissipation portions 1-11 are provided on the core layer 1-1, each heat dissipation portion 1-11 is in contact with the first bonding layer 3, and the heat dissipation portions 1-11 are filled with a heat conductive material.

Specifically, the heat dissipation portion 1-11 may be made by punching and filling a heat conductive material in the core particle layer 1-1. The heat conductive material may be a material with high thermal conductivity, such as diamond. The specific positions and numbers of the heat dissipating parts 1 to 11 are selected according to the actual situation, and the embodiment of the present invention is not limited. By adding the heat dissipation part 1-11 on the core particle layer 1-1, a micrometer-sized local heat dissipation channel can be provided, so that rapid heat conduction in the vertical direction in the sheet can be realized, and the heat stability of the core particle can be improved. The first heat dissipation layer 2 provides an off-chip heat dissipation channel, so that the rapid and uniform distribution of heat in the horizontal direction is facilitated, and the heat dissipation efficiency of the whole superconducting quantum chip is remarkably improved due to the arrangement of an on-chip heat dissipation path and an off-chip heat dissipation path.

Fig. 11 is a schematic structural view of a superconducting quantum chip according to an eleventh embodiment of the present invention, as shown in fig. 11, further, an electrical interconnection line 12 is disposed on a substrate 1-2, a first end of the electrical interconnection line 12 is connected to a bump 1-3, and a second end of the electrical interconnection line 12 is connected to a coaxial line 14 through a lead 13.

The core layer 1-1 may be in electrical communication through the bump 1-3, the electrical interconnect 12, the lead 13, and the coaxial line 14. Electrical communication between QIC and EIC of the core layer 1-1 may be achieved through corresponding bumps and electrical interconnections.

Fig. 12 is a schematic structural diagram of a quantum computer according to a twelfth embodiment of the present invention, and as shown in fig. 12, the quantum computer according to the embodiment of the present invention includes a superconducting quantum chip 1201 and a dilution refrigerator according to any of the foregoing embodiments, the dilution refrigerator includes a first cold plate 1202 and a second cold plate 1203, and the superconducting quantum chip 1201 is disposed between the first cold plate 1202 and the second cold plate 1203 and is in contact with the first cold plate 1202 and the second cold plate 1203, respectively. The superconducting quantum chip 1201 is cooled down by heat conduction with the first cold plate 1202 and the second cold plate 1203.

For example, fig. 13 is a schematic structural diagram of a quantum computer according to a thirteenth embodiment of the present invention, and as shown in fig. 13, the quantum computer according to the embodiment of the present invention includes a superconducting quantum chip 101, a first cold plate 102, and a second cold plate 103, where:

The upper surface of the superconducting quantum chip 101 is in contact with the first cold plate 102, and the lower surface of the superconducting quantum chip 101 is in contact with the second cold plate 103.

The superconducting quantum chip 101 comprises a chip module 1, a first heat dissipation layer 2, a first bonding layer 3, a crystal back layer 4, a second heat dissipation layer 5, a second bonding layer 6, a base 7, a second transition layer 8, a thermoelectric region 9 and a first transition layer 11. The chip module 1 comprises a core particle layer 1-1 and a substrate 1-2, wherein the substrate 1-2 is connected with the core particle layer 1-1 through a bump 1-3. The crystalline back layer 4 is connected to the substrate 1-2, and the thermal expansion coefficient of the substrate 1-2 is larger than the thermal expansion coefficient of the crystalline back layer 4 and the thermal expansion coefficient of the first heat dissipation layer 2. The base 7 wraps the second bonding layer 6, the second heat dissipation layer 5, and the second transition layer 8.

The core particle layer 1-1 is provided with a plurality of heat dissipation parts 1-11, each heat dissipation part 1-11 is contacted with the first bonding layer 3, and the heat dissipation parts 1-11 are filled with a heat conduction material.

The crystal back layer 4 comprises an optical waveguide area 4-1, the optical waveguide area 4-1 is connected with an off-chip optical fiber 10 through a first coupler 15, a PIC bridging structure 1-21 is arranged on the substrate 1-2, the PIC bridging structure 1-21 is connected with corresponding convex points, a second coupler 4-2 corresponding to the PIC bridging structure 1-21 is arranged in the optical waveguide area 4-1, and the second coupler 4-2 is used for realizing optical signal transmission between the PIC bridging structure 1-21 and the optical waveguide area 4-1.

An electrical interconnection 12 is provided on the substrate 1-2, a first end of the electrical interconnection 12 is connected to the bump 1-3, and a second end of the electrical interconnection 12 is connected to a coaxial line 14 through a lead 13.

The heat generated by the chip module 1 can be transferred to the first heat dissipation layer 2 through the first bonding layer 3, and then transferred to the first cold plate 102 through the first transition layer 11 by the first heat dissipation layer 2. The heat generated by the chip module 1 can be transferred to the second heat dissipation layer 5 through the die attach layer 4 and the second bonding layer 6, and then transferred to the base 7 through the second transition layer 8 by the second heat dissipation layer 5, and the base 7 transfers the heat to the second cold plate 103. Since the plurality of heat dissipation parts 1-11 are arranged on the core particle layer 1-1, the heat generated by the core particle layer 1-1 can be transferred to the first bonding layer 3 through the plurality of heat dissipation parts 1-11 and then transferred to the first heat dissipation layer 2. Heat in the second heat spreader layer 5, the second bonding layer 6, and the second transition layer 8 may also be transferred to the submount 7 through the thermoelectric region 9.

The base 7 may facilitate routing and fixing of the off-chip optical fibers 10 and the coaxial lines 14. The second cold plate 103 may facilitate the routing and fixing of the coaxial line 14. The first cold plate 102 is provided with a through hole to facilitate routing of the off-chip optical fiber 10 and the coaxial line 14.

Fig. 14 is a schematic flow chart of a method for manufacturing a superconducting quantum chip according to a fourteenth embodiment of the present invention, and as shown in fig. 14, the method for manufacturing a superconducting quantum chip according to the embodiment of the present invention includes:

1401. Manufacturing each core particle;

specifically, QIC and/or EIC are produced on the preparation sheet to obtain the core particle. The core particle may include an active region, and a side of the core particle including the active region may be bumped.

1402. Obtaining a first assembly based on each core particle and a first heat dissipation layer, wherein the first assembly comprises the first heat dissipation layer and a core particle layer formed by each core particle;

Specifically, each core particle is bonded with the first heat dissipation layer, and the first assembly is obtained. The first component comprises a core particle layer formed by the first heat dissipation layer and each core particle. The first heat dissipation layer may be made of a material with high thermal conductivity.

For example, the first heat dissipation layer is made of diamond, and the diamond has very high hardness and is difficult to process, so that no special machining requirement is made on the whole piece of sheet-shaped diamond.

1403. Obtaining a second component based on the substrate material, the second component comprising a substrate;

Specifically, the second component is obtained by manufacturing the electrical interconnect, the wiring layer, the PIC bridge structure, the through-hole corresponding to the PIC bridge structure, and the like based on the substrate material. The second component includes a substrate. The substrate material may be sapphire, silicon, or the like, and is selected according to actual needs, which is not limited by the embodiment of the present invention.

1404. Preparing salient points on each core particle of the core particle layer, and manufacturing salient points corresponding to the salient points of each core particle on the substrate;

Specifically, bump materials are deposited on each core particle, and the bumps on each core particle are obtained. And depositing a bump material on the substrate to obtain bumps corresponding to the bumps of each core particle. Since the bonding process requires a high bump thickness, a bump material 5-10 μm thick can be deposited alternatively. The bump material may be deposited by thermal evaporation or electron beam evaporation or electroplating, etc., to rapidly complete the deposition of the bump material.

1405. And integrating the first component and the second component based on the salient points on the core grains of the core grain layer and the salient points on the substrate to obtain the superconducting quantum chip.

Specifically, bonding is performed on the salient points on each core particle and the salient points on the substrate in an inert atmosphere or a reducing atmosphere, so that the first component and the second component are integrated together to form the superconducting quantum chip. Solid bonding or liquid bonding can be selected, the temperature of the solid bonding is low, and adverse effects of a high-temperature process on the quantum components can be avoided. Wherein, the inert atmosphere can adopt nitrogen, and the reducing atmosphere can adopt formic acid.

The superconducting quantum chip comprises a substrate, a first component, a second component, a substrate, a first component, a second component and a third component, wherein the first component is obtained based on each core particle and a first heat dissipation layer, the first component comprises a core particle layer formed by the first heat dissipation layer and each core particle, the second component comprises a substrate, the substrate is provided with bumps, bumps corresponding to the bumps of each core particle are manufactured on each core particle of the core particle layer, the first component and the second component are integrated based on the bumps of each core particle of the core particle layer and the bumps of the substrate, and the first heat dissipation layer is arranged on the core particle layer, so that the effective heat exchange area is improved, and the heat dissipation efficiency of the superconducting quantum chip is improved. In addition, the first bonding layer is used for connecting the core particle layer and the first heat dissipation layer, so that the difficulty of the manufacturing process is reduced.

Further, on the basis of the above embodiments, the making each core particle includes:

Specifically, for each core particle, in the manufacturing process, a hole may be punched at a preset position on a side of the core particle opposite to the first heat dissipation layer, and a heat dissipation portion may be formed by filling a heat conductive material. In filling the thermally conductive material, diamond particles may be deposited in the pores using a Microwave PLASMA CHEMICAL Vapor Deposition (MPCVD) technique. The perforation may be performed using an etching process. Wherein, the heat conducting material can adopt diamond. The preset position is set according to the actual situation, and the embodiment of the invention is not limited.

Fig. 15 is a schematic flow chart of a method for manufacturing a superconducting quantum chip according to a fifteenth embodiment of the present invention, as shown in fig. 15, further, based on the above embodiments, the obtaining a first component based on each core particle and the first heat dissipation layer material includes:

S1501, sputtering metal nano particles on one side surface of a first heat dissipation layer, and sputtering metal nano particles on one side surface of each core particle;

Specifically, metal nanoparticles are sputtered on one side surface of the first heat dissipation layer, and metal nanoparticles are sputtered on one side surface of each core particle. Wherein one side surface of each core particle sputtered metal nanoparticle is not an active region of the core particle. The first heat dissipation layer may be made of a material with high thermal conductivity, such as diamond. The metal nano-particles can be Au nano-particles or Ag nano-particles.

The preparation of the metal nanoparticles can be obtained by a physical vapor deposition method or a pulse laser deposition method. Compared with the method for preparing the metal nano particles by adopting a solution method, the method for preparing the metal nano particles by adopting a physical vapor deposition method or a pulse laser deposition method solves the problem that the metal nano particles are easy to agglomerate, and the problem that the metal nano particles are polluted by insufficient organic solvent due to the fact that the organic solvent is introduced by adopting the solution method, and meanwhile, the metal nano particles prepared by adopting the physical vapor deposition method or the pulse laser deposition method are loose and dispersed, have large surface area, have higher surface energy and activity, and are beneficial to reducing bonding temperature.

It should be noted that the redundant metal nanoparticles on the first heat dissipation layer may not be treated.

Further, before sputtering the metal nanoparticles on the one side surface of the first heat dissipation layer and/or the core particle, tiW or Cu may be sputtered as a primer layer on the one side surface of the first heat dissipation layer and/or the core particle, and then the metal nanoparticles may be sputtered on the primer layer. The TiW/Cu priming layer can be patterned by a stripping process rather than a wet etching process, so that the metal nano particles on the bonding region can be effectively protected. If a wet etching process is adopted, tiW/Cu is required to be deposited firstly, then a high-pressure sputtering nanoparticle process is carried out, then photoetching is carried out, and the nanoparticles on the surface of the bonding area are protected by photoresist, so that the excessive TiW/Cu outside the bonding area is removed by wet etching. In this case, the metal nanoparticles of the protected region are likely to be contaminated by the photoresist, and some desorption occurs with dissolution and removal of the photoresist. In the scheme of the application, the photoetching process is firstly carried out, the bonding area is not covered by photoresist, after the metal nano particles are sputtered under high pressure, the photoresist in the non-bonding area is only soaked by acetone and ethanol once, so that the nano particles on the surface of the non-bonding area can be taken away without causing obvious adverse effect on the nano particles in the bonding area, and in addition, the residual ethanol is easy to volatilize and cannot influence the subsequent bonding process.

And S1502, bonding the surface of the first heat dissipation layer with the metal nano particles and the surface of each core particle with the metal nano particles at a preset temperature to obtain the first component.

Specifically, bonding is performed on the surface of the first heat dissipation layer material with the metal nano particles and the surface with the metal nano particles of each core particle at a preset temperature, so that the first component is obtained. And a layer bonded between the first heat dissipation layer and each core particle is used as a first bonding layer. In the bonding process, core particle alignment is performed first, then pre-bonding is performed, and finally low-temperature annealing is performed. The metal nanoparticles have a low melting point and can compensate for the problem of the flatness of the recessed surface in the CMP process, thus helping to reduce the annealing temperature required for bonding. The method is helpful for ensuring that the annealing process does not adversely affect the Josephson junctions on the quantum functional core particles. The preset temperature is 150 ℃ for example, and is set according to actual needs, and the embodiment of the invention is not limited.

Because the qubit in the core particle is very fragile, the high-temperature treatment cannot be carried out for a long time, and the low-temperature bonding is carried out at a preset temperature, so that the qubit cannot be damaged. The metal nano particles are adopted for bonding, and due to the existence of a nano effect, the melting point of the metal nano structure can be greatly reduced, in addition, the surface energy of the metal nano structure is relatively high, and the metal nano structure is easy to combine with other atoms, so that the bonding of the first heat dissipation layer and each core particle can be realized at a preset temperature. Because the metal nano particles can be filled with the concave and the micro-hole on the surface after being sintered at low temperature, the surface of the area to be bonded is flattened, the requirement on flattening before the bonding process of the first heat dissipation layer and the core particles is reduced, and the adverse effect caused by the fact that the surface of the chip is still uneven after the flattening process is relieved.

On the basis of the above embodiments, the method for manufacturing a superconducting quantum chip according to the embodiment of the present invention further includes:

And manufacturing a first transition layer on the first heat dissipation layer.

In particular, the thermal interface material may be a viscous body or solid with high viscosity, and may be brought into good contact with the substrate by applying pressure and tightly adhered together to form the first transition layer. Thermal interface materials include, but are not limited to, thermally conductive gels, thermally conductive silicone greases, thermally conductive cements, indium sheets, and the like.

Fig. 16 is a schematic flow chart of a method for manufacturing a superconducting quantum chip according to a sixteenth embodiment of the present invention, as shown in fig. 16, further, the second component further includes a crystal back layer on the basis of the above embodiments, and correspondingly, the obtaining the second component based on the substrate material includes:

s1601, manufacturing a substrate based on the substrate-based material;

Specifically, the substrate is manufactured based on the substrate material, and the substrate can be also provided with structures such as an electric interconnection line, a wiring layer, a PIC bridging structure, a through hole corresponding to the PIC bridging structure, and the like.

S1602, manufacturing a crystal back layer on the substrate, wherein the thermal expansion coefficient of the substrate is larger than that of the crystal back layer and that of the first heat dissipation layer.

Specifically, the crystalline back layer is fabricated on the side surface of the substrate opposite to the bump preparation by a material growth technique including, but not limited to CVD, PVD, ALD and the like, which is selected according to the actual need.

The thermal expansion coefficient of the substrate is larger than the thermal expansion coefficient of the crystal back layer and the thermal expansion coefficient of the first heat dissipation layer. By manufacturing the crystal back layer, and the thermal expansion coefficient of the substrate is larger than that of the crystal back layer and that of the first heat dissipation layer, the warping degree of the first heat dissipation layer-chip module structure can be relieved to a certain extent, and the risk of mechanical failure is further reduced.

Fig. 17 is a schematic flow chart of a method for manufacturing a superconducting quantum chip according to a seventeenth embodiment of the present invention, as shown in fig. 17, further, on the basis of the foregoing embodiments, the second assembly further includes a second heat dissipation layer, and correspondingly, the obtaining the second assembly based on the substrate material further includes:

S1701, sputtering metal nano-particles on the surface of a nonfunctional area of the crystal back layer, and sputtering metal nano-particles on the surface of a corresponding area on one side of the second heat dissipation layer;

Specifically, after a crystalline back layer is fabricated on the substrate, metal nanoparticles are sputtered on the surface of the nonfunctional area of the crystalline back layer, and metal nanoparticles are sputtered on the surface of the corresponding area on one side of the second heat dissipation layer. The surface of the corresponding area on one side of the second heat dissipation layer is the surface bonded with the surface of the nonfunctional area of the crystal back layer. The second heat dissipation layer can be made of diamond or other materials with high heat conductivity. The metal nano-particles can be Au nano-particles or Ag nano-particles. In the present application, the nonfunctional area of the crystalline back layer means an area which is not adversely affected by sputtering of metal nanoparticles, such as an area other than the optical waveguide area.

Further, before sputtering metal nanoparticles on the surface of the nonfunctional area of the crystalline back layer and/or the corresponding area on one side of the second heat dissipation layer, tiW or Cu may be sputtered as a primer layer on one side surface of the crystalline back layer and/or the second heat dissipation layer, and then the metal nanoparticles may be sputtered on the primer layer. The TiW/Cu priming layer can be patterned by a stripping process rather than a wet etching process, so that the metal nano particles on the bonding region can be effectively protected. If a wet etching process is adopted, tiW/Cu is required to be deposited firstly, then a high-pressure sputtering nanoparticle process is carried out, then photoetching is carried out, and the nanoparticles on the surface of the bonding area are protected by photoresist, so that the excessive TiW/Cu outside the bonding area is removed by wet etching. In this case, the metal nanoparticles of the protected region are likely to be contaminated by the photoresist, and some desorption occurs with dissolution and removal of the photoresist. In the scheme of the application, the photoetching process is firstly carried out, the bonding area is not covered by photoresist, after the metal nano particles are sputtered under high pressure, the photoresist in the non-bonding area is only soaked by acetone and ethanol once, so that the nano particles on the surface of the non-bonding area can be taken away without causing obvious adverse effect on the nano particles in the bonding area, and in addition, the residual ethanol is easy to volatilize and cannot influence the subsequent bonding process.

S1702, bonding a surface of the second heat dissipation layer having metal nanoparticles with a surface of the crystal back layer having metal nanoparticles.

Specifically, the surface of the second heat dissipation layer with the metal nano-particles is bonded with the surface of the crystal back layer with the metal nano-particles. In the bonding process, the second heat dissipation layer is aligned, then pre-bonding is performed, and finally low-temperature annealing is performed. The metal nanoparticles have a low melting point and can compensate for the problem of the flatness of the recessed surface in the CMP process, thus helping to reduce the annealing temperature required for bonding.

Specifically, the thermal interface material may be a viscous body or a solid state with higher viscosity, and may be brought into good contact with the second heat dissipation layer by applying pressure and tightly adhered together to form the first transition layer. Thermal interface materials include, but are not limited to, thermally conductive gels, thermally conductive silicone greases, thermally conductive cements, indium sheets, and the like.

Further, on the basis of the above embodiments, the fabricating a crystalline back layer on the substrate includes:

And manufacturing an optical waveguide area on the crystal back layer.

Specifically, in the process of fabricating a crystalline back layer on the substrate, a signal line required for optical communication may be prepared on the crystalline back layer by photolithography technique, and an optical waveguide region may be obtained. Since optical signal communication is not required to be performed over the entire crystal back layer, an optical waveguide region can be formed by selecting a partial region of the crystal back layer. The specific position of the optical waveguide region on the crystal back layer is selected according to actual needs, and the embodiment of the invention is not limited.

Further, after the optical waveguide region is manufactured, a second coupler may be further manufactured at a position of the through hole corresponding to the PIC bridge connecting structure of the substrate in the optical waveguide region.

The crystalline back layer may be made of silicon nitride material. The integrated optical waveguide based on the silicon nitride material has the characteristics of broadband low loss and no two-photon absorption, and has certain local capability on light. In addition, the silicon nitride material can be used for preparing other types of on-chip optical devices as required, and the silicon nitride material is used as a common CMOS compatible optical thin film dielectric material and has very rich optical characteristics. Silicon nitride has a refractive index between that of silicon dioxide and silicon, a lower refractive index, a larger band gap, and a wide range of transparent optical windows. In addition, through adjusting relevant gas parameters in the preparation process, the silicon-rich silicon nitride film material which keeps the optical characteristics of common silicon nitride and has relatively high refractive index can be prepared, so that the refractive index range of the silicon nitride material is expanded to be 1.9-3.2, and the corresponding extinction coefficient and nonlinear coefficient also have adjustable intervals, thereby greatly enriching the freedom of device design.

Specifically, the base may be finished as desired and then the unitary structure including the first and second components may be mounted to the base. The base is used for bearing the whole structure. The base can be made of a heat conducting metal material, such as copper, and the heat conductivity of copper at low temperature is still high, so that the base can take on the function of rapid heat dissipation. The base can be further provided with a through hole which is convenient for the coaxial line and the off-chip optical fiber to pass through, thereby being convenient for the fixation and wiring of the coaxial line and the off-chip optical fiber.

Further, the cross section of the base may be concave, and the recess of the base may be provided with an integral structure including the first component and the second component. The concave convex part of the base wraps at least part of the structure from the base plate to the base so as to increase the heat dissipation area. Thermoelectric conversion devices may be disposed between the concave-shaped protruding portions of the base and the encased structure.

In the description of the present specification, reference to the terms "one embodiment," "one particular embodiment," "some embodiments," "for example," "an example," "a particular example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the scope of the invention, but to limit the invention to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the invention are intended to be included within the scope of the invention.

Claims

1. A superconducting quantum chip, characterized in that it comprises a chip module and a first heat dissipation layer, wherein:

The chip module comprises a core particle layer and a substrate, wherein the substrate is connected to the core particle layer via bumps;

The core particle layer is connected to the first heat dissipation layer via a first bonding layer.

2. The superconducting quantum chip according to claim 1 is characterized in that it also includes a crystal back layer, the crystal back layer is connected to the substrate, and the thermal expansion coefficient of the substrate is greater than the thermal expansion coefficient of the crystal back layer and the thermal expansion coefficient of the first heat dissipation layer.

3. The superconducting quantum chip according to claim 2, further comprising a second heat dissipation layer, wherein the second heat dissipation layer is connected to the crystal back layer through a second bonding layer.

4. The superconducting quantum chip according to claim 3, further comprising a base, wherein the base is connected to the second heat dissipation layer.

5 . The superconducting quantum chip according to claim 4 , characterized in that a second transition layer is provided between the base and the second heat dissipation layer.

6 . The superconducting quantum chip according to claim 4 , wherein the base at least covers a portion of the structure from the substrate to the base.

7. The superconducting quantum chip according to claim 6, characterized in that a thermoelectric zone is provided between the base and the wrapped structure.

8. The superconducting quantum chip according to claim 2 is characterized in that the crystal back layer includes an optical waveguide region, the optical waveguide region is connected to the off-chip optical fiber through a first coupler, a photon integrated chip bridge structure is arranged on the substrate, the photon integrated chip bridge structure is connected to the corresponding bump, and a second coupler corresponding to the photon integrated chip bridge structure is arranged in the optical waveguide region, and the second coupler is used to realize the optical signal transmission between the photon integrated chip bridge structure and the optical waveguide region.

9 . The superconducting quantum chip according to claim 1 , further comprising a first transition layer, wherein the first transition layer is connected to the first heat dissipation layer.

10 . The superconducting quantum chip according to claim 1 , wherein the core particle layer is provided with a plurality of heat dissipation parts, each heat dissipation part is in contact with the first bonding layer, and the heat dissipation parts are filled with heat conductive material.

11. The superconducting quantum chip according to any one of claims 1 to 10, characterized in that an electrical interconnection line is arranged on the substrate, a first end of the electrical interconnection line is connected to the bump, and a second end of the electrical interconnection line is connected to a coaxial line through a lead.

12. A quantum computer, characterized in that it comprises the superconducting quantum chip according to any one of claims 1 to 11 and a dilution refrigerator, wherein the dilution refrigerator comprises a first cold plate and a second cold plate, and the superconducting quantum chip is arranged between the first cold plate and the second cold plate and contacts the first cold plate and the second cold plate respectively.

13. A method for manufacturing a superconducting quantum chip, comprising:

Making each core particle;

Based on each core particle and the first heat dissipation layer, a first component is obtained; the first component includes the first heat dissipation layer and the core particle layer composed of each core particle;

Based on the substrate material, a second component is obtained; the second component includes a substrate;

Producing bumps on each core particle of the core particle layer, and producing bumps on the substrate corresponding to the bumps of each core particle;

Based on the bumps on each core particle of the core particle layer and the bumps on the substrate, the first component and the second component are integrated to obtain the superconducting quantum chip.

14. The method according to claim 13, wherein the manufacturing of each core particle comprises:

A hole is punched at a preset position on a side of the core particle opposite to the first heat dissipation layer and filled with a heat conductive material to form a heat dissipation portion.

15. The method according to claim 13, characterized in that the step of obtaining the first component based on the respective core particles and the first heat dissipation layer material comprises:

sputtering metal nanoparticles on one side surface of the first heat dissipation layer, and sputtering metal nanoparticles on one side surface of each core particle;

The surface of the first heat dissipation layer having metal nanoparticles is bonded to the surface of each core particle having metal nanoparticles at a preset temperature to obtain the first component.

16. The method according to claim 13, further comprising:

A first transition layer is manufactured on the first heat dissipation layer.

17. The method according to claim 13, characterized in that the second component further comprises a back layer; accordingly, obtaining the second component based on the substrate material comprises:

Based on the substrate material, manufacturing a substrate;

A crystal back layer is manufactured on the substrate; wherein the thermal expansion coefficient of the substrate is greater than the thermal expansion coefficient of the crystal back layer and the thermal expansion coefficient of the first heat dissipation layer.

18. The method according to claim 17, characterized in that the second component further comprises a second heat dissipation layer; accordingly, obtaining the second component based on the substrate material further comprises:

sputtering metal nanoparticles on the surface of the non-functional area of the crystal back layer, and sputtering metal nanoparticles on the surface of the corresponding area on one side of the second heat dissipation layer;

The surface of the second heat dissipation layer having metal nanoparticles is bonded to the surface of the non-functional region of the crystal back layer having metal nanoparticles.

19. The method according to claim 18, further comprising:

A second transition layer is formed on the surface of the second heat dissipation layer.

20. The method according to claim 17, wherein the step of manufacturing a back layer on the substrate comprises:

An optical waveguide region is fabricated on the crystal back layer.

21. The method according to any one of claims 13 to 20, further comprising:

The whole structure including the first component and the second component is arranged on a base.