CN118870662B - A method for improving the analysis capability of IC substrate circuits - Google Patents
A method for improving the analysis capability of IC substrate circuits Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
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Abstract
The invention discloses a method for improving the line analysis capability of an IC carrier plate, which comprises the steps of setting a plurality of different contrast negative compensation values according to initial negative compensation values, setting a plurality of different contrast exposure energy values according to initial exposure energy values, combining the values to form a plurality of different experiment groups, exposing each experiment group, screening out experiment groups capable of realizing vertical films after finishing, respectively detecting line widths of the experiment groups capable of realizing vertical films, selecting a group of experiment groups with highest line width precision after detection, and setting the corresponding contrast negative compensation values and the contrast exposure energy values in an exposure program of mass production. The structure of the invention can be used for obtaining the most effective result after screening the negative compensation value and the contrast exposure energy value based on the initial negative compensation value and the initial exposure energy value and applying the result to exposure, so that the circuit has higher resolving power.
Description
Technical Field
The present invention relates to a circuit processing method, and more particularly, to a method for improving the circuit resolution of an IC carrier.
Background
The statements in this section merely provide background information related to the present disclosure and may not constitute prior art.
In the existing market, along with the expansion of 5G technology, more and more consumer electronic products are pursuing extremely miniaturization and mobility, so that on the basis of lighter, thinner, shorter and smaller electronic product shells, the requirements of higher performance and stability are still maintained. Therefore, there is a higher demand for IC carrier circuits used in electronic products.
IC carrier circuit refers to connection and support structures on integrated circuits (INTEGRATED CIRCUIT, IC) and printed circuit boards (Printed Circuit Board, PCB), and relates to layout, connection modes and related design technologies of IC chips and surrounding electronic elements on the PCB, wherein the production process of the IC carrier circuit needs to be completed through steps of film pressing, exposure, development and the like. The dry film for the compression mold generally adopts a single photosensitive dry film, and under the parameter collocation conditions of collocating different film pressing, exposing and developing processes, a vertical film state without short circuit and open circuit is finally pursued, but under the condition of a thin line size, the vertical film state is affected by a plurality of uncontrollable environmental factors, and when the dry film is directly exposed by adopting an initial default negative compensation value and an exposure energy value, a finished circuit with high precision, high quality and high analytic capability is often difficult to obtain. Under severe conditions, even the problem of incapability of realizing vertical film and reduced yield can be caused.
At present, no method for improving the line analysis capability of an IC carrier board is available.
Disclosure of Invention
The invention aims to provide a method for improving the analytical capability of an IC carrier circuit, which can be used for obtaining the most effective result after screening a negative compensation value and a contrast exposure energy value based on the initial negative compensation value and the initial exposure energy value and applying the result to exposure, so that the circuit has higher analytical capability.
In order to achieve the above objective, the present invention discloses a method for improving the circuit resolving capability of an IC carrier board, wherein an original exposure program includes an initial negative compensation value and an initial exposure energy value, and the method for improving the circuit resolving capability of the IC carrier board includes:
setting a plurality of different contrast negative compensation values according to the initial negative compensation value, wherein the absolute value of the difference value between each contrast negative compensation value and the initial negative compensation value is within a first preset range;
setting a plurality of different contrast exposure energy values according to the initial exposure energy value, wherein the absolute value of the difference value between each contrast exposure energy value and the initial exposure energy value is in a second preset range;
Combining each different contrast negative compensation value with each different contrast exposure energy value respectively to form a plurality of different experimental groups, exposing each experimental group under the conditions of the same line and the same monitoring quantity, and screening out the experimental groups capable of realizing vertical film completely after finishing;
and detecting line widths of all experimental groups for realizing vertical films respectively, selecting a group of experimental groups with highest line width precision after the detection is completed, and setting the corresponding contrast negative compensation value and the corresponding contrast exposure energy value in an exposure program of mass production.
Further, in step "setting a plurality of different contrast negative compensation values according to the initial negative compensation value", a plurality of the contrast negative compensation values are between-1.5 um and-2 um.
Further, in the step of setting a plurality of different comparative exposure energy values according to the initial exposure energy value, a plurality of the comparative exposure energy values are between 66mJ and 74 mJ.
Further, the plurality of the comparative exposure energy values are set as an arithmetic progression with a difference of 2 mJ.
Further, in the step of exposing each experimental group under the same line and the same monitoring number, and screening out the experimental groups capable of completely realizing standing films after finishing, the size of the line is 12/12um, the screened film standing conditions are that the line is observed by using a 40-time optical microscope, and the bottom and the side wall of the dry film are detected by using a scanning electron microscope, so that the standing films are realized without overexposure which can cause edge collapse or without defect state of underexposure which can cause image blurring.
Further, in the step of performing the detection of the line widths of the experimental groups for all the vertical films, after the detection is completed, a group of experimental groups with the highest line width accuracy is selected, and the detection includes the average value of the line widths, the standard deviation of the line widths, and the range of the line widths.
Further, according to a default specification upper limit, a specification median value and a specification lower limit of the line width, calculating the accuracy and precision of the line width of each experimental group, and according to the accuracy and precision of the line width of each group, calculating the precision.
Further, in the step of combining each of the different contrast negative compensation values with each of the different contrast exposure energy values, respectively, to form a plurality of different experimental groups, the number of samples of each of the experimental groups is 144.
Further, in the step of "detecting line widths of the experimental groups each of which realizes the vertical film, after the detection is completed, selecting a group of the experimental groups having the highest line width accuracy", selecting 9 samples from each group of the experimental groups to perform the detection, and repeating the monitoring 3 times.
By the technical scheme, the invention has the following beneficial effects:
According to the method for improving the analytical capability of the IC carrier circuit, disclosed by the invention, the alternative scheme capable of realizing the vertical film is obtained by comparing and screening a plurality of experimental groups after recombination based on a plurality of different contrast negative compensation values and different contrast exposure energy values which are set in the preset range of the initial negative compensation value and the initial exposure energy value, and the line width is continuously detected in the alternative scheme, and the optimal contrast negative compensation value and the optimal contrast exposure energy value scheme are selected through precision and applied to actual mass production, so that the finished circuit with the highest precision, high quality and high analytical capability which can be realized under the existing condition can be produced in a mass way.
Drawings
In order to more clearly illustrate the embodiments of the present description or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some of the embodiments described in the present description, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of an experimental group for realizing vertical membrane of a method for improving the circuit resolution capability of an IC carrier board according to an embodiment of the present disclosure;
Fig. 2 is a schematic diagram of line width detection of a method for improving line resolution of an IC carrier according to an embodiment of the present disclosure;
Fig. 3 is a schematic diagram illustrating a method for improving circuit resolution of an IC carrier according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of laser drilling for a method for improving the circuit resolution of an IC carrier according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of chemical copper of a method for improving the circuit resolution of an IC carrier according to an embodiment of the present disclosure;
FIG. 6 is a schematic diagram illustrating a pre-lithography process for improving the circuit resolution of an IC carrier according to one embodiment of the present disclosure;
FIG. 7 is a schematic diagram of a photolithography module for improving the circuit resolution of an IC carrier according to an embodiment of the present disclosure;
FIG. 8 is an exposure/development schematic diagram of a method for improving the circuit resolution of an IC carrier according to an embodiment of the present disclosure;
FIG. 9 is a schematic diagram illustrating a method for improving circuit resolution of an IC carrier according to an embodiment of the present disclosure;
Fig. 10 is a schematic diagram illustrating a method for improving the circuit resolution capability of an IC carrier according to an embodiment of the present disclosure;
FIG. 11 is an etching schematic diagram of a method for improving the circuit resolution of an IC carrier according to an embodiment of the present disclosure;
Fig. 12 is a schematic diagram of a first screening experiment set of a method for improving the circuit resolution capability of an IC carrier according to an embodiment of the present disclosure;
Fig. 13 is a schematic diagram of a second screening experiment set of a method for improving the circuit resolution capability of an IC carrier according to an embodiment of the present disclosure;
Detailed Description
In order to make the technical solutions in the present specification better understood by those skilled in the art, the technical solutions in the embodiments of the present specification will be clearly and completely described below with reference to the drawings in the embodiments of the present specification, and it is obvious that the described embodiments are only some embodiments of the present specification, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are intended to be within the scope of the present disclosure.
In the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "upper", "middle", "lower", "inner", "outer", "front", "rear", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the apparatus or component to be referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention. The terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art. Hereinafter, an embodiment of the present invention will be described in terms of its overall structure.
The embodiment provides a method for improving the line analysis capability of an IC carrier plate, wherein an original exposure program comprises an initial negative compensation value and an initial exposure energy value, and the method for improving the line analysis capability of the IC carrier plate comprises the following steps:
setting a plurality of different contrast negative compensation values according to the initial negative compensation value, wherein the absolute value of the difference value between each contrast negative compensation value and the initial negative compensation value is within a first preset range;
Setting a plurality of different contrast exposure energy values according to the initial exposure energy value, wherein the absolute value of the difference value between each contrast exposure energy value and the initial exposure energy value is in a second preset range;
Combining each different contrast negative compensation value with each different contrast exposure energy value respectively to form a plurality of different experimental groups, exposing each experimental group under the conditions of the same line and the same monitoring quantity, and screening out experimental groups capable of completely realizing vertical film after finishing;
And respectively detecting line widths of a plurality of experimental groups for realizing vertical films, selecting a group of experimental groups with highest line width precision after the detection is finished, and setting corresponding contrast negative compensation values and contrast exposure energy values in an exposure program of mass production.
Aiming at the process, according to the factory side of processing equipment or the original experience, the initial negative compensation value and the initial exposure energy value which are commonly used in the existing exposure stage are obtained, under the production conditions of the default initial negative compensation value and the initial exposure energy value, the situation that the produced IC carrier board circuit cannot stand the film frequently occurs, that is to say, under the influence of the existing external conditions, the overexposure condition which leads to the edge collapse of the dry film or the underexposure condition which leads to the image blurring of the dry film can occur, and the problem of the yield which influences the normal use of the product, such as short circuit or open circuit, can occur.
The basic composition of the dry film photoresist in the link is mainly composed of high molecular polymer, functional monomer, initiator and the like, and the main component of the photoresist is the initiator, so that the absorption capability of the initiator, which shows difference in the exposure process, is the final reason of influence, and the initiator is taken as the original production basis, and is not easy to change from the viewpoint of cost and the like, therefore, the situation can be effectively improved by adjusting the initial negative compensation value and the initial exposure energy value of the exposure machine in the exposure process to reasonable parameters. Firstly, a parameter range needs to be selected in the embodiment, based on an initial negative compensation value and an initial exposure energy value, a plurality of values which are set in a preset range and have different front and rear sizes in two directions but are similar are used as available contrast negative compensation values and contrast exposure energy values, and then the contrast negative compensation values and the contrast exposure energy values are arranged and combined, so that each contrast negative compensation value is matched with another contrast exposure energy value to form groups, a plurality of corresponding experimental groups are finally obtained, and the next experimental group screening link capable of realizing vertical film can be performed. Specifically, the first preset range is a set of at least one value selected from a certain reasonable deviation range before and after the initial negative compensation value based on the initial negative compensation value, and can be theoretically used in a normal working situation of the exposure machine, and the second preset range is a set of exposure energy of a reasonable deviation range established based on the initial exposure energy value.
After the experimental group which can not realize the vertical film is removed, the rest experimental group which can realize the vertical film accords with the production requirement of the IC carrier circuit to a certain extent, and then the screening of the line width detection of the next link can be carried out. In the screening of the round, firstly, the line width of an experimental group object capable of realizing vertical film is required to be measured, after a plurality of groups of detection results are converged, the line width result of each experimental group is analyzed by a method such as process capability analysis (Process Capability Analysis) in Statistical Process Control (SPC), and corresponding precision values in each experimental group are obtained, finally, the contrast negative compensation value and the contrast exposure energy value of one of the experimental groups with the highest precision can be directly adopted to input into an exposure machine, and the production of a finished circuit with high precision, high quality and high analytic capability is realized through the data in mass production. Specifically, the exposure machine used is a solar ORC and IP series laser exposure machine.
In the process, the obtained result can be directly put into the existing exposure application by carrying out calculation after screening for multiple times based on the existing equipment and parameters, the exposure high-resolution capability is further improved, the production quality is improved, the equipment and raw materials are not required to be added or replaced in a large batch in the whole link, only a small degree of experiments are required, the cost is low, and the exposure precision quality can be obviously improved.
In this embodiment, experiments are performed based on SAP (Semi-Additive Process) technology, and since the metal layer to be etched in the SAP technology is thin, the bottom metal layer can be removed by rapid etching, so that the problem of side etching can be solved, and the method is suitable for fine circuit manufacturing, and can realize rapid screening of experiments.
Specifically, in the SAP process of the present embodiment, the other steps before the exposure experiment are all constant in the controlled variable method, maintaining a consistent operation. Wherein, in the step of laminating as shown in fig. 3, a dielectric layer is laminated by using a lamination roller, and a GL series ABF film is matched under the condition; in the laser drilling step shown in fig. 4, a laser drilling device is used to drill through the first dielectric layer to form a blind hole; in the step of chemical copper shown in fig. 5, a layer of chemical copper is deposited on the dielectric layer, the thickness of the chemical copper is between 0.5um and 1um, the main purpose is to realize resin and glass cloth metallization on the blind holes and the non-conductor parts of the hole wall around the dielectric layer, the chemical copper is used as a substrate of the subsequent electroplating copper process, the chemical copper comprises whole holes, activation, rapid solidification and chemical copper, wherein the whole holes are formed by negatively charging the hole wall after drilling, the negatively charged tin-palladium Colloid (Pd/Sn Colloid) is adsorbed on the hole wall in a positive-negative phase absorption manner, and the electric property is adjusted by using a whole hole agent (surfactant), so that the hole wall is converted from negative to positive to facilitate the adsorption of the tin-palladium Colloid, wherein the activation is to enable the palladium Colloid to be adsorbed on the hole wall, promote the chemical copper precipitation, the deposition of copper atoms is provided, the rapid solidification is to strip the tin shell, the tin-palladium Colloid is exposed, and the chemical copper is well adhered and covered by a completely conductive layer on the hole wall, so as to be beneficial to the subsequent electroplating substrate; in the pre-process step of the micro-lithography shown in FIG. 6, copper surface is roughened first for better binding force between dry film and copper, the micro-etching is performed with sulfuric acid with concentration of 6+ -2% and copper surface oxide is removed, under the condition, GL series ABF film is matched, maximum height roughness of copper surface is 2 μm-3 μm, average roughness is 0.1 μm-0.4 μm, in addition, brush with different materials can be used to achieve the roughness condition, in the process of micro-lithography shown in FIG. 7, and (3) using a pressing method (Lamination), matching a solar RD series negative photoresist dry film with the thickness of 15-25 um, pressing a photosensitive dry film (photosensitive resin) on a substrate by using a roller, and selecting according to the copper thickness specification, wherein the pressure is set to be between 0.1MPa and 0.4MPa, the film pressing temperature is set to be between 70 and 90 ℃, and the baking is required to match the standing time of 10-20 min, so that the adhesion of the misplaced salts of the copper surface is better.
After the above steps, as shown in fig. 8, the exposing/developing steps in this embodiment can be performed, and the circuit is transferred to the photoresist covered by the copper surface by using the energy of ultraviolet light as a photomask, so as to form a photochemical reaction to generate a chain. And then, performing exposure operation by using a corresponding contrast negative compensation value and a contrast exposure energy value, and baking at 70-100 ℃ for 1 minute after exposure, wherein the curing degree of the exposed dry film is mainly enhanced. The dry film (negative photoresist) is exposed, the solubility of the dry film is reduced, the dry film is not dissolved in the developing process, the unexposed position is dissolved by the developing solution, wherein in the developing condition, the developing spray pressure is set to be 1.0bar-1.6bar, the developing temperature is set to be 50-60 ℃, in addition, a developing point test is needed, in particular, a developing line process capability checking method mainly confirming the developing capability is needed, in the embodiment, the step is to directly develop after film pressing on a copper plate, the whole dry film substrate is required to be dissolved within 40% of the groove length of a developing groove body, and copper plates are required to be displayed beyond 40%, namely, in the embodiment, the condition is required to be less than 40% in the developing point, and only the area with the maximum 40% is allowed to show the state that the resist is completely removed, so as to meet the requirement.
After the batch of experimental groups is completed, the experimental groups with the best exposure effect are screened out by the preamble method of the embodiment.
After the optimal experimental group is selected as a fixed parameter, in the mass production step, the steps of depositing a layer of electroplated copper on the copper as a substrate layer in the electroplating step shown in fig. 9, removing the solidified dry film by using a Stripping liquid in the Stripping step shown in fig. 10, attacking the solidified dry film by using strong alkali (NaOH or KOH) in the embodiment so as to cause swelling (Swelling), stripping (Stripping) and finally removing the stripped dry film by using physical flushing, and etching the chemical copper below (at the bottom) of the dry film in the etching step shown in fig. 11, wherein wet etching is used in the embodiment, specifically, the carrier plate manufacturing process is matched with a horizontal device, etching the bottom chemical copper in a physical flushing (spraying) mode, matching the etching liquid in the embodiment with sulfuric acid hydrogen peroxide, and finally adding a bank protecting agent, wherein the bank protecting agent can preferentially dissolve and remove the chemical copper (electroless copper) and inhibit the corrosion (side etching) of the electrolytic copper part so that the line width & line thickness are almost not lost. Thus, the production operation of the batch circuit boards is completed. Further, in the step of setting a plurality of different contrast negative compensation values according to the initial negative compensation value, the plurality of contrast negative compensation values are selected to be between-1.5 um and-2 um, specifically, the contrast negative compensation value in the present embodiment is selected to be two values of-1.5 um and-2 um, and simultaneously, the plurality of contrast exposure energy values are set to be an arithmetic progression having a difference of 2mJ, specifically, the contrast exposure energy values are selected to be five values of 66mJ, 68mJ, 70mJ, 72mJ, 74mJ, that is, the number of combined experimental groups in the present embodiment is 10 groups. The above selection is based on the initial negative compensation value of-3 um and the initial exposure energy value of 69mJ recommended by the manufacturers of daily series raw materials, and is obtained by combining the negative compensation value of the historical optimal exposure quality parameter of-1.5 um and the exposure energy value of 70mJ to extend and explore, and of course, in other embodiments, the comparison negative compensation values and the comparison exposure energy values with different numbers and different numerical spans can be selected according to the needs, but the number of experimental groups may be excessive, the experimental screening efficiency is affected, or the number of the experimental groups is too small, and the performance of the final effective result is affected.
Further, in the step of exposing each experimental group under the same line and the same monitoring number, and screening out the experimental groups capable of completely realizing standing films after finishing, the line size is 12/12um, the detection number is 144 in each group, the screened realizing standing film condition is that the line is observed by using a 40-time optical microscope, and then the bottom and the side wall of the dry film are detected by using a scanning electron microscope, so that the standing film is realized without overexposure which can cause edge collapse or defect-free state which can cause insufficient image blurring. Wherein, scanning electron microscope is SEM (Scanning Electron Microscope), uses its electron gun to produce electron beam to detect the bottom and side wall of dry film, ensures that it can have the electric property that accords with the expectations. Specifically, with the control variables, the dimensions of the lines for the experimental groups, the exposure time, and the number of samples in each experimental group were all the same except for the difference between the comparative negative compensation value and the comparative exposure energy value for each experimental group, and experimental data shown in fig. 12 were obtained.
As can be seen from the experimental results in fig. 12, among the above 10 experimental groups, the experimental group 5 using-1.5 um of the comparative negative compensation value and the comparative exposure energy value of 74mJ, the experimental group 9 using-2 um of the comparative negative compensation value and the comparative exposure energy value of 72mJ, and the experimental group 10 using-2 um of the comparative negative compensation value and the comparative exposure energy value of 74mJ passed the screening of standing films. Therefore, the 3 sets of data in this embodiment can enter the line width detection of the next link.
Further, in the step of "detecting the line widths of all the experimental groups for realizing the vertical film, respectively, after the detection is completed, a group of experimental groups with highest line width accuracy is selected", and the detection includes the average value of the line widths, the standard deviation of the line widths, and the range of the line widths. And calculating the accuracy and precision of the line width of each experimental group according to the default specification upper limit, specification median and specification lower limit of the line width, and calculating the precision according to the accuracy and precision of the line width of each group. Wherein the analysis is performed by a process capability analysis (Process Capability Analysis) in Statistical Process Control (SPC).
In this embodiment, USL is the upper specification limit, defaults to 17um, T is the median specification, defaults to 12um, LSL is the lower specification limit, defaults to 7um, μ is the average of the samples, and σ is the process standard deviation.
The accuracy is Ca value, which is the deviation degree of the average value of the process relative to the specification center value, wherein Ca is positive value to indicate that the actual result value is higher, ca is negative value to indicate that the actual result value is lower, and Ca is smaller to indicate that the actual result is closer to the target value;
The accuracy is Cp, which is the number of + -3σ (i.e. 6σ) that can be accommodated between the upper and lower limits of the specification when the variation width of the process is measured to be different from the upper and lower limits of the specification. The smaller the degree of variation of the process, the better the precision;
The accuracy is Cpk, which is a comprehensive index of Cp and Ca, and reflects the actual effect of the present embodiment by considering the position of the average value of the process and the degree of variation of the process.
Specifically, the calculation method of the accuracy is Ca= (μ -T)/((USL-LSL)/2);
the calculation method of the precision is Cp= (USL-LSL)/(6σ);
the calculation method of the precision is Cpk= (1- |Ca|) Cp.
In summary, for data from 3 experimental groups, 9 samples were selected from each experimental group for testing, and the monitoring was repeated 3 times, and the results are shown in fig. 13.
The specific result can be referred to fig. 2, and finally it can be obtained that the experimental set 9 has the highest accuracy, that is, the negative contrast compensation value-2 um and the exposure energy value 72mJ in the experimental set 9 can be adopted and set in the exposure machine for the exposure operation of the mass production operation, so that the best accuracy is provided, and the resolving power of the IC carrier circuit can be significantly improved.
In addition, in another embodiment, after the experimental set 9 is obtained with the highest accuracy, a step of performing a shear force test on the experimental set 9 is required, and the shear force required to meet the finally screened IC carrier board circuit is greater than 0.3kN/m, preferably controlled between 0.3kN/m and 0.4kN/m, so as to meet the quality and reliability of the subsequent input mass production.
Further, in the above embodiment, the matched substrates are of uniform type, specifically 510mmx510mm size, 0.2mm-2.4mm thickness, 12-100um wire grade and 10-30um copper thick substrate product.
Although various embodiments are described in this disclosure, the present application is not limited to the specific embodiments described in the industry standard or examples, and some industry standard or embodiments modified by the use of custom or embodiment described herein may achieve the same, equivalent or similar results as the embodiments described in the embodiments described above, or as expected after modification. Examples of data acquisition, processing, output, judgment, etc. using these modifications or variations are still within the scope of alternative embodiments of the present application.
Although the present application has been described by way of examples, one of ordinary skill in the art will recognize that there are many variations and modifications of the present application without departing from the spirit of the application, and it is intended that the appended embodiments encompass such variations and modifications without departing from the application.
Claims (7)
1. A method for improving the line analysis capability of an IC carrier plate is characterized in that the method for improving the line analysis capability of the IC carrier plate comprises the following steps of:
setting a plurality of different contrast negative compensation values according to the initial negative compensation value, wherein the absolute value of the difference value between each contrast negative compensation value and the initial negative compensation value is within a first preset range;
setting a plurality of different contrast exposure energy values according to the initial exposure energy value, wherein the absolute value of the difference value between each contrast exposure energy value and the initial exposure energy value is in a second preset range;
Combining each different contrast negative compensation value with each different contrast exposure energy value respectively to form a plurality of different experimental groups, exposing each experimental group under the conditions of the same line and the same monitoring quantity, and screening out the experimental groups capable of realizing vertical film completely after finishing;
detecting the line widths of all experimental groups for realizing vertical films, selecting a group of experimental groups with highest line width precision after the detection is finished, and setting the corresponding contrast negative compensation value and the corresponding contrast exposure energy value in an exposure program for mass production;
Wherein a plurality of said contrast negative compensation values are between-1.5 um and-2 um and a plurality of said contrast exposure energy values are between 66mJ and 74 mJ.
2. The method of claim 1, wherein the plurality of contrast exposure values are arranged in an arithmetic progression having a difference of 2 mJ.
3. The method for improving the analytical capability of the circuit of the IC carrier board according to claim 1, wherein in the step of exposing each experimental group under the same circuit and the same monitoring number, and screening out the experimental groups capable of fully realizing the standing film after finishing, the size of the circuit is 12/12um, the screening realizing standing film condition is that the circuit is observed by using a 40 times optical microscope, and then the bottom and the side wall of the dry film are detected by using a scanning electron microscope, so that the standing film is realized without overexposure which can cause edge collapse and without defect state of underexposure which can cause image blurring.
4. The method for improving the circuit resolution of an IC carrier according to claim 1, wherein in the step of detecting the line widths of the plurality of experimental groups which all realize vertical films, respectively, after the detection is completed, a group of experimental groups with the highest line width accuracy is selected, and the detection includes the average value of the line widths, the standard deviation of the line widths, and the range of the line widths.
5. The method of claim 4, wherein the accuracy and precision of the line widths of each of the experimental groups are calculated according to default upper, middle and lower specification limits of the line widths, and the precision is calculated according to the accuracy and precision of the line widths of each of the experimental groups.
6. The method of claim 1, wherein in the step of combining each different contrast negative compensation value with each different contrast exposure energy value to form a plurality of different test groups, the number of samples in each test group is 144.
7. The method according to claim 6, wherein in the step of detecting the line widths of the plurality of experimental groups each of which realizes the vertical film, after the detection is completed, 9 samples are selected from each of the experimental groups to perform the detection, and the detection is repeated 3 times.
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| CN116170955A (en) * | 2023-04-21 | 2023-05-26 | 广州添利电子科技有限公司 | Dynamic etching compensation method for fine circuit |
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| CN116170955A (en) * | 2023-04-21 | 2023-05-26 | 广州添利电子科技有限公司 | Dynamic etching compensation method for fine circuit |
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