CN118826429B

CN118826429B - Power conversion devices and electronic equipment

Info

Publication number: CN118826429B
Application number: CN202410913803.XA
Authority: CN
Inventors: 王益峰
Original assignee: Shanghai Awinic Technology Co Ltd
Current assignee: Shanghai Awinic Technology Co Ltd
Priority date: 2024-07-08
Filing date: 2024-07-08
Publication date: 2025-08-29
Anticipated expiration: 2044-07-08
Also published as: CN118826429A

Abstract

The embodiment of the invention provides a power conversion device and electronic equipment. The power conversion device comprises a power conversion circuit, a signal processing circuit and a power output circuit, wherein the power conversion circuit comprises a first switching tube, a second switching tube and an inductance unit, one end of the inductance unit is connected to a first bias voltage, the other end of the inductance unit is connected to a second bias voltage through the first switching tube, the signal processing circuit is connected with the power conversion circuit and is used for conducting pulse width modulation on an input signal to obtain a first PWM signal and a second PWM signal with time sequence matching, the first PWM signal and the second PWM signal are respectively output to the first switching tube and the second switching tube to alternately control on-off of the first switching tube and the second switching tube, and the power output circuit is connected to the other end of the inductance unit through the second switching tube and is used for outputting an output conversion signal of the input signal.

Description

Power conversion device and electronic equipment

Technical Field

The embodiment of the invention relates to the technical field of electronic circuits, in particular to a power conversion device and electronic equipment.

Background

A power conversion device such as a power converter changes a signal voltage by boosting or stepping down, wherein a signal processing circuit performs signal processing to obtain a series of PWM (Pulse Width Modulation ) signals, and performs power amplification and signal output through signal conversion to drive a capacitive load to operate. Such power conversion devices are widely used in applications requiring voltage conversion and power amplification, such as audio amplifiers, power supplies, motor drivers, and the like.

In the prior art, when signal conversion is performed, a PWM signal is required to control on-off of a large number of switching tubes, however, a large number of switching tubes often occupy a large area, which is not beneficial to miniaturization of the power conversion device and the electronic device carrying the power conversion device.

Disclosure of Invention

In view of the above, an embodiment of the present invention provides a power conversion device and an electronic apparatus to solve the above-mentioned problems.

According to a first aspect of the embodiment of the invention, a power conversion device is provided, which comprises a power conversion circuit, a signal processing circuit and a power output circuit, wherein the power conversion circuit comprises a first switch tube, a second switch tube and an inductance unit, one end of the inductance unit is connected to a first bias voltage, the other end of the inductance unit is connected to a second bias voltage through the first switch tube, the signal processing circuit is connected with the power conversion circuit and is used for carrying out pulse width modulation on an input signal to obtain a first PWM signal and a second PWM signal with time sequences matched, and the first PWM signal and the second PWM signal are respectively output to the first switch tube and the second switch tube so as to alternately control the on-off state of the first switch tube and the second switch tube, and the power output circuit is connected to the other end of the inductance unit through the second switch tube and is used for outputting an output conversion signal of the input signal.

In another implementation mode of the invention, the power conversion circuit further comprises a third switching tube, the power output circuit is connected to the other end of the inductance unit through the third switching tube, the signal processing circuit is used for conducting pulse width modulation on the input signal in the first half period of the whole period of the input signal to obtain a first PWM signal and a second PWM signal with time sequence matching, and conducting pulse width modulation on the input signal in the second half period of the whole period of the input signal to obtain a first PWM signal and a third PWM signal with time sequence matching, and the first PWM signal and the third PWM signal are respectively used for controlling on-off of the first switching tube and the third switching tube.

In another implementation mode of the invention, the signal processing circuit is used for carrying out pulse width modulation on the input signal at a sampling point of the first half period according to a first preset duty ratio to obtain a first PWM signal and a second PWM signal which are matched in time sequence in the first half period, and carrying out pulse width modulation on the input signal at a sampling point of the second half period according to a second preset duty ratio to obtain a first PWM signal and a third PWM signal which are matched in time sequence in the second half period, wherein the first preset duty ratio and the second preset duty ratio are complementary.

In another implementation of the present invention, the third PWM signal is used to control the third switching tube to be in a normally-off state in the second half period, and the second PWM signal is used to control the second switching tube to be in a normally-off state in the second half period.

In another implementation manner of the present invention, the power output circuit includes a first output terminal and a second output terminal, the first output terminal is connected to the other end of the inductance unit through the second switching tube, and the second output terminal is connected to the other end of the inductance unit through the third switching tube, wherein the power output circuit outputs an output conversion signal of the input signal between the first output terminal and the second output terminal.

In another implementation of the present invention, the power output circuit further includes a fourth switching tube connected between the first output terminal and a third bias voltage, and a fifth switching tube connected between the second output terminal and the third bias voltage. The signal processing circuit is further configured to generate a first commutation signal for controlling the fourth switching tube to be normally off in the first half period and to be normally on in the second half period, and a second commutation signal for controlling the fifth switching tube to be normally on in the first half period and to be normally off in the second half period.

In another implementation of the invention, the first output is connected to a positive pole of a capacitive load and the second output is connected to a negative pole of the capacitive load in an in-phase switching mode, and the first output is connected to a negative pole of the capacitive load and the second output is connected to a positive pole of the capacitive load in an anti-phase switching mode.

In another implementation manner of the present invention, the power conversion device further includes a substrate selection circuit, at least one of the second switching tube and the third switching tube is a MOS tube, and the substrate selection circuit is connected to a source electrode, a drain electrode and a substrate of the MOS tube, respectively. The substrate selection circuit connects the substrate to one of the drain and the source with a higher voltage if the MOS transistor is a P-type MOS transistor, and connects the substrate to one of the drain and the source with a lower voltage if the MOS transistor is an N-type MOS transistor.

In another implementation of the invention, the first bias voltage is greater than the second bias voltage in a boost conversion mode, and the first bias voltage is less than the second bias voltage in a buck conversion mode.

According to a second aspect of an embodiment of the present invention, there is provided an electronic device comprising a capacitive load, and a power conversion arrangement according to the first aspect, the power conversion arrangement providing an output conversion signal to the capacitive load.

In the capacitive load driving scheme of the embodiment of the invention, the switching-on and switching-off of the first switching tube and the second switching tube are alternately controlled through the converted first PWM signal and the converted second PWM signal, and the power output circuit obtains a voltage signal matched with the waveform of the input signal. In addition, when the on-off of the first switching tube and the second switching tube are alternately controlled, the transient current of the inductance unit is unchanged to generate reverse electromotive force, so that the power output circuit obtains a voltage signal of the first bias voltage after the first bias voltage is boosted or reduced through the voltage difference between the second bias voltage and the first bias voltage, the switching tubes are multiplexed to perform power conversion and waveform matching, the number of switching tubes in the power conversion device is reduced, and further the device miniaturization of the power conversion device is facilitated.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the embodiments of the present invention, and other drawings may be obtained according to these drawings for a person having ordinary skill in the art.

Fig. 1 is a schematic block diagram of a power conversion apparatus according to some embodiments of the present invention.

Fig. 2 is a schematic block diagram of a further example power conversion apparatus of the embodiment of fig. 1.

Fig. 3 is a circuit diagram of the power conversion apparatus of the embodiment of fig. 1 and 2.

Fig. 4 is a signal timing diagram of each switching tube in the embodiment of fig. 3.

Fig. 5 is a circuit diagram of the substrate selection circuit in the power conversion device in the embodiment of fig. 1.

Fig. 6 is a schematic structural diagram of the substrate selection circuit of fig. 5.

Fig. 7A and 7B are block diagrams of other modifications of the switching tube.

Fig. 8 is a schematic structural view of an electronic device according to other embodiments of the present invention.

Detailed Description

In order to better understand the technical solutions in the embodiments of the present invention, the following description will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which are derived by a person skilled in the art based on the embodiments of the present invention, shall fall within the scope of protection of the embodiments of the present invention.

The implementation of the embodiments of the present invention will be further described below with reference to the accompanying drawings.

Fig. 1 illustrates a power conversion apparatus of some embodiments of the invention. The power conversion apparatus 100 of fig. 1 includes a power conversion circuit 110, a signal processing circuit 120, and a power output circuit 130.

Specifically, the power conversion circuit 110 includes a first switching tube, a second switching tube, and an inductance unit, wherein one end of the inductance unit is connected to a first bias voltage, and the other end of the inductance unit is connected to a second bias voltage through the first switching tube.

It should be understood that the M1 tube may be an example of a first switching tube, the M2 tube may be an example of a second switching tube, the inductance L is an example of an inductance unit, and the inductance unit may further include a structure formed by connecting a plurality of inductances in series or in parallel. In addition, in the boost conversion mode, the first bias voltage is larger than the second bias voltage, for example, the voltage value of VDD (an example of the first bias voltage) is larger than the ground voltage value (an example of the second bias voltage), and in the buck conversion mode, the first bias voltage is smaller than the second bias voltage, for example, the ground voltage value (an example of the first bias voltage) is smaller than the voltage value of VDD (an example of the second bias voltage).

Further, the signal processing circuit 120 is connected to the power conversion circuit, and the signal processing circuit 120 is configured to pulse-width modulate an input signal to obtain a first PWM signal (e.g., PWM1 signal in fig. 1) and a second PWM signal (e.g., PWM2 signal in fig. 1) that are time-series-matched, and output the first PWM signal and the second PWM signal to the first switching transistor and the second switching transistor, respectively, so as to alternately control on-off of the first switching transistor and the second switching transistor, that is, the other end SW (switch) of the inductance unit is switched between a state connected to the second bias voltage and a state connected to the first output terminal.

It should be appreciated that in some examples, the signal processing circuit may pulse width modulate the sampling points of the input signal according to a first preset duty cycle to obtain a first PWM signal and a second PWM signal that are time-matched. For example, the first PWM signal and the second PWM signal are time-sequentially matched, so that the first switching tube and the second switching tube are alternately switched on and off, and the high voltage and the low voltage are alternately output at the first output end, so that an output conversion signal is formed. That is, the boosted voltage of the first bias voltage is set to a high voltage, the third bias voltage is set to a low voltage, or the third bias voltage is set to a high point voltage, and the stepped down voltage of the first bias voltage is set to a low voltage.

Further, the power output circuit 130 is connected to the other end of the inductance unit through a second switching tube, and the power output circuit 130 is used for outputting an output conversion signal of the input signal.

It should be appreciated that the power output circuit 130 includes a first output terminal (Vout 1) and a second output terminal (not shown) between which a capacitive load (CAPACITIVE LOAD), such as a capacitor or piezoelectric actuator, may be connected. In general, a capacitive load refers to a load that exhibits capacitive characteristics when a current passes through, i.e., the capacitive load is capable of storing electrical energy and releasing such energy when needed. In some examples, one of the first output terminal and the second output terminal may be connected to the other end of the inductance unit through a second switching tube, and the other is connected to a third bias voltage, which may have a voltage value independent of the first bias voltage and the second bias voltage.

In the embodiment of fig. 1, the waveform of the input signal may be a periodic waveform, which may or may not have half-cycle symmetry.

In the capacitive load driving scheme of the embodiment of the invention, the switching-on and switching-off of the first switching tube and the second switching tube are alternately controlled through the converted first PWM signal and the converted second PWM signal, and the power output circuit obtains a voltage signal matched with the waveform of the input signal. In addition, when the on-off of the first switching tube and the second switching tube are alternately controlled, the transient current of the inductance unit is unchanged to generate reverse electromotive force, so that the power output circuit obtains a voltage signal of the first bias voltage after the first bias voltage is boosted or reduced through the voltage difference between the second bias voltage and the first bias voltage, the switching tubes are multiplexed to perform power conversion and waveform matching, the number of switching tubes in the power conversion device is reduced, and the device miniaturization of the power conversion device is facilitated.

Fig. 2 shows a further example of a power conversion arrangement of the embodiment of fig. 1. As shown in fig. 2, the power conversion circuit 110 further includes a third switching tube, the power output circuit 130 includes a capacitive load, two ends of the capacitive load are a first output end and a second output end, the first output end is connected to the other end of the inductance unit through the second switching tube, and the second output end is connected to the other end of the inductance unit through a third switching tube (M3 tube is an example of the third switching tube). In addition, examples of the first PWM signal, the second PWM signal, and the third PWM signal are the PWM1 signal, the PWM2 signal, and the PWM3 signal in fig. 2, respectively.

In the embodiment of fig. 2, the waveform of the input signal has half-cycle symmetry, i.e. the first half-cycle and the second half-cycle are centered about the horizontal axis characterizing time. More specifically, for an input signal of a sinusoidal waveform, the first half-cycle may also be a positive half-cycle and the second half-cycle may be a negative half-cycle, because the sinusoidal waveform has a positive signal amplitude in the first half-cycle and a negative signal amplitude in the second half-cycle, which characterizes the longitudinal axis of the signal amplitude. Correspondingly, the signal processing circuit 120 is configured to perform pulse width modulation on an input signal in a first half period of the whole period of the input signal to obtain a first PWM signal and a second PWM signal with matched time sequences, and perform pulse width modulation on the input signal in a second half period of the whole period of the input signal to obtain a first PWM signal and a third PWM signal with matched time sequences, where the first PWM signal and the third PWM signal are respectively used to control on-off of the first switching tube and the third switching tube.

That is, in the first half period, the other end (SW) of the inductance unit is switched between a state connected to the second bias voltage and a state connected to the first output terminal by the first PWM signal and the second PWM signal. In the second half period, the other end (SW) of the inductance unit is switched between a state of being connected to the second bias voltage and a state of being connected to the second output terminal by the first PWM signal and the third PWM signal.

In the scheme of the embodiment of the invention, the switching-on and switching-off of the first switching tube and the third switching tube are alternately controlled through the converted first PWM signal and the converted third PWM signal, and the power output circuit obtains a voltage signal matched with the waveform of the input signal. In addition, when the on-off of the first switching tube and the third switching tube are alternately controlled, the transient current of the inductance unit is unchanged to generate reverse electromotive force, so that the power output circuit obtains a voltage signal of the first bias voltage after the first bias voltage is boosted or reduced through the voltage difference between the second bias voltage and the first bias voltage, the switching tubes are multiplexed to perform power conversion and waveform matching, the number of switching tubes in the power conversion device is reduced, and further the device miniaturization of the power conversion device is facilitated.

In addition, the first PWM signal and the second PWM signal are time-sequentially matched in the first half period, and the first PWM signal and the third PWM signal are time-sequentially matched in the second half period, so that conversion of the reverse symmetrical waveform signal in the whole period such as a sinusoidal waveform or a triangular waveform is realized. The first PWM signal controls the on-off of the first switching tube in the whole period, and the waveform conversion capability of the first switching tube is fully utilized, so that the number of switching tubes is further saved. For waveform signals such as sinusoidal waveforms, the first half-cycle may be a positive half-cycle and the second half-cycle may be a negative half-cycle in some examples, alternatively, the first half-cycle may be a negative half-cycle and the second half-cycle may be a positive half-cycle.

Further, in the present embodiment, the first output terminal may be connected to the other end of the inductance unit through the second switching tube, and the second output terminal may be connected to the other end of the inductance unit through the third switching tube.

Without loss of generality, when the connection is made through a switching tube, the connection may be made through a non-control end of the switching tube. In the example where the switching tube is a MOS tube, the source and drain are non-control terminals and the gate is a control terminal. When the switching tube is a transistor, one of the collector, the emitter and the base may be a control terminal, and the other two may be non-control terminals (first and second terminals). For example, a first end of the second switching tube is connected to the first output terminal, and a second end of the second switching tube is connected to the other end of the inductance unit. For another example, a first end of the third switching tube is connected to the second output terminal, and a second end of the third switching tube is connected to the other end of the inductance unit.

That is, the first output terminal is connected to the other end of the inductance unit through the second switching tube, and the second output terminal is connected to the other end of the inductance unit through the third switching tube, wherein the power output circuit outputs an output switching signal of the input signal between the first output terminal and the second output terminal.

In the connection relation of the present embodiment, the input terminal of the signal processing circuit receives an input signal, and after processing of the input signal is performed, a first PWM signal, a second PWM signal, and a third PWM signal, which are time-sequentially matched, are output from a first output terminal, a second output terminal, and a third output terminal (not shown), respectively. The first output end, the second output end and the third output end are respectively connected to the control end of the first switching tube, the control end of the second switching tube and the control end of the third switching tube.

In other specific examples, the signal processing circuit is configured to pulse width modulate the input signal at the sampling point of the first half cycle according to a first preset duty cycle to obtain a first PWM signal and a second PWM signal that are time-sequentially matched in the first half cycle. For example, the first PWM signal and the second PWM signal are time-sequentially matched in the first half period, so that the first switching tube and the second switching tube are alternately switched on and off to alternately output high and low voltages at the first output terminal, and an output conversion signal is formed.

The signal processing circuit is further used for carrying out pulse width modulation at sampling points of the second half period according to a second preset duty ratio to obtain a first PWM signal and a third PWM signal which are matched in time sequence in the second half period, wherein the first preset duty ratio and the second preset duty ratio are complementary. For example, the first PWM signal and the third PWM signal are time-sequentially matched in the second half period, so that the first switching tube and the third switching tube are alternately switched on and off to alternately output high and low voltages at the second output terminal, and an output conversion signal is formed.

As another example, as an example in which the first preset duty cycle and the second preset duty cycle are complementary, the sum of the first preset duty cycle and the second preset duty cycle is 1, at this time, the amplitude of the output waveform of the first half cycle and the amplitude of the output waveform of the second half cycle are precisely symmetrical about the time axis.

In other specific examples, the third PWM signal is used to control the third switching tube to be in a normally-off state in the second half period, and the second PWM signal is used to control the second switching tube to be in a normally-off state in the second half period, so that the second switching tube and the third switching tube are in the normally-off state in the corresponding half period under the condition of ensuring continuous output of the PWM signal. In addition, in this way, the influence of the third bias voltage on the output switching signal can be canceled between the first output terminal and the second output terminal.

In other embodiments, the power output circuit further includes a fourth switching tube connected between the first output terminal and the third bias voltage and a fifth switching tube connected between the second output terminal and the third bias voltage. The signal processing circuit is further used for generating a first reversing signal and a second reversing signal, wherein the first reversing signal is used for controlling the fourth switching tube to be normally closed in a front half period and to be normally open in a rear half period, and the second reversing signal is used for controlling the fifth switching tube to be normally open in the front half period and to be normally closed in the rear half period, so that under the condition that continuous output of the reversing signal is ensured, normally closed states and normally open states of the fourth switching tube and the fifth switching tube in corresponding half periods are avoided, and the fourth switching tube and the fifth switching tube are prevented from being simultaneously in an on state or simultaneously in an off state. In addition, the normally-off state and the normally-on state of the fourth switching tube and the fifth switching tube in the corresponding half periods reduce the integral on-off operation times of each switching tube in the power conversion circuit, and save the power consumption caused by on-off operation.

The signal conversion process of some embodiments of the present invention will be described in detail below in conjunction with fig. 3 and 4. Fig. 3 is a circuit diagram generally describing the signal conversion process of the present embodiment. Fig. 4 shows a timing diagram of the respective control signals, specifically, described and illustrated in connection with the positive half-cycle and the negative half-cycle of the sinusoidal waveform signal, respectively.

It should be understood that in the example of fig. 3, the first switching tube is an M1 tube, the second switching tube is an M2 tube, the third switching tube is an M3 tube, and the inductance unit is exemplarily implemented as an inductance L. In the first half period (for example, a T1 period in fig. 4), the other end (SW) of the inductance unit is switched between a state connected to the second bias voltage and a state connected to the first output terminal by the first PWM signal and the second PWM signal. In the latter half period (for example, the T2 period in fig. 4), the other end (SW) of the inductance unit is switched between a state connected to the second bias voltage and a state connected to the second output terminal by the first PWM signal and the third PWM signal.

The first bias voltage is VDD, and the second bias voltage is ground. In addition, as shown in fig. 3, the first output terminal Vout1 outputs an HDP signal, and the second output terminal Vout2 outputs an HDN signal. In the embodiments of fig. 3 and 4, taking a sine waveform (i.e., sin waveform) signal as an example, the entire period of the sine waveform may be divided into a first half period, which may be a positive half period, and a second half period, which may be a negative half period. For example, the positive half cycle and the negative half cycle are the T1 period and the T2 period in fig. 4, respectively. That is, the first half cycle of each full cycle is in time succession to the second half cycle of the full cycle, and the second half cycle of each full cycle is in time succession to the first half cycle of the next full cycle. For a sinusoidal waveform signal, the first half-cycle is a positive half-cycle and the second half-cycle is a negative half-cycle.

It should also be appreciated that in the present embodiment, the power conversion apparatus performs signal amplification processing, that is, the first bias voltage is greater than the second bias voltage, for example, the first bias voltage is VDD and the second bias voltage is ground.

It should also be appreciated that in the example shown in fig. 3, the power output circuit includes a fourth switching tube and a fifth switching tube, with M4 being an example of the fourth switching tube and M5 being an example of the fifth switching tube. The LS1 signal is an example of a first commutation signal for controlling the on-off of M4, and the LS2 signal is an example of a second commutation signal for controlling the on-off of M5. The power output circuit further includes a first output for outputting a high side Positive drive signal (HIGH SIDE DRIVE Positive, HDP) and a second output for outputting a high side negative drive signal (HIGH SIDE DRIVE NEGATIVE, HDN). In addition, a capacitive load such as a capacitor or a piezoelectric actuator is connected between the first output terminal and the second output terminal, that is, an input signal is output from between the first output terminal and the second output terminal after being converted by the power conversion device.

It is also understood that the input signal is the signal to be converted, and in the boost conversion mode, the voltage difference Vpp between the peak and the valley of the input signal has a smaller magnitude, and the voltage difference Vpp between the peak and the valley of the output conversion signal has a larger magnitude. The signal processing circuit performs pulse width modulation on the input signal to obtain a first PWM signal, a second PWM signal, and a third PWM signal including information of "input signal", for example, PWM1 signal, PWM2 signal, and PWM3 signal in fig. 4, respectively. The first PWM signal, the second PWM signal, and the third PWM signal are used to control the M1 pipe, the M2 pipe, and the M3 pipe, respectively.

As shown in fig. 4, the output conversion signal of the HDP signal in the period T1 is a sinusoidal waveform signal of a positive half period, the signal of the HDN signal in the period T2 is a sinusoidal waveform signal of a negative half period, and the sinusoidal waveform signal of the positive half period and the sinusoidal waveform signal of the negative half period are spliced to obtain a sinusoidal waveform signal of a full period. It should be appreciated that switching between the polarity of the output switching signal of the first half cycle and the polarity of the output switching signal of the second half cycle is performed through the M4 pipe and the M5 pipe.

It should be appreciated that while in the example of fig. 4, the schematic high level indicates that the switching tube has an on state and the schematic low level indicates that the switching tube is in an off state, for a particular implementation of the switching tube, the on and off states of the switching tube have actual level states, not necessarily schematic level states. For another example, in the first half period, the PWM1 signal and the PWM2 signal have opposite level states, and in the second half period, the PWM1 signal and the PWM3 signal have opposite level states. However, the foregoing examples are for the purpose of illustration and explanation only and are not to be construed as limiting the embodiments of the present invention.

Further, in the T1 period, the amplification factor of the power conversion device is determined by the signal processing circuit, and corresponding PWM1 signal and PWM2 signal are generated. As shown in fig. 4, during the period T1, the M3 pipe is in a normally-off state, the M4 pipe is in a normally-off state by the control of the LS1 signal, and the M5 pipe is in a normally-on state by the control of the LS2 signal. The signal processing circuit receives a positive half cycle of a sinusoidal waveform signal as an input signal, and pulse width modulates the sinusoidal waveform signal to obtain a PWM1 signal and a PWM2 signal including signal information of the input signal. In the period T1, the on-off of the M1 pipe and the M2 pipe are respectively controlled through the PWM1 signal and the PWM2 signal, the sine waveform signal is amplified to the HDP signal to be output, and at the moment, the output of the HDN signal in the period T1 is VS (an example of a third bias voltage) and is the voltage. That is, the M5 tube is normally open during the T1 period, the HDN signal has a voltage VS during the T1 period, and the HDP signal has a sine waveform signal of an amplified positive half cycle during the T1 period. Accordingly, in the T1 period, the voltage difference Vp of the HDP signal and the HDN signal is a sinusoidal waveform signal of a positive half period (VDD is boosted to PVDD in the boost conversion mode), which is loaded to the capacitive load between the first output terminal of the HDP signal and the second output terminal of the HDN signal.

Without loss of generality, the third PWM signal is used for controlling the third switching tube to be in a normally-off state in the second half period, and the second PWM signal is used for controlling the second switching tube to be in a normally-off state in the second half period, so that the second switching tube and the third switching tube are in the normally-off state in the corresponding half period under the condition of ensuring continuous output of the PWM signal. In addition, in this way, the influence of the third bias voltage on the output switching signal can be canceled between the first output terminal and the second output terminal.

Further, in the T2 period, the amplification factor of the power conversion device is determined by the signal processing circuit, and corresponding PWM1 signal and PWM3 signal are generated. As shown in fig. 4, at time T2, the M2 pipe is in a normally-off state, the M5 pipe is in a normally-off state by the control of the LS2 signal, and the M4 pipe is in a normally-on state by the control of the LS1 signal. The signal processing circuit receives a negative half cycle of a sinusoidal waveform signal as an input signal, and pulse width modulates the sinusoidal waveform signal to obtain a PWM1 signal and a PWM3 signal including signal information of the input signal. In the period T2, the on-off of the M1 pipe and the M3 pipe are controlled by the PWM1 signal and the PWM3 signal, respectively, and the sinusoidal waveform signal is amplified to the HDN signal to be output, and at this time, the output of the HDP signal in the period T1 is VS (an example of the third bias voltage). That is, the M4 tube is in a normally open state during the T2 period, the voltage of the HDP signal is VS during the T2 period, and the HDN signal is an amplified sine waveform signal of a negative half cycle during the T2 period. Accordingly, the voltage difference Vp of the HDP signal and the HDN signal is a sine waveform signal of a negative half period (VDD is boosted to PVDD in the boost conversion mode), the capacitive load applied between the first output terminal of the HDP signal and the second output terminal of the HDN signal ensures that the amplified sine waveform signal as the output conversion signal is in phase with the sine waveform signal as the input signal, forming a signal output of the full period, and the voltage difference Vpp between the peak and the valley of the output conversion signal is illustratively up to 2PVDD.

It should also be appreciated that the HDP signal is the output signal at the first output and the HDN signal is the output signal at the second output. Without loss of generality, the signal processing circuit outputs a first commutation signal (e.g., LS1 signal) and a second commutation signal (e.g., LS2 signal) from the fourth output terminal and the fifth output terminal, respectively, which are output to the control terminal of the fourth switching tube (e.g., M4) and the control terminal of the fifth switching tube (e.g., M5), respectively. For example, the fourth output terminal and the fifth output terminal (not shown) are connected to the control terminal of the fourth switching tube and the control terminal of the fifth switching tube, respectively. It is understood that the normally-off state and the normally-on state of the fourth switching tube and the fifth switching tube in the corresponding half periods reduce the overall on-off operation times of each switching tube in the power conversion circuit, and save the power consumption caused by on-off operation.

Alternatively, in the case of signal commutation, if the M3 tube is in a normally-off state in the T2 period, the M4 tube is in a normally-off state in the T2 period by control of the LS1 signal, and the M5 tube is in a normally-on state in the T2 period by control of the LS2 signal, the signal processing circuit pulse-width modulates the received sine waveform signal of the negative half period to obtain a PWM1 signal and a PWM2 signal, and the PWM1 signal and the PWM2 signal are used to control the M1 tube and the M2 tube, respectively, while amplifying the sine waveform signal to an HDP signal for output, and the output of the HDN signal is VS. At this time, the voltage difference between the HDP signal and the HDN signal is a sine waveform signal of a positive half period, and the inversion processing of the output conversion signal and the input signal in the inversion conversion mode is realized.

Without loss of generality, in the in-phase switching mode, the first output is connected to the positive pole of the capacitive load and the second output is connected to the negative pole of the capacitive load. That is, the output terminal connected to the positive electrode of the capacitive load is regarded as the first output terminal, and the output terminal connected to the negative electrode of the capacitive load is regarded as the second output terminal.

Accordingly, in the inverting switching mode, the first output terminal is connected to the negative pole of the capacitive load and the second output terminal is connected to the positive pole of the capacitive load. That is, the output terminal connected to the positive electrode of the capacitive load is regarded as the second output terminal, and the output terminal connected to the negative electrode of the capacitive load is regarded as the first output terminal.

In other embodiments, the power conversion device 100 further includes a substrate selection circuit, at least one of the second switching tube and the third switching tube is a MOS tube, and the substrate selection circuit is connected to a source, a drain, and a substrate of the MOS tube, respectively. The substrate selection circuit connects the substrate to one of the drain and the source with a higher voltage if the MOS transistor is a P-type MOS transistor, and connects the substrate to one of the drain and the source with a lower voltage if the MOS transistor is an N-type MOS transistor. As shown in fig. 5, as some examples, the substrate selection circuit is connected to a second switching tube (e.g., M2 tube) and a third switching tube (e.g., M3 tube). Without loss of generality, in the case where any one of the first switching tube, the second switching tube, the third switching tube, the fourth switching tube, and the fifth switching tube is a MOS tube, the substrate selection circuit may be connected to a source, a drain, and a substrate of the MOS tube.

Specifically, as shown in fig. 6, in an example in which a MOS transistor is used as an M2 transistor or an M3 transistor, the substrate selection circuit includes a comparator. The first input end and the second input end of the comparator are respectively connected to the drain electrode and the source electrode of the MOS tube, for example, as shown in FIG. 6, the positive input end "+" of the comparator is connected to the drain electrode of the MOS tube, and the negative input end "-" of the comparator is connected to the source electrode of the MOS tube. The comparator outputs one of the drain and source voltages, which is higher in voltage, from the output terminal by comparing the drain voltage and the source voltage when the MOS transistor is a P-type MOS transistor, and the substrate selection circuit connects the substrate to the one of the drain and the source, which is higher in voltage. When the MOS transistor is an N-type MOS transistor, the lower voltage of the drain and the source is outputted from the output terminal, and the substrate selection circuit connects the substrate to the lower voltage of the drain and the source.

In other embodiments, any switching tube (e.g., a first switching tube, a second switching tube, a third switching tube, a fourth switching tube, and a fifth switching tube) in the power conversion device may be implemented by connecting at least two MOS tubes in series. For example, in the example of fig. 7A, the M11 tube and the M12 tube are P-type MOS tubes, the drain electrode of the M11 tube is connected to the drain electrode of the M12 tube, the source electrode of the M11 tube and the source electrode of the M12 tube are two non-control ends of the switch tube, and the gate electrode of the M11 tube and the gate electrode of the M12 tube may be control ends of the switch ends. For another example, in the example of fig. 7B, the M13 tube and the M14 tube are P-type MOS tubes, the source of the M13 tube is connected to the source of the M14 tube, the drain of the M13 tube and the drain of the M14 tube are used as two non-control ends of the switching tube, and the gate of the M13 tube and the gate of the M14 tube may be used as control ends of the switching ends.

The embodiment of the invention also provides an electronic device 800, and the electronic device 800 includes the power conversion device 100 and the capacitive load 810. It should be understood that, specific implementations in the electronic device may refer to corresponding steps, modules or corresponding descriptions in the embodiments of the power conversion device, and have corresponding beneficial effects, which are not described herein. It will be clear to those skilled in the art that, for convenience and brevity of description, specific operation of the power conversion apparatus in the electronic device may be described with reference to corresponding procedures in the foregoing embodiments of the power conversion apparatus, which are not described herein again.

Thus, particular embodiments of the present subject matter have been described. Other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may be advantageous.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, as relevant to see a section of the description of method embodiments.

The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and variations of the present application will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the application are to be included in the scope of the claims of the present application.

Claims

1. A power conversion device, comprising:

A power conversion circuit, comprising a first switching tube, a second switching tube and an inductor unit, wherein one end of the inductor unit is connected to a first bias voltage, and the other end of the inductor unit is connected to a second bias voltage through the first switching tube;

a signal processing circuit connected to the power conversion circuit, the signal processing circuit being configured to perform pulse width modulation on an input signal to obtain a first PWM signal and a second PWM signal with matching timings, and output the first PWM signal and the second PWM signal to the first switching transistor and the second switching transistor, respectively, to alternately control the on and off of the first switching transistor and the second switching transistor;

a power output circuit, connected to the other end of the inductor unit through the second switch tube, the power output circuit being configured to output an output conversion signal of the input signal;

The power conversion circuit further includes a third switch tube, and the power output circuit is connected to the other end of the inductor unit through the third switch tube;

The signal processing circuit is used to: perform pulse width modulation on the input signal in the first half of the full cycle of the input signal to obtain a first PWM signal and a second PWM signal with timing matching; and perform pulse width modulation on the input signal in the second half of the full cycle of the input signal to obtain a first PWM signal and a third PWM signal with timing matching, wherein the first PWM signal and the third PWM signal are respectively used to control the on and off of the first switching tube and the third switching tube.

2. The power conversion device according to claim 1 , wherein the signal processing circuit is configured to: perform pulse width modulation on the input signal at sampling points of the first half cycle according to a first preset duty cycle to obtain first and second PWM signals with timing matching in the first half cycle; and perform pulse width modulation on the input signal at sampling points of the second half cycle according to a second preset duty cycle to obtain first and third PWM signals with timing matching in the second half cycle, wherein the first preset duty cycle and the second preset duty cycle are complementary.

3. The power conversion device according to claim 1 , wherein the third PWM signal is used to control the third switch tube to be in a normally off state during the second half cycle, and the second PWM signal is used to control the second switch tube to be in a normally off state during the second half cycle.

4. The power conversion device according to claim 3 is characterized in that the power output circuit includes a first output end and a second output end, the first output end is connected to the other end of the inductor unit through the second switching tube, and the second output end is connected to the other end of the inductor unit through the third switching tube, wherein the power output circuit outputs an output conversion signal of the input signal between the first output end and the second output end.

5. The power conversion device according to claim 4, wherein the power output circuit further comprises a fourth switching tube and a fifth switching tube, the fourth switching tube being connected between the first output terminal and a third bias voltage, and the fifth switching tube being connected between the second output terminal and the third bias voltage;

The signal processing circuit is also used to: generate a first commutation signal and a second commutation signal, the first commutation signal is used to control the fourth switch tube to be normally closed in the first half cycle and normally open in the second half cycle, wherein the second commutation signal is used to control the fifth switch tube to be normally open in the first half cycle and normally closed in the second half cycle.

6. The power conversion device according to claim 4 is characterized in that, in the in-phase conversion mode, the first output end is connected to the positive pole of the capacitive load, and the second output end is connected to the negative pole of the capacitive load; in the inverse conversion mode, the first output end is connected to the negative pole of the capacitive load, and the second output end is connected to the positive pole of the capacitive load.

7. The power conversion device according to claim 4, further comprising a substrate selection circuit, at least one of the second switching transistor and the third switching transistor is a MOS transistor, and the substrate selection circuit is respectively connected to a source, a drain, and a substrate of the MOS transistor;

Among them, the substrate selection circuit connects the substrate to the one with a higher voltage between the drain and the source when the MOS transistor is a P-type MOS transistor, and connects the substrate to the one with a lower voltage between the drain and the source when the MOS transistor is an N-type MOS transistor.

8 . The power conversion device according to claim 1 , wherein in a boost conversion mode, the first bias voltage is greater than the second bias voltage.

9. An electronic device, comprising:

Capacitive load;

The power conversion device according to any one of claims 1 to 8, wherein the power conversion device provides an output conversion signal to the capacitive load.