[go: up one dir, main page]

CN118737973A - 电子器件封装 - Google Patents

电子器件封装 Download PDF

Info

Publication number
CN118737973A
CN118737973A CN202410818471.7A CN202410818471A CN118737973A CN 118737973 A CN118737973 A CN 118737973A CN 202410818471 A CN202410818471 A CN 202410818471A CN 118737973 A CN118737973 A CN 118737973A
Authority
CN
China
Prior art keywords
electronic device
device package
interposer
redistribution layer
electronic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202410818471.7A
Other languages
English (en)
Inventor
Z·丁
B·刘
Y·佘
H·I·金
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to CN202410818471.7A priority Critical patent/CN118737973A/zh
Publication of CN118737973A publication Critical patent/CN118737973A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0652—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D
    • H01L25/071—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/18—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48155—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48157—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/85005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1436—Dynamic random-access memory [DRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1438—Flash memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/145—Read-only memory [ROM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/145—Read-only memory [ROM]
    • H01L2924/1451—EPROM
    • H01L2924/14511—EEPROM
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

公开了电子器件封装技术。根据本公开的电子器件封装可以包括电子组件、再分布层和电耦合再分布层与电子组件的中介层。中介层可以在顶侧上具有电耦合到电子组件的互连接口，并且在底侧上具有电耦合到再分布层的互连接口。顶侧上的互连接口的密度可以大于底侧上的互连接口的密度。还公开了相关系统和方法。

Description

电子器件封装
技术领域
本文描述的实施例总体上涉及电子器件封装，并且更具体地涉及电子器件封装中的互连组件。
背景技术
随着移动(例如，蜂窝电话、平板电脑等)和可穿戴市场需要更多功能，存储和性能、组件密度逐渐提高，以在这些小形状因子的应用中提供空间节约。例如，用于这些应用的系统级封装(SiP)通常需要多堆叠管芯以及异构集成电路和组件集成技术。在这些SiP中广泛实现高密度互连(HDI)基板。多堆叠管芯通常以引线键合连接电连接到基板。
附图说明
根据下面结合附图的详细描述，发明特征和优点将变得清楚，附图通过示例的方式一起例示了各种发明实施例；并且，其中：
图1例示了根据示例实施例的电子器件封装的示意性截面图；
图2A和2B例示了根据示例实施例的电子器件封装的中介层的示意性截面图；
图3A-3G例示了根据示例实施例的用于制造电子器件封装的方法的各方面；
图4A-4F例示了根据另一示例实施例的用于制造电子器件封装的方法的各方面；以及
图5是示例性计算系统的示意图。
现在将参考所例示的示例性实施例，并且本文将使用特定语言来描述它们。然而，将要理解的是，在此没有限制范围或将范围局限于特定的发明实施例的意图。
具体实施方式
在公开和描述发明实施例之前，应当理解，不旨在限制到本文公开的特定结构、工艺步骤或材料，而是还要包括相关领域的普通技术人员将认识到的其等同物。还应该理解，本文采用的术语仅用于描述特定示例的目的并且不旨在进行限制。不同附图中的相同附图标记表示相同元素。在流程图和过程中提供的数字是为了例示步骤和操作中的清楚性提供的，并不一定指示特定的顺序或序列。除非另有定义，否则本文使用的所有技术和科学术语具有与本公开所属领域的普通技术人员通常理解的含义相同的含义。
如在该书面描述中使用的，单数形式“一”、“一个”和“该”提供对复数个指示对象的明确支持，除非上下文另有明确规定。因此，例如，对“层”的提及包括多个这样的层。
在本申请中，“包括”、“包括有”、“包含”和“具有”以及诸如此类可以具有美国专利法中赋予它们的含义并且可以意味着“包含”、“包含有”以及诸如此类，并且通常被解释为开放式术语。术语“由……组成”或“由……构成”是封闭式术语，并且仅包括结合此类术语具体列出的组件、结构、步骤或者诸如此类，以及根据美国专利法的那些。“基本上由......组成”或“基本由......构成”具有美国专利法通常赋予它们的含义。特别是，此类术语通常是封闭式术语，例外是允许包含其他项目、材料、组件、步骤或元素，不实质性影响与其结合使用的(一个或多个)项目的基本和新颖特征或功能。例如，如果在“基本上由......组成”语言下存在，则组合物中存在但不影响组合物性质或特性的微量元素将是可允许的，即使在此类术语之后的项目列表中没有明确记载。当在书面描述中使用开放式术语，如“包含”或“包括”时，应当理解如同明确说明的那样，也将提供对于语言“基本上由……组成”以及语言“由……组成”的直接支持，并且反之亦然。
说明书和权利要求书中的术语“第一”、“第二”、“第三”、“第四”以及诸如此类，如果有的话，用于在相似的元素之间进行区分，并且不一定用于描述特定顺序或时间次序。应当理解，如此使用的术语在适当的情况下是可互换的，使得本文描述的实施例例如能够以不同于本文所示的或以其他方式描述的顺序的顺序操作。类似地，如果在此将方法描述为包括一系列步骤，则本文给出的此类步骤的顺序不一定就是可以执行此类步骤的仅有顺序，并且可能可以省略阐述步骤中某些和/或可能可以将本文未描述的某些其他步骤添加到所述方法。
说明书和权利要求中的术语“左”、“右”、“前”、“后”、“顶”、“底”、“上方”、“下方”以及诸如此类，如果有的话，被用于描述性目的并且不一定用于描述永久的相对位置。应当理解，如此使用的术语在适当的情况下是可互换的，使得本文描述的实施例例如能够以不同于本文所示的或以其他方式描述的方向的方向操作。
如本文所使用的术语“耦合的”被定义为以电或非电方式直接或间接地连接的。“直接耦合的”项目或对象是彼此物理接触并附接。本文描述为彼此“相邻”的对象可能彼此物理接触、彼此非常接近、或者在彼此相同的总的区域或区中，如适于使用该短语的上下文的那样。
在本文中短语“在一个实施例中”或“在一个方面中”的出现并不一定都指代相同的实施例或方面。
如本文所使用的，术语“基本上”指动作、特性、性质、状态、结构、项目或结果的完全或接近完全的范围或程度。例如，“基本上”封闭的对象将意味着该对象被完全封闭或几乎完全封闭。在某些情况下，与绝对完整性的偏差的确切的可允许程度可能取决于具体上下文。然而，一般而言，完成的接近程度将从而具有相同的总体结果，就好像获得绝对和完全完成一样。当在负面含义中使用时，“基本上”的使用同样适用于指代动作、特性、性质、状态、结构、项目或结果的完全或几乎完全缺乏。例如，“基本上不含”颗粒的组合物要么完全缺乏颗粒，要么几乎完全缺乏颗粒，其效果与完全缺乏颗粒的情况相同。换句话说，“基本上不含”成分或元素的组合物实际上仍旧包含此类项目，只要不存在其可测量的影响即可。
如本文所使用的，术语“约”用于通过提供给定值可以在端点“之上一点”或断点“之下一点”来向数值范围端点提供灵活性。
如本文所使用的，为方便起见，可以在共同列表中呈现多个项目、结构元素、组成元素和/或材料。然而，应将这些列表解释为如同列表的每个成员都被单独地标识为独立和独特的成员。因此，不应仅基于它们出现在共同组中而没有相反的指示就将此类列表的单独员解释为事实上相同列表的任何其他成员的等同物。
浓度、量、大小和其他数值数据可以以范围格式在本文中表达或呈现。应当理解，这样的范围格式仅仅用于方便和简洁并且因此应该被灵活地解释为不仅包括明确记载为范围限制的数值，而且还包括所有单独的数值或包含在该范围内的子范围，好像每个数值和子范围都被明确地记载那样。举例来说，“大约1至大约5”的数值范围应该被解释为不仅包括大约1至大约5的明确记载的值，而且还包括在指定的范围内的单独值和子范围。因此，包括在该数值范围内的是单独值，例如2、3和4以及子范围，例如从1-3、从2-4和从3-5等，以及单独的1、2、3、4和5。
此相同的原理应用于将仅一个数值记载作为最小值或最大值的范围。此外，无论被描述的特性或范围的广度如何，都应该应用这种解释。
贯穿本说明书对“示例”的引用意味着结合该示例描述的特定特征、结构或特性被包括在至少一个实施例中。因此，贯穿本说明书在各个地方短语“在示例中”的出现不一定都指的是相同实施例。
此外，所描述的特征、结构或特性可以在一个或多个实施例中以任何合适的方式组合。在本描述中，提供了许多具体细节，例如布局、距离、网络示例等的示例。然而，相关领域的技术人员将认识到，在没有一个或多个具体细节的情况下或具有其他方法、组件、布局、测量等的情况下，很多变型是可能的。在其他情况下，未详细示出或描述公知的结构、材料或操作，但是这些公知的结构、材料或操作被认为在本公开的范围内。
示例实施例
下面提供技术实施例的初步概述，并且然后进一步详细描述具体技术实施例。该初步概述旨在帮助读者更快地理解本技术，但不旨在标识本技术的关键或基本特征，也不旨在限制所要求保护的主题的范围。
虽然在小形状因子的应用中广泛实现HDI基板，但与其他替换方案相比，这些基板增加了成本和Z高度。虽然存在具有多层的再分布层(RDL)技术，其提供比HDI基板精细得多的线间距、宽度和厚度，但是多层RDL较为昂贵，并且由于该结构中缺乏机械强度，因此多层RDL可能无法承受与基于引线键合的集成电路(如ASIC、DRAM和NAND)耦合的引线键合互连。
因此，公开了一种电子器件封装，其可以适应与基板技术耦合的引线键合互连，该基板技术能够以比HDI基板和多层RDL更低的成本提供降低的Z高度。在一个示例中，根据本公开的电子器件封装可以包括电子组件、再分布层和电耦合所述再分布层与所述电子组件的中介层。所述中介层可以在顶侧上具有电耦合到所述电子组件的互连接口，并且在底侧上具有电耦合到所述再分布层的互连接口。顶侧上的互连接口的密度可以大于底侧上的互连接口的密度。还公开了相关系统和方法。
参考图1，示意性地以截面图例示了示例性电子器件封装100。电子器件封装100可以包括再分布层110。电子器件封装100还可以包括电耦合到再分布层110的一个或多个电子组件。在120a-h和121-124处标识了电子组件。另外，电子器件封装100可以包括一个或多个中介层130a、130b，其电耦合再分布层110与所述电子组件中的至少一些。例如，中介层130a可以将电子组件120a-d电耦合到再分布层110，并且中介层130b可以将电子组件120e-h电耦合到再分布层110。
电子组件可以是可以包括在电子器件封装中的任何电子器件或组件，所述电子器件封装如半导体器件(例如，管芯、芯片、处理器、计算机存储器等)。在一个实施例中，电子组件中的一些可以表示分立芯片，其可以包括集成电路。电子组件可以是以下各项、包括以下各项或是以下各项的一部分：处理器、存储器(例如，ROM、RAM、EEPROM、闪存等)、专用集成电路(ASIC)或无源电组件。在一些实施例中，电子组件中的一个或多个可以是片上系统(SOC)或封装叠加(POP)。在一些实施例中，电子器件封装100可以是系统级封装(SIP)。应该认识到，可以包括任何合适数量的电子组件。
再分布层110可以包括任何合适的材料，如典型的半导体材料和/或介电材料。在一个实施例中，再分布层110可以包括基于环氧树脂的层压结构。在其他实施例中，再分布层110可以包括其他合适的材料或配置。例如，再分布层110可以由以下材料形成：任何合适的半导体材料(例如，硅、镓、铟、锗或其变体或组合以及其他基板)、一种或多种绝缘材料(如玻璃增强环氧树脂，如FR-4、聚四氟乙烯(特氟龙)、棉纸增强环氧树脂(CEM-3)、酚醛玻璃(G3)、纸酚醛树脂(FR-1或FR-2)、聚酯玻璃(CEM-5)、ABF(Ajinomoto Build-up Film(堆膜)))、任何其他介电材料(如玻璃)、或诸如可以用于再分布层的其任何组合。
在一个方面中，再分布层110可以被配置成促进将电子器件封装100与外部电子组件(如基板(例如，诸如母板之类的电路板))电耦合，以进一步路由电信号和/或提供电力。电子器件封装100可以包括互连，如焊球111，其耦合到再分布层110，以用于将电子器件封装100与外部电子组件电耦合。
电子组件可以根据包括引线键合、倒装芯片配置等的各种合适配置来电耦合到再分布层110。可以使用互连结构(例如，所例示的引线键合125a、125b和/或焊球126)将电子组件中的一个或多个电耦合到再分布层110，所述互连结构被配置成在电子组件与再分布层110之间路由电信号。在一些实施例中，互连结构可以被配置成路由电信号，所述电信号诸如例如与电子组件的操作相关联的I/O信号和/或电力或接地信号。
中介层130a、130b可以促进将电子组件中的至少一些电耦合到再分布层110。例如，中介层130a可以促进将电子组件120a-d电耦合到再分布层110。互连结构(例如，引线键合125a)可以耦合到中介层130a的互连接口131a，该互连接口131a可以经由互连接口132a耦合到再分布层110。另外，中介层130b可以促进将电子组件120e-h电耦合到再分布层110。互连结构(例如，引线键合125b)可以耦合到中介层130b的互连接口131b，该互连接口131b可以经由互连接口132b耦合到再分布层110。
再分布层110可以包括电路由特征，其被配置成经由焊球111在封装100的任何电子组件与外部电子组件之间路由电信号和/或电力。电路由特征可以在再分布层110的内部和/或外部。例如，在一些实施例中，再分布层110可以包括电路由特征，如焊盘、通孔和/或迹线(未示出)，如本领域中公知的，它们被配置成接收互连结构(例如，引线键合和焊球)和互连接口131a-b、132a-b，并将电信号路由到电子组件或从电子组件路由电信号。再分布层110的焊盘、通孔和迹线可以由相同或相似的导电材料构成，或由不同的导电材料构成。在一些实施例中，与在其他实施例中可能包括的多层相反，再分布层110可以仅具有单层。
在一个方面中，电子组件120a-h可以处于堆叠关系，例如以节约空间并且使得能够实现更小的形状因子。应该认识到，可以在堆叠中包括任何合适数量的电子组件。堆叠电子组件中的至少一些可以是基于引线键合的集成电路(例如，ASIC、DRAM和NAND)。这种基于引线键合的集成电路可以通过引线键合连接彼此电耦合。例如，电子组件120a-d可以通过引线键合125a彼此电耦合，并且电子组件120e-h可以通过引线键合125b彼此电耦合。如上所述，引线键合125a、125b可以耦合到中介层130a、130b。因此，每个中介层可以促进将多个电子组件电耦合到再分布层110。
模塑料材料140(例如，环氧树脂)可以包封电子组件和中介层130a、130b中的一个或多个。例如，图1示出了包封电子组件和中介层的模塑料140。
图2A和2B例示了代表性中介层130的示意性截面视图。中介层130可以在顶侧上具有互连接口131，以(例如经由引线键合125)与电子组件电耦合。因此，中介层130的顶侧上的互连接口131可以包括引线键合焊盘或平台(landing)或促进与引线键合进行电耦合的任何其他合适结构。另外，中介层130可以在底侧上具有互连接口132，以与再分布层110电耦合。中介层130的底侧上的互连接口132可以包括焊盘、触点、引脚或促进通过任何合适的工艺或技术(如表面安装技术(例如，利用焊接连接、焊球等))与再分布层110电耦合的任何其他合适的结构。
中介层130可以包括电路由特征，其被配置成在互连接口131与互连接口132之间路由电信号和/或电力。电路由特征可以在中介层130的内部和/或外部。例如，在一些实施例中，中介层130可以包括电路由特征，如通孔133和/或迹线134，如本领域中公知的，它们被配置成将电信号路由到互连接口131、132或从互连接口131、132路由电信号。中介层130的互连接口131、132、通孔133和迹线134可以由相同或相似的导电材料构成，或由不同的导电材料构成。
由于引线键合连接可以彼此非常接近地终止，因此互连接口131(例如，引线键合焊盘)的尺寸(例如，直径)可以是约75-100μm，并且互连接口131的间隔(通常由焊盘间距来定义)可以是约150-200μm。另一方面，互连接口132的尺寸(例如，直径)和间距可以大于互连接口131的尺寸(例如，直径)和间距。互连接口132的相对大的尺寸和间距可以有益于可以被配置成与互连接口132耦合的再分布层110中的路由。在一个方面中，互连接口131、132的密度可以由互连接口的间距来定义。因此，中介层130的顶侧上的互连接口131的密度可以大于中介层130的底侧上的互连接口132的密度。如图2B中所示，电路由特征(例如，通孔133和迹线134)可以从互连接口131的相对细的间距“扇出”到互连接口132的较大间距。可以以任何合适的方式实现电路由特征的这种扇出。提供图2B中所示的配置作为示例。
中介层130可以包括任何合适的材料，如典型的半导体材料和/或介电材料。在一个实施例中，中介层130可以包括基于环氧树脂的层压结构。在其他实施例中，中介层130可以包括其他合适的材料和/或配置。例如，中介层130可以由以下材料形成：任何合适的半导体材料(例如，硅、镓、铟、锗或其变体或组合以及其他基板)、一种或多种绝缘材料(如玻璃增强环氧树脂，如FR-4、聚四氟乙烯(特氟龙)、棉纸增强环氧树脂(CEM-3)、酚醛玻璃(G3)、纸酚醛树脂(FR-1或FR-2)、聚酯玻璃(CEM-5)、ABF(Ajinomoto Build-up Film))、任何其他介电材料(如玻璃)、或诸如可以用于中介层130的其任何组合。
图3A-3G示意性地例示了用于制造电子器件封装(如电子器件封装100)的示例性方法或工艺的各方面。图3A例示了设置在临时载体160(如晶圆)上的粘合剂层150的侧截面视图。如图3B中所示，中介层130a、130b可以设置在临时载体160上，使得中介层的底侧与粘合剂层接触。另外，各种电子组件121-124(例如，ASIC和/或无源组件)也可以设置在临时载体160上，与粘合剂层150接触。因此，中介层130a、130b和电子组件121-124可以由临时载体160支撑。
如图3C中所示，电子组件120a-h(例如，各种集成电路)可以设置在临时载体160上，与粘合剂层150接触。电子组件120a-h可以是堆叠布置。电子组件120a-d可以通过引线键合连接彼此电耦合，并且电子组件120e-h可以通过引线键合连接彼此电耦合。另外，电子组件120a-d可以通过引线键合连接电耦合到中介层130a，并且电子组件120e-h可以通过引线键合连接电耦合到中介层130b。
然后可以用模塑料140包封电子组件120a-h和121-124以及中介层130a、130b，如图3D中所示。此后，如图3E中所示，可以从模塑料140和中介层130a、130b的底部移除临时载体和粘合剂层。这可以暴露中介层130a、130b的底部上的互连接口132a、132b以及电子组件121-124的互连结构。如图3F中所示，再分布层110可以设置在模塑料140、中介层130a、130b和电子组件121-124的底部上。中介层130a、130b和电子组件121-124可以电耦合到再分布层110。在一些实施例中，可以在该位置中形成再分布层110。焊球111可以设置在再分布层110的底部上或附接到再分布层110的底部，如图3G中所示，以达成完成的电子器件封装100。图3A-3G中例示的方法示出了制造电子器件封装100的方法，在该方法中，“最后”形成或组装再分布层110，或者换言之，在组装电子组件和中介层之后形成或组装再分布层110。
在一个方面中，图3B-3D例示了电子器件封装前体的实施例，每个电子器件封装前体包括由临时载体160支撑的中介层130a、130b。可以对这些电子器件封装前体中的每一个进行如上所述的进一步处理，以产生根据本公开的电子器件封装。
图4A-4F示意性地例示了用于制造电子器件封装(如电子器件封装100)的示例性方法或工艺的各方面。图4A例示了设置在临时载体160上的再分布层110的侧截面视图。在一些实施例中，可以在该位置中形成再分布层110。如图4B中所示，中介层130a、130b可以设置在再分布层110上。此外，各种电子组件121-124(例如，ASIC和/或无源组件)也可以设置在再分布层110上。因此，中介层130a、130b和电子组件121-124可以由临时载体160支撑。中介层130a、130b和电子组件121-124可以电耦合到再分布层110。可以利用表面安装技术来安置电子组件121-124和中介层130a、130b并将它们电耦合到再分布层110。
如图4C中所示，电子组件120a-h(例如，各种集成电路)可以设置在再分布层110上。电子组件120a-h可以是堆叠布置。可以使用管芯附着膜(未示出)来在组装期间保持电子组件120a-h处于堆叠。电子组件120a-d可以通过引线键合连接彼此电耦合，并且电子组件120e-h可以通过引线键合连接彼此电耦合。另外，电子组件120a-d可以通过引线键合连接电耦合到中介层130a，并且电子组件120e-h可以通过引线键合连接电耦合到中介层130b。因为再分布层110可能相对较薄且缺乏机械强度，因此中介层130a、130b的存在可以由于具有承受许多(即，数千)引线键合平台的机械强度而不是使再分布层110受到这些压力来在制造期间提供机械益处。因此，如本文公开的中介层可以为封装提供电气和机械益处。
然后可以用模塑料140包封电子组件120a-h和121-124以及中介层130a、130b，如图4D中所示。如图4E中所示，可以从再分布层110的底部移除临时载体。然后，焊球111可以设置在再分布层110的底部上或附接到再分布层110的底部，如图4F中所示，以达成完成的电子器件封装100。图4A-4F中例示的方法示出了制造电子器件封装100的方法，在该方法中，“首先”形成或组装再分布层110，或者换言之，在组装电子组件和中介层之前形成或组装再分布层110。
在一个方面中，图4B-4D例示了电子器件封装前体的实施例，每个电子器件封装前体包括由临时载体160支撑的中介层130a、130b。在这种情况下，中介层130a、130b也耦合到再分布层110。可以对这些电子器件封装前体中的每一个进行如上所述的进一步处理，以产生根据本公开的电子器件封装。
图5示意性地例示了示例计算系统201。计算系统201可以包括如本文公开的电子器件封装200，其耦合到母板202。在一个方面中，计算系统201还可以包括处理器203、存储器器件204、无线电装置205、冷却系统(例如，散热器和/或散热片)206、端口207、插槽或可以可操作地耦合到母板270的任何其他合适的设备或组件。计算系统201可以包括任何类型的计算系统，如台式计算机、膝上型计算机、平板计算机、智能电话、服务器、可穿戴电子设备等。其他实施例不需要包括图5中指定的所有特征，并且可以包括图5中未指定的替换特征。
示例
以下示例涉及另外的实施例。
在一个示例中提供了一种电子器件封装，其包括电子组件，再分布层，以及电耦合所述再分布层与所述电子组件的中介层，所述中介层在顶侧上具有电耦合到所述电子组件的互连接口并且在底侧上具有电耦合到所述再分布层的互连接口，其中顶侧上的互连接口的密度大于底侧上的互连接口的密度。
在电子器件封装的一个示例中，所述中介层顶侧上的互连接口包括引线键合平台。
在电子器件封装的一个示例中，通过引线键合连接来电耦合所述中介层与所述电子组件。
在电子器件封装的一个示例中，所述中介层底侧上的互连接口包括焊盘。
在一个示例中，电子器件封装包括包封所述电子组件和所述中介层的模塑料。
在电子器件封装的一个示例中，所述模塑料包括环氧树脂。
在电子器件封装的一个示例中，所述再分布层包括单个层。
在电子器件封装的一个示例中，所述电子组件包括以堆叠布置的多个电子组件。
在电子器件封装的一个示例中，所述多个电子组件中的至少一些通过引线键合连接彼此电耦合。
在一个示例中，电子器件封装包括第二电子组件，以及电耦合所述再分布层与所述第二电子组件的第二中介层。
在电子器件封装的一个示例中，所述第二电子组件包括以堆叠布置的多个第二电子组件。
在电子器件封装的一个示例中，所述多个第二电子组件中的至少一些通过引线键合连接彼此电耦合。
在一个示例中，电子器件封装包括互连结构，其耦合到所述再分布层的底侧，以促进所述电子器件封装与外部电子组件的电耦合。
在电子器件封装的一个示例中，所述互连结构包括焊球。
在电子器件封装的一个示例中，所述电子组件包括集成电路。
在电子器件封装的一个示例中，所述集成电路包括专用集成电路、计算机存储器、或其组合。
在电子器件封装的一个示例中，所述互连接口的密度由所述互连接口的间距来定义。
在一个示例中提供了电子器件封装前体，其包括临时载体，以及由所述临时载体支撑的中介层，所述中介层在顶侧上具有互连接口以电耦合到电子组件并且在底侧上具有互连接口以电耦合到再分布层，其中顶侧上的互连接口的密度大于底侧上的互连接口的密度。
在一个示例中，电子器件封装前体包括粘合剂层，所述粘合剂层设置在所述临时载体上并与所述中介层的底侧接触。
在一个示例中，电子器件封装前体包括电子组件，所述电子组件由所述临时载体支撑并与所述粘合剂层接触。
在电子器件封装前体的一个示例中，所述电子组件电耦合到所述中介层。
在电子器件封装前体的一个示例中，所述中介层顶侧上的互连接口包括引线键合平台。
在电子器件封装前体的一个示例中，通过引线键合连接来电耦合所述中介层与所述电子组件。
在一个示例中，电子器件封装前体包括包封所述电子组件和所述中介层的模塑料。
在电子器件封装前体的一个示例中，所述模塑料包括环氧树脂。
在电子器件封装前体的一个示例中，所述电子组件包括以堆叠布置的多个电子组件。
在电子器件封装前体的一个示例中，所述多个电子组件中的至少一些通过引线键合连接彼此电耦合。
在一个示例中，电子器件封装前体包括由所述临时载体支撑的第二电子组件，以及由所述临时载体支撑并与所述粘合剂层接触的第二中介层，所述第二中介层电耦合到所述第二电子组件。
在电子器件封装前体的一个示例中，所述第二电子组件包括以堆叠布置的多个第二电子组件。
在电子器件封装前体的一个示例中，所述多个第二电子组件中的至少一些通过引线键合连接彼此电耦合。
在电子器件封装前体的一个示例中，所述电子组件包括集成电路。
在电子器件封装前体的一个示例中，所述集成电路包括专用集成电路、计算机存储器、或其组合。
在一个示例中，电子器件封装前体包括再分布层，所述再分布层由所述临时载体支撑并电耦合到所述中介层。
在一个示例中，电子器件封装前体包括由所述临时载体支撑的电子组件。
在电子器件封装前体的一个示例中，所述电子组件电耦合到所述中介层。
在电子器件封装前体的一个示例中，所述中介层顶侧上的互连接口包括引线键合平台。
在电子器件封装前体的一个示例中，通过引线键合连接来电耦合所述中介层与所述电子组件。
在一个示例中，电子器件封装前体包括包封所述电子组件和所述中介层的模塑料。
在电子器件封装前体的一个示例中，所述模塑料包括环氧树脂。
在电子器件封装前体的一个示例中，所述再分布层包括单个层。
在电子器件封装前体的一个示例中，所述电子组件包括以堆叠布置的多个电子组件。
在电子器件封装前体的一个示例中，所述多个电子组件中的至少一些通过引线键合连接彼此电耦合。
在一个示例中，电子器件封装前体包括由所述临时载体支撑的第二电子组件，以及由所述临时载体支撑的第二中介层，所述第二中介层电耦合到所述再分布层和所述第二电子组件。
在电子器件封装前体的一个示例中，所述第二电子组件包括以堆叠布置的多个第二电子组件。
在电子器件封装前体的一个示例中，所述多个第二电子组件中的至少一些通过引线键合连接彼此电耦合。
在电子器件封装前体的一个示例中，所述电子组件包括集成电路。
在电子器件封装前体的一个示例中，所述集成电路包括专用集成电路、计算机存储器、或其组合。
在电子器件封装前体的一个示例中，所述中介层底侧上的互连接口包括焊盘。
在电子器件封装前体的一个示例中，所述互连接口的密度由所述互连接口的间距来定义。
在一个示例中，提供了一种计算系统，其包括母板，以及可操作地耦合到所述母板的电子器件封装。所述电子器件封装包括电子组件，再分布层，以及电耦合所述再分布层与所述电子组件的中介层，所述中介层在顶侧上具有电耦合到所述电子组件的互连接口并且在底侧上具有电耦合到所述再分布层的互连接口，其中顶侧上的互连接口的密度大于底侧上的互连接口的密度。
在计算系统的一个示例中，所述计算系统包括台式计算机、膝上型电脑、平板电脑、智能电话、服务器、可穿戴电子设备、或其组合。
在计算系统的一个示例中，所述计算系统还包括可操作地耦合到所述母板的处理器、存储器器件、冷却系统、无线电装置、插槽、端口、或其组合。
在一个示例中提供了一种用于制造电子器件封装的方法，包括获得中介层，所述中介层在顶侧上具有互连接口以电耦合到电子组件并且在底侧上具有互连接口以电耦合到再分布层，其中顶侧上的互连接口的密度大于底侧上的互连接口的密度，以及用临时载体支撑所述中介层。
在一个示例中，用于制造电子器件封装的方法包括在所述临时载体上设置粘合剂层，以及在所述粘合剂层上设置所述中介层，使得所述中介层的底侧与所述粘合剂层接触。
在一个示例中，用于制造电子器件封装的方法包括将电子组件设置在所述临时载体上，与所述粘合剂层接触。
在一个示例中，用于制造电子器件封装的方法包括电耦合所述电子组件与所述中介层。
在用于制造电子器件封装的方法的一个示例中，所述中介层顶侧上的互连接口包括引线键合平台。
在用于制造电子器件封装的方法的一个示例中，通过引线键合连接来电耦合所述中介层与所述电子组件。
在一个示例中，用于制造电子器件封装的方法包括用模塑料包封所述电子组件和所述中介层。
在用于制造电子器件封装的方法的一个示例中，所述模塑料包括环氧树脂。
在一个示例中，用于制造电子器件封装的方法包括从所述模塑料和所述中介层的底部移除所述临时载体和所述粘合剂层。
在一个示例中，用于制造电子器件封装的方法包括在所述模塑料和所述中介层的底部上设置再分布层，以及电耦合所述再分布层和所述中介层。
在一个示例中，用于制造电子器件封装的方法包括在所述再分布层的底部设置焊球。
在用于制造电子器件封装的方法的一个示例中，所述电子组件包括多个电子组件，并且还包括以堆叠布置来设置所述多个电子组件。
在一个示例中，用于制造电子器件封装的方法包括通过引线键合连接将所述多个电子组件中的至少一些彼此电耦合。
在一个示例中，用于制造电子器件封装的方法包括用所述临时载体支撑第二电子组件，将第二中介层设置在所述临时载体上，与所述粘合剂层接触，以及电耦合所述第二中介层与所述第二电子组件。
在用于制造电子器件封装的方法的一个示例中，所述第二电子组件包括多个第二电子组件，并且还包括以堆叠布置来设置所述多个第二电子组件。
在一个示例中，用于制造电子器件封装的方法包括通过引线键合连接将所述多个第二电子组件中的至少一些彼此电耦合。
在用于制造电子器件封装的方法的一个示例中，所述电子组件包括集成电路。
在用于制造电子器件封装的方法的一个示例中，所述集成电路包括专用集成电路、计算机存储器、或其组合。
在一个示例中，用于制造电子器件封装的方法包括在所述临时载体上设置再分布层，以及电耦合所述再分布层和所述中介层。
在一个示例中，用于制造电子器件封装的方法包括在所述临时载体上设置电子组件。
在一个示例中，用于制造电子器件封装的方法包括电耦合所述电子组件与所述中介层。
在用于制造电子器件封装的方法的一个示例中，所述中介层顶侧上的互连接口包括引线键合平台。
在用于制造电子器件封装的方法的一个示例中，通过引线键合连接来电耦合所述中介层与所述电子组件。
在一个示例中，用于制造电子器件封装的方法包括用模塑料包封所述电子组件和所述中介层。
在用于制造电子器件封装的方法的一个示例中，所述模塑料包括环氧树脂。
在一个示例中，用于制造电子器件封装的方法包括从所述再分布层的底部移除所述临时载体。
在一个示例中，用于制造电子器件封装的方法包括在所述再分布层的底部设置焊球。
在用于制造电子器件封装的方法的一个示例中，所述再分布层包括单个层。
在用于制造电子器件封装的方法的一个示例中，所述电子组件包括多个电子组件，并且还包括以堆叠布置来设置所述多个电子组件。
在一个示例中，用于制造电子器件封装的方法包括通过引线键合连接将所述多个电子组件中的至少一些彼此电耦合。
在一个示例中，用于制造电子器件封装的方法包括用所述临时载体支撑第二电子组件，在所述再分布层上设置第二中介层，以及将所述第二中介层电耦合到所述再分布层和所述第二电子组件。
在用于制造电子器件封装的方法的一个示例中，所述第二电子组件包括多个第二电子组件，并且还包括以堆叠布置来设置所述多个第二电子组件。
在一个示例中，用于制造电子器件封装的方法包括通过引线键合连接将所述多个第二电子组件中的至少一些彼此电耦合。
在用于制造电子器件封装的方法的一个示例中，所述电子组件包括集成电路。
在用于制造电子器件封装的方法的一个示例中，所述集成电路包括专用集成电路、计算机存储器、或其组合。
在用于制造电子器件封装的方法的一个示例中，所述中介层底侧上的互连接口包括焊盘。
在用于制造电子器件封装的方法的一个示例中，所述互连接口的密度由所述互连接口的间距来定义。
电子器件封装的电子组件或器件(例如管芯)中使用的电路可以包括硬件、固件、程序代码、可执行代码、计算机指令和/或软件。电子组件和器件可以包括非暂时性计算机可读存储介质，其可以是不包括信号的计算机可读存储介质。在可编程计算机上的程序代码执行的情况下，本文所记载的计算设备可包括处理器、处理器可读的存储介质(包括易失性和非易失性存储器和/或存储元件)、至少一个输入设备和至少一个输出设备。易失性和非易失性存储器和/或存储元件可以是RAM、EPROM、闪存驱动器、光盘驱动器、磁性硬盘驱动器、固态驱动器或用于存储电子数据的其他介质。节点和无线设备还可以包括收发器模块、计数器模块、处理模块、和/或时钟模块或定时器模块。可以实现或利用本文描述的任何技术的一个或多个程序可以使用应用编程接口(API)、可重复使用的控件以及诸如此类。此类程序可以用高级程序或面向对象编程语言来实现，以与计算机系统通信。然而，如果需要，(一个或多个)程序也可以用汇编语言或机器语言实现。在任何情况下，语言可以是编译的或解释的语言，并与硬件实现相结合。
虽然前述示例例示了在一种或多种特定应用中的具体实施例，但本领域普通技术人员将清楚，可在形式、使用和实现的细节方面进行多个修改而不偏离本文阐述的原则和概念。

Claims (15)

1.一种电子器件封装，包括：
电子组件；
再分布层；
在所述再分布层上并且与所述电子组件横向间隔开的中介层，所述中介层电耦合所述再分布层与所述电子组件，所述中介层在顶侧上具有电耦合到所述电子组件的互连接口并且在底侧上具有电耦合到所述再分布层的互连接口，并且所述中介层具有位于所述顶侧和所述底侧之间的第一最外侧壁和第二最外侧壁，所述第二最外侧壁与所述第一最外侧壁横向相对，其中，所述顶侧上的所述互连接口的密度大于所述底侧上的所述互连接口的密度并且其中，所述再分布层横向延伸超过所述中介层的所述第一最外侧壁和所述第二最外侧壁；以及
包封所述电子组件和所述中介层的模塑料，所述模塑料在所述再分布层上。
2.根据权利要求1所述的电子器件封装，其中，所述中介层的所述顶侧上的所述互连接口包括引线键合平台。
3.根据权利要求2所述的电子器件封装，其中，通过引线键合连接来电耦合所述中介层与所述电子组件。
4.根据权利要求1所述的电子器件封装，其中，所述中介层的所述底侧上的所述互连接口包括焊盘。
5.根据权利要求1所述的电子器件封装，其中，所述模塑料包括环氧树脂。
6.根据权利要求1所述的电子器件封装，其中，所述再分布层包括单个层。
7.根据权利要求1所述的电子器件封装，其中，所述电子组件包括以堆叠布置的多个电子组件。
8.根据权利要求7所述的电子器件封装，其中，所述多个电子组件中的至少一些通过引线键合连接彼此电耦合。
9.根据权利要求1所述的电子器件封装，还包括第二电子组件，以及电耦合所述再分布层与所述第二电子组件的第二中介层。
10.根据权利要求9所述的电子器件封装，其中，所述第二电子组件包括以堆叠布置的多个第二电子组件。
11.根据权利要求10所述的电子器件封装，其中，所述多个第二电子组件中的至少一些通过引线键合连接彼此电耦合。
12.根据权利要求1所述的电子器件封装，还包括互连结构，其耦合到所述再分布层的底侧，以促进所述电子器件封装与外部电子组件的电耦合。
13.根据权利要求12所述的电子器件封装，其中，所述互连结构包括焊球。
14.根据权利要求1所述的电子器件封装，其中，所述电子组件包括集成电路。
15.根据权利要求14所述的电子器件封装，其中，所述集成电路包括专用集成电路、计算机存储器、或其组合。
CN202410818471.7A 2016-12-31 2016-12-31 电子器件封装 Pending CN118737973A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202410818471.7A CN118737973A (zh) 2016-12-31 2016-12-31 电子器件封装

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CN202410818471.7A CN118737973A (zh) 2016-12-31 2016-12-31 电子器件封装
CN201680091259.9A CN110050332A (zh) 2016-12-31 2016-12-31 电子器件封装
PCT/US2016/069644 WO2018125254A1 (en) 2016-12-31 2016-12-31 Electronic device package

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN201680091259.9A Division CN110050332A (zh) 2016-12-31 2016-12-31 电子器件封装

Publications (1)

Publication Number Publication Date
CN118737973A true CN118737973A (zh) 2024-10-01

Family

ID=57851363

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201680091259.9A Pending CN110050332A (zh) 2016-12-31 2016-12-31 电子器件封装
CN202410818471.7A Pending CN118737973A (zh) 2016-12-31 2016-12-31 电子器件封装

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN201680091259.9A Pending CN110050332A (zh) 2016-12-31 2016-12-31 电子器件封装

Country Status (5)

Country Link
US (1) US11830848B2 (zh)
KR (1) KR102647213B1 (zh)
CN (2) CN110050332A (zh)
DE (1) DE112016007561T5 (zh)
WO (1) WO2018125254A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102556518B1 (ko) * 2018-10-18 2023-07-18 에스케이하이닉스 주식회사 상부 칩 스택을 지지하는 서포팅 블록을 포함하는 반도체 패키지
KR102767617B1 (ko) * 2019-08-12 2025-02-17 에스케이하이닉스 주식회사 적층 반도체 칩을 포함하는 반도체 패키지
EP4211723A1 (en) * 2020-09-10 2023-07-19 Smoltek AB Electronic component package with integrated component and redistribution layer stack
US12494447B2 (en) 2021-07-27 2025-12-09 Stmicroelectronics Pte Ltd Low cost wafer level packages and silicon

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001102479A (ja) * 1999-09-27 2001-04-13 Toshiba Corp 半導体集積回路装置およびその製造方法
US6332782B1 (en) 2000-06-19 2001-12-25 International Business Machines Corporation Spatial transformation interposer for electronic packaging
US6459039B1 (en) * 2000-06-19 2002-10-01 International Business Machines Corporation Method and apparatus to manufacture an electronic package with direct wiring pattern
SG146460A1 (en) 2007-03-12 2008-10-30 Micron Technology Inc Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor components
US9875911B2 (en) * 2009-09-23 2018-01-23 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interposer with opening to contain semiconductor die
US20110193235A1 (en) * 2010-02-05 2011-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC Architecture with Die Inside Interposer
KR101688005B1 (ko) * 2010-05-10 2016-12-20 삼성전자주식회사 이중 랜드를 갖는 반도체패키지 및 관련된 장치
KR101692441B1 (ko) * 2010-08-25 2017-01-03 삼성전자주식회사 반도체 패키지
IN2014CN03370A (zh) 2011-12-16 2015-07-03 Intel Corp
US20130187284A1 (en) * 2012-01-24 2013-07-25 Broadcom Corporation Low Cost and High Performance Flip Chip Package
US8658473B2 (en) 2012-03-27 2014-02-25 General Electric Company Ultrathin buried die module and method of manufacturing thereof
KR102043369B1 (ko) * 2012-11-21 2019-11-11 삼성전자주식회사 반도체 메모리 칩 및 이를 포함하는 적층형 반도체 패키지
KR102144367B1 (ko) 2013-10-22 2020-08-14 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
US9679839B2 (en) 2013-10-30 2017-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9472533B2 (en) * 2013-11-20 2016-10-18 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming wire bondable fan-out EWLB package
US10327197B2 (en) * 2014-01-31 2019-06-18 Qualcomm Incorporated Distributed clustering of wireless network nodes
JP2015198093A (ja) * 2014-03-31 2015-11-09 凸版印刷株式会社 インターポーザー、半導体装置、インターポーザーの製造方法、半導体装置の製造方法
US10177115B2 (en) * 2014-09-05 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming
JP2016535462A (ja) * 2014-09-26 2016-11-10 インテル コーポレイション ワイヤボンディングされたマルチダイスタックを有する集積回路パッケージ
KR101760025B1 (ko) * 2015-04-29 2017-07-21 주식회사 아이지스시스템 역방향 주행 차량 감지 경보시스템
US10109617B2 (en) * 2016-07-21 2018-10-23 Samsung Electronics Co., Ltd. Solid state drive package
KR101994748B1 (ko) * 2016-09-12 2019-07-01 삼성전기주식회사 팬-아웃 반도체 패키지

Also Published As

Publication number Publication date
CN110050332A (zh) 2019-07-23
KR20190100176A (ko) 2019-08-28
KR102647213B1 (ko) 2024-03-15
WO2018125254A1 (en) 2018-07-05
US20210265305A1 (en) 2021-08-26
US11830848B2 (en) 2023-11-28
DE112016007561T5 (de) 2019-10-02

Similar Documents

Publication Publication Date Title
US9510463B2 (en) Coreless packaging substrate and fabrication method thereof
US20230361043A1 (en) Electrical interconnect bridge
CN107424975B (zh) 模块基板和半导体模块
KR102527137B1 (ko) 전자 디바이스 패키지
US9564390B2 (en) Package structure and fabrication method thereof
US11587844B2 (en) Electronic device package on package (POP)
CN118737973A (zh) 电子器件封装
US9343421B2 (en) Semiconductor package and fabrication method thereof
US12374626B2 (en) Architectures and methods of fabricating 3D stacked packages
US20190229093A1 (en) Electronic device package
CN103227164A (zh) 半导体封装构造及其制造方法
US11552051B2 (en) Electronic device package
CN105720021B (zh) 集成电路封装件及其制造方法
US20180047662A1 (en) Interposer substrate and method of manufacturing the same
US9601407B2 (en) System-in-package module and method for forming the same
TWI435667B (zh) 印刷電路板組件
US8698008B2 (en) Packaging substrate and fabrication method thereof
US20200075446A1 (en) Electronic device package
TWI487042B (zh) 封裝製程

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination