CN118674603A - Time-based frame generation via time-aware machine learning model - Google Patents

Abstract

The title of the present disclosure is "time-based frame generation via a time-aware machine learning model". Described herein is a graphics processor configured to perform time-based frame generation via a time-aware machine learning model that enables generation of frames at a target timestamp relative to a rendering time of an input frame. For example, for an extrapolated frame generated by a time-aware machine learning model, a low relative timestamp would indicate that the extrapolated frame would occur temporally near, and should occur relatively near, the last frame in the sequence of frames. A higher relative timestamp would indicate that the extrapolated frame should show a greater degree of convolution based on optical flow.

Description

Time-based frame generation via a time-aware machine learning model

Cross-references

This application claims priority to U.S. Provisional Application No. 63/490,618 (filed on March 16, 2023), which is hereby incorporated herein by reference.

Technical Field

The present disclosure relates generally to data processing via graphics processors, and more particularly to methods that enable time-based frame generation via time-aware machine learning models.

Background Art

The neural network that performs frame generation can be trained based on rendered frame data and optical flow data. The optical flow data can be a combination of optical flow generated by the game engine and optical flow data generated by the hardware based on analysis of rendered frames. The neural network will then learn to generate new frames based on a certain number of input frames and the optical flow between those frames.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments described herein are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like reference numerals indicate similar elements and in which:

FIG1 is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein;

2A-2D illustrate parallel processor components;

3A-3C are block diagrams of a graphics multiprocessor and a multiprocessor-based GPU;

4A-4F illustrate an exemplary architecture in which multiple GPUs are communicatively coupled to multiple multi-core processors;

FIG5 illustrates a graphics processing pipeline;

Figure 6 illustrates a machine learning software stack;

FIG7 illustrates a general purpose graphics processing unit;

FIG8 illustrates a multi-GPU computing system;

9A-9B illustrate the layers of an exemplary deep neural network;

FIG10 illustrates an exemplary recurrent neural network;

Figure 11 illustrates the training and deployment of a deep neural network;

FIG12A is a block diagram illustrating distributed learning;

FIG12B is a block diagram illustrating a programmable network interface and a data processing unit;

FIG13 illustrates an exemplary inference system on a chip (SOC) suitable for performing inference using a trained model;

FIG14 is a block diagram of a processing system;

15A-15C illustrate a computing system and a graphics processor;

16A-16C illustrate block diagrams of additional graphics processor and computing accelerator architectures;

FIG17 is a block diagram of a graphics processing engine of a graphics processor;

18A-18C illustrate thread execution logic including an array of processing elements employed in a graphics processor core;

FIG19 illustrates a slice of a multi-chip processor according to an embodiment;

FIG20 is a block diagram illustrating a graphics processor instruction format;

FIG21 is a block diagram of an additional graphics processor architecture;

22A-22B illustrate a graphics processor command format and command sequence;

FIG23 illustrates an exemplary graphics software architecture for a data processing system;

FIG24A is a block diagram illustrating an IP core development system;

FIG24B illustrates a cross-sectional side view of an integrated circuit package assembly;

FIG. 24C illustrates a package assembly including a hardware logic chiplet of multiple units connected to a substrate (e.g., a base die);

FIG24D illustrates a package assembly including interchangeable chiplets;

FIG25 is a block diagram illustrating an exemplary system-on-chip integrated circuit;

26A-26B are block diagrams illustrating an exemplary graphics processor for use within a SoC;

FIG27 is a block diagram of a data processing system according to an embodiment;

28A-28B illustrate matrix operations performed by an instruction pipeline according to an embodiment;

FIG29 illustrates a computational block including decomposition systolic logic for codec enablement;

30A-30B illustrate a system for frame extrapolation and frame interpolation using a unified time-aware machine learning model, according to an embodiment;

FIG31 illustrates a timeline of end-to-end operations for frame rendering on a graphics processor;

FIG32 illustrates a timeline in which neural frame generation is used to maintain a target frame pace;

33A-33B illustrate multiple GPU engines with multiple associated command buffers enabling asynchronous rendering and compute operations;

FIG34 illustrates a method of generating a time-aware machine learning model, according to an embodiment;

FIG35 illustrates a method of time-based frame generation via a time-aware machine learning model, according to an embodiment;

FIG36 illustrates a method for time-based frame generation asynchronous to a rendering rate, according to an embodiment;

FIG. 37 illustrates a system for maintaining consistent frame cadence via time-aware frame generation; and

38 is a block diagram of a computing device including a graphics processor, according to an embodiment.

DETAILED DESCRIPTION

Current parallel graphics data processing includes systems and methods developed to perform specific operations on graphics data, such as, for example, linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors have used fixed-function compute units to process graphics data. More recently, however, portions of graphics processors have been made programmable, enabling such processors to support a wider variety of operations to process vertex and fragment data.

To further improve performance, graphics processors typically implement processing techniques such as pipelining, which attempt to process as much graphics data as possible in parallel throughout different parts of the graphics pipeline. Parallel graphics processors with a single instruction multiple thread (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In the SIMT architecture, groups of parallel threads attempt to execute program instructions together synchronously as frequently as possible to improve processing efficiency. A general overview of software and hardware for the SIMT architecture can be found in Shane Cook's "CUDA Programming", Chapter 3, pages 37-51 (2013).

A graphics processing unit (GPU) is communicatively coupled to a host/processor core to accelerate, for example, graphics operations, machine learning operations, pattern analysis operations, and/or various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to a host processor/core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). Alternatively, the GPU may be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus/interconnect (i.e., inside the package or chip). Regardless of the manner in which the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands/instructions contained in a work descriptor. The GPU then uses dedicated circuit modules/logic to efficiently process these commands/instructions.

In the following description, numerous specific details are set forth to provide a more thorough understanding. However, it will be apparent to those skilled in the art that the embodiments described herein may be practiced without one or more of these specific details. In other instances, well-known features are not described to avoid obscuring the details of the current embodiments.

Described herein is a technique that enables time-based frame generation via a time-aware machine learning model. The frame generation model is trained to not only generate new frames based on input frames and optical flow, but also evolve the optical flow to target a specific future timestamp.

System Overview

FIG. 1 is a block diagram illustrating a computing system 100 configured to implement one or more aspects of the embodiments described herein. The computing system 100 includes a processing subsystem 101 having one or more processors 102 and a system memory 104 communicating via an interconnect path, which may include a memory hub 105. The memory hub 105 may be a separate component within a chipset component, or may be integrated within one or more processors 102. The memory hub 105 is coupled to an I/O subsystem 111 via a communication link 106. The I/O subsystem 111 includes an I/O hub 107 that enables the computing system 100 to receive input from one or more input devices 108. In addition, the I/O hub 107 enables a display controller (which may be included in one or more processors 102) to provide output to one or more display devices 110A. In one embodiment, the one or more display devices 110A coupled to the I/O hub 107 may include local, internal, or embedded display devices.

The processing subsystem 101 includes, for example, one or more parallel processors 112 coupled to the memory hub 105 via a bus or other communication link 113. The communication link 113 can be one of any number of standard-based communication link technologies or protocols, such as but not limited to PCI Express, or can be a vendor-specific communication interface or communication fabric. The one or more parallel processors 112 can form a parallel or vector processing system in a computational concentration that can include a large number of processing cores and/or processing clusters, such as, for example, a many integrated core (MIC) processor. For example, the one or more parallel processors 112 form a graphics processing subsystem that can output pixels to one of the one or more display devices 110A coupled via the I/O hub 107. The one or more parallel processors 112 may also include a display controller and a display interface (not shown) for enabling direct connection to one or more display devices 110B.

Within the I/O subsystem 111, a system storage unit 114 may be connected to the I/O hub 107 to provide a storage mechanism for the computing system 100. An I/O switch 116 may be used to provide an interface mechanism to enable connection between the I/O hub 107 and other components, such as a network adapter 118 and/or a wireless network adapter 119 that may be integrated into the platform, and various other devices that may be added via one or more plug-in devices 120. The plug-in device(s) 120 may also include, for example, one or more external graphics processor devices, graphics cards, and/or computing accelerators. The network adapter 118 may be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 may include one or more of the following: Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more wireless radio devices.

Computing system 100 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I/O hub 107 . The communication paths interconnecting the various components in FIG. 1 may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI Express), or any other bus or point-to-point communication interface and/or protocol(s), such as NVLink high-speed interconnect, Compute Express Link ^TM (CXLTM) (e.g., CXL.mem), Infinity Fabric (IF), Ethernet (IEEE 802.3), remote direct memory access (RDMA), InfiniBand, Internet Wide Area RDMA Protocol (iWARP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), quick UDP Internet Connections (QUIC), RDMA over Converged Ethernet (RoCE), Intel Quick Path Interconnect (QPI), Intel Ultra Path Interconnect (Intel Ultra Path Interconnect), Intel 802.3 High Speed Interconnect (Intel 802.3 High Speed Interconnect (Intel 802.3 High Speed Interconnect (Intel 802.3 High Speed Interconnect (Intel 802.3 High Speed Interconnect (Intel 802.3 High Speed Interconnect (Intel 802.3 High Speed Interconnect (Intel 802.3 High Speed Interconnect (Intel 802.3 High Speed Interconnect (QPI)), Intel Ultra Path Interconnect (Intel Ultra Path Interconnect, UPI), Intel On-Chip System Fabric (IOSF), Omnipath, HyperTransport, Advanced Microcontroller Bus Architecture (AMBA) interconnect, OpenCAPI, Gen-Z, Cache Coherent Interconnect for Accelerators (CCIX), 3GPP Long Term Evolution (LTE) (4G), 3GPP 5G and its variants, or a wired or wireless interconnect protocol known in the art. In some examples, data can be copied or stored to a virtualized storage node using a protocol such as non-volatile memory express (NVMe) (non-volatile memory express over Fabrics, NVME-oF) or NVMe.

One or more parallel processors 112 may include circuit modules optimized for graphics and video processing (including, for example, video output circuit modules) and constitute a graphics processing unit (GPU). Alternatively or additionally, as described in more detail herein, one or more parallel processors 112 may include circuit modules optimized for general-purpose processing while retaining the underlying computing architecture. Components of the computing system 100 may be integrated on a single integrated circuit with one or more other system elements. For example, one or more parallel processors 112, a memory hub 105, (one or more) processors 102, and an I/O hub 107 may be integrated into a system-on-chip (SoC) integrated circuit. Alternatively, components of the computing system 100 may be integrated into a single package to form a system-in-package (SIP) configuration. In one embodiment, at least a portion of the components of the computing system 100 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules into a modular computing system.

It will be appreciated that the computing system 100 shown herein is illustrative, and variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of (one or more) processors 102, and the number of (one or more) parallel processors 112, may be modified as desired. For example, the system memory 104 may be connected to the (one or more) processors 102 directly rather than through a bridge, while other devices communicate with the system memory 104 via the memory hub 105 and the (one or more) processors 102. In other alternative topologies, the (one or more) parallel processors are connected to the I/O hub 107 or directly to one of the one or more processors 102, rather than to the memory hub 105. In other embodiments, the I/O hub 107 and the memory hub 105 may be integrated into a single chip. It is also possible for two or more sets of processors 102 to be attached via multiple slots, which may be coupled to two or more instances of the (one or more) parallel processors 112.

Some of the specific components shown herein are optional, and may not be included in all implementations of computing system 100. For example, any number of plug-in cards or peripherals may be supported, or some components may be eliminated. In addition, some architectures may use different terminology for components similar to those illustrated in FIG. 1 . For example, memory hub 105 may be referred to as a north bridge in some architectures, while I/O hub 107 may be referred to as a south bridge.

FIG. 2A illustrates a parallel processor 200. The parallel processor 200 may be a GPU, a GPGPU, etc. as described herein. The various components of the parallel processor 200 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). The illustrated parallel processor 200 may be one or more of the parallel processor(s) 112 shown in FIG. 1 .

Parallel processor 200 includes parallel processing unit 202. Parallel processing unit includes I/O unit 204 that enables communication with other devices, including other instances of parallel processing unit 202. I/O unit 204 can be directly connected to other devices. For example, I/O unit 204 is connected to other devices via the use of a hub or switch interface (such as memory hub 105). The connection between memory hub 105 and I/O unit 204 forms communication link 113. Within parallel processing unit 202, I/O unit 204 is connected to host interface 206 and memory cross switch 216, wherein host interface 206 receives commands related to performing processing operations and memory cross switch 216 receives commands related to performing memory operations.

When the host interface 206 receives the command buffer via the I/O unit 204, the host interface 206 can direct the work operations for executing those commands to the front end 208. In one embodiment, the front end 208 is coupled with a scheduler 210, which is configured to distribute commands or other work items to the processing cluster array 212. The scheduler 210 ensures that the processing cluster array 212 is properly configured and in a valid state before the task is distributed to the processing clusters in the processing cluster array 212. The scheduler 210 can be implemented via firmware logic executed on a microcontroller. The microcontroller-implemented scheduler 210 can be configured to perform complex scheduling and work distribution operations at coarse and fine granularity, thereby achieving fast preemption and context switching of threads executed on the processing cluster array 212. Preferably, the host software can confirm the workload for scheduling on the processing cluster array 212 via one of a plurality of graphics processing doorbells. In other examples, polling for new workloads or interrupts can be used to identify or indicate the availability of work to be executed. The workload may then be automatically distributed across the processing cluster array 212 by the scheduler 210 logic within the scheduler microcontroller.

The processing cluster array 212 may include up to "N" processing clusters (e.g., cluster 214A, cluster 214B to cluster 214N). Each cluster 214A-214N in the processing cluster array 212 may execute a large number of concurrent threads. The scheduler 210 may allocate work to the clusters 214A-214N in the processing cluster array 212 using various scheduling and/or work distribution algorithms, which may vary depending on the workload generated for each type of program or calculation. Scheduling may be handled dynamically by the scheduler 210, or may be partially assisted by compiler logic during the compilation of program logic configured for execution by the processing cluster array 212. Optionally, different clusters 214A-214N in the processing cluster array 212 may be allocated to process different types of programs or to perform different types of calculations.

Processing cluster array 212 may be configured to perform various types of parallel processing operations. For example, processing cluster array 212 is configured to perform general-purpose parallel computing operations. For example, processing cluster array 212 may include logic for performing processing tasks including filtering of video and/or audio data, performing modeling operations including physical operations, and performing data transformations.

Processing cluster array 212 is configured to perform parallel graphics processing operations. In such embodiments where parallel processor 200 is configured to perform graphics processing operations, processing cluster array 212 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, and tessellation logic and other vertex processing logic. In addition, processing cluster array 212 may be configured to execute graphics processing related shader programs, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. Parallel processing unit 202 may transfer data from system memory via I/O unit 204 for processing. During processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 222) during processing, and then the data may be written back to system memory.

In embodiments where parallel processing units 202 are used to perform graphics processing, scheduler 210 may be configured to divide the processing workload into tasks of approximately equal size to better enable distribution of graphics processing operations to multiple clusters 214A-214N in processing cluster array 212. In some of these embodiments, portions of processing cluster array 212 may be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations to produce a rendered image for display. Intermediate data generated by one or more of clusters 214A-214N may be stored in a buffer to allow the intermediate data to be transferred between clusters 214A-214N for further processing.

During operation, the processing cluster array 212 may receive processing tasks to be executed via the scheduler 210, which receives commands defining the processing tasks from the front end 208. For graphics processing operations, the processing tasks may include data to be processed, such as surface (patch) data, primitive data, vertex data, and/or pixel data, and state parameters and commands defining how the data is to be processed (e.g., what program is to be executed). The scheduler 210 may be configured to fetch an index corresponding to the task, or may receive the index from the front end 208. The front end 208 may be configured to ensure that the processing cluster array 212 is configured to a valid state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

Each of the one or more instances of the parallel processing unit 202 may be coupled to a parallel processor memory 222. The parallel processor memory 222 may be accessed via a memory crossbar switch 216, which may receive memory requests from the processing cluster array 212 and the I/O unit 204. The memory crossbar switch 216 may access the parallel processor memory 222 via a memory interface 218. The memory interface 218 may include a plurality of partition units (e.g., partition unit 220A, partition unit 220B, up to partition unit 220N), each of which may be coupled to a portion (e.g., memory unit) of the parallel processor memory 222. The number of partition units 220A-220N may be configured to be equal to the number of memory units, such that the first partition unit 220A has a corresponding first memory unit 224A, the second partition unit 220B has a corresponding second memory unit 224B, and the Nth partition unit 220N has a corresponding Nth memory unit 224N. In other embodiments, the number of partition units 220A-220N may not be equal to the number of memory devices.

The memory units 224A-224N may include various types of memory devices, including dynamic random-access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. Optionally, the memory units 224A-224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will appreciate that the specific implementation of the memory units 224A-224N may vary and may be selected from one of a variety of conventional designs. Rendering targets such as frame buffers or texture maps may be stored across the memory units 224A-224N, thereby allowing the partition units 220A-220N to write portions of each rendering target in parallel to efficiently use the available bandwidth of the parallel processor memory 222. In some embodiments, local instances of the parallel processor memory 222 may be eliminated in favor of a unified memory design that utilizes system memory in conjunction with local cache memory.

Optionally, any of the clusters 214A-214N in the processing cluster array 212 has the capability to process data to be written to any of the memory units 224A-224N within the parallel processor memory 222. The memory crossbar 216 may be configured to transmit the output of each cluster 214A-214N to any partition unit 220A-220N or to another cluster 214A-214N, which may perform additional processing operations on the output. Each cluster 214A-214N may communicate with a memory interface 218 through the memory crossbar 216 to read from or write to various external memory devices. In one embodiment of an embodiment having a memory crossbar switch 216, the memory crossbar switch 216 has connections to a memory interface 218 to communicate with the I/O unit 204 and has connections to a local instance of a parallel processor memory 222, thereby enabling processing units within different processing clusters 214A-214N to communicate with system memory or other memory that is not local to the parallel processing unit 202. In general, the memory crossbar switch 216 may be able to separate traffic flows between the clusters 214A-214N and the partition units 220A-220N using virtual channels, for example.

Although a single instance of parallel processing unit 202 is illustrated in parallel processor 200, any number of instances of parallel processing unit 202 may be included. For example, multiple instances of parallel processing unit 202 may be arranged on a single plug-in card, or multiple plug-in cards may be interconnected. For example, parallel processor 200 may be a plug-in device, such as, plug-in device 120 of Fig. 1, which may be a graphics card (such as, including one or more GPUs, one or more memory devices, and a discrete graphics card of a device to device or network or structure interface). Different instances of parallel processing unit 202 may be configured to interoperate even if different instances have different numbers of processing cores, different amounts of local parallel processor memory, and/or other configuration differences. Optionally, some instances of parallel processing unit 202 may include higher precision floating point units relative to other instances. Systems comprising one or more instances of parallel processing unit 202 or parallel processor 200 may be implemented in various configurations and form factors, including, but not limited to, desktop computers, laptop computers, or handheld personal computers, servers, workstations, game consoles, and/or embedded systems. The orchestrator may form composite nodes for workload execution using one or more of the following: decomposed processor resources, cache resources, memory resources, storage resources, and networking resources.

In one embodiment, parallel processing unit 202 can be partitioned into multiple instances. Those multiple instances can be configured to execute workloads associated with different clients in an isolated manner, so that a predetermined quality of service is provided for each client. For example, each cluster 214A-214N can be partitioned and isolated from other clusters, thereby allowing processing cluster array 212 to be partitioned into multiple computing partitions or instances. In such configurations, the workload executed on the isolated partition is protected from errors or errors associated with different workloads executed on different partitions. Partition units 220A-220N can be configured to enable dedicated paths and/or isolated paths to the memory of clusters 214A-214N associated with corresponding computing partitions. This data path isolation enables the computing resources within the partition to communicate with one or more assigned memory units 224A-224N without being disturbed by the activities of other partitions.

FIG. 2B is a block diagram of a partition unit 220. The partition unit 220 may be an example of a partition unit in the partition units 220A-220N of FIG. 2A. As shown, the partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and an ROP 226 (grid operation unit). The L2 cache 221 is a read/write cache configured to perform load and store operations received from the memory crossbar switch 216 and the ROP 226. Read misses and urgent write-back requests are output by the L2 cache 221 to the frame buffer interface 225 for processing. Updates may also be sent to the frame buffer via the frame buffer interface 225 for processing. In one embodiment, the frame buffer interface 225 interfaces with a memory unit 224 in the memory unit 224A-224N in the parallel processor memory 222 of FIG. The partition unit 220 may also additionally or alternatively interface with a memory unit in the memory unit of the parallel processor memory via a memory controller (not shown).

In graphics applications, ROP 226 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. ROP 226 then outputs processed graphics data, which is stored in graphics memory. In some embodiments, ROP 226 includes or is coupled to a codec (CODEC) 227 that includes compression logic for compressing depth or color data written to memory or L2 cache 221 and decompressing depth or color data read from memory or L2 cache 221. The compression logic may be lossless compression logic that utilizes one or more of a variety of compression algorithms. The type of compression performed by CODEC 227 may vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, delta color compression is performed on depth and color data on a slice-by-slice basis. In one embodiment, CODEC 227 includes compression and decompression logic that can compress and decompress computational data associated with machine learning operations. CODEC 227 can, for example, compress sparse matrix data for sparse machine learning operations. CODEC 227 can also compress sparse matrix data encoded in a sparse matrix format (e.g., coordinate list encoding (COO), compressed sparse row (CSR), compressed sparse column (CSC), etc.) to generate compressed and encoded sparse matrix data. Compressed and encoded sparse matrix data can be decompressed and/or decoded before being processed by a processing element, or a processing element can be configured to consume compressed, encoded, or compressed and encoded data for processing.

ROP 226 may be included within each processing cluster (e.g., clusters 214A-214N of FIG. 2A ) rather than within partition unit 220. In such embodiments, read and write requests for pixel data rather than pixel fragment data are communicated through memory crossbar 216. The processed graphics data may be displayed on a display device (such as one of the one or more display devices 110A-110B of FIG. 1 ), routed for further processing by processor(s) 102, or routed for further processing by one of the processing entities within parallel processor 200 of FIG. 2A .

FIG. 2C is a block diagram of a processing cluster 214 within a parallel processing unit. For example, a processing cluster is an instance of a processing cluster in the processing clusters 214A-214N of FIG. 2A. The processing cluster 214 may be configured to execute many threads in parallel, wherein the term "thread" refers to an instance of a specific program executed on a set of specific input data. Optionally, a single-instruction, multiple-data (SIMD) instruction issuance technique may be used to support the parallel execution of a large number of threads without providing multiple independent instruction units. Alternatively, a single-instruction, multiple-thread (SIMT) technique may be used to support the parallel execution of a large number of threads that are generally synchronized using a common instruction unit that is configured to issue instructions to a set of processing engines within each processing cluster in the processing cluster. Unlike the SIMD execution mechanism in which all processing engines typically execute the same instruction, SIMT execution allows different threads to more easily follow the divergent execution path through a given thread program. It will be appreciated by those skilled in the art that the SIMD processing mechanism represents a functional subset of the SIMT processing mechanism.

The operation of the processing cluster 214 can be controlled via a pipeline manager 232 that distributes processing tasks to SIMT parallel processors. The pipeline manager 232 receives instructions from the scheduler 210 of FIG. 2A and manages the execution of those instructions via the graphics multiprocessor 234 and/or the texture unit 236. The illustrated graphics multiprocessor 234 is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors of different architectures can be included in the processing cluster 214. One or more instances of the graphics multiprocessor 234 can be included in the processing cluster 214. The graphics multiprocessor 234 can process data, and the data crossbar 240 can be used to distribute the processed data to one of a plurality of possible destinations, including facilitating the exchange of data between the graphics multiprocessors within the processing cluster 214. The pipeline manager 232 can facilitate the distribution of processed data by specifying a destination for the processed data to be distributed via the data crossbar 240.

Each graphics multiprocessor 234 within a processing cluster 214 may include an identical set of function execution logic (e.g., arithmetic logic units, load-store units, etc.). The function execution logic may be configured in a pipelined manner in which new instructions may be issued before previous instructions are completed. The function execution logic supports a variety of operations, including integer and floating point arithmetic, comparison operations, Boolean operations, bit shifts, and calculation of various algebraic functions. The same functional unit hardware may be utilized to perform different operations, and any combination of functional units may exist.

The instructions transmitted to the processing cluster 214 constitute threads. A collection of threads executed across a collection of parallel processing engines is a thread group. A thread group executes the same program on different input data. Each thread within a thread group can be assigned to a different processing engine within the graphics multiprocessor 234. A thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 234. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle during which the thread group is being processed. A thread group may also include more threads than the number of processing engines within the graphics multiprocessor 234. When a thread group includes more threads than the number of processing engines within the graphics multiprocessor 234, processing may be performed in consecutive clock cycles. Optionally, multiple thread groups may be executed concurrently on the graphics multiprocessor 234.

The graphics multiprocessor 234 may include internal cache memory to perform load and store operations. Optionally, the graphics multiprocessor 234 may abandon the internal cache and use the cache memory (e.g., the first level (level 1, L1) cache 248) within the processing cluster 214. Each graphics multiprocessor 234 also has access to the second level (L2) cache within the partition unit (e.g., the partition unit 220A-220N of Figure 2A), which is shared between all processing clusters 214 and can be used to transfer data between threads. The graphics multiprocessor 234 can also access off-chip global memory, which can include one or more of the local parallel processor memory and/or system memory. Any memory external to the parallel processing unit 202 can be used as global memory. In embodiments where the processing cluster 214 includes multiple instances of the graphics multiprocessor 234, common instructions and data can be shared, which can be stored in the L1 cache 248.

Each processing cluster 214 may include an MMU 245 (memory management unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of the MMU 245 may reside within the memory interface 218 of FIG. 2A. The MMU 245 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of slices, and optionally includes a cache line index. The MMU 245 may include an address translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 234 or L1 cache 248 of the processing cluster 214. The physical address is processed to distribute surface data access locality, thereby allowing efficient request interleaving between partition units. The cache line index can be used to determine whether a request for a cache line is a hit or a miss.

In graphics and computing applications, the processing clusters 214 may be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data is read from an internal texture L1 cache (not shown), or in some embodiments, from an L1 cache within the graphics multiprocessor 234 and retrieved from an L2 cache, local parallel processor memory, or system memory as needed. Each graphics multiprocessor 234 outputs processed tasks to a data crossbar 240 to provide the processed tasks to another processing cluster 214 for further processing, or stores the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 216. A preROP 242 (pre-raster operations unit) is configured to receive data from the graphics multiprocessor 234 and direct the data to ROP units, which may be located with partition units (e.g., partition units 220A-220N of FIG. 2A ) as described herein. The preROP 242 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

It will be appreciated that the core architecture described herein is illustrative, and variations and modifications are possible. Any number of processing units (e.g., graphics multiprocessor 234, texture unit 236, preROP 242, etc.) may be included within a processing cluster 214. Further, while only one processing cluster 214 is shown, a parallel processing unit as described herein may include any number of instances of a processing cluster 214. Optionally, each processing cluster 214 may be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 caches, L2 caches, etc.

2D shows an example of a graphics multiprocessor 234, where the graphics multiprocessor 234 is coupled to the pipeline manager 232 of the processing cluster 214. The graphics multiprocessor 234 has an execution pipeline that includes, but is not limited to, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general purpose graphics processing unit (GPGPU) cores 262, and one or more load/store units 266. The GPGPU cores 262 and the load/store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268. The graphics multiprocessor 234 may additionally include a tensor and/or ray tracing core 263 that includes hardware logic for accelerating matrix and/or ray tracing operations.

The instruction cache 252 may receive an instruction stream to be executed from the pipeline manager 232. The instructions are cached in the instruction cache 252 and dispatched for execution by the instruction unit 254. The instruction unit 254 may dispatch the instructions as a thread group (e.g., a unit group (warp)), wherein each thread in the thread group is assigned to a different execution unit within the GPGPU core 262. The instruction may access any of the local address space, the shared address space, or the global address space by specifying an address within the unified address space. The address mapping unit 256 may be used to translate the address in the unified address space into different memory addresses that can be accessed by the load/store unit 266.

The register file 258 provides a collection of registers for the functional units of the graphics multiprocessor 234. The register file 258 provides temporary storage for operands of data paths of the functional units (e.g., GPGPU core 262, load/store unit 266) connected to the graphics multiprocessor 234. The register file 258 may be divided between each of the functional units so that each functional unit is assigned a dedicated portion of the register file 258. For example, the register file 258 may be divided between different groups of units executed by the graphics multiprocessor 234.

The GPGPU cores 262 may each include a floating point unit (FPU) and/or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 234. In some implementations, the GPGPU cores 262 may include hardware logic that may otherwise reside within the tensor and/or ray tracing cores 263. The GPGPU cores 262 may be similar in architecture, or may be different in architecture. For example and in one embodiment, the first portion of the GPGPU core 262 includes a single-precision FPU and an integer ALU, while the second portion of the GPGPU core includes a double-precision FPU. Optionally, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic, or enable variable-precision floating-point arithmetic. The graphics multiprocessor 234 may additionally include one or more fixed-function or special-function units for performing specific functions, such as copying rectangles or pixel blending operations. One or more of the GPGPU cores in the GPGPU core may also include fixed-function or special-function logic.

GPGPU core 262 may include SIMD logic capable of executing a single instruction to multiple sets of data. Optionally, GPGPU core 262 can physically execute SIMD4, SIMD8 and SIMD16 instructions, and logically execute SIMD1, SIMD2 and SIMD32 instructions. SIMD instructions for GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. Multiple threads of a program configured for a SIMT execution model can be executed via a single SIMD instruction. For example and in one embodiment, eight SIMT threads can be executed in parallel via a single SIMD8 logic unit, and these eight SIMT threads perform the same or similar operations.

The memory and cache interconnect 268 is an interconnect network that connects each of the functional units of the graphics multiprocessor 234 to the register file 258 and to the shared memory 270. For example, the memory and cache interconnect 268 is a crossbar interconnect that allows the load/store unit 266 to implement load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, so data transfers between the GPGPU core 262 and the register file 258 are very low latency. The shared memory 270 can be used to enable communication between threads executed on the functional units within the graphics multiprocessor 234. The cache memory 272 can be used as a data cache, for example, to cache texture data passed between the functional unit and the texture unit 236. The shared memory 270 can also be used as a managed cached program. The shared memory 270 and the cache memory 272 can be coupled with the data crossbar 240 to enable communication with other components of the processing cluster. Threads executing on GPGPU core 262 can programmatically store data in shared memory in addition to automatically cached data stored in cache memory 272 .

3A-3C illustrate additional graphics multiprocessors according to an embodiment. FIG. 3A-3B illustrate graphics multiprocessors 325, 350, which are related to the graphics multiprocessor 234 of FIG. 2C and can be used in place of one of those graphics multiprocessors. Therefore, the disclosure of any feature in conjunction with the graphics multiprocessor 234 herein also discloses the corresponding combination with the graphics multiprocessor 325, 350, but is not limited thereto. FIG. 3C illustrates a graphics processing unit (GPU) 380, which includes a collection of dedicated graphics processing resources arranged as multi-core groups 365A-365N, which correspond to the graphics multiprocessors 325, 350. The illustrated graphics multiprocessors 325, 350 and multi-core groups 365A-365N can be streaming multiprocessors (SMs) capable of executing a large number of execution threads simultaneously.

The graphics multiprocessor 325 of FIG. 3A includes multiple additional instances of execution resource units relative to the graphics multiprocessor 234 of FIG. 2D. For example, the graphics multiprocessor 325 may include multiple instances of instruction units 332A-332B, register files 334A-334B, and (one or more) texture units 344A-344B. The graphics multiprocessor 325 also includes multiple graphics or compute execution unit sets (e.g., GPGPU cores 336A-336B, tensor cores 337A-337B, ray tracing cores 338A-338B) and multiple load/store unit sets 340A-340B. The execution resource units have a common instruction cache 330, texture and/or data cache memory 342, and shared memory 346.

The components may communicate via an interconnect structure 327. The interconnect structure 327 may include one or more crossbar switches to enable communication between the components of the graphics multiprocessor 325. The interconnect structure 327 is a separate, high-speed network fabric layer on which each component of the graphics multiprocessor 325 is stacked. The components of the graphics multiprocessor 325 communicate with remote components via the interconnect structure 327. For example, the cores 336A-336B, 337A-337B, and 338A-338B may each communicate with the shared memory 346 via the interconnect structure 327. The interconnect structure 327 may arbitrate communications within the graphics multiprocessor 325 to ensure fair bandwidth allocation between components.

The graphics multiprocessor 350 of FIG. 3B includes a plurality of execution resource sets 356A-356D, wherein, as illustrated in FIG. 2D and FIG. 3A , each execution resource set includes a plurality of instruction units, register files, GPGPU cores, and load storage units. The execution resources 356A-356D may work in coordination with (one or more) texture units 360A-360D for texture operations, while sharing an instruction cache 354 and a shared memory 353. For example, the execution resources 356A-356D may share multiple instances of an instruction cache 354 and a shared memory 353 and texture and/or data cache memories 358A-358B. The components may communicate via an interconnect structure 352 similar to the interconnect structure 327 of FIG. 3A .

Those skilled in the art will appreciate that the architectures described in FIG. 1 , FIG. 2A-FIG. 2D, and FIG. 3A-FIG. 3B are illustrative and not limiting in terms of the scope of the present embodiments. Therefore, the techniques described herein may be implemented on any appropriately configured processing unit without departing from the scope of the embodiments described herein, including but not limited to: one or more mobile application processors; one or more desktop or server central processing units (CPUs), including multi-core CPUs; one or more parallel processor units, such as the parallel processing unit 202 of FIG. 2A, and one or more graphics processors or special processing units.

The parallel processor or GPGPU described herein can be communicatively coupled to a host/processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor/core via a bus or another interconnect (e.g., a high-speed interconnect, such as PCIe, NVLink, or other known protocols, standardized protocols, or proprietary protocols). In other embodiments, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus/interconnect (i.e., inside the package or chip). Regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands/instructions contained in a work descriptor. The GPU then uses dedicated circuit modules/logic to efficiently process these commands/instructions.

3C illustrates a graphics processing unit (GPU) 380 that includes a dedicated set of graphics processing resources arranged as multi-core groups 365A-365N. Although details of only a single multi-core group 365A are provided, it will be appreciated that other multi-core groups 365B-365N may be equipped with the same or similar set of graphics processing resources. The details described with respect to multi-core groups 365A-365 may also be applied to any graphics multiprocessor 234, 325, 350 described herein.

As illustrated, multi-core group 365A may include a set 370 of graphics cores, a set 371 of tensor cores, and a set 372 of ray tracing cores. Scheduler/dispatcher 368 schedules and dispatches graphics threads for execution on the respective cores 370, 371, 372. A set 369 of register files stores operand values used by cores 370, 371, 372 when executing graphics threads. These register files may include, for example, integer registers for storing integer values, floating point registers for storing floating point values, vector registers for storing packed data elements (integer and/or floating point data elements), and slice registers for storing tensor/matrix values. Slice registers may be implemented as a combined set of vector registers.

One or more combined first level (L1) caches and shared memory units 373 store graphics data locally within each multi-core group 365A, such as texture data, vertex data, pixel data, light data, bounding volume data, etc. One or more texture units 374 can also be used to perform texture operations, such as texture mapping and sampling. A second level (L2) cache 375 shared by all multi-core groups 365A-365N or a subset of multi-core groups 365A-365N stores graphics data and/or instructions for multiple concurrent graphics threads. As shown, the L2 cache 375 can be shared across multiple multi-core groups 365A-365N. One or more memory controllers 367 couple the GPU 380 to a memory 366, which can be a system memory (e.g., DRAM) and/or a dedicated graphics memory (e.g., GDDR6 memory).

The input/output (I/O) circuit module 363 couples the GPU 380 to one or more I/O devices 362, such as a digital signal processor (DSP), a network controller, or a user input device. On-chip interconnects may be used to couple the I/O devices 362 to the GPU 380 and memory 366. One or more I/O memory management units (IOMMUs) 364 of the I/O circuit module 363 directly couple the I/O devices 362 to the system memory 366. Optionally, the IOMMU 364 manages a plurality of page table sets for mapping virtual addresses to physical addresses in the system memory 366. The I/O devices 362, the CPU(s) 361, and the GPU(s) 380 may then share the same virtual address space.

In one implementation of the IOMMU 364, the IOMMU 364 supports virtualization. In this case, the IOMMU 364 can manage a first set of page tables for mapping guest/graphics virtual addresses to guest/graphics physical addresses and a second set of page tables for mapping guest/graphics physical addresses to system/host physical addresses (e.g., within system memory 366). The base address of each of the first set of page tables and the second set of page tables can be stored in a control register and swapped out at a context switch (e.g., so that the new context is provided with access to the relevant set of page tables). Although not illustrated in FIG. 3C, each of the cores 370, 371, 372 and/or the multi-core groups 365A-365N may include a translation lookaside buffer (TLB) for caching guest virtual to guest physical translations, guest physical to host physical translations, and guest virtual to host physical translations.

(One or more) CPU 361, GPU 380 and I/O device 362 can be integrated on a single semiconductor chip and/or chip package. The illustrated memory 366 can be integrated on the same chip, or can be coupled to a memory controller 367 via an off-chip interface. In one implementation, memory 366 includes GDDR6 memory that shares the same virtual address space as other physical system-level memory, but the basic principles described herein are not limited to this particular implementation.

Tensor core 371 may include multiple execution units specifically designed to perform matrix operations, which are basic computational operations for performing deep learning operations. For example, synchronized matrix multiplication operations may be used for neural network training and inference. Tensor core 371 may perform matrix processing using a variety of operand precisions, including single-precision floating point (e.g., 32 bits), half-precision floating point (e.g., 16 bits), integer words (16 bits), bytes (8 bits), and half bytes (4 bits). For example, a neural network implementation extracts features of each rendered scene, potentially combining details from multiple frames to build a high-quality final image.

In a deep learning implementation, parallel matrix multiplication work may be scheduled for execution on the tensor core 371. The training of neural networks in particular requires a large number of matrix dot product operations. To handle the inner product formulation of the N x N x N matrix multiplication, the tensor core 371 may include at least N dot product processing elements. Before the matrix multiplication begins, a complete matrix is loaded into the slice register, and for each of the N cycles, at least one column of the second matrix is loaded. For each cycle, there are N dot products that are processed.

Depending on the specific implementation, matrix elements can be stored with different precisions, including 16-bit words, 8-bit bytes (e.g., INT8), and 4-bit nibbles (e.g., INT4). Different precision modes can be specified for the tensor core 371 to ensure that the most efficient precision is used for different workloads (e.g., such as inference workloads, which can tolerate quantization to bytes and nibbles). Supported formats additionally include 64-bit floating point (FP64) and non-IEEE floating point formats, such as the bfloat16 format (e.g., Brain floating point), a 16-bit floating point format with one sign bit, eight exponent bits, and eight significand bits (seven of which are explicitly stored). One embodiment includes support for a reduced precision tensor floating point (TF32) mode that performs calculations using the range of FP32 (8 bits) and the precision of FP16 (10 bits). Reduced precision TF32 operations can be performed on FP32 inputs and produce FP32 outputs with higher performance relative to FP32 and increased precision relative to FP16. In one embodiment, one or more 8-bit floating point formats (FP32) are supported.

In one embodiment, the tensor core 371 supports a sparse operation mode for matrices in which the vast majority of values are zero. The tensor core 371 includes support for sparse input matrices encoded in sparse matrix representations (e.g., coordinate list encoding (COO), compressed sparse rows (CSR), compressed sparse columns (CSC), etc.). The tensor core 371 also includes support for compressed sparse matrix representations in the case where the sparse matrix representation can be further compressed. Compressed matrix data, encoded matrix data, and/or compressed and encoded matrix data and associated compression and/or encoding metadata can be read by the tensor core 371, and non-zero values can be extracted. For example, for a given input matrix A, non-zero values can be loaded from at least a portion of the compressed and/or encoded representation of matrix A. Based on the position of the non-zero value in matrix A (which can be determined from the index or coordinate metadata associated with the non-zero value), the corresponding value in the input matrix B can be loaded. Depending on the operation to be performed (e.g., multiplication), if the corresponding value is a zero value, loading the value from the input matrix B can be bypassed. In one embodiment, the pairing of values for certain operations (such as multiplication operations) can be pre-scanned by the scheduler logic, and only operations between non-zero inputs are scheduled. Depending on the dimensions of matrix A and matrix B and the operations to be performed, the output matrix C can be dense or sparse. In the case where the output matrix C is sparse and depending on the configuration of the tensor core 371, the output matrix C can be output in a compressed format, sparse coding, or compressed sparse coding.

Ray tracing core 372 can accelerate ray tracing operations for both real-time ray tracing implementations and non-real-time ray tracing implementations. Specifically, ray tracing core 372 may include a ray traversal/intersection circuit module that uses a bounding volume hierarchy (BVH) to perform ray traversals and identify intersections between rays and primitives enclosed within the BVH volume. Ray tracing core 372 may also include circuit modules for performing depth testing and culling (e.g., using a Z buffer or similar arrangement). In one implementation, ray tracing core 372 performs traversal and intersection operations in conjunction with the image denoising techniques described herein, at least portions of which may be performed on tensor core 371. For example, tensor core 371 may implement a deep learning neural network to perform denoising on frames generated by ray tracing core 372. However, the CPU(s) 361, graphics core 370, and/or ray tracing core 372 may also implement all or portions of the denoising and/or deep learning algorithms.

In addition, as described above, a distributed approach to noise reduction may be employed, wherein GPU 380 is in a computing device coupled to other computing devices via a network or high-speed interconnect. According to the distributed approach, the interconnected computing devices may share neural network learning/training data to improve the speed at which the entire system learns to perform noise reduction for different types of image frames and/or different graphics applications.

The ray tracing core 372 can handle all BVH traversals and/or ray-primitive intersections, thereby preventing the graphics core 370 from being overloaded with thousands of instructions for each ray. For example, each ray tracing core 372 includes a first set of specialized circuit modules for performing bounding box tests (e.g., for traversal operations) and/or a second set of specialized circuit modules for performing ray-triangle intersection tests (e.g., intersecting rays that have been traversed). Thus, for example, the multi-core group 365A can simply start ray detection, and the ray tracing core 372 independently performs ray traversals and intersections and returns hit data (e.g., hits, no hits, multiple hits, etc.) to the thread context. While the ray tracing core 370 performs traversal and intersection operations, the other cores 371, 372 are freed up to perform other graphics or computational work.

Optionally, each ray tracing core 372 may include a traversal unit for performing BVH test operations and/or an intersection unit for performing ray-primitive intersection tests. The intersection unit generates a "hit", "no hit", or "multiple hits" response, which it provides to the appropriate thread. During traversal and intersection operations, execution resources of other cores (e.g., graphics core 370 and tensor core 371) are freed up to perform other forms of graphics work.

In one optional embodiment described below, a hybrid rasterization/ray tracing approach is used in which the work is distributed between graphics core 370 and ray tracing core 372 .

The ray tracing core 372 (and/or other cores 370, 371) may include hardware support for ray tracing instruction sets, such as Microsoft's DirectX Ray Tracing (DXR), which includes the DispatchRays command; and ray generation shaders, nearest hit shaders, any hit shaders, and miss shaders, which enable unique shader and texture sets to be assigned to each object. Another ray tracing platform that may be supported by the ray tracing core 372, graphics core 370, and tensor core 371 is the Vulkan API (e.g., Vulkan version 1.1.85, or later). However, it should be noted that the basic principles described herein are not limited to any particular ray tracing ISA.

In general, each core 372, 371, 370 may support a ray tracing instruction set including instructions/functions for one or more of the following: ray generation, nearest hit, any hit, ray-primitive intersection, per-primitive and hierarchy bounding box construction, misses, visits, and exceptions. More specifically, preferred embodiments include ray tracing instructions for performing one or more of the following functions:

Ray Generation —Ray generation instructions can be executed for each pixel, sample, or other user-defined work assignment.

Closest Hit - Closest hit instructions can be executed to locate the closest intersection of a ray with a primitive within the scene.

Any Hit - The Any Hit directive identifies multiple intersections between rays and primitives within the scene, potentially identifying a new closest intersection point.

Intersect - The Intersect command performs a ray-primitive intersection test and outputs the result.

Per-primitive bounding box construction - This instruction builds a bounding box around a given primitive or group of primitives (e.g., when building a new BVH or other acceleration data structure).

Miss - Indicates that the ray missed the scene or all geometry within a specified area of the scene.

Visits – Indicates the subvolumes that the ray will traverse.

Exceptions - includes various types of exception handlers (eg, called for various error conditions).

In one embodiment, the ray tracing core 372 may be adapted to accelerate general computing operations that can be accelerated using computing techniques similar to ray intersection testing. A computing framework may be provided that enables shader programs to be compiled into low-level instructions and/or primitives that perform general computing operations via the ray tracing core. Exemplary computing problems that may benefit from computing operations performed on the ray tracing core 372 include calculations involving the propagation of beams, waves, rays, or particles within a coordinate space. Interactions associated with that propagation may be calculated relative to geometry or meshes within the coordinate space. For example, calculations associated with the propagation of electromagnetic signals through an environment may be accelerated using instructions or primitives that are executed via the ray tracing core. Refraction and reflection of signals through objects in the environment may be calculated as direct ray tracing simulations.

The ray tracing core 372 can also be used to perform calculations that are not directly similar to ray tracing. For example, the ray tracing core 372 can be used to accelerate mesh projection, mesh refinement, and volume sampling calculations. General coordinate space calculations, such as nearest neighbor calculations, can also be performed. For example, a set of points near a given point can be found by defining a bounding box around the given point in the coordinate space. The BVH and ray detection logic in the ray tracing core 372 can then be used to determine the set of intersections of points within the bounding box. The intersection constitutes the origin and the nearest neighbor of that origin. The calculations performed using the ray tracing core 372 can be performed in parallel with the calculations performed on the graphics core 372 and the tensor core 371. The shader compiler can be configured to compile a compute shader or other general graphics processing program into a low-level primitive that can be parallelized across the graphics core 370, the tensor core 371, and the ray tracing core 372.

Technologies for GPU to host processor interconnect

FIG. 4A illustrates an exemplary architecture in which multiple GPUs 410-413 (e.g., parallel processors 200 such as shown in FIG. 2A ) are communicatively coupled to multiple multi-core processors 405-406 via high-speed links 440A-440D (e.g., buses, point-to-point interconnects, etc.). Depending on the implementation, high-speed links 440A-440D may support 4 GB/s, 30 GB/s, 80 GB/s, or higher communication throughput. Various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the basic principles described herein are not limited to any particular communication protocol or throughput.

Two or more of the GPUs 410-413 may be interconnected via high-speed links 442A-442B, which may be implemented using the same or different protocols/links as those used for high-speed links 440A-440D. Similarly, two or more of the multi-core processors 405-406 may be connected via high-speed link 443, which may be a symmetric multi-processor (SMP) bus operating at 20 GB/s, 30 GB/s, 120 GB/s, or lower or higher speeds. Alternatively, all communications between the various system components shown in FIG. 4A may be implemented using the same protocol/link (e.g., via a common interconnect structure). However, as mentioned, the basic principles described herein are not limited to any particular type of interconnect technology.

Each of the multi-core processors 405 and 406 may be communicatively coupled to processor memories 401-402 via memory interconnects 430A-430B, respectively, and each GPU 410-413 may be communicatively coupled to GPU memories 420-423, respectively, via GPU memory interconnects 450A-450D. Memory interconnects 430A-430B and 450A-450D may utilize the same or different memory access technologies. By way of example and not limitation, processor memories 401-402 and GPU memories 420-423 may be volatile memories such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and/or may be non-volatile memories such as 3D Xpoint/Optane or Nano-Ram. For example, a portion of the memory may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy). The memory subsystem described herein may be compatible with several memory technologies, such as the double data rate version published by JEDEC (Joint Electronic Device Engineering Council).

As described below, although each processor 405-406 and GPU 410-413 may be physically coupled to a specific memory 401-402, 420-423, respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed among all of the various physical memories. For example, processor memories 401-402 may each include 64GB of system memory address space, and GPUs 420-423 may each include 32GB of system memory address space (resulting in a total of 256GB of addressable memory in this example).

4B illustrates additional optional details of the interconnection between the multi-core processor 407 and the graphics acceleration module 446. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card that is coupled to the processor 407 via the high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated on the same package or chip as the processor 407.

The illustrated processor 407 includes a plurality of cores 460A-460D, each of which has a translation lookaside buffer 461A-461D and one or more caches 462A-462D. The core may include various other components for executing instructions and processing data, which are not illustrated to avoid obscuring the basic principles of the components described herein (e.g., instruction fetch units, branch prediction units, decoders, execution units, reorder buffers, etc.). Caches 462A-462D may include first-level (L1) caches and second-level (L2) caches. In addition, one or more shared caches 456 may be included in the cache hierarchy and shared by the set 460A-460D of cores. For example, one embodiment of the processor 407 includes 24 cores, each of which has its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, one of the L2 cache and the L3 cache is shared by two adjacent cores. Processor 407 and graphics accelerator integrated module 446 are connected to system memory 441, which may include processor memories 401-402.

Coherence is maintained for data and instructions stored in each cache 462A-462D, 456 and system memory 441 via inter-core communications over coherence bus 464. For example, each cache may have a cache coherence logic/circuitry module associated therewith to communicate over coherence bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented over coherence bus 464 to snoop cache accesses. Cache snooping/coherence techniques are well understood by those skilled in the art and will not be described in detail herein to avoid obscuring the basic principles described herein.

A proxy circuit 425 may be provided that communicatively couples the graphics acceleration module 446 to the coherence bus 464, thereby allowing the graphics acceleration module 446 to participate in a cache coherence protocol as a peer of the core. Specifically, an interface 435 provides connectivity to the proxy circuit 425 via a high-speed link 440 (e.g., a PCIe bus, NVLink, etc.), and an interface 437 connects the graphics acceleration module 446 to the high-speed link 440.

In one implementation, the accelerator integrated circuit 436 provides cache management, memory access, context management, and interrupt management services on behalf of multiple graphics processing engines 431, 432...N of the graphics acceleration module 446. The graphics processing engines 431, 432...N may each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432...N may include different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder/decoder), a sampler, and a block image transfer (BLIT) engine. In other words, the graphics acceleration module may be a GPU with multiple graphics processing engines 431-432...N, or the graphics processing engines 431-432...N may be separate GPUs integrated on a common package, line card, or chip. The graphics processing engines 431-432...N may be configured using any graphics processor or computing accelerator architecture described herein.

The accelerator integrated circuit 436 may include a memory management unit (MMU) 439 for performing various memory management functions such as virtual to physical memory translation (also known as effective to real memory translation) and memory access protocols for accessing the system memory 441. The MMU 439 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual/effective to physical/real address translations. In one implementation, the cache 438 stores commands and data for efficient access by the graphics processing engines 431, 432...N. The data stored in the cache 438 and the graphics memories 433-434...M may be kept consistent with the core caches 462A-462D, 456 and the system memory 441. As mentioned, this may be accomplished via proxy circuitry 425, which participates in cache coherence mechanisms on behalf of cache 438 and memories 433-434...M (e.g., sending updates to cache 438 related to modifications/accesses of cache lines on processor caches 462A-462D, 456, and receiving updates from cache 438).

The set of registers 445 stores context data for threads executed by the graphics processing engines 431-432...N, and the context management circuit 448 manages these thread contexts. For example, the context management circuit 448 may perform save and restore operations to save and restore the context of each thread during a context switch (e.g., where a first thread is saved and a second thread is restored so that the second thread can be executed by the graphics processing engine). For example, upon a context switch, the context management circuit 448 may store the current register value to a specified area in memory (e.g., identified by a context pointer). When returning to that context, it may then restore the register value. The interrupt management circuit 447 may, for example, receive an interrupt from a system device and process the interrupt received from the system device.

In one implementation, the virtual/effective address from the graphics processor engine 431 is translated into the actual/physical address in the system memory 441 by the MMU 439. Optionally, the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and/or other accelerator devices. The graphics accelerator module 446 may be dedicated to a single application executed on the processor 407, or may be shared between multiple applications. Optionally, a virtualized graphics execution environment is provided in which the resources of the graphics processing engines 431-432 ... N are shared with multiple applications, virtual machines (VMs) or containers. Resources can be subdivided into "slices" that are allocated to different VMs and/or applications based on processing requirements and priorities associated with the VMs and/or applications or based on a predetermined partition profile for the graphics accelerator module 446. VMs and containers may be used interchangeably herein.

A virtual machine (VM) can be software that runs an operating system and one or more applications. A VM can be defined by specifications, configuration files, virtual disk files, non-volatile random access memory (NVRAM) settings files, and log files, and is backed up by the physical resources of the host computing platform. A VM may include an operating system (OS) or application environment installed on software that mimics dedicated hardware. End users have the same experience on a virtual machine as they would on dedicated hardware. Specialized software called a hypervisor completely emulates the CPU, memory, hard disk, network, and other hardware resources of a PC client or server, enabling virtual machines to share resources. A hypervisor can emulate multiple virtual hardware platforms that are isolated from each other, allowing virtual machines to run on the same underlying physical host. Server, VMware ESXi, and other operating systems.

A container can be a package of applications, configurations, and dependencies so that the application runs reliably from one computing environment to another. Containers can share the operating system installed on a server platform and run as isolated processes. Containers can be software packages that contain everything the software needs to run, such as system tools, libraries, and settings. Containers are not installed like traditional software programs, which allows them to be isolated from other software and from the operating system itself. The isolated nature of containers provides several benefits. First, the software in the container will run the same way in different environments. For example, a container that includes PHP and MySQL can be installed in the same way as in the container. Computer and The machines run in exactly the same way on both. Second, containers provide increased security because the software will not affect the host operating system. While installed applications can change system settings and modify resources (such as the Windows registry), containers can only modify settings within the container.

Thus, the accelerator integrated circuit 436 acts as a bridge to the system for the graphics acceleration module 446 and provides address translation and system memory caching services. In one embodiment, to facilitate the bridging function, the accelerator integrated circuit 436 may also include a shared I/O 497 (e.g., PCIe, USB, or other elements) and hardware to enable system control of voltage, clock control, performance, heat, and security. The shared I/O 497 may utilize separate physical connections or may span the high-speed link 440. In addition, the accelerator integrated circuit 436 may provide virtualization facilities for the host processor to manage virtualization of the graphics processing engine, interrupts, and memory management.

Since the hardware resources of the graphics processing engines 431-432...N are explicitly mapped to the actual address space seen by the host processor 407, any host processor can directly address these resources using effective address values. An optional function of the accelerator integrated circuit 436 is to physically separate the graphics processing engines 431-432...N so that they appear as independent units to the system.

One or more graphics memories 433-434 ... M may be respectively coupled to each of the graphics processing engines 431-432 ... N. Graphics memories 433-434 ... M store instructions and data processed by each of the graphics processing engines 431-432 ... N. Graphics memories 433-434 ... M may be volatile memories such as DRAM (including stacked DRAM), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and/or may be non-volatile memories such as 3D Xpoint/Optane, Samsung Z-NAND, or Nano-Ram.

To reduce the amount of data traffic on high-speed link 440, biasing techniques may be used to ensure that the data stored in graphics memory 433-434 ... M is data that will be used most frequently by graphics processing engines 431-432 ... N and preferably not used (at least not frequently) by cores 460A-460D. Similarly, the biasing mechanism attempts to keep data needed by the cores (and preferably not graphics processing engines 431-432 ... N) within system memory 441 and the cores' caches 462A-462D, 456.

According to a variation shown in FIG4C , an accelerator integrated circuit 436 is integrated within the processor 407. The graphics processing engines 431-432 ... N communicate directly to the accelerator integrated circuit 436 via the high-speed link 440, via the interface 437 and the interface 435 (which again may utilize any form of bus or interface protocol). The accelerator integrated circuit 436 may perform the same operations as those described with respect to FIG4B , but given its close proximity to the coherency bus 464 and caches 462A-462D, 456, it is potentially able to perform operations at a higher throughput.

The described embodiments may support different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The latter may include a programming model controlled by the accelerator integrated circuit 436 and a programming model controlled by the graphics acceleration module 446.

In an embodiment of a dedicated process model, graphics processing engines 431, 432, ..., N can be dedicated to a single application or process under a single operating system. A single application can leak other application requests to graphics engines 431, 432, ..., N, thereby providing virtualization within a VM/partition.

In a dedicated process programming model, graphics processing engines 431, 432...N can be shared by multiple VM/application partitions. The shared model requires the hypervisor to virtualize graphics processing engines 431-432...N to allow access by each operating system. For a single partition system without a hypervisor, graphics processing engines 431-432...N are owned by the operating system. In both cases, the operating system can virtualize graphics processing engines 431-432...N to provide access to each process or application.

For the shared programming model, the graphics acceleration module 446 or the individual graphics processing engines 431-432 ... N use a process handle to select a process element. The process element may be stored in the system memory 441 and may be addressable using the effective address to real address translation techniques described herein. The process handle may be an implementation-specific value provided to the host process when registering its context with the graphics processing engine 431-432 ... N (i.e., calling the system software to add the process element to the process element linked list). The lower 16 bits of the process handle may be the offset of the process element within the process element linked list.

4D illustrates an exemplary accelerator integrated slice 490. As used herein, a "slice" includes a specified portion of the processing resources of the accelerator integrated circuit 436. The application effective address space 482 within the system memory 441 stores process elements 483. The process element 483 may be stored in response to a GPU call 481 from an application 480 executed on the processor 407. The process element 483 contains the process state of the corresponding application 480. The work descriptor (WD) 484 contained in the process element 483 may be a single job requested by the application, or may contain a pointer to a job queue. In the latter case, WD 484 is a pointer to a job request queue in the address space 482 of the application.

Graphics acceleration module 446 and/or each graphics processing engine 431-432 ... N can be shared by all processes in the system or a subset of processes in the system. For example, the technology described herein may include an infrastructure for establishing a process state and sending WD484 to graphics acceleration module 446 to start a job in a virtualized environment.

In one implementation, the dedicated process programming model is implementation specific. In this model, a single process owns the graphics acceleration module 446 or a separate graphics processing engine 431. Since the graphics acceleration module 446 is owned by a single process, when the graphics acceleration module 446 is assigned, the hypervisor initializes the accelerator integrated circuit 436 for the owning partition, and the operating system initializes the accelerator integrated circuit 436 for the owning process.

In operation, the WD acquisition unit 491 in the accelerator integrated slice 490 acquires the next WD 484, which includes an indication of the work to be completed by one of the graphics processing engines of the graphics acceleration module 446. As illustrated, data from the WD 484 may be stored in the register 445 and used by the MMU 439, the interrupt management circuit 447, and/or the context management circuit 448. For example, the MMU 439 may include a segment/page walk circuit module for accessing the segment table/page table 486 within the OS virtual address space 485. The interrupt management circuit 447 may process the interrupt event 492 received from the graphics acceleration module 446. When performing graphics operations, the effective address 493 generated by the graphics processing engine 431-432 ... N is translated into an actual address by the MMU 439.

The same register set 445 may be replicated for each graphics processing engine 431-432 ... N and/or graphics acceleration module 446 and may be initialized by a hypervisor or operating system. Each of these replicated registers may be included in an accelerator integrated slice 490. In one embodiment, each graphics processing engine 431-432 ... N may be presented to a hypervisor 496 as a different graphics processor device. QoS settings may be configured for clients of a particular graphics processing engine 431-432 ... N, and data isolation between clients of each engine may be enabled. Exemplary registers that may be initialized by a hypervisor are shown in Table 1.

Table 1 - Registers initialized by the hypervisor

Exemplary registers that may be initialized by the operating system are shown in Table 2.

Table 2 - Registers initialized by the operating system

1 Process and thread identities 2 Effective Address (EA) context save/restore pointer 3 Virtual Address (VA) Accelerator Utilizes Record Pointer 4 Virtual Address (VA) Segment Table Pointer 5 Permission Mask 6 Job Descriptor

Each WD 484 may be specific to a particular graphics acceleration module 446 and/or graphics processing engine 431-432 ... N. It contains all the information needed by the graphics processing engine 431-432 ... N to do its job, or it may be a pointer to a memory location where a command queue where an application has set up work to be done is located.

Figure 4E illustrates additional optional details of the sharing model. It includes a hypervisor real address space 498 in which a process element list 499 is stored. The hypervisor real address space 498 is accessible via a hypervisor 496, which virtualizes the graphics acceleration module engine for the operating system 495.

The shared programming model allows all processes or a subset of processes from all partitions in the system or a subset of partitions in the system to use the graphics acceleration module 446. There are two programming models in which the graphics acceleration module 446 is shared by multiple processes and partitions: time-sharing and graphics-directed sharing.

In this model, the hypervisor 496 owns the graphics acceleration module 446 and makes its functionality available to all operating systems 495. In order for the graphics acceleration module 446 to support virtualization by the hypervisor 496, the graphics acceleration module 446 may comply with the following requirements: 1) The application's job requests must be autonomous (i.e., state does not need to be maintained between jobs), or the graphics acceleration module 446 must provide a context save and restore mechanism. 2) The application's job requests are guaranteed by the graphics acceleration module 446 to complete within a specified amount of time, including any conversion errors, or the graphics acceleration module 446 provides the ability to preempt processing of jobs. 3) The graphics acceleration module 446 must be guaranteed fairness between processes when operating in a directed sharing programming model.

For the directed sharing model, the application 480 may be required to make an operating system 495 system call with a graphics acceleration module 446 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save/restore area pointer (CSRP). The graphics acceleration module 446 type describes the target acceleration function for the system call. The graphics acceleration module 446 type may be a system-specific value. The WD is formatted specifically for the graphics acceleration module 446, and the WD may take the form of a graphics acceleration module 446 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure for describing the work to be done by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state to be used for the current process. The value is passed to the operating system similar to the application setting the AMR. If the accelerator integrated circuit 436 and graphics acceleration module 446 implementation do not support the User Authority Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. The hypervisor 496 may optionally apply the current Authority Mask Override Register (AMOR) value before placing the AMR into the process element 483. The CSRP may be one of the registers 445 that contains the effective address of an area in the application's address space 482 for the graphics acceleration module 446 to use to save and restore context state. This pointer is optional if no state is required to be saved between jobs or when a job is preempted. The context save/restore area may be pinned system memory.

Upon receiving the system call, the operating system 495 may verify that the application 480 has been registered and has been given permission to use the graphics acceleration module 446. The operating system 492 then calls the hypervisor 496 with the information shown in Table 3.

Table 3 - OS call parameters to the hypervisor

Upon receiving the hypervisor call, the hypervisor 496 verifies that the operating system 495 has registered and has been given permission to use the graphics acceleration module 446. The hypervisor 496 then places the process element 483 in the process element linked list for the corresponding type of graphics acceleration module 446. The process element may include the information shown in Table 4.

Table 4 - Process element information

1 Work Descriptor (WD) 2 The authority mask register (AMR) value (potentially masked). 3 Effective Address (EA) Context Save/Restore Region Pointer (CSRP) 4 Process ID (PID) and optionally thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN) 8 Interrupt vector table, derived from the hypervisor call parameters. 9 Status register (SR) value 10 Logical partition ID (LPID) 11 Real Address (RA) Manager Accelerator Utilizes Record Pointers 12 Storage Descriptor Register (SDR)

The hypervisor may initialize registers 445 of the plurality of accelerator integrated slices 490 .

As shown in FIG. 4F , in an optional implementation, a unified memory addressable via a common virtual memory address space is employed, which is used to access physical processor memory 401-402 and GPU memory 420-423. In this implementation, operations executed on GPU 410-413 utilize the same virtual/effective memory address space to access processor memory 401-402 and vice versa, thereby simplifying programmability. A first portion of the virtual/effective address space may be allocated to processor memory 401, a second portion may be allocated to second processor memory 402, a third portion may be allocated to GPU memory 420, and so on. The entire virtual/effective memory space (sometimes referred to as an effective address space) can thus be distributed across each of processor memory 401-402 and GPU memory 420-423, thereby allowing any processor or GPU to access the physical memory using a virtual address mapped to any physical memory.

Bias/consistency management circuit modules 494A-494E within one or more of the MMUs 439A-439E may be provided that ensure cache coherence between the cache of the host processor (e.g., 405) and the cache of the GPUs 410-413 and implement biasing techniques that indicate the physical memory in which certain types of data should be stored. Although multiple instances of bias/consistency management circuit modules 494A-494E are illustrated in FIG. 4F , bias/consistency circuit modules may be implemented within the MMUs of one or more host processors 405 and/or within the accelerator integrated circuit 436.

The GPU-attached memory 420-423 can be mapped as part of the system memory and accessed using shared virtual memory (SVM) technology, but does not suffer from the typical performance defects associated with full system cache coherence. The ability of the GPU-attached memory 420-423 to be accessed as system memory without heavy cache coherence overhead provides a beneficial operating environment for GPU migration. This arrangement allows the host processor 405 to set the operation object and access the calculation results without the overhead of traditional I/O DMA data replication. Such traditional replication involves driver calls, interrupts, and memory-mapped I/O (MMIO) accesses, which are all inefficient relative to simple memory accesses. At the same time, the ability to access the GPU-attached memory 420-423 without cache coherence overhead can be critical for the execution time of the migrated calculation. For example, in the case of a large amount of streaming write memory traffic, the cache coherence overhead may significantly reduce the effective write bandwidth seen by the GPU 410-413. The efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computation all play a role in determining the effectiveness of GPU migration.

The selection between GPU bias and host processor bias may be driven by a bias tracker data structure. For example, a bias table may be used, which may be a page-granular structure (i.e., controlled at the granularity of a memory page) comprising 1 or 2 bits per GPU-attached memory page. The bias table may be implemented in a stolen memory range of one or more GPU-attached memories 420-423, with or without a bias cache in the GPUs 410-413 (e.g., for caching frequently/recently used entries of the bias table). Alternatively, the entire bias table may be maintained within the GPU.

In one implementation, the bias table entry associated with each access to the GPU-attached memory 420-423 is accessed prior to the actual access to the GPU memory, resulting in the following operations. First, local requests from the GPU 410-413 for pages that find them in the GPU bias are forwarded directly to the corresponding GPU memory 420-423. Local requests from the GPU for pages that find them in the host bias are forwarded to the processor 405 (e.g., as discussed above, over a high-speed link). Optionally, requests from the processor 405 for pages that find the requested page in the host processor bias complete the request like a normal memory read. Alternatively, requests involving pages in the GPU bias may be forwarded to the GPU 410-413. If the GPU is not currently using the page, the GPU may then convert the page to the host processor bias.

The bias state of a page may be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of situations, by a purely hardware-based mechanism.

One mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn calls the GPU's device driver, which in turn sends a message (or enqueues a command descriptor) to the GPU directing the GPU to change the bias state and perform a cache flush operation in the host for some transitions. A cache flush operation is required for a transition from host processor 405 bias to GPU bias, but not for the reverse transition.

Cache coherency may be maintained by temporarily rendering GPU-biased pages that are not cacheable by host processor 405. To access these pages, processor 405 may request access from GPU 410, which may or may not grant immediate access, depending on the implementation. Therefore, to reduce communication between host processor 405 and GPU 410, it is beneficial to ensure that GPU-biased pages are those pages that are needed by the GPU but not by host processor 405, and vice versa.

Graphics Processing Pipeline

FIG. 5 illustrates a graphics processing pipeline 500. A graphics multiprocessor (such as the graphics multiprocessor 234 in FIG. 2D, the graphics multiprocessor 325 in FIG. 3A, the graphics multiprocessor 350 in FIG. 3B) may implement the illustrated graphics processing pipeline 500. The graphics multiprocessor may be included in a parallel processing subsystem as described herein, such as the parallel processor 200 in FIG. 2A, which may be associated with the parallel processor(s) 112 in FIG. 1 and may be used in place of one of those parallel processors. Various parallel processor systems may implement the graphics processing pipeline 500 via one or more instances of a parallel processing unit (e.g., the parallel processing unit 202 in FIG. 2A) as described herein. For example, a shader unit (e.g., the graphics multiprocessor 234 in FIG. 2C) may be configured to perform the functions of one or more of the following: a vertex processing unit 504, a tessellation control processing unit 508, a tessellation evaluation processing unit 512, a geometry processing unit 516, and a fragment/pixel processing unit 524. The functions of the data assembler 502, the primitive assemblers 506, 514, 518, the tessellation unit 510, the rasterizer 522, and the raster operation unit 526 may also be performed by other processing engines and corresponding partition units (e.g., partition units 220A-220N of FIG. 2A) within a processing cluster (e.g., processing cluster 214 of FIG. 2A). The graphics processing pipeline 500 may also be implemented using dedicated processing units for one or more functions. It is also possible that one or more portions of the graphics processing pipeline 500 are executed by parallel processing logic within a general-purpose processor (e.g., a CPU). Optionally, one or more portions of the graphics processing pipeline 500 may access on-chip memory (e.g., parallel processor memory 222 in FIG. 2A) via a memory interface 528, which may be an instance of the memory interface 218 of FIG. 2A. The graphics processor pipeline 500 may also be implemented via a multi-core group 365A as in FIG. 3C.

The data assembler 502 is a processing unit that can collect vertex data for surfaces and primitives. The data assembler 502 then outputs the vertex data to the vertex processing unit 504, which includes vertex attributes. The vertex processing unit 504 is a programmable execution unit that executes the vertex shader program to illuminate and transform the vertex data as specified by the vertex shader program. The vertex processing unit 504 reads data stored in a cache, local or system memory for use in processing vertex data, and can be programmed to transform vertex data from an object-based coordinate representation to a world space coordinate space or a normalized device coordinate space.

A first instance of primitive assembler 506 receives vertex attributes from vertex processing unit 504. Primitive assembler 506 reads the stored vertex attributes as needed and builds graphics primitives for processing by tessellation control processing unit 508. Graphics primitives include triangles, line segments, points, patches, etc. as supported by various graphics processing application programming interfaces (APIs).

The tessellation control processing unit 508 treats the input vertices as control points of a geometric patch. The control points are transformed from an input representation from the patch (e.g., a basis for the patch) to a representation suitable for use in a surface evaluation performed by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 may also calculate tessellation factors for edges of the geometric patch. The tessellation factors are applied to individual edges and quantize the view-dependent level of detail associated with the edge. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and to tessellate the patch into a plurality of geometric primitives (such as line, triangle, or quadrilateral primitives), which are transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the tessellated patch to generate a surface representation and vertex attributes for each vertex associated with the geometric primitive.

The second instance of primitive assembler 514 receives vertex attributes from tessellation evaluation processing unit 512 as needed, reads the stored vertex attributes, and builds graphics primitives for processing by geometry processing unit 516. Geometry processing unit 516 is a programmable execution unit that executes geometry shader programs to transform graphics primitives received from primitive assembler 514 as specified by the geometry shader programs. Geometry processing unit 516 can be programmed to tessellate graphics primitives into one or more new graphics primitives and calculate parameters used to rasterize the new graphics primitives.

The geometry processing unit 516 may be able to add or delete elements in the geometry stream. The geometry processing unit 516 outputs parameters and vertices that specify new graphics primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and builds graphics primitives for processing by the viewport scaling, culling, and clipping unit 520. The geometry processing unit 516 reads data stored in the parallel processor memory or system memory for use in processing the geometry data. The viewport scaling, culling, and clipping unit 520 performs clipping, culling, and viewport scaling, and outputs the processed graphics primitives to the rasterizer 522.

The rasterizer 522 may perform depth culling and other depth-based optimizations. The rasterizer 522 also performs scan conversion on new graphics primitives to generate fragments and outputs those fragments and associated coverage data to the fragment/pixel processing unit 524. The fragment/pixel processing unit 524 is a programmable execution unit configured to execute a fragment shader program or a pixel shader program. The fragment/pixel processing unit 524 transforms the fragments or pixels received from the rasterizer 522 as specified by the fragment or pixel shader program. For example, the fragment/pixel processing unit 524 may be programmed to perform operations including but not limited to texture mapping, shading, blending, texture correction, and perspective correction to generate shaded fragments or pixels output to the raster operation unit 526. The fragment/pixel processing unit 524 may read data stored in a parallel processor memory or system memory for use in processing fragment data. The fragment or pixel shader program may be configured to shade at a sample, pixel, slice, or other granularity depending on the sampling rate configured for the processing unit.

The raster operation unit 526 is a processing unit that performs raster operations including, but not limited to, stenciling, z-testing, blending, etc., and outputs pixel data as processed graphics data to be stored in graphics memory (e.g., parallel processor memory 222 in FIG. 2A and/or system memory 104 in FIG. 1 ), to be displayed on one or more display devices 110A-110B, or for further processing by one of the one or more processors 102 or parallel processors 112. The raster operation unit 526 may be configured to compress z-data or color data written to memory and decompress z-data or color data read from memory.

Machine Learning Overview

The architecture described above can be applied to perform training and inference operations using machine learning models. Machine learning has been successful in solving many types of tasks. The calculations generated when training and using machine learning algorithms (e.g., neural networks) are naturally suitable for efficient parallel implementations. Accordingly, parallel processors such as general purpose graphics processing units (GPGPUs) have played an important role in the actual implementation of deep neural networks. Parallel graphics processors with single instruction multiple threads (SIMT) architectures are designed to maximize the amount of parallel processing in the graphics pipeline. In the SIMT architecture, groups of parallel threads attempt to execute program instructions together synchronously as frequently as possible to increase processing efficiency. The efficiency provided by the parallel machine learning algorithm implementation allows the use of high-capacity networks and enables those networks to be trained to larger data sets.

A machine learning algorithm is an algorithm that is capable of learning based on a set of data. For example, a machine learning algorithm can be designed to model high-level abstractions within a data set. For example, an image recognition algorithm can be used to determine which of several categories a given input belongs to; a regression algorithm can output a numerical value given an input; and a pattern recognition algorithm can be used to generate converted text or perform text-to-speech and/or speech recognition.

An exemplary type of machine learning algorithm is a neural network. There are many types of neural networks; a simple type of neural network is a feedforward network. A feedforward network can be implemented as an acyclic graph in which nodes are arranged in layers. Typically, a feedforward network topology includes an input layer and an output layer separated by at least one hidden layer. The hidden layer transforms the input received by the input layer into a representation useful for generating output in the output layer. The network nodes are fully connected to the nodes in the adjacent layers via edges, but there are no edges between the nodes within each layer. Data received at the nodes of the input layer of the feedforward network is propagated (i.e., "fed forward") to the nodes of the output layer via an activation function, which calculates the state of the nodes of each consecutive layer in the network based on coefficients ("weights") associated with each of the edges connecting these layers. Depending on the specific model being represented by the algorithm being executed, the output from the neural network algorithm can take various forms.

Before a machine learning algorithm can be used to model a particular problem, the algorithm is trained using a training data set. Training a neural network involves: selecting a network topology; using a set of training data that represents the problem being modeled by the network; and adjusting weights until the network model performs with minimal error for all instances of the training data set. For example, during a supervised learning training process for a neural network, the output generated by the network in response to an input representing an instance in the training data set is compared to the "correct" labeled output for that instance, an error signal representing the difference between the output and the labeled output is calculated, and as the error signal is propagated backward through the layers of the network, the weights associated with the connections are adjusted to minimize that error. The network is considered "trained" when the error for each of the outputs generated from the instances of the training data set is minimized.

The accuracy of a machine learning algorithm can be significantly affected by the quality of the data set used to train the algorithm. The training process can be computationally intensive and can take a significant amount of time on a conventional general-purpose processor. Accordingly, many types of machine learning algorithms are trained using parallel processing hardware. This is particularly useful for optimizing the training of neural networks, as the calculations performed when adjusting the coefficients in a neural network are naturally suited to parallel implementations. In particular, many machine learning algorithms and software applications have been adapted to exploit the parallel processing hardware within general-purpose graphics processing devices.

6 is a generalized diagram of a machine learning software stack 600. A machine learning application 602 is any logic that can be configured to train a neural network using a training data set or to implement machine intelligence using a trained deep neural network. The machine learning application 602 may include training and inference functions for the neural network and/or specialized software that can be used to train the neural network before deployment. The machine learning application 602 may implement any type of machine intelligence, including but not limited to: image recognition, map creation and positioning, autonomous navigation, speech synthesis, medical imaging, or language translation. Example machine learning applications 602 include but are not limited to voice-based virtual assistants, image or facial recognition algorithms, autonomous navigation, and software tools used to train machine learning models used by the machine learning application 602.

Hardware acceleration for machine learning applications 602 can be enabled via a machine learning framework 604. The machine learning framework 604 can provide a library of machine learning primitives. Machine learning primitives are basic operations typically performed by machine learning algorithms. Without the machine learning framework 604, developers of machine learning algorithms will be required to create and optimize the main computing logic associated with the machine learning algorithm, and then re-optimize the computing logic when developing new parallel processors. Instead, machine learning applications can be configured to use primitives provided by the machine learning framework 604 to perform necessary calculations. Exemplary primitives include tensor convolutions, activation functions, and pooling, which are computational operations performed when training convolutional neural networks (CNNs). The machine learning framework 604 can also provide primitives to implement basic linear algebra subroutines performed by many machine learning algorithms, such as matrix and vector operations. Examples of machine learning frameworks 604 include, but are not limited to, TensorFlow, TensorRT, PyTorch, MXNet, Caffee, and other advanced machine learning frameworks.

The machine learning framework 604 can process input data received from the machine learning application 602 and generate appropriate inputs to the computing framework 606. The computing framework 606 can abstract the underlying instructions provided to the GPGPU driver 608 so that the machine learning framework 604 can take advantage of hardware acceleration via the GPGPU hardware 610 without the machine learning framework 604 being very familiar with the architecture of the GPGPU hardware 610. In addition, the computing framework 606 can enable hardware acceleration for the machine learning framework 604 across various types and generations of GPGPU hardware 610. Exemplary computing frameworks 606 include CUDA computing frameworks and associated machine learning libraries, such as CUDA Deep Neural Network (cuDNN) libraries. The machine learning software stack 600 may also include a communication library or framework to facilitate multi-GPU and multi-node computing.

GPGPU machine learning acceleration

FIG7 illustrates a general purpose graphics processing unit 700, which may be the parallel processor 200 of FIG2A or the parallel processor(s) 112 of FIG1. The general purpose processing unit (GPGPU) 700 may be configured to provide support for hardware acceleration of primitives provided by a machine learning framework to accelerate processing of computational workloads of the type associated with training deep neural networks. In addition, the GPGPU 700 may be directly linked to other instances of the GPGPU to create a multi-GPU cluster, thereby improving the training speed of deep neural networks in particular. Primitives are also supported to accelerate inference operations for deployed neural networks.

GPGPU 700 includes a host interface 702 for enabling connection to a host processor. Host interface 702 may be a PCI Express interface. However, the host interface may also be a vendor-specific communication interface or communication structure. GPGPU 700 receives commands from the host processor and uses a global scheduler 704 to distribute execution threads associated with those commands to a collection of processing clusters 706A-706H. Processing clusters 706A-706H share cache memory 708. Cache memory 708 may act as a higher level cache for cache memory within processing clusters 706A-706H. The illustrated processing clusters 706A-706H may correspond to processing clusters 214A-214N as shown in FIG. 2A.

GPGPU 700 includes memory 714A-714B coupled to processing clusters 706A-706H via a set of memory controllers 712A-712B. Memories 714A-714B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. Memories 714A-714B may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM).

Each of the processing clusters 706A-706H may include a collection of graphics multiprocessors, such as the graphics multiprocessor 234 of FIG. 2D , the graphics multiprocessor 325 of FIG. 3A , the graphics multiprocessor 350 of FIG. 3B , or may include a multi-core group 365A-365N as in FIG. 3C . The graphics multiprocessors of the computing clusters include multiple types of integer and floating point logic units capable of performing computational operations with a range of precisions including those suitable for machine learning computations. For example, at least a subset of the floating point units in each of the processing clusters 706A-706H may be configured to perform 16-bit or 32-bit floating point operations, while a different subset of the floating point units may be configured to perform 64-bit floating point operations.

Multiple instances of GPGPU 700 can be configured to operate as a computing cluster. The communication mechanism used by the computing cluster for synchronization and data exchange varies across embodiments. For example, multiple instances of GPGPU 700 communicate through a host interface 702. In one embodiment, GPGPU 700 includes an I/O hub 709 that couples GPGPU 710 with a GPU link 710 that enables direct connection to other instances of GPGPU. GPU link 710 may be coupled to a dedicated GPU to GPU bridge that enables communication and synchronization between multiple instances of GPGPU 700. Optionally, GPU link 710 is coupled to a high-speed interconnect to transmit data to and receive data from other GPGPUs or parallel processors. Multiple instances of GPGPU 700 may be located in separate data processing systems and may communicate via a network device that may be accessed via host interface 702. In addition to or in lieu of host interface 702 , GPU link 710 may be configured to enable connection to a host processor.

Although the illustrated configuration of GPGPU 700 may be configured for training neural networks, alternative configurations of GPGPU 700 may be configured for deployment within a high-performance or low-power inference platform. In the inference configuration, relative to the training configuration, GPGPU 700 includes fewer processing clusters in processing clusters 706A-706H. In addition, the memory technology associated with memory 714A-714B may differ between the inference configuration and the training configuration. In one embodiment, the inference configuration of GPGPU 700 may support inference specific instructions. For example, the inference configuration may provide support for one or more 8-bit integer or floating point dot product instructions, which are typically used during inference operations for deployed neural networks.

FIG8 illustrates a multi-GPU computing system 800. The multi-GPU computing system 800 may include a processor 802 coupled to a plurality of GPGPUs 806A-806D via a host interface switch 804. The host interface switch 804 may be a PCI Express switch device that couples the processor 802 to a PCI Express bus, over which the processor 802 can communicate with a collection of GPGPUs 806A-806D. Each of the plurality of GPGPUs 806A-806D may be an instance of the GPGPU 700 of FIG7 . The GPGPUs 806A-806D may be interconnected via a collection of high-speed point-to-point GPU-to-GPU links 816. The high-speed GPU-to-GPU links may be connected to each of the GPGPUs 806A-806D via a dedicated GPU link, such as the GPU link 710 of FIG7 . P2P GPU link 816 enables direct communication between each of GPGPUs 806A-806D without requiring communication through a host interface bus to which processor 802 is connected. With GPU-to-GPU traffic directed to the P2P GPU link, the host interface bus remains available for system memory access, or for communicating with other instances of multi-GPU computing system 800, for example, via one or more network devices. Although GPGPUs 806A-806D are connected to processor 802 via host interface switch 804 in FIG. 8 , processor 802 may alternatively include direct support for P2P GPU link 816 and connect directly to GPGPUs 806A-806D. In one embodiment, P2P GPU link 816 enables multi-GPU computing system 800 to operate as a single logical GPU.

Machine Learning Neural Network Implementation

The computing architecture described herein can be configured to perform a type of parallel processing that is particularly suitable for training and deploying neural networks for machine learning. A neural network can be generalized as a network of functions with a graph relationship. As is known in the art, there are various types of neural network implementations used in machine learning. One exemplary type of neural network is a feedforward network as previously described.

The second exemplary type of neural network is a convolutional neural network (CNN). A CNN is a specialized feedforward neural network for processing data (such as image data) with a known, grid-like topology. Accordingly, CNNs are commonly used in computer vision and image recognition applications, but they can also be used for other types of pattern recognition, such as speech and language processing. The nodes in the input layer of a CNN are organized as a set of "filters" (feature detectors inspired by the receptive fields found in the retina), and the output of each filter set is propagated to the nodes in the successive layers of the network. The calculations used for a CNN include applying a convolution mathematical operation to each filter to produce the output of the filter. Convolution is a specialized type of mathematical operation performed by two functions to produce a third function, which is a modified version of one of the two original functions. In convolutional network terminology, the first function to the convolution may be referred to as the input, and the second function may be referred to as the convolution kernel. The output may be referred to as a feature map. For example, the input to a convolutional layer may be a multidimensional data array defining the various color components of the input image. The convolution kernel may be a multidimensional parameter array, where the parameters are adapted by a training process for the neural network.

A recurrent neural network (RNN) is a series of feedforward neural networks that include feedback connections between layers. RNNs enable modeling of sequential data by sharing parameter data across different parts of the neural network. The architecture for RNNs includes loops. These loops represent the effect of the current value of a variable on its own value at future moments, because at least part of the output data from the RNN is used as feedback for processing subsequent inputs in the sequence. This feature makes RNNs particularly useful for language processing due to the mutable nature of language data that can be composed.

The figures described below present exemplary feedforward networks, CNN networks, and RNN networks, and describe the general process for training and deploying each of those types of networks, respectively. It will be understood that these descriptions are exemplary and non-limiting with respect to any specific embodiments described herein, and that the concepts illustrated are generally applicable to deep neural networks and machine learning techniques in general.

The exemplary neural network described above can be used to perform deep learning. Deep learning is machine learning using deep neural networks. Unlike shallow neural networks that include only a single hidden layer, the deep neural networks used in deep learning are artificial neural networks composed of multiple hidden layers. Deeper neural networks are generally more computationally intensive to train. However, the additional hidden layers of the network enable multi-step pattern recognition that results in reduced output errors relative to shallow machine learning techniques.

The deep neural network used in deep learning typically includes a front-end network for performing feature recognition, which is coupled to a back-end network that represents a mathematical model that can perform operations (e.g., object classification, speech recognition, etc.) based on the feature representation provided to the mathematical model. Deep learning enables machine learning to be performed without the need to perform manual feature engineering for the model. In contrast, deep neural networks can learn features based on statistical structures or correlations within the input data. The learned features can be provided to a mathematical model that can map the detected features to an output. The mathematical model used by the network is typically dedicated to a specific task to be performed, and different models will be used to perform different tasks.

Once the neural network is structured, a learning model can be applied to the network to train the network to perform a specific task. The learning model describes how to adjust the weights within the model to reduce the output error of the network. Back propagation of errors is a common method for training neural networks. An input vector is presented to the network for processing. The output of the network is compared to the desired output using a loss function, and an error value is calculated for each neuron in the output layer. Subsequently, the error values are propagated backward until each neuron has an associated error value that roughly represents the contribution of the neuron to the original output. The network can then learn from those errors using an algorithm (such as a stochastic gradient descent algorithm) to update the weights of the neural network.

9A-9B illustrate an exemplary convolutional neural network. FIG. 9A illustrates the various layers within a CNN. As shown in FIG. 9A , an exemplary CNN for modeling image processing may receive an input 902 describing the red, green, and blue (RGB) components of an input image. The input 902 may be processed by a plurality of convolutional layers (e.g., convolutional layer 904, convolutional layer 906). The outputs from a plurality of convolutional layers may optionally be processed by a collection of fully connected layers 908. As previously described for feedforward networks, neurons in a fully connected layer have full connections to all activations in the previous layer. The outputs from the fully connected layer 908 may be used to generate output results from the network. Matrix multiplication may be used instead of convolution to calculate activations within the fully connected layer 908. Not all CNN implementations utilize a fully connected layer 908. For example, in some implementations, a convolutional layer 906 may generate the output of a CNN.

The convolutional layers are sparsely connected, which is different from the traditional neural network configuration found in the fully connected layer 908. Traditional neural network layers are fully connected so that each output unit interacts with each input unit. However, as illustrated, the convolutional layers are sparsely connected because the output of the convolution of the receptive field (rather than the corresponding state value of each node in the receptive field) is input to the nodes of the subsequent layer. The kernel associated with the convolutional layer performs a convolution operation, the output of which is sent to the next layer. The dimensionality reduction performed within the convolutional layer is one aspect that enables CNNs to scale to process large images.

9B illustrates an exemplary computational stage within a convolutional layer of a CNN. An input 912 to a convolutional layer of a CNN may be processed in three stages of a convolutional layer 914. The three stages may include a convolution stage 916, a detector stage 918, and a pooling stage 920. The convolutional layer 914 may then output data to a successive convolutional layer. The final convolutional layer of the network may generate output feature map data or provide input to a fully connected layer, for example to generate a classification value for input to a CNN.

Several convolutions are performed in parallel in the convolution stage 916 to produce a set of linear activations. The convolution stage 916 may include an affine transformation, which is any transformation that can be specified as a linear transformation plus a translation. Affine transformations include rotations, translations, scaling, and combinations of these transformations. The convolution stage calculates the output of a function (e.g., a neuron) connected to specific regions in the input, which can be determined as local regions associated with the neuron. The neuron calculates the dot product between the weight of the neuron and the weight of the region in the local input to which the neuron is connected. The output from the convolution stage 916 defines a set of linear activations processed by successive stages of the convolution layer 914.

The linear activations may be processed by the detector stage 918. In the detector stage 918, each linear activation is processed by a nonlinear activation function. The nonlinear activation function increases the nonlinear nature of the overall network without affecting the receptive field of the convolutional layer. Several types of nonlinear activation functions may be used. One particular type is the rectified linear unit (ReLU), which uses an activation function defined as f(x) = max(0, x) so that the threshold of the activation is zero.

The pooling stage 920 uses a pooling function that replaces the output of the convolutional layer 906 with summary statistics of nearby outputs. The pooling function can be used to introduce translation invariance into the neural network so that a small translation to the input does not change the pooled output. The invariance of local translation can be useful in scenarios where the presence of features in the input data is more important than the precise location of the features. Various types of pooling functions can be used during the pooling stage 920, including maximum pooling, average pooling, and l2 norm pooling. In addition, some CNN implementations do not include a pooling stage. Instead, such implementations are alternative and additional convolution stages with an increased span relative to the previous convolution stage.

The output from the convolutional layer 914 may then be processed by the next layer 922. The next layer 922 may be an additional convolutional layer or a layer in the fully connected layer 908. For example, the first convolutional layer 904 of FIG. 9A may output to the second convolutional layer 906, and the second convolutional layer may output to the first layer in the fully connected layer 908.

FIG. 10 illustrates an exemplary recurrent neural network 1000. In a recurrent neural network (RNN), the previous state of the network affects the output of the current state of the network. RNNs can be established in various ways and using various functions. The use of RNNs generally revolves around using mathematical models to predict the future based on previous sequences of inputs. For example, RNNs can be used to perform statistical language modeling to predict upcoming words given previous sequences of words. The illustrated RNN 1000 can be described as having an input layer 1002 that receives an input vector, a hidden layer 1004 for implementing a recurrent function, a feedback mechanism 1005 for enabling 'memory' of previous states, and an output layer 1006 for outputting results. RNN 1000 operates based on time steps. The state of the RNN at a given time step is affected via a feedback mechanism 1005 based on previous time steps. For a given time step, the state of the hidden layer 1004 is defined by the previous state and the input at the current time step. The initial input (x1) at the first time step can be processed by the hidden layer 1004. The second input (x2) may be processed by the hidden layer 1004 using state information determined during processing of the initial input (x1). A given state may be calculated as s _t =f(Ux _t +Ws _t-1 ), where U and W are parameter matrices. The function f is generally nonlinear, such as a variant of the hyperbolic tangent function (Tanh) or a modified function f(x)=max(0,x). However, the specific mathematical function used in the hidden layer 1004 may vary depending on the specific implementation details of the RNN 1000.

In addition to the basic CNN and RNN networks described, acceleration for variants of those networks can also be enabled. An example RNN variant is a long short term memory (LSTM) RNN. LSTM RNN is able to learn long-term dependencies, which may be necessary for processing longer language sequences. A variant of CNN is a convolutional deep belief network, which has a similar structure to CNN and is trained in a similar manner to a deep belief network. A deep belief network (DBN) is a generative neural network consisting of multiple layers of stochastic (random) variables. DBN can be trained layer by layer using greedy unsupervised learning. The learned weights of the DBN can then be used to provide a pre-trained neural network by determining the optimal initial set of weights for the neural network. In a further embodiment, acceleration for reinforcement learning is enabled. In reinforcement learning, an artificial agent learns by interacting with its environment. The agent is configured to optimize certain goals to maximize cumulative returns.

FIG11 illustrates the training and deployment of a deep neural network. Once a given network has been structured for a task, the neural network is trained using a training data set 1102. Various training frameworks 1104 have been developed to enable hardware acceleration of the training process. For example, the machine learning framework 604 of FIG6 can be configured as a training framework 1104. The training framework 1104 can access an untrained neural network 1106 and enable the untrained neural network to be trained using the parallel processing resources described herein to generate a trained neural network 1108.

To start the training process, weights can be randomly selected or initial weights can be selected by pre-training using a deep belief network. Subsequently, a training cycle is performed in a supervised or unsupervised manner.

Supervised learning is a learning method in which training is performed as a mediated operation, such as when the training data set 1102 includes an input paired with an expected output of the input, or when the training data set includes an input with a known output and the output of the neural network is manually graded. The network processes the input and compares the resulting output with the expected output or a set of expected outputs. Subsequently, the error is propagated back through the system. The training framework 1104 can be adjusted to adjust the weights that control the untrained neural network 1106. The training framework 1104 can provide tools to monitor how well the untrained neural network 1106 is converging to a model suitable for generating the correct answer based on the known input data. The training process occurs repeatedly as the weights of the network are adjusted to refine the output generated by the neural network. The training process can continue until the neural network reaches a statistically expected accuracy associated with the trained neural network 1108. The trained neural network 1108 can then be deployed to implement any number of machine learning operations to generate inference results 1114 based on the input of new data 1112.

Unsupervised learning is a learning method in which a network attempts to train itself using unlabeled data. Thus, for unsupervised learning, the training data set 1102 will include input data that does not have any associated output data. The untrained neural network 1106 can learn groupings within the unlabeled inputs and can determine how the individual inputs are related to the entire data set. Unsupervised training can be used to generate a self-organizing map, which is a class of trained neural networks 1108 that can perform operations useful in reducing the dimensionality of the data. Unsupervised training can also be used to perform anomaly detection, which allows identification of data points in the input data set that deviate from the normal pattern of the data.

Variations of supervised and unsupervised training may also be employed. Semi-supervised learning is a technique in which a mixture of labeled and unlabeled data having the same distribution is included in the training data set 1102. Incremental learning is a variation of supervised learning in which input data is used continuously to further train the model. Incremental learning enables a trained neural network 1108 to adapt to new data 1112 without forgetting the knowledge embedded in the network during initial training.

Whether supervised or unsupervised, the training process for particularly deep neural networks may be too computationally intensive for a single computing node. The training process can be accelerated using a distributed network of computing nodes rather than using a single computing node.

FIG12A is a block diagram illustrating distributed learning. Distributed learning is a training model that uses multiple distributed computing nodes to perform supervised or unsupervised training of a neural network. The distributed computing nodes may each include one or more host processors or one or more general-purpose processing nodes in a general-purpose processing node, such as the highly parallel general-purpose graphics processing unit 700 in FIG7. As illustrated, distributed learning can be performed with model parallelism 1202, data parallelism 1204, or a combination of model and data parallelism 1206.

In model parallelism 1202, different computing nodes in a distributed system can perform training computations for different parts of a single network. For example, each layer of a neural network can be trained by a different processing node of the distributed system. Benefits of model parallelism include the ability to scale to particularly large models. Splitting the computations associated with different layers of a neural network enables training of very large neural networks where the weights of all layers would not fit into the memory of a single node. In some instances, model parallelism can be particularly useful when performing unsupervised training of large neural networks.

In data parallelism 1204, different nodes of the distributed network have complete instances of the model, and each node receives a different portion of the data. The results from different nodes are then combined. Although different ways to implement data parallelism are possible, all data parallel training methods require techniques to combine the results and synchronize the model parameters between each node. Exemplary methods for combining data include parameter averaging and update-based data parallelism. Parameter averaging trains each node on a subset of the training data, and sets global parameters (e.g., weights, biases) to the average value of the parameters from each node. Parameter averaging uses a central parameter server that maintains parameter data. Update-based data parallelism is similar to parameter averaging, with the exception that updates to the model are transmitted instead of transmitting parameters from the node to the parameter server. In addition, update-based data parallelism can be performed in a decentralized manner, where updates are compressed and transmitted between nodes.

Combined model and data parallelism 1206 can be implemented, for example, in a distributed system where each computing node includes multiple GPUs. Each node can have a complete instance of the model, where separate GPUs within each node are used to train different parts of the model.

Distributed training has increased overhead relative to training on a single machine. However, the parallel processors and GPGPUs described herein can each implement various techniques to reduce the overhead of distributed training, including techniques for enabling high-bandwidth GPU-to-GPU data transfer and accelerated remote data synchronization.

12B is a block diagram illustrating a programmable network interface 1210 and a data processing unit. The programmable network interface 1210 is a programmable network engine that can be used to accelerate network-based computing tasks within a distributed environment. The programmable network interface 1210 can be coupled to a host system via a host interface 1270. The programmable network interface 1210 can be used to accelerate network or storage operations for a CPU or GPU of a host system. The host system can be, for example, a node of a distributed learning system for performing distributed training, for example, as shown in FIG. 12A. The host system can also be a data center node within a data center.

In one embodiment, access to a remote storage device containing model data may be accelerated by the programmable network interface 1210. For example, the programmable network interface 1210 may be configured to present the remote storage device as a local storage device of the host system. The programmable network interface 1210 may also accelerate remote direct memory access (RDMA) operations performed between a GPU of the host system and a GPU of the remote system. In one embodiment, the programmable network interface 1210 may enable storage functions such as, but not limited to, NVME-oF. The programmable network interface 1210 may also accelerate encryption, data integrity, compression, and other operations for the remote storage device on behalf of the host system, thereby allowing the remote storage device to approach the latency of a storage device directly attached to the host system.

The programmable network interface 1210 may also perform resource allocation and management on behalf of the host system. Storage security operations may be migrated to the programmable network interface 1210 and performed in coordination with the allocation and management of remote storage resources. Network-based operations for managing access to remote storage devices that would otherwise be performed by the host system's processor may be performed instead by the programmable network interface 1210.

In one embodiment, network and/or data security operations may be migrated from the host system to the programmable network interface 1210. Data center security policies for data center nodes may be handled by the programmable network interface 1210 rather than by the processor of the host system. For example, the programmable network interface 1210 may detect and mitigate attempted network-based attacks (e.g., DDoS) on the host system, thereby preventing the attack from compromising the availability of the host system.

The programmable network interface 1210 may include a system on chip (SoC 1220) that executes an operating system via multiple processor cores 1222. The processor core 1222 may include a general-purpose processor (e.g., CPU) core. In one embodiment, the processor core 1222 may also include one or more GPU cores. The SoC 1220 may execute instructions stored in a memory device 1240. The storage device 1250 may store local operating system data. The storage device 1250 and the memory device 1240 may also be used to cache remote data for a host system. The network ports 1260A-1260B enable connection to a network or structure and facilitate network access for the SoC 1220 and facilitate network access for the host system via the host interface 1270. The programmable network interface 1210 may also include an I/O interface 1275, such as a USB interface. The I/O interface 1275 may be used to couple an external device to the programmable network interface 1210 or to couple as a debug interface. Programmable network interface 1210 also includes a management interface 1230 that enables software on a host device to manage and configure programmable network interface 1210 and/or SoC 1220. In one embodiment, programmable network interface 1210 may also include one or more accelerators or GPUs 1245 to accept migration of parallel computing tasks from SoC 1220, a host system, or a remote system coupled via network ports 1260A-1260B.

Example Machine Learning Applications

Machine learning can be applied to solve various technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. The application range of computer vision is from reproducing human visual capabilities (such as recognizing faces) to creating new categories of visual capabilities. For example, computer vision applications can be configured to identify sound waves from vibrations induced in objects visible in a video. Parallel processor-accelerated machine learning enables computer vision applications to be trained using significantly larger training data sets than previously feasible training data sets, and enables inference systems to be deployed using low-power parallel processors.

Parallel processor-accelerated machine learning has autonomous driving applications, including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train driving models based on data sets that define appropriate responses to specific training inputs. The parallel processors described in this article enable rapid training of increasingly complex neural networks for autonomous driving solutions and enable the deployment of low-power inference processors in mobile platforms suitable for integration into autonomous vehicles.

Deep neural networks accelerated by parallel processors have enabled machine learning approaches for automatic speech recognition (ASR). ASR involves creating a function that computes the most likely speech sequence given a sequence of input sounds. Accelerated machine learning using deep neural networks has enabled replacements for the hidden Markov models (HMM) and Gaussian mixture models (GMM) previously used for ASR.

Parallel processor accelerated machine learning can also be used to accelerate natural language processing. The automatic learning process can utilize statistical inference algorithms to produce models that are robust to erroneous or unfamiliar inputs. Exemplary natural language processor applications include automatic machine translation between human languages.

The parallel processing platform for machine learning can be divided into a training platform and a deployment platform. The training platform is generally highly parallel and includes optimizations for accelerating multi-GPU single-node training and multi-node multi-GPU training. Exemplary parallel processors suitable for training include the general-purpose graphics processing unit 700 of Figure 7 and the multi-GPU computing system 800 of Figure 8. In contrast, the deployed machine learning platform generally includes a lower-power parallel processor suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

In addition, machine learning techniques can also be applied to accelerate or enhance graphics processing activities. For example, a machine learning model can be trained to recognize output generated by a GPU-accelerated application and generate an amplified version of the output. Such techniques can be applied to accelerate the generation of high-resolution images for gaming applications. Various other graphics pipeline activities can benefit from the use of machine learning. For example, a machine learning model can be trained to perform tessellation operations on geometric data to increase the complexity of the geometric model, thereby allowing more detailed geometry to be automatically generated from relatively low-detail geometry.

FIG. 13 illustrates an exemplary inference system-on-chip (SOC) 1300 suitable for performing inference using a trained model. SOC 1300 may integrate processing components, including a media processor 1302, a visual processor 1304, a GPGPU 1306, and a multi-core processor 1308. GPGPU 1306 may be a GPGPU described herein, such as GPGPU 700, and multi-core processor 1308 may be a multi-core processor described herein, such as multi-core processors 405-406. SOC 1300 may additionally include on-chip memory 1305, which may enable a shared on-chip data pool that can be accessed by each of the processing components. The processing components may be optimized for low-power operation to enable deployment of various machine learning platforms including autonomous vehicles and autonomous robots. For example, an implementation of SOC 1300 may be used as part of a master control system for an autonomous vehicle. Where the SOC 1300 is configured for use in an autonomous vehicle, the SOC is designed and configured to comply with relevant functional safety standards of the deployment jurisdiction.

During operation, the media processor 1302 and the visual processor 1304 can work in tandem to accelerate computer vision operations. The media processor 1302 can enable low latency decoding of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video streams can be written to a buffer in the on-chip memory 1305. The visual processor 1304 can then parse the decoded video and perform preliminary processing operations on the frames of the decoded video to prepare for processing the frames using a trained image recognition model. For example, the visual processor 1304 can accelerate convolution operations for a CNN that is used to perform image recognition on high-resolution video data, while the back-end model calculations are performed by the GPGPU 1306.

The multi-core processor 1308 may include control logic for assisting in sequencing and synchronizing data transfers and shared memory operations performed by the media processor 1302 and the vision processor 1304. The multi-core processor 1308 may also act as an application processor for executing software applications that can utilize the inference computing capabilities of the GPGPU 1306. For example, at least a portion of navigation and steering logic may be implemented in software executing on the multi-core processor 1308. Such software may issue computational workloads directly to the GPGPU 1306, or computational workloads may be issued to the multi-core processor 1308, which may migrate at least a portion of those operations to the GPGPU 1306.

GPGPU 1306 may include a computing cluster, such as low-power configuration processing clusters 706A-706H within general purpose graphics processing unit 700. The computing cluster within GPGPU 1306 may support instructions specifically optimized to perform inference calculations on trained neural networks. For example, GPGPU 1306 may support instructions for performing low-precision calculations such as 8-bit and 4-bit integer vector operations.

Additional System Overview

FIG. 14 is a block diagram of a processing system 1400. Elements of FIG. 14 with the same or similar names as elements of any other figures herein describe the same elements as in the other figures, can operate or run in a similar manner as in the other figures, can include the same components, and can be linked to other entities, such as those described elsewhere in this document, but not limited thereto. System 1400 can be used in the following: a single-processor desktop computer system, a multi-processor workstation system, or a server system with a large number of processors 1402 or processor cores 1407. System 1400 can be a processing platform incorporated into a system-on-chip (SoC) integrated circuit for use in a mobile device, a handheld device, or an embedded device, such as for use in an Internet-of-things (IoT) device with wired or wireless connectivity to a local area network or a wide area network.

System 1400 may be a processing system having components corresponding to those of Figure 1. For example, in different configurations, processor(s) 1402 or processor core(s) 1407 may correspond to processor(s) 102 of Figure 1. Graphics processor(s) 1408 may correspond to parallel processor(s) 112 of Figure 1. External graphics processor 1418 may be one of plug-in device(s) 120 of Figure 1.

The system 1400 may include, be coupled with, or be integrated into: a server-based gaming platform; a gaming console, including gaming and media consoles; a mobile gaming console, a handheld gaming console, or an online gaming console. The system 1400 may be part of a mobile phone, a smart phone, a tablet computing device, or a mobile internet-connected device, such as a laptop with low internal storage capacity. The processing system 1400 may also include, be coupled with, or be integrated into: a wearable device, such as a smart watch wearable device; smart glasses or clothing that is enhanced with augmented reality (AR) or virtual reality (VR) features to provide visual, audio, or tactile output to supplement the real-world visual, audio, or tactile experience or otherwise provide text, audio, graphics, video, holographic images or video, or tactile feedback; other augmented reality (AR) devices; or other virtual reality (VR) devices. The processing system 1400 may include, or may be part of a television or set-top box device. System 1400 may include, be coupled to, or be integrated within an autonomous vehicle, such as a bus, a tractor trailer, an automobile, an electric or electrical cycle, an airplane, or a glider (or any combination thereof). An autonomous vehicle may use system 1400 to process the environment sensed around the vehicle.

The one or more processors 1402 may include one or more processor cores 1407 for processing instructions that, when executed, perform operations for system and user software. At least one of the one or more processor cores 1407 may be configured to process a specific instruction set 1409. The instruction set 1409 may facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). The one or more processor cores 1407 may process different instruction sets 1409, which may include instructions for facilitating emulation of other instruction sets. The processor core 1407 may also include other processing devices, such as a digital signal processor (DSP).

The processor 1402 may include a cache memory 1404. Depending on the architecture, the processor 1402 may have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared between various components of the processor 1402. In some embodiments, the processor 1402 also uses an external cache (e.g., a third level (L3) cache or a last level cache (Last Level Cache, LLC)) (not shown), which can be shared between the processor cores 1407 using known cache coherence techniques. A register file 1406 may be additionally included in the processor 1402 and may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. Some registers may be general purpose registers, while other registers may be specific to the design of the processor 1402.

One or more processors 1402 may be coupled to one or more interface buses 1410 to transmit communication signals, such as address, data, or control signals, between the processor 1402 and other components in the system 1400. In one of these embodiments, the interface bus 1410 may be a processor bus, such as a version of a Direct Media Interface (DMI) bus. However, the processor bus is not limited to a DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. For example, the processor(s) 1402 may include an integrated memory controller 1416 and a platform controller hub 1430. The memory controller 1416 facilitates communication between memory devices and other components of the system 1400, while the platform controller hub (PCH) 1430 provides connections to I/O devices via a local I/O bus.

The memory device 1420 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device having suitable performance to act as a process memory. The memory device 1420 may, for example, operate as a system memory for the system 1400 to store data 1422 and instructions 1421 for use when one or more processors 1402 execute applications or processes. The memory controller 1416 is also coupled to an optional external graphics processor 1418, which may communicate with one or more graphics processors 1408 in the processor 1402 to perform graphics operations and media operations. In some embodiments, graphics operations, media operations, and/or computing operations may be assisted by an accelerator 1412, which is a coprocessor that may be configured to perform a collection of specialized graphics operations, media operations, or computing operations. For example, the accelerator 1412 may be a matrix multiplication accelerator for optimizing machine learning or computing operations. The accelerator 1412 may be a ray tracing accelerator that may be used to perform ray tracing operations in coordination with the graphics processor 1408. In one embodiment, an external accelerator 1419 may be used instead of the accelerator 1412 or in coordination with the accelerator 1412.

A display device 1411 may be provided and may be connected to the processor(s) 1402. The display device 1411 may be one or more of an internal display device, such as in a mobile electronic device or laptop device, or an external display device attached via a display interface (e.g., a display port, etc.). The display device 1411 may be a head mounted display (HMD), such as a stereoscopic display device for use in virtual reality (VR) applications or augmented reality (AR) applications.

The platform controller hub 1430 can enable peripheral devices to be connected to the memory device 1420 and the processor 1402 via a high-speed I/O bus. The I/O peripherals include, but are not limited to, an audio controller 1446, a network controller 1434, a firmware interface 1428, a wireless transceiver 1426, a touch sensor 1425, a data storage device 1424 (e.g., non-volatile memory, volatile memory, hard drive, flash memory, NAND, 3D NAND, 3D Xpoint/Optane, etc.). The data storage device 1424 can be connected via a storage interface (e.g., SATA) or via a peripheral bus (e.g., PCI, PCI Express). The touch sensor 1425 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. The wireless transceiver 1426 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, 5G, or Long-Term Evolution (LTE) transceiver. The firmware interface 1428 enables communication with the system firmware and can be, for example, a unified extensible firmware interface (UEFI). The network controller 1434 can enable network connection to a wired network. In some embodiments, a high-performance network controller (not shown) is coupled to the interface bus 1410. The audio controller 1446 can be a multi-channel high-definition audio controller. In some of these embodiments, the system 1400 includes an optional traditional I/O controller 1440 for coupling traditional (e.g., Personal System 2 (PS/2)) devices to the system. The platform controller hub 1430 can also be connected to one or more Universal Serial Bus (USB) controllers 1442 to connect to input devices, such as a keyboard and mouse 1443 combination, a camera 1444, or other USB input devices.

It will be appreciated that the illustrated system 1400 is exemplary and not limiting, as other types of data processing systems configured in different manners may also be used. For example, instances of the memory controller 1416 and the platform controller hub 1430 may be integrated into a discrete external graphics processor, such as the external graphics processor 1418. The platform controller hub 1430 and/or the memory controller 1416 may be external to the one or more processors 1402. For example, the system 1400 may include the external memory controller 1416 and the platform controller hub 1430, which may be configured as a memory controller hub and a peripheral controller hub within a system chipset that communicates with the processor(s) 1402.

For example, a circuit board ("sled") may be used on which components (such as CPUs, memory and other components) are placed and on which components (such as CPUs, memory and other components) are designed to achieve improved thermal performance. Processing components such as processors may be located on the top side of the sled, while nearby memory such as DIMMs are located on the bottom side of the sled. As a result of the enhanced airflow provided by the design, components can operate at higher frequencies and power levels than in typical systems, thereby improving performance. In addition, the sled is configured to blindly mate power and data communication cables in a rack, thereby enhancing their ability to be quickly removed, upgraded, reinstalled and/or replaced. Similarly, the various components (such as processors, accelerators, memory and data storage drives) located on the sled are configured to be easily upgraded due to their increased spacing from each other. In an illustrative embodiment, the components additionally include hardware authentication features for proving their authenticity.

The data center may utilize a single network architecture ("fabric") that supports multiple other network architectures, including Ethernet and omni-path. The sleds may be coupled to the switches via optical fiber, which provides higher bandwidth and lower latency than typical twisted pair cabling (e.g., Category 5, Category 5e, Category 6, etc.). Due to the high-bandwidth, low-latency interconnect and network architecture, the data center may, in use, centralize physically dispersed resources such as memory, accelerators (e.g., GPUs, graphics accelerators, FPGAs, ASICs, neural network and/or artificial intelligence accelerators, etc.), and data storage drives, and provide them to computing resources (e.g., processors) as needed, thereby enabling the computing resources to access these centralized resources as if the centralized resources were local.

A power supply or power source can provide voltage and/or current to the system 1400 or any component or system described herein. In one example, the power supply includes an AC to DC (alternating current to direct current) adapter that plugs into a wall socket. Such AC power can be a renewable energy (e.g., solar) power source. In one example, the power source includes a DC power source, such as an external AC to DC converter. The power source or power supply can also include wireless charging hardware for charging by approaching a charging field. The power source can include an internal battery, an AC supply, a motion-based power supply, a solar power supply, or a fuel cell source.

Figures 15A-15C illustrate a computing system and a graphics processor. Elements of Figures 15A-15C having the same or similar names as elements of any other figure herein describe the same elements as in the other figures, can operate or function in a similar manner as in the other figures, can include the same components, and can be linked to other entities such as, but not limited to, those described elsewhere herein.

FIG. 15A is a block diagram of a processor 1500, which may be a variant of one of the processors 1402 and may be used in place of one of those processors. Thus, the disclosure of any feature herein in conjunction with the processor 1500 also discloses the corresponding combination with (one or more) processors 1402, but is not limited thereto. The processor 1500 may have one or more processor cores 1502A-1502N, an integrated memory controller 1514, and an integrated graphics processor 1508. In the case where the integrated graphics processor 1508 is excluded, a system including the processor will include a graphics processor device within a system chipset or coupled via a system bus. The processor 1500 may include additional cores, up to and including additional cores 1502N represented by dashed boxes. Each of the processor cores 1502A-1502N includes one or more internal cache units 1504A-1504N. In some embodiments, each processor core 1502A-1502N also has access to one or more shared cache units 1506. The internal cache units 1504A-1504N and the shared cache units 1506 represent a cache memory hierarchy within the processor 1500. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as a second level (L2), third level (L3), fourth level (L4), or other level of cache, where the highest level of cache before external memory is classified as LLC. In some embodiments, cache coherency logic maintains coherency between each cache unit 1506 and 1504A-1504N.

The processor 1500 may also include a set of one or more bus controller units 1516 and a system agent core 1510. The one or more bus controller units 1516 manage a set of peripheral buses, such as one or more PCI buses or PCI Express buses. The system agent core 1510 provides management functions for various processor components. The system agent core 1510 may include one or more integrated memory controllers 1514 for managing access to various external memory devices (not shown).

For example, one or more of the processor cores 1502A-1502N may include support for simultaneous multithreaded operations. The system agent core 1510 includes components for coordinating and operating the cores 1502A-1502N during multithreaded processing. The system agent core 1510 may additionally include a power control unit (PCU) that includes logic and components for regulating the power state of the processor cores 1502A-1502N and the graphics processor 1508.

The processor 1500 may additionally include a graphics processor 1508 for performing graphics processing operations. In some of these embodiments, the graphics processor 1508 is coupled to a set of shared cache units 1506 and a system agent core 1510, which includes one or more integrated memory controllers 1514. The system agent core 1510 may also include a display controller 1511 for driving the graphics processor output to one or more coupled displays. The display controller 1511 may also be a separate module coupled to the graphics processor via at least one interconnect, or may be integrated within the graphics processor 1508.

A ring-based interconnect 1512 may be used to couple internal components of the processor 1500. However, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other technologies, including those known in the art. In some of these embodiments with a ring-based interconnect 1512, the graphics processor 1508 is coupled to the ring-based interconnect 1512 via an I/O link 1513.

Exemplary I/O link 1513 represents at least one of a plurality of various I/O interconnects, including an on-package I/O interconnect that facilitates communication between various processor components and a high-performance memory module 1518, such as an eDRAM module or a high-bandwidth memory (HMB) module. Optionally, each of processor cores 1502A-1502N and graphics processor 1508 may use high-performance memory module 1518 as a shared last-level cache.

The processor cores 1502A-1502N may be, for example, isomorphic cores that execute the same instruction set architecture. Alternatively, the processor cores 1502A-1502N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more of the processor cores 1502A-1502N execute a first instruction set and at least one of the other cores executes a subset of the first instruction set or a different instruction set. The processor cores 1502A-1502N may be heterogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. As another example, the processor cores 1502A-1502N are heterogeneous in terms of computing power. In addition, the processor 1500 may be implemented on one or more chips, or as a SoC integrated circuit having the illustrated components in addition to other components.

Figure 15B is a block diagram of the hardware logic of a graphics processor core block 1519 according to some embodiments described herein. In some embodiments, the elements of Figure 15B having the same reference numerals (or names) as the elements of any other figures herein can be operated or run in a manner similar to that described elsewhere herein. In one embodiment, a graphics processor core block 1519 is an example of a partition of a graphics processor. A graphics processor core block 1519 may be included in an integrated graphics processor 1508 of Figure 15A or a discrete graphics processor, a parallel processor and/or a computing accelerator. A graphics processor as described herein may include multiple graphics core blocks based on a target power and performance envelope. Each graphics processor core block 1519 may include a functional block 1530 coupled to multiple graphics cores 1521A-1521F, and multiple graphics cores 1521A-1521F include modular blocks of fixed function logic and general programmable logic. Graphics processor core block 1519 also includes a shared/cache memory 1536 that is accessible by all graphics cores 1521A- 1521F, rasterizer logic 1537 , and additional fixed function logic 1538 .

In some embodiments, functional block 1530 includes a geometry/fixed function pipeline 1531 that can be shared by all graphics cores in graphics processor core block 1519. In various embodiments, geometry/fixed function pipeline 1531 includes a 3D geometry pipeline, a video front end unit, a thread generator and a global thread dispatcher, and a unified return buffer manager that manages a unified return buffer. In one embodiment, functional block 1530 also includes a graphics SoC interface 1532, a graphics microcontroller 1533, and a media pipeline 1534. Graphics SoC interface 1532 provides an interface between graphics processor core block 1519 and other core blocks within a graphics processor or computing accelerator SoC. Graphics microcontroller 1533 is a programmable subprocessor that can be configured to manage various functions of graphics processor core block 1519, including thread dispatching, scheduling, and preemption. Media pipeline 1534 includes logic for facilitating decoding, encoding, preprocessing, and/or post-processing of multimedia data (including image and video data). The media pipeline 1534 implements media operations via requests to computational or sampling logic within the graphics cores 1521A-1521F. One or more pixel backends 1535 may also be included within the functional block 1530. The pixel backend 1535 includes a buffer memory for storing pixel color values and is capable of performing blending operations and lossless color compression on rendered pixel data.

In one embodiment, the graphics SoC interface 1532 enables the graphics processor core block 1519 to communicate with a general-purpose application processor core (e.g., CPU) and/or other components within the SoC or within a system host CPU coupled to the SoC via a peripheral interface. The graphics SoC interface 1532 also enables communication with off-chip memory hierarchy elements, such as shared last-level cache memory, system RAM, and/or embedded on-chip or on-package DRAM. The SoC interface 1532 can also enable communication with fixed-function devices within the SoC, such as a camera imaging pipeline, and enable the use and/or implementation of global memory atomicity, which can be shared between the graphics processor core block 1519 and the CPU within the SoC. The graphics SoC interface 1532 can also implement power management controls for the graphics processor core block 1519 and enable interfaces between the clock domain of the graphics processor core block 1519 and other clock domains within the SoC. In one embodiment, graphics SoC interface 1532 enables receiving command buffers from a command stream converter and global thread dispatcher configured to provide commands and instructions to each of one or more graphics cores within a graphics processor. Commands and instructions can be dispatched to media pipeline 1534 when media operations are to be performed, and can be dispatched to geometry and fixed function pipeline 1531 when graphics processing operations are to be performed. When compute operations are to be performed, compute dispatch logic can dispatch commands to graphics cores 1521A-1521F, thereby bypassing the geometry pipeline and the media pipeline.

The graphics microcontroller 1533 may be configured to perform various scheduling and management tasks for the graphics processor core block 1519. In one embodiment, the graphics microcontroller 1533 may execute graphics workloads and/or computational workloads scheduled on the various vector engines 1522A-1522F, 1524A-1524F and matrix engines 1523A-1523F, 1525A-1525F within the graphics cores 1521A-1521F. In this scheduling model, host software executing on the CPU core of the SoC including the graphics processor core block 1519 may submit a workload to one of a plurality of graphics processor doorbells, which invokes a scheduling operation to the appropriate graphics engine. The scheduling operation includes determining which workload to run next, submitting the workload to the command stream converter, preempting an existing workload running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is completed. In one embodiment, graphics microcontroller 1533 can also facilitate a low power or idle state for graphics processor core block 1519, thereby providing graphics processor core block 1519 with the ability to save and restore registers within graphics processor core block 1519 across low power state transitions independent of the operating system and/or graphics driver software on the system.

The graphics processor core block 1519 may have more or fewer graphics cores 1521A-1521F than those shown, up to a maximum of N modular graphics cores. For each set of N graphics cores, the graphics processor core block 1519 may also include: a shared/cache memory 1536, which may be configured as a shared memory or a cache memory; a rasterizer logic 1537; and additional fixed function logic 1538 for accelerating various graphics and compute processing operations.

Included within each graphics core 1521A-1521F is a collection of execution resources that can be used to perform graphics operations, media operations, and compute operations in response to requests made by a graphics pipeline, a media pipeline, or a shader program. Graphics cores 1521A-1521F include multiple vector engines 1522A-1522F, 1524A-1524F, matrix acceleration units 1523A-1523F, 1525A-1525D, cache/shared local memory (SLM), samplers 1526A-1526F, and ray tracing units 1527A-1527F.

The vector engines 1522A-1522F, 1524A-1524F are general purpose graphics processing units capable of performing floating point and integer/fixed point logic operations to serve graphics operations, media operations, or computing operations (including graphics programs, media programs, or computing/GPGPU programs). The vector engines 1522A-1522F, 1524A-1524F are capable of operating with variable vector widths using SIMD execution mode, SIMT execution mode, or SIMT+SIMD execution mode. The matrix acceleration units 1523A-1523F, 1525A-1525D include matrix-matrix and matrix-vector acceleration logic that improves the performance of matrix operations, especially low-precision and mixed-precision (e.g., INT8, FP16, BF16, FP8) matrix operations for machine learning. In one embodiment, each of the matrix acceleration units 1523A-1523F, 1525A-1525D includes one or more systolic arrays of processing elements capable of performing concurrent matrix multiplication or dot product operations on matrix elements.

Samplers 1526A-1526F can read media data or texture data into memory and can sample data in different ways based on the configured sampler state and the texture/media format being read. Threads executing on vector engines 1522A-1522F, 1524A-1524F or matrix acceleration units 1523A-1523F, 1525A-1525D can utilize caches/SLMs 1528A-1528F within each of graphics cores 1521A-1521F. Caches/SLMs 1528A-1528F can be configured as a pool of cache memory or shared memory local to each of the corresponding graphics cores 1521A-1521F. Ray tracing units 1527A-1527F within graphics cores 1521A-1521F include ray traversal/intersection circuitry modules for performing ray traversals using a bounding volume hierarchy (BVH) and identifying intersections between rays and primitives enclosed within the BVH volume. In one embodiment, ray tracing units 1527A-1527F include circuitry modules for performing depth testing and culling (e.g., using a depth buffer or similar arrangement). In one implementation, ray tracing units 1527A-1527F perform traversal and intersection operations in coordination with image denoising, at least a portion of which may be performed using associated matrix acceleration units 1523A-1523F, 1525A-1525D.

15C is a block diagram of a general purpose graphics processing unit (GPGPU) 1570 according to an embodiment described herein, which GPGPU 1570 can be configured as a graphics processor (e.g., graphics processor 1508) and/or a computing accelerator. GPGPU 1570 can be interconnected with a host processor (e.g., one or more CPUs 1546) and memories 1571, 1572 via one or more system and/or memory buses. Memory 1571 can be a system memory that can be shared with one or more CPUs 1546, while memory 1572 is a device memory dedicated to GPGPU 1570. For example, components within GPGPU 1570 and memory 1572 can be mapped to memory addresses that can be accessed by one or more CPUs 1546. Access to memories 1571 and 1572 can be facilitated via a memory controller 1568. Memory controller 1568 may include an internal direct memory access (DMA) controller 1569, or may include logic for performing operations that would otherwise be performed by a DMA controller.

GPGPU 1570 includes a plurality of cache memories, including an L2 cache 1553, an L1 cache 1554, an instruction cache 1555, and a shared memory 1556, at least a portion of which may also be partitioned as a cache memory. GPGPU 1570 also includes a plurality of computing units 1560A-1560N. Each computing unit 1560A-1560N includes a set 1561 of vector registers, a set 1562 of scalar registers, a set 1563 of vector logic units, and a set 1564 of scalar logic units. Computing units 1560A-1560N may also include a local shared memory 1565 and a program counter 1566. Computing units 1560A-1560N may be coupled to a constant cache 1567, which may be used to store constant data, which is data that does not change during the execution of a kernel program or a shader program executed on GPGPU 1570. The constant cache 1567 may be a scalar data cache, and the cached data may be directly fetched into the scalar register 1562 .

During operation, one or more CPUs 1546 may write commands to registers in GPGPU 1570, or to memory in GPGPU 1570 that has been mapped into an accessible address space. Command processor 1557 may read commands from registers or memory and determine how to process those commands within GPGPU 1570. Thread dispatcher 1558 may then be used to dispatch threads to computing units 1560A-1560N to execute those commands. Each computing unit 1560A-1560N may execute threads independently of other computing units. In addition, each computing unit 1560A-1560N may be independently configured for conditional computation, and may conditionally output the results of the computation to memory. Command processor 1557 may interrupt one or more CPUs 1546 when the submitted commands are completed.

Figures 16A-16C illustrate block diagrams of additional graphics processor and computing accelerator architectures provided by the embodiments described herein, for example, according to Figures 15A-15C. Elements of Figures 16A-16C having the same or similar names as elements of any other figure herein describe the same elements as in the other figures, can operate or function in a similar manner as in the other figures, can include the same components, and can be linked to other entities, such as those described elsewhere herein, but not limited thereto.

FIG. 16A is a block diagram of a graphics processor 1600, which may be a discrete graphics processing unit, or may be a graphics processor integrated with multiple processing cores or other semiconductor devices, such as but not limited to memory devices or network interfaces. Graphics processor 1600 may be a variant of graphics processor 1508 and may be used in place of graphics processor 1508. Therefore, the disclosure of any feature in conjunction with graphics processor 1508 herein also discloses the corresponding combination with graphics processor 1600, but is not limited thereto. The graphics processor may communicate via a memory-mapped I/O interface to registers on the graphics processor and using commands placed into processor memory. Graphics processor 1600 may include a memory interface 1614 for accessing memory. Memory interface 1614 may be an interface to local memory, one or more internal caches, one or more shared external caches, and/or to system memory.

Optionally, the graphics processor 1600 also includes a display controller 1602 for driving display output data to a display device 1618. The display controller 1602 includes hardware for compositing one or more overlay planes of a display and multiple layers of video or user interface elements. The display device 1618 can be an internal or external display device. In one embodiment, the display device 1618 is a head mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. The graphics processor 1600 may include a video codec engine 1606 for encoding media to one or more media coding formats, decoding media from one or more media coding formats, or transcoding media between one or more media coding formats, including but not limited to: Moving Picture Experts Group (MPEG) formats (such as MPEG-2), Advanced Video Coding (AVC) formats (such as H.264/MPEG-4 AVC, H.265/HEVC, Alliance for Open Media (AOMedia) VP8, VP9), and the Society of Motion Picture & Television Engineers (SMPTE) 421M/VC-1, and Joint Photographic Experts Group (JPEG) formats (such as JPEG and Motion JPEG (MJPEG) formats).

Graphics processor 1600 may include a block image transfer (BLIT) engine 1603 for performing two-dimensional (2D) rasterizer operations, including, for example, bit-boundary block transfers. However, alternatively, 2D graphics operations may be performed using one or more components of a graphics processing engine (GPE) 1610. In some embodiments, GPE 1610 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

GPE 1610 may include a 3D pipeline 1612 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act on 3D primitive shapes (e.g., rectangles, triangles, etc.). 3D pipeline 1612 includes programmable and fixed-function elements that perform various tasks within the element and/or spawn execution threads to 3D/media subsystem 1615. While 3D pipeline 1612 may be used to perform media operations, embodiments of GPE 1610 also include a media pipeline 1616 that is specifically used to perform media operations, such as video post-processing and image enhancement.

The media pipeline 1616 may include fixed-function or programmable logic units for performing one or more specialized media operations, such as video decoding acceleration, video deinterlacing, and video encoding acceleration, instead of, or on behalf of, the video codec engine 1606. The media pipeline 1616 may additionally include a thread generation unit for generating threads for execution on the 3D/media subsystem 1615. The generated threads perform calculations for media operations on one or more graphics execution units included in the 3D/media subsystem 1615.

3D/media subsystem 1615 may include logic for executing threads generated by 3D pipeline 1612 and media pipeline 1616. The pipeline may send thread execution requests to 3D/media subsystem 1615, which includes thread dispatch logic for arbitrating and dispatching various requests for available thread execution resources. Execution resources include an array of graphics execution units for processing 3D threads and media threads. 3D/media subsystem 1615 may include one or more internal caches for thread instructions and data. In addition, 3D/media subsystem 1615 may also include shared memory for sharing data between threads and for storing output data, which includes registers and addressable memory.

FIG. 16B illustrates a graphics processor 1620 that is a variant of graphics processor 1600 and can be used in place of graphics processor 1600 and vice versa. Therefore, the disclosure of any feature herein in conjunction with graphics processor 1600 also discloses the corresponding combination with graphics processor 1620, but is not limited thereto. According to the embodiments described herein, graphics processor 1620 has a slice architecture. Graphics processor 1620 may include a graphics processing engine cluster 1622 having multiple instances of graphics processor engine 1610 of FIG. 16A within graphics engine slices 1610A-1610D. Each graphics engine slice 1610A-1610D may be interconnected via a set of slice interconnects 1623A-1623F. Each graphics engine slice 1610A-1610D may also be connected to a memory module or memory device 1626A-1626D via a memory interconnect 1625A-1625D. The memory devices 1626A-1626D may use any graphics memory technology. For example, the memory devices 1626A-1626D may be graphics double data rate (GDDR) memory. The memory devices 1626A-1626D may be high bandwidth memory (HBM) modules that may be on the die with their corresponding graphics engine slices 1610A-1610D. The memory devices 1626A-1626D may be stacked memory devices that may be stacked on top of their corresponding graphics engine slices 1610A-1610D. Each graphics engine slice 1610A-1610D and associated memory 1626A-1626D may reside on separate chiplets that are bonded to a base die or base substrate, as described in further detail in FIGS. 24B-24D.

Graphics processor 1620 may be configured with a non-uniform memory access (NUMA) system in which memory devices 1626A-1626D are coupled to associated graphics engine slices 1610A-1610D. A given memory device may be accessed by a graphics engine slice different from the graphics engine slice to which the memory device is directly connected. However, when accessing the local slice, access latency to memory devices 1626A-1626D may be minimized. In one embodiment, a cache coherent NUMA (ccNUMA) system is enabled that uses slice interconnects 1623A-1623F to enable communication between cache controllers within graphics engine slices 1610A-1610D to maintain a consistent memory image when more than one cache stores the same memory location.

The graphics processing engine cluster 1622 may be connected to an on-chip or on-package fabric interconnect 1624. In one embodiment, the fabric interconnect 1624 includes a network processor, a network on a chip (NoC), or another switching processor for enabling the fabric interconnect 1624 to function as a packet-switched fabric interconnect for exchanging data packets between components of the graphics processor 1620. The fabric interconnect 1624 may enable communication between the graphics engine slices 1610A-1610D and components such as the video codec 1606 and one or more replication engines 1604. The replication engines 1604 may be used to move data out of the memory devices 1626A-1626D and memory external to the graphics processor 1620 (e.g., system memory), move data into the memory devices 1626A-1626D and memory external to the graphics processor 1620 (e.g., system memory), and move data between the memory devices 1626A-1626D and memory external to the graphics processor 1620 (e.g., system memory). Fabric interconnect 1624 may also be used to interconnect graphics engine slices 1610A-1610D. Graphics processor 1620 may optionally include display controller 1602 to enable connection to external display device 1618. Graphics processor may also be configured as a graphics accelerator or a computing accelerator. In an accelerator configuration, display controller 1602 and display device 1618 may be omitted.

Graphics processor 1620 may be connected to a host system via host interface 1628. Host interface 1628 may enable communication between graphics processor 1620, system memory, and/or other system components. Host interface 1628 may be, for example, a PCI Express bus or another type of host system interface. For example, host interface 1628 may be an NVLink or NVSwitch interface. Host interface 1628 and fabric interconnect 1624 may collaborate to enable multiple instances of graphics processor 1620 to act as a single logical device. Collaboration between host interface 1628 and fabric interconnect 1624 may also enable individual graphics engine slices 1610A-1610D to be presented to the host system as different logical graphics devices.

FIG. 16C illustrates a computing accelerator 1630 according to an embodiment described herein. The computing accelerator 1630 may include architectural similarities to the graphics processor 1620 of FIG. 16B and is optimized for computing acceleration. The computing engine cluster 1632 may include a collection of computing engine slices 1640A-1640D, which include execution logic optimized for parallel or vector-based general computing operations. The computing engine slices 1640A-1640D may not include fixed-function graphics processing logic, but in some embodiments, one or more of the computing engine slices 1640A-1640D may include logic for performing media acceleration. The computing engine slices 1640A-1640D may be connected to the memory 1626A-1626D via the memory interconnect 1625A-1625D. 16B . The memory 1626A-1626D and memory interconnect 1625A-1625D may be similar technologies as in the graphics processor 1620, or may be different technologies. The compute engine slices 1640A-1640D may also be interconnected via a set of slice interconnects 1623A-1623F, and may be connected to and/or interconnected through the fabric interconnect 1624. In one embodiment, the compute accelerator 1630 includes a large L3 cache 1636 that may be configured as a device-wide cache. The compute accelerator 1630 may also be connected to a host processor and memory via a host interface 1628 in a manner similar to the graphics processor 1620 of FIG. 16B .

The computing accelerator 1630 may also include an integrated network interface 1642. In one embodiment, the integrated network interface 1642 includes a network processor and controller logic that enables the computing engine cluster 1632 to communicate over a physical layer interconnect 1644 without the data having to cross the memory of the host system. In one embodiment, one of the computing engine slices 1640A-1640D is replaced by the network processor logic, and the data to be transmitted or received via the physical layer interconnect 1644 can be directly transmitted to or from the memory 1626A-1626D. Multiple instances of the computing accelerator 1630 can be combined into a single logical device via the physical layer interconnect 1644. Alternatively, each computing engine slice 1640A-1640D can be presented as a different network accessible computing accelerator device.

Graphics processing engine

FIG. 17 is a block diagram of a graphics processing engine 1710 of a graphics processor according to some embodiments. Graphics processing engine (GPE) 1710 may be a version of GPE 1610 shown in FIG. 16A and may also represent graphics engine slices 1610A-1610D of FIG. 16B. Elements of FIG. 17 having the same or similar names as elements of any other figures herein describe the same elements in the other figures, may operate or run in a similar manner as in the other figures, may include the same components, and may be linked to other entities, such as those described elsewhere herein, but not limited thereto. For example, 3D pipeline 1612 and media pipeline 1616 of FIG. 16A are also illustrated in FIG. 17. Media pipeline 1616 is optional in some embodiments of GPE 1710 and may not be explicitly included in GPE 1710. For example and in at least one embodiment, a separate media and/or image processor is coupled to GPE 1710.

The GPE 1710 may be coupled to or include a command stream converter 1703 that provides a command stream to the 3D pipeline 1612 and/or the media pipeline 1616. Alternatively or additionally, the command stream converter 1703 may be directly coupled to a unified return buffer 1718. The unified return buffer 1718 may be communicatively coupled to the graphics core cluster 1714. Optionally, the command stream converter 1703 is coupled to a memory, which may be a system memory, or one or more of an internal cache memory and a shared cache memory. The command stream converter 1703 may receive commands from the memory and send these commands to the 3D pipeline 1612 and/or the media pipeline 1616. These commands are instructions taken from a ring buffer that stores commands for the 3D pipeline 1612 and the media pipeline 1616. The ring buffer may additionally include a batch command buffer that stores a batch of multiple commands. Commands for the 3D pipeline 1612 may also include references to data stored in memory, such as, but not limited to, vertex data and geometry data for the 3D pipeline 1612 and/or image data and memory objects for the media pipeline 1616. The 3D pipeline 1612 and the media pipeline 1616 process commands and data by performing operations via logic within the corresponding pipelines or by dispatching one or more execution threads to the graphics core cluster 1714. The graphics core cluster 1714 may include one or more graphics core blocks (e.g., graphics core block 1715A, graphics core block 1715B), each block including one or more graphics cores. Each graphics core includes a collection of graphics execution resources, including: general and graphics-specific execution logic for performing graphics operations and compute operations; and fixed-function texture processing logic and/or machine learning and artificial intelligence acceleration logic.

In various embodiments, the 3D pipeline 1612 may include fixed function and programmable logic for processing one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core cluster 1714. The graphics core cluster 1714 provides a unified execution resource block for use in processing these shader programs. The multi-function execution logic (e.g., execution units) within the graphics core blocks 1715A-1715B of the graphics core cluster 1714 includes support for various 3D API shader languages and can execute multiple simultaneous execution threads associated with multiple shaders.

Graphics core cluster 1714 may include execution logic for performing media functions such as video and/or image processing. In addition to graphics processing operations, the execution units may also include general logic that can be programmed to perform parallel general computing operations. The general logic may perform processing operations in parallel or in conjunction with general logic within processor core(s) 1407 of FIG. 14 or cores 1502A-1502N as in FIG. 15A.

Output data generated by threads executing on graphics core cluster 1714 can output data to memory in unified return buffer (URB) 1718. URB 1718 can store data for multiple threads. URB 1718 can be used to send data between different threads executing on graphics core cluster 1714. URB 1718 can additionally be used for synchronization between threads on graphics core cluster 1714 and fixed function logic within shared function logic 1720.

Optionally, graphics core clusters 1714 may be scalable such that the array includes a variable number of graphics cores, each with a variable number of execution units based on the target power and performance level of GPE 1710. Execution resources may be dynamically scalable such that execution resources may be enabled or disabled as needed.

The graphics core cluster 1714 is coupled to shared function logic 1720, which includes a plurality of resources shared between the graphics cores in the graphics core array. The shared functions within the shared function logic 1720 are hardware logic units that provide specialized supplemental functions to the graphics core cluster 1714. In various embodiments, the shared function logic 1720 includes, but is not limited to, sampler 1721 logic, math 1722 logic, and inter-thread communication (ITC) 1723 logic. In addition, one or more caches 1725 within the shared function logic 1720 may be implemented.

Shared functionality is implemented at least in cases where demand for a given specialized function is insufficient to be included within the graphics core cluster 1714. Instead, a single instantiation of that specialized function is implemented as an independent entity in shared functionality logic 1720 and shared between execution resources within the graphics core cluster 1714. The exact set of functions shared between the graphics core clusters 1714 and included within the graphics core cluster 1714 varies from embodiment to embodiment. Specific shared functions within the shared functionality logic 1720 that are widely used by the graphics core cluster 1714 may be included within the shared functionality logic 1716 within the graphics core cluster 1714. Optionally, the shared functionality logic 1716 within the graphics core cluster 1714 may include some or all of the logic within the shared functionality logic 1720. All logic elements within the shared functionality logic 1720 may be replicated within the shared functionality logic 1716 of the graphics core cluster 1714. Alternatively, the shared functionality logic 1720 is excluded in favor of the shared functionality logic 1716 within the graphics core cluster 1714.

Graphics processing resources

Figures 18A-18C illustrate the execution logic of the processing element array used in the graphics processor according to the embodiments described herein. Figure 18A illustrates a graphics core cluster according to an embodiment. Figure 18B illustrates a vector engine of a graphics core according to an embodiment. Figure 18C illustrates a matrix engine of a graphics core according to an embodiment. The elements of Figures 18A-18C with the same reference numerals as the elements of any other figures herein can be operated or run in any manner similar to the manner described elsewhere in this article, but are not limited thereto. For example, the elements of Figures 18A-18C can be considered in the context of the graphics processor core block 1519 of Figure 15B and/or the graphics core blocks 1715A-1715B of Figure 17. In one embodiment, the elements of Figures 18A-18C have functions similar to the equivalent components of the graphics processor 1508 of Figure 15A or the GPGPU 1570 of Figure 15C.

As shown in FIG. 18A , in one embodiment, graphics core cluster 1714 includes graphics core block 1715, which may be graphics core block 1715A or graphics core block 1715B of FIG. 17 . Graphics core block 1715 may include any number of graphics cores (e.g., graphics core 1815A, graphics core 1815B, all the way to graphics core 1815N). Multiple instances of graphics core block 1715 may be included. In one embodiment, the elements of graphics cores 1815A-1815N have similar or equivalent functions to the elements of graphics cores 1521A-1521F of FIG. 15B . In such embodiments, graphics cores 1815A-1815N each include circuit modules including, but not limited to, vector engines 1802A-1802N, matrix engines 1803A-1803N, memory load/store units 1804A-1804N, instruction caches 1805A-1805N, data caches/shared local memory 1806A-1806N, ray tracing units 1808A-1808N, and samplers 1810A-1810N. The circuit modules of graphics cores 1815A-1815N may additionally include fixed function logic 1812A-1812N. The number of vector engines 1802A-1802N and matrix engines 1803A-1803N within a designed graphics core 1815A-1815N may vary based on the workload, performance, and power targets for the design.

With reference to graphics core 1815A, vector engine 1802A and matrix engine 1803A are configurable to perform parallel computation operations on data in various integer and floating point data formats based on instructions associated with shader programs. Each vector engine 1802A and matrix engine 1803A can act as a programmable general purpose computing unit capable of executing multiple synchronous hardware threads while processing multiple data elements in parallel for each thread. Vector engine 1802A and matrix engine 1803A support processing of variable width vectors in various SIMD widths, including but not limited to SIMD8, SIMD16 and SIMD32. Input data elements can be stored in registers as compact data types, and vector engine 1802A and matrix engine 1803A can process each element based on the data size of the element. For example, when operating on a 256-bit wide vector, the 256 bits of the vector are stored in registers, and the vector is processed as four separate 64-bit packed data elements (quad-word (QW)) size data elements), eight separate 32-bit packed data elements (double-word (DW)) size data elements), sixteen separate 16-bit packed data elements (word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements). However, different vector widths and register sizes are possible. In one embodiment, the vector engine 1802A and the matrix engine 1803A can also be configured to perform SIMT operations on various sizes of unit groups and thread groups (e.g., 8, 16 or 32 threads).

Continuing with the graphics core 1815A, the memory load/store unit 1804A services memory access requests issued by the vector engine 1802A, the matrix engine 1803A, and/or other components of the graphics core 1815A that have access to memory. The memory access request can be processed by the memory load/store unit 1804A to load or store the requested data into a cache or memory, or from a cache or memory into a register file associated with the vector engine 1802A and/or the matrix engine 1803A. The memory load/store unit 1804A can also perform prefetch operations. Referring also to FIG. 19, in one embodiment, the memory load/store unit 1804A is configured to provide SIMT scatter/gather prefetch or block prefetch for data stored in memory 1910, from memory that is local to other slices via the slice interconnect 1908, or from system memory. Prefetching may be performed to a specific L1 cache (e.g., data cache/shared local memory 1806A), L2 cache 1904, or L3 cache 1906. In one embodiment, prefetching to L3 cache 1906 automatically causes the data to be stored in L2 cache 1904.

Instruction cache 1805A stores instructions to be executed by graphics core 1815A. In one embodiment, graphics core 1815A also includes an instruction acquisition and pre-fetch circuit module that fetches or pre-fetches instructions into instruction cache 1805A. Graphics core 1815A also includes instruction decoding logic for decoding instructions within instruction cache 1805A. Data cache/shared local memory 1806A can be configured as a data cache managed by a cache controller that implements a cache replacement strategy and/or configured as a shared memory that is explicitly managed. Ray tracing unit 1808A includes a circuit module for accelerating ray tracing operations. Sampler 1810A provides texture sampling for 3D operations and media sampling for media operations. Fixed function logic 1812A includes a fixed function circuit module that is shared between instances of vector engine 1802A and matrix engine 1803A. Graphics cores 1815B-1815N can operate in a similar manner to graphics core 1815A.

The functions of the instruction caches 1805A-1805N, data caches/shared local memory 1806A-1806N, ray tracing units 1808A-1808N, samplers 1810A-1812N, and fixed function logic 1812A-1812N correspond to the equivalent functions in the graphics processor architecture described herein. For example, the instruction caches 1805A-1805N can operate in a manner similar to the instruction cache 1555 of FIG. 15C. The data caches/shared local memory 1806A-1806N, ray tracing units 1808A-1808N, and samplers 1810A-1812N can operate in a manner similar to the caches/SLMs 1528A-1528F, ray tracing units 1527A-1527F, and samplers 1526A-1526F of FIG. 15B. Fixed function logic 1812A-1812N may include elements of geometry/fixed function pipeline 1531 of Figure 15B and/or additional fixed function logic 1538. In one embodiment, ray tracing units 1808A-1808N include circuit modules for performing ray tracing acceleration operations performed by ray tracing core 372 of Figure 3C.

As shown in FIG. 18B , in one embodiment, the vector engine 1802 includes an instruction fetch unit 1837, a general register file array (GRF) 1824, an architectural register file array (ARF) 1826, a thread arbiter 1822, an issue unit 1830, a branch unit 1832, a set of SIMD floating point units (FPUs) 1834, and a set of integer SIMD ALUs 1835 in one embodiment. The GRF 1824 and ARF 1826 include a set of general register files and architectural register files associated with each hardware thread that can be active in the vector engine 1802. In one embodiment, the per-thread architectural state is maintained in the ARF 1826, while data used during thread execution is stored in the GRF 1824. The execution state of each thread, including the instruction pointer for each thread, can be saved in thread-specific registers in the ARF 1826. Register renaming can be used to dynamically assign registers to hardware threads.

In one embodiment, the vector engine 1802 has an architecture that is a combination of Simultaneous Multi-Threading (SMT) and fine-grained Interleaved Multi-Threading (IMT). The architecture has a modular configuration that can be fine-tuned at design time based on the target number of simultaneous threads and the number of registers per graphics core, where graphics core resources are divided across logic for executing multiple simultaneous threads. The number of logical threads that can be executed by the vector engine 1802 is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread.

In one embodiment, the vector engine 1802 can issue multiple instructions in coordination, and these instructions can be different instructions respectively. The thread arbiter 1822 can dispatch instructions to one of the send unit 1830, the branch unit 1832 or (one or more) SIMD FPU 1834 for execution. Each execution thread can access 128 general registers in the GRF 1824, wherein each register can store 32 bytes that can be accessed as a variable width vector with 32-byte data elements. In one embodiment, each thread has access to 4 kilobytes in the GRF 1824, but the embodiment is not limited thereto, and more or less register resources can be provided in other embodiments. In one embodiment, the vector engine 1802 is partitioned into seven hardware threads that can independently perform computing operations, but the number of threads of each vector engine 1802 can also vary according to the embodiment. For example, in one embodiment, a maximum of 16 hardware threads are supported. In an embodiment in which seven threads can access 4 kilobytes, the GRF 1824 can store a total of 28 kilobytes. With 16 threads accessing 4 kilobytes, a total of 64 kilobytes can be stored by GRF 1824. Flexible addressing modes allow registers to be addressed together, effectively creating wider registers or representing strided rectangular block data structures.

In one embodiment, memory operations, sampler operations, and other longer latency system communications are dispatched via "send" instructions executed by message passing send unit 1830. In one embodiment, branch instructions are dispatched to a dedicated branch unit 1832 to facilitate SIMD scatter and eventual convergence.

In one embodiment, the vector engine 1802 includes one or more SIMD floating point units (FPU(s)) 1834 for performing floating point operations. In one embodiment, FPU(s) 1834 also supports integer calculations. In one embodiment, FPU(s) 1834 can perform up to M 32-bit floating point (or integer) operations, or up to 2M 16-bit integer or 16-bit floating point operations. In one embodiment, at least one of the FPU(s) provides extended math capabilities that support high throughput transcendental math functions and double precision 64-bit floating points. In some embodiments, a set 1835 of 8-bit integer SIMD ALUs also exists and can be specifically optimized to perform operations associated with machine learning calculations. In one embodiment, the SIMD ALUs are replaced by a set 1834 of additional SIMD ALUs that can be configured to perform integer and floating point operations. In one embodiment, SIMD FPU 1834 and SIMD ALU 1835 can be configured to execute SIMT programs. In one embodiment, combined SIMD+SIMT operations are supported.

In one embodiment, an array of multiple instances of vector engine 1802 may be instantiated in a graphics core. For scalability, product architects may choose the exact number of vector engines grouped per graphics core. In one embodiment, vector engine 1802 may execute instructions across multiple execution lanes. In further embodiments, each thread executed on vector engine 1802 is executed on a different lane.

As shown in Figure 18C, in one embodiment, matrix engine 1803 includes an array of processing elements configured to perform tensor operations, and the tensor operations include vector/matrix operations and matrix/matrix operations, such as but not limited to matrix multiplication and/or dot product operations. Matrix engine 1803 can be configured using processing elements (1852AA-1852MN) of M rows and N columns, and the processing elements (PE 1852AA-PE-1852MN) include multipliers and adder circuits organized in a pipelined manner. In one embodiment, processing elements 1852AA-1852MN form the physical pipeline stage of the systolic array of N width and M depth, and the systolic array can be used to perform vector/matrix operations or matrix/matrix operations in a data parallel manner, including matrix multiplication, fusion multiplication and addition, dot product or other general matrix-matrix multiplication (GEMM) operations. In one embodiment, matrix engine 1803 supports 16-bit and 8-bit floating point operations, as well as 8-bit, 4-bit, 2-bit and binary integer operations. The matrix engine 1803 may also be configured to accelerate certain machine learning operations. In such embodiments, the matrix engine 1803 may be configured with support for a bfloat (brain floating point) 16-bit floating point format with a different number of mantissa bits and exponent bits relative to the Institute of Electrical and Electronics Engineers (IEEE) 754 format, or a tensor floating point 32-bit floating point format (TF32).

In one embodiment, during each cycle, each stage may add the result of the operation performed at that stage to the output of the previous stage. In other embodiments, after a set of computation cycles, the pattern of data movement between processing elements 1852AA-1852MN may vary based on the instructions or macro operations executed. For example, in one embodiment, a partial sum loopback is enabled, and the processing element may instead add the output of the current cycle to the output generated in the previous cycle. In one embodiment, the final stage of the systolic array may be configured with a loop to the initial stage of the systolic array. In such embodiments, the number of physical pipeline stages may be decoupled from the number of logical pipeline stages supported by the matrix engine 1803. For example, where the processing elements 1852AA-1852MN are configured as a systolic array of M physical stages, a loop from stage M to the initial pipeline stage may enable the processing elements 1852AA-1852MN to operate as a systolic array of logical pipeline stages, such as 2M, 3M, 4M, etc.

In one embodiment, matrix engine 1803 includes memory 1841A-1841N, 1842A-1842M, for storing input data in the form of row and column data for input matrix. Memory 1842A-1842M can be configured to store the row elements (A0-Am) of the first input matrix, and memory 1841A-1841N can be configured to store the column elements (B0-Bn) of the second input matrix. Row elements and column elements are provided as input to processing element 1852AA-1852MN for processing. In one embodiment, the element row and column elements of the input matrix can be stored in the systolic register stack 1840 in the matrix engine 1803 before these elements are provided to memory 1841A-1841N, 1842A-1842M. In one embodiment, systolic register file 1840 is excluded and memories 1841A-1841N, 1842A-1842M are loaded from registers in an associated vector engine (e.g., GRF 1824 of vector engine 1802 of FIG. 18B ) or other memory of a graphics core including matrix engine 1803 (e.g., data cache/shared local memory 1806A for matrix engine 1803A of FIG. 18A ). Results generated by processing elements 1852AA-1852MN are then output to output buffers and/or written to register files (e.g., systolic register file 1840, GRF 1824, data cache/shared local memory 1806A-1806N) for further processing by other functional units of the graphics processor or for output to memory.

In some embodiments, the matrix engine 1803 is configured with support for input sparsity, wherein multiplication operations of sparse regions of input data can be bypassed by skipping multiplication operations of operands with zero values. In one embodiment, processing elements 1852AA-1852MN are configured to skip the execution of certain operations with zero-value inputs. In one embodiment, the sparsity within the input matrix can be detected, and operations with known zero output values can be bypassed before being submitted to processing elements 1852AA-1852MN. Loading zero-value operands into processing elements can be bypassed, and processing elements 1852AA-1852MN can be configured to perform multiplication on non-zero-value input elements. The matrix engine 1803 can also be configured with support for output sparsity, so that operations with results predetermined to zero can be bypassed. For input sparsity and/or output sparsity, in one embodiment, metadata is provided to processing elements 1852AA-1852MN to indicate which processing elements and/or data channels will be active during the cycle for a certain processing cycle.

In one embodiment, the matrix engine 1803 includes hardware for enabling operations on sparse data with a compressed representation of a sparse matrix, which stores non-zero values and metadata identifying the location of the non-zero values in the matrix. Exemplary compressed representations include, but are not limited to, compressed tensor representations, such as, compressed sparse rows (CSR) representations, compressed sparse columns (CSC) representations, compressed sparse fibers (CSF) representations. Support for compressed representations enables operations to be performed on inputs in compressed tensor format without the need for compressed representations to be decompressed or decoded. In such embodiments, operations can be performed only on non-zero input values, and the resulting non-zero output values can be mapped into the output matrix. In some embodiments, hardware support for machine-specific lossless data compression formats is also provided, which are used when transmitting data within hardware or across system buses. Such data can be retained in a compressed format for sparse input data, and the matrix engine 1803 can use compressed metadata for compressed data to enable operations to be performed only on non-zero values or to enable blocks of zero data input to be bypassed for multiplication operations.

In various embodiments, the input data may be provided by the programmer in a compressed tensor representation, or the codec may compress the input data into a compressed tensor representation or another sparse data encoding. In addition, in order to support the compressed tensor representation, streaming compression of the sparse input data may be performed before the input data is provided to the processing element 1852AA-1852MN. In one embodiment, compression is performed on the data written to the cache memory associated with the graphics core cluster 1714, wherein the compression is performed using the encoding supported by the matrix engine 1803. In one embodiment, the matrix engine 1803 includes support for inputs with structured sparsity, in which a predetermined level or predetermined pattern of sparsity is applied to the input data. The data may be compressed to a known compression ratio, wherein the compressed data is processed by the compression element 1852AA-1852MN according to metadata associated with the compressed data.

FIG. 19 illustrates a slice 1900 of a multi-slice processor according to an embodiment. In one embodiment, slice 1900 represents one of the graphics engine slices 1610A-1610D of FIG. 16B or the compute engine slices 1640A-1640D of FIG. 16C . Slice 1900 of a multi-slice graphics processor includes an array of graphics core clusters (e.g., graphics core cluster 1714A, graphics core cluster 1714B, all the way to graphics core cluster 1714N), wherein each graphics core cluster has an array 515A-515N of graphics cores. Slice 1900 also includes a global dispatcher 1902 for dispatching threads to processing resources of slice 1900.

Slice 1900 may include or be coupled with L3 cache 1906 and memory 1910. In various embodiments, L3 cache 1906 may be excluded, or slice 1900 may include additional levels of cache, such as L4 cache. In one embodiment, such as in FIG. 16B and FIG. 16C, each instance of slice 1900 in a multi-slice graphics processor has an associated memory 1910. In one embodiment, the multi-slice processor may be configured as a multi-chip module in which L3 cache 1906 and/or memory 1910 reside on a separate chiplet that is different from the graphics core cluster 1714A-1714N. In this context, a chiplet is an at least partially packaged integrated circuit that includes different logic units that can be assembled into a larger package with other chiplets. For example, L3 cache 1906 may be included in a dedicated cache chiplet, or reside on the same chiplet as the graphics core cluster 1714A-1714N. In one embodiment, the L3 cache 1906 may be included in an active base die or an active interposer as illustrated in FIG. 24C .

Memory structure 1903 enables communication between graphics core clusters 1714A-1714N, L3 cache 1906, and memory 1910. L2 cache 1904 is coupled to memory structure 1903 and is configurable to cache transactions executed via memory structure 1903. Slice interconnect 1908 enables communication with other slices on the graphics processor and may be one of slice interconnects 1623A-1623F of FIGS. 16B and 16C. In embodiments where L3 cache 1906 is excluded from slice 1900, L2 cache 1904 may be configured as a combined L2/L3 cache. Memory structure 1903 may be configured to route data to L3 cache 1906 or to a memory controller associated with memory 1910 based on the presence or absence of L3 cache 1906 in a particular implementation. L3 cache 1906 may be configured as a per-tile cache that is dedicated to the processing resources of tile 1900 or may be part of a GPU-wide L3 cache.

FIG. 20 is a block diagram illustrating a graphics processor instruction format 2000. The graphics processor execution unit supports an instruction set having instructions in a variety of formats. Solid line boxes illustrate components that are typically included in the execution unit instructions, while dashed lines include components that are optional or included only in a subset of the instructions. In some embodiments, the graphics processor instruction format 2000 described and illustrated are macroinstructions because they are instructions supplied to the execution unit, as opposed to micro-operations that result from instruction decoding that is performed once the instruction is processed. Therefore, a single instruction can cause the hardware to perform multiple micro-operations.

As described herein, the graphics processor execution unit can natively support instructions of the 128-bit instruction format 2010. Based on the selected instructions, instruction options, and the number of operands, the 64-bit compact instruction format 2030 can be used for some instructions. The native 128-bit instruction format 2010 provides access to all instruction options, while some options and operations are limited in the 64-bit format 2030. The native instructions available in the 64-bit format 2030 vary from embodiment to embodiment. The instructions are partially compressed using a set of index values in the index field 2013. The execution unit hardware references a set of compression tables based on the index values and uses the compression table output to reconstruct the native instructions of the 128-bit instruction format 2010. Instructions of other sizes and formats can be used.

For each format, the instruction opcode 2012 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an addition instruction, the execution unit performs a synchronous addition operation across each color channel representing a texture element or a picture element. By default, the execution unit executes each instruction across all data channels of the operand. The instruction control field 2014 can enable control of certain execution options (such as channel selection (e.g., predication) and data channel order (e.g., swizzle)). For instructions in the 128-bit instruction format 2010, the execution size field 2016 limits the number of data channels that will be executed in parallel. The execution size field 2016 may not be available for the 64-bit compact instruction format 2030.

Some execution unit instructions have up to three operands, including two source operands src0 2020, src1 2022 and one destination operand (dest 2018). Other instructions (such as, for example, data manipulation instructions, dot product instructions, multiply-add instructions, or multiply-accumulate instructions) may have a third source operand (e.g., src2 2024). The instruction opcode 2012 determines the number of source operands. The last source operand of the instruction may be an immediate (e.g., hard-coded) value passed with the instruction. The execution unit may also support multiple destination instructions, where one or more of the destinations are implicit or implicit based on the instruction and/or the specified destination.

The 128-bit instruction format 2010 may include an access/addressing mode field 2026 that specifies, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register addresses of one or more operands are provided directly by bits in the instruction.

128-bit instruction format 2010 may also include an access/addressing mode field 2026, which specifies the addressing mode and/or access mode of the instruction. The access mode may be used to define the data access alignment of the instruction. The access mode may support access modes including 16-byte aligned access modes and 1-byte aligned access modes, wherein the byte alignment of the access mode determines the access alignment of the instruction operand. For example, when in the first mode, the instruction may use byte-aligned addressing for source operands and destination operands, and when in the second mode, the instruction may use 16-byte aligned addressing for all source operands and destination operands.

The addressing mode portion of the access/addressing mode field 2026 may determine whether the instruction uses direct or indirect addressing. When direct register addressing mode is used, the bits in the instruction directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands may be calculated based on the address register value and the address immediate field in the instruction.

Instructions can be grouped based on the opcode 2012 bit fields to simplify opcode decoding 2040. For 8-bit opcodes, bit 4, bit 5, and bit 6 allow the execution unit to determine the type of opcode. The exact opcode grouping shown is only an example. Move and logic opcode group 2042 can include data movement and logic instructions (e.g., move (mov), compare (cmp)). Move and logic group 2042 can share five least significant bits (least significant bit, LSB), wherein the move (mov) instruction adopts the form of 0000xxxxb, and the logic instruction adopts the form of 0001xxxxb. Flow control instruction group 2044 (e.g., call (call), jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). Miscellaneous instruction group 2046 includes a mixture of instructions, including synchronization instructions (e.g., wait (wait), send (send)) in the form of 0011xxxxb (e.g., 0x30). The parallel math instruction group 2048 includes component-by-component arithmetic instructions (e.g., addition, multiplication (mul)) of the form 0100xxxxb (e.g., 0x40). The parallel math instruction group 2048 performs arithmetic operations in parallel across data channels. The vector math group 2050 includes arithmetic instructions (e.g., dp4) of the form 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic on vector operands, such as dot product calculations. In one embodiment, the illustrated opcode decoding 2040 can be used to determine which portion of the execution unit will be used to execute the decoded instructions. For example, some instructions may be designated as systolic instructions to be executed by a systolic array. Other instructions, such as ray tracing instructions (not shown), may be routed to a ray tracing core or ray tracing logic within a slice or partition of the execution logic.

Graphics Pipeline

Figure 21 is a block diagram of a graphics processor 2100 according to another embodiment. Elements of Figure 21 having the same or similar names as elements of any other figures herein describe the same elements as in the other figures, can operate or function in a similar manner as in the other figures, can include the same components, and can be linked to other entities such as, but not limited to, those described elsewhere herein.

The graphics processor 2100 may include different types of graphics processing pipelines, such as a geometry pipeline 2120, a media pipeline 2130, a display engine 2140, a thread execution logic 2150, and a rendering output pipeline 2170. The graphics processor 2100 may be a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor may be controlled by register writes to one or more control registers (not shown) or via commands issued to the graphics processor 2100 through a ring interconnect 2102. The ring interconnect 2102 may couple the graphics processor 2100 to other processing components (such as other graphics processors or general-purpose processors). Commands from the ring interconnect 2102 are interpreted by a command stream converter 2103, which supplies instructions to various components of the geometry pipeline 2120 or the media pipeline 2130.

The command stream converter 2103 may direct the operation of the vertex fetcher 2105, which reads vertex data from memory and executes vertex processing commands provided by the command stream converter 2103. The vertex fetcher 2105 may provide the vertex data to the vertex shader 2107, which performs coordinate space transformation and lighting operations on each vertex. The vertex fetcher 2105 and the vertex shader 2107 may execute the vertex processing instructions by dispatching execution threads to the graphics cores 2152A-2152B via the thread dispatcher 2131.

The graphics cores 2152A-2152B may be an array of vector processors with instruction sets for performing graphics operations and media operations. The graphics cores 2152A-2152B may have an attached L1 cache 2151 that is dedicated to each array or shared between arrays. The cache may be configured as a data cache, an instruction cache, or partitioned into a single cache containing data and instructions in different partitions.

The geometry pipeline 2120 may include a tessellation component for performing hardware accelerated tessellation of 3D objects. A programmable shell shader 2111 may configure tessellation operations. A programmable domain shader 2117 may provide back-end evaluation of tessellation output. The tessellation 2113 may operate under the direction of the shell shader 2111 and may contain dedicated logic for generating a detailed set of geometric objects based on a coarse geometric model that is provided as input to the geometry pipeline 2120. In addition, if tessellation is not used, the tessellation component (e.g., the shell shader 2111, the tessellation 2113, and the domain shader 2117) may be bypassed. The tessellation component may operate based on data received from the vertex shader 2107.

The complete geometric object may be processed by the geometry shader 2119 via one or more threads dispatched to the graphics core 2152A-2152B, or may proceed directly to the clipper 2129. The geometry shader may operate on the entire geometric object, rather than on vertices or patches of vertices as in previous stages of the graphics pipeline. If tessellation is disabled, the geometry shader 2119 receives input from the vertex shader 2107. The geometry shader 2119 may be programmable by a geometry shader program to perform geometry tessellation when the tessellation unit is disabled.

Before rasterization, the clipper 2129 processes the vertex data. The clipper 2129 can be a fixed function clipper or a programmable clipper with clipping and geometry shader functions. The rasterizer and depth test component 2173 in the render output pipeline 2170 can dispatch a pixel shader to convert the geometric object into a pixel-by-pixel representation. The pixel shader logic can be included in the thread execution logic 2150. Optionally, the application can bypass the rasterizer and depth test component 2173 and access the unrasterized vertex data via the outflow unit 2123.

The graphics processor 2100 has an interconnect bus, interconnect structure, or some other interconnect mechanism that allows data and messages to be passed between the main components of the processor. In some embodiments, the graphics core 2152A-2152B and associated logic units (e.g., L1 cache 2151, sampler 2154, texture cache 2158, etc.) are interconnected via data ports 2156 to perform memory accesses and communicate with the rendering output pipeline components of the processor. Samplers 2154, caches 2151, 2158, and graphics cores 2152A-2152B can each have a separate memory access path. Optionally, texture cache 2158 can also be configured as a sampler cache.

The rendering output pipeline 2170 may include a rasterizer and depth test component 2173, which converts vertex-based objects into associated pixel-based representations. The rasterizer logic may include a window device/masker unit for performing fixed-function triangle and line rasterization. In some embodiments, an associated rendering buffer 2178 and a depth buffer 2179 are also available. A pixel operation component 2177 performs pixel-based operations on data, but in some instances, pixel operations associated with 2D operations (e.g., using mixed bit block image transmission) are performed by the 2D engine 2141, or replaced by a display controller 2143 using an overlay display plane when displayed. A shared L3 cache 2175 may be available to all graphics components, allowing data to be shared without using main system memory.

The media pipeline 2130 may include a media engine 2137 and a video front end 2134. The video front end 2134 may receive pipeline commands from the command stream converter 2103. The media pipeline 2130 may include a separate command stream converter. The video front end 2134 may process the media commands before sending them to the media engine 2137. The media engine 2137 may include a thread generation function for generating threads for dispatching to the thread execution logic 2150 via the thread dispatcher 2131.

The graphics processor 2100 may include a display engine 2140. The display engine 2140 may be external to the processor 2100 and may be coupled to the graphics processor via a ring interconnect 2102, or some other interconnect bus or structure. The display engine 2140 may include a 2D engine 2141 and a display controller 2143. The display engine 2140 may contain dedicated logic capable of operating independently of the 3D pipeline. The display controller 2143 may be coupled to a display device (not shown), which may be a system-integrated display device such as in a laptop or an external display device attached via a display device connector.

The geometry pipeline 2120 and the media pipeline 2130 can be configured to perform operations based on multiple graphics and media programming interfaces and are not dedicated to any one application programming interface (API). Driver software for a graphics processor can convert API calls dedicated to a specific graphics or media library into commands that can be processed by the graphics processor. Support can be provided for all Open Graphics Library (OpenGL), Open Computing Language (OpenCL) and/or Vulkan graphics and computing APIs from the Khronos Group. Support can also be provided for the Direct3D library from Microsoft. Combinations of these libraries can be supported. Support can also be provided for the OpenSource Computer Vision Library (OpenCV). If a mapping from the pipeline of a future API to the pipeline of a graphics processor can be performed, future APIs with compatible 3D pipelines will also be supported.

Graphics pipeline programming

FIG. 22A is a block diagram illustrating a graphics processor command format 2200 for programming a graphics processing pipeline, such as, for example, the pipelines described herein in conjunction with FIGS. 16A , 17 , and 21 . FIG. 22B is a block diagram illustrating a graphics processor command sequence 2210 according to an embodiment. The solid line boxes in FIG. 22A illustrate components that are generally included in a graphics command, while the dashed lines include components that are optional or included only in a subset of graphics commands. The exemplary graphics processor command format 2200 of FIG. 22A includes fields for identifying a client 2202 of a command, a command operation code (opcode) 2204, and a data field 2206. A subopcode 2205 and a command size 2208 are also included in some commands.

Client 2202 may specify a client unit of a graphics device that processes command data. A graphics processor command parser may check the client field of each command to adjust further processing of the command and route the command data to the appropriate client unit. A graphics processor client unit may include a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit may have a corresponding processing pipeline for processing commands. Once a command is received by a client unit, the client unit reads an opcode 2204 and a subopcode 2205 (if present) to determine the operation to be performed. The client unit uses the information in the data field 2206 to execute the command. For some commands, an explicit command size 2208 is expected to specify the size of the command. The command parser may automatically determine the size of at least some of the commands based on the command opcode. Commands may be aligned via multiples of double words. Other command formats may also be used.

The flowchart in FIG22B illustrates an exemplary graphics processor command sequence 2210. Software or firmware of a data processing system featuring an exemplary graphics processor may use a version of the command sequence shown to establish, execute, and terminate a set of graphics operations. The sample command sequence is shown and described for exemplary purposes only, and is not limited to these particular commands or command sequences. In addition, commands may be issued as batches of commands in a command sequence so that the graphics processor will process the command sequence in an at least partially concurrent manner.

The graphics processor command sequence 2210 can begin with a pipeline flush command 2212 to cause any active graphics pipeline to complete currently pending commands for the pipeline. Optionally, the 3D pipeline 2222 and the media pipeline 2224 may not operate concurrently. The pipeline flush is performed to cause the active graphics pipeline to complete any pending commands. In response to the pipeline flush, the command parser for the graphics processor will suspend command processing until the active paint engines complete pending operations and the associated read caches are invalidated. Optionally, any data marked as "dirty" in the render cache can be flushed to memory. The pipeline flush command 2212 can be used for pipeline synchronization, or can be used before placing the graphics processor in a low power state.

When a command sequence requires the graphics processor to explicitly switch between pipelines, a pipeline select command 2213 may be used. A pipeline select command 2213 may be required only once in an execution context before issuing a pipeline command, unless the context is issuing commands for both pipelines. A pipeline flush command 2212 may be required immediately before a pipeline switch via a pipeline select command 2213.

Pipeline control commands 2214 may configure the graphics pipeline for operation and may be used to program 3D pipeline 2222 and media pipeline 2224. Pipeline control commands 2214 may configure pipeline states for active pipelines. Pipeline control commands 2214 may be used for pipeline synchronization and to clear data from one or more cache memories within an active pipeline before processing a batch of commands.

Commands associated with return buffer state 2216 may be used to configure a set of return buffers for a corresponding pipeline for writing data. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers into which the operation writes intermediate data during processing. A graphics processor may also use one or more return buffers to store output data and perform cross-thread communication. Return buffer state 2216 may include selecting the size and number of return buffers to be used for a set of pipeline operations.

The remaining commands in the command sequence differ based on the active pipeline for operation. Based on pipeline decision 2220 , the command sequence is tailored for either 3D pipeline 2222 starting at 3D pipeline state 2230 , or media pipeline 2224 starting at media pipeline state 2240 .

The commands for configuring the 3D pipeline state 2230 include 3D state setup commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables that will be configured before processing 3D primitive commands. The values of these commands are determined at least in part based on the specific 3D API in use. The 3D pipeline state 2230 commands may also be able to selectively disable or bypass certain pipeline elements if those elements will not be used.

3D primitive 2232 commands can be used to submit 3D primitives to be processed by the 3D pipeline. The commands and associated parameters passed to the graphics processor via the 3D primitive 2232 commands are forwarded to the vertex acquisition function in the graphics pipeline. The vertex acquisition function uses the 3D primitive 2232 command data to generate a vertex data structure. The vertex data structure is stored in one or more return buffers. The 3D primitive 2232 commands can be used to perform vertex operations on 3D primitives via a vertex shader. In order to process the vertex shader, the 3D pipeline 2222 dispatches the shader execution thread to the graphics processor execution unit.

The 3D pipeline 2222 can be triggered via an execute 2234 command or event. A register can be written to trigger a command execution. Execution can be triggered via a "go" or "kick" command in a command sequence. Command execution can be triggered using a pipeline synchronization command to flush the command sequence through the graphics pipeline. The 3D pipeline will perform geometry processing for 3D primitives. Once the operation is completed, the resulting geometric objects are rasterized and the pixel engine shades the resulting pixels. For those operations, additional commands for controlling pixel shading and pixel backend operations may also be included.

When performing media operations, the graphics processor command sequence 2210 may follow the media pipeline 2224 path. In general, the specific purpose and manner of programming the media pipeline 2224 depends on the media or computing operations to be performed. During media decoding, specific media decoding operations may be migrated to the media pipeline. The media pipeline may also be bypassed, and the media decoding may be performed in whole or in part using resources provided by one or more general-purpose processing cores. The media pipeline may also include elements for general-purpose graphics processor unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using compute shader programs that are not explicitly related to the rendering of graphics primitives.

The media pipeline 2224 can be configured in a similar manner to the 3D pipeline 2222. A set of commands for configuring the media pipeline state 2240 are dispatched or placed into a command queue before the media object commands 2242. The commands for the media pipeline state 2240 may include data for configuring the media pipeline elements that will be used to process the media objects. This includes data for configuring the video decoding and video encoding logic within the media pipeline, such as encoding or decoding formats. The commands for the media pipeline state 2240 may also support the use of one or more pointers to "indirect" state elements that contain batches of state settings.

The media object command 2242 may supply a pointer to a media object for processing by the media pipeline. The media object includes a memory buffer that contains the video data to be processed. Optionally, all media pipeline states must be valid before issuing the media object command 2242. Once the pipeline state is configured and the media object command 2242 is queued, the media pipeline 2224 is triggered via an execute command 2244 or an equivalent execute event (e.g., a register write). The output from the media pipeline 2224 may then be post-processed by operations provided by the 3D pipeline 2222 or the media pipeline 2224. GPGPU operations may be configured and executed in a manner similar to media operations.

Graphics Software Architecture

FIG. 23 illustrates an exemplary graphics software architecture for a data processing system 2300. Such a software architecture may include a 3D graphics application 2310, an operating system 2320, and at least one processor 2330. Processor 2330 may include a graphics processor 2332 and one or more general-purpose processor cores 2334. Processor 2330 may be a variant of processor 1402 or any other processor described herein. Processor 2330 may be used in place of processor 1402 or any other processor described herein. Therefore, the disclosure of any feature in conjunction with processor 1402 or any other processor described herein also discloses the corresponding combination with graphics processor 2330, but is not limited thereto. In addition, elements of FIG. 23 having the same or similar names as elements of any other figures herein describe the same elements in other figures, can operate or run in a similar manner as in other figures, may include the same components, and may be linked to other entities, such as those described elsewhere herein, but not limited thereto. Graphics application 2310 and operating system 2320 are each executed in system memory 2350 of the data processing system.

The 3D graphics application 2310 may include one or more shader programs including shader instructions 2312. The shader language instructions may be in a high-level shader language, such as Direct3D's High-Level Shader Language (HLSL), OpenGL Shader Language (GLSL), etc. The application may also include executable instructions 2314 in a machine language suitable for execution by a general purpose processor core 2334. The application may also include graphics objects 2316 defined by vertex data.

The operating system 2320 may be a system from Microsoft Corporation. An operating system, a proprietary UNIX-like operating system, or an open source UNIX-like operating system using a variant of the Linux kernel. The operating system 2320 may support a graphics API 2322, such as a Direct3D API, an OpenGL API, or a Vulkan API. When the Direct3D API is in use, the operating system 2320 uses a front-end shader compiler 2324 to compile any shader instructions 2312 using HLSL into a lower-level shader language. The compilation may be just-in-time (JIT) compilation or application executable shader precompilation. During the compilation of the 3D graphics application 2310, high-level shaders may be compiled into low-level shaders. The shader instructions 2312 may be provided in an intermediate form, such as a version of the Standard Portable Intermediate Representation (SPIR) used by the Vulkan API.

The user mode graphics driver 2326 may include a backend shader compiler 2327 to compile shader instructions 2312 into a hardware specific representation. When the OpenGL API is in use, shader instructions 2312 in the GLSL high level language are passed to the user mode graphics driver 2326 for compilation. The user mode graphics driver 2326 may use operating system kernel mode functions 2328 to communicate with the kernel mode graphics driver 2329. The kernel mode graphics driver 2329 may communicate with the graphics processor 2332 to dispatch commands and instructions.

IP core implementation

One or more aspects may be implemented by representative code stored on a machine-readable medium that represents and/or defines logic within an integrated circuit (such as a processor). For example, a machine-readable medium may include instructions representing various logic within a processor. When read by a machine, the instructions may cause the machine to manufacture logic for performing the techniques described herein. Such representations (referred to as "IP cores") are reusable units of logic for an integrated circuit that can be stored on a tangible, machine-readable medium as a hardware model describing the structure of the integrated circuit. The hardware model may be supplied to each customer or manufacturing facility that loads the hardware model on a manufacturing machine that manufactures the integrated circuit. The integrated circuit may be manufactured so that the circuit performs the operations described in association with any of the embodiments described herein.

FIG. 24A is a block diagram illustrating an IP core development system 2400 that can be used to manufacture an integrated circuit to perform operations according to an embodiment. The IP core development system 2400 can be used to generate a modular, reusable design that can be incorporated into a larger design or used to build an entire integrated circuit (e.g., a SOC integrated circuit). The design facility 2430 can generate a software simulation 2410 of the IP core design using a high-level programming language (e.g., C/C++). The software simulation 2410 can be used to design, test, and verify the behavior of the IP core using a simulation model 2412. The simulation model 2412 can include functional simulation, behavioral simulation, and/or timing simulation. A register transfer level (RTL) design 2415 can then be created or synthesized from the simulation model 2412. The RTL design 2415 is an abstraction of the behavior of an integrated circuit (including associated logic executed using the modeled digital signals) that models the flow of digital signals between hardware registers. In addition to the RTL design 2415, a lower level design at the logic level or transistor level can also be created, designed, or synthesized. Thus, the specific details of the initial design and simulation can be different.

The RTL design 2415 or equivalent may be further synthesized by the design facility into a hardware model 2420, which may be in a hardware description language (HDL) or some other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. The IP core design may be stored using a non-volatile memory 2440 (e.g., a hard disk, flash memory, or any non-volatile storage medium) for delivery to a third-party manufacturing facility 2465. Alternatively, the IP core design may be transmitted via a wired connection 2450 or a wireless connection 2460 (e.g., via the Internet). The manufacturing facility 2465 may then manufacture an integrated circuit based at least in part on the IP core design. The manufactured integrated circuit may be configured to perform operations according to at least one embodiment described herein.

24B illustrates a cross-sectional side view of an integrated circuit package assembly 2470. The integrated circuit package assembly 2470 illustrates an implementation of one or more processors or accelerator devices as described herein. The package assembly 2470 includes a plurality of hardware logic units 2472, 2474 connected to a substrate 2480. The logic 2472, 2474 may be implemented at least in part in configurable logic or fixed-function logic hardware, and may include one or more portions of any of the (one or more) processor cores, (one or more) graphics processors, or other accelerator devices described herein. Each logic unit 2472, 2474 may be implemented within a semiconductor die and coupled to the substrate 2480 via an interconnect organization 2473. The interconnect organization 2473 may be configured to route electrical signals between the logic 2472, 2474 and the substrate 2480, and may include interconnects such as, but not limited to, bumps or pillars. The interconnection organization 2473 can be configured to route electrical signals, such as, for example, input/output (I/O) signals and/or power or ground signals associated with the operation of the logic 2472, 2474. Optionally, the substrate 2480 can be an epoxy-based laminate substrate. The substrate 2480 can also include other suitable types of substrates. The package assembly 2470 can be connected to other electrical devices via the package interconnect 2483. The package interconnect 2483 can be coupled to the surface of the substrate 2480 to route electrical signals to other electrical devices, such as a motherboard, other chipsets, or multi-chip modules.

The logic units 2472, 2474 may be electrically coupled to a bridge 2482 configured to route electrical signals between the logic 2472 and the logic 2474. The bridge 2482 may be a dense interconnection fabric that provides routing for electrical signals. The bridge 2482 may include a bridge substrate composed of glass or a suitable semiconductor material. Circuit features may be formed on the bridge substrate to provide a chip-to-chip connection between the logic 2472 and the logic 2474.

Although two logic units 2472, 2474 and bridge 2482 are illustrated, the embodiments described herein may include more or fewer logic units on one or more dies. The one or more dies may be connected by zero or more bridges, as bridge 2482 may be excluded when the logic is included on a single die. Alternatively, multiple dies or logic units may be connected by one or more bridges. In addition, multiple logic units, dies, and bridges may be connected together in other possible configurations, including three-dimensional configurations.

FIG24C illustrates a package assembly 2490 including a hardware logic chiplet of multiple units connected to a substrate 2480 (e.g., a base die). A graphics processing unit, parallel processor, and/or computing accelerator as described herein may be composed of various silicon chiplets manufactured separately. In this context, a chiplet is an integrated circuit that is at least partially packaged and includes different logic units that can be assembled into a larger package with other chiplets. Chipsets with various sets of different IP core logic can be assembled into a single device. In addition, chiplets can be integrated into a base die or base chiplet using active interposer technology. The concepts described herein enable interconnection and communication between different forms of IP within a GPU. IP cores can be manufactured using different process technologies and constructed during manufacturing, which avoids the complexity of converging multiple IPs into the same manufacturing process, especially for large SoCs with several styles of IP. Allowing the use of multiple process technologies improves time to market and provides a cost-effective method to create multiple product SKUs. Furthermore, decomposed IP is more easily modified to be independently power gated, and components not in use for a given workload can be shut down, thereby reducing overall power consumption.

In various embodiments, the package assembly 2490 may include a fewer or greater number of components and chiplets interconnected by structures 2485 or one or more bridges 2487. The chiplets within the package assembly 2490 may have a 2.5D arrangement using chip-on-wafer-on-substrate stacking, where multiple dies are stacked side-by-side on a silicon interposer that includes through-silicon vias (TSVs) to couple the chiplets with a substrate 2480 that includes electrical connections to the package interconnects 2483.

In one embodiment, the silicon interposer is an active interposer 2489 that includes embedded logic in addition to TSVs. In such embodiments, the chiplets within the package assembly 2490 are arranged on top of the active interposer 2489 using 3D face-to-face die stacking. The active interposer 2489 may include hardware logic for I/O 2491, cache memory 2492, and other hardware logic 2493 in addition to the interconnect structure 2485 and the silicon bridge 2487. The structure 2485 enables communication between the various logic chiplets 2472, 2474 and the logic 2491, 2493 within the active interposer 2489. The structure 2485 can be a NoC interconnect or another form of packet switching structure that exchanges data packets between components of the package assembly. For complex components, the structure 2485 can be a dedicated chiplet that enables communication between the hardware logics of the package assembly 2490.

A bridge structure 2487 within the active interposer 2489 may be used to facilitate point-to-point interconnection between, for example, a logic or I/O chiplet 2474 and a memory chiplet 2475. In some implementations, the bridge structure 2487 may also be embedded within the substrate 2480.

The hardware logic chiplets may include dedicated hardware logic chiplets 2472, logic or I/O chiplets 2474, and/or memory chiplets 2475. The hardware logic chiplets 2472 and logic or I/O chiplets 2474 may be implemented at least in part in configurable logic or fixed-function logic hardware and may include one or more portions of any of the processor core(s), graphics processor(s), parallel processors, or other accelerator devices described herein. The memory chiplets 2475 may be DRAM (e.g., GDDR, HBM) memory or cache (SRAM) memory. The cache memory 2492 within the active interposer 2489 (or substrate 2480) may act as a global cache for the package assembly 2490, as part of a distributed global cache, or as a dedicated cache for the structure 2485.

Each chiplet may be fabricated as a separate semiconductor die and may be coupled to a base die that is embedded within or coupled to a substrate 2480. Coupling to the substrate 2480 may be performed via an interconnect organization 2473. The interconnect organization 2473 may be configured to route electrical signals between various chiplets and logic within the substrate 2480. The interconnect organization 2473 may include interconnects such as, but not limited to, bumps or pillars. In some embodiments, the interconnect organization 2473 may be configured to route electrical signals, such as, for example, input/output (I/O) signals and/or power or ground signals associated with the operation of logic, I/O, and memory chiplets. In one embodiment, an additional interconnect organization couples the active interposer 2489 to the substrate 2480.

Substrate 2480 may be an epoxy-based laminate substrate, however, it is not limited thereto, and substrate 2480 may also include other suitable types of substrates. Package assembly 2490 may be connected to other electrical devices via package interconnect 2483. Package interconnect 2483 may be coupled to the surface of substrate 2480 to route electrical signals to other electrical devices, such as a motherboard, other chipsets, or multi-chip modules.

The logic or I/O chiplet 2474 and the memory chiplet 2475 can be electrically coupled via a bridge 2487, which is configured to route electrical signals between the logic or I/O chiplet 2474 and the memory chiplet 2475. The bridge 2487 can be a dense interconnect organization that provides routing for electrical signals. The bridge 2487 may include a bridge substrate composed of glass or a suitable semiconductor material. Circuit features may be formed on the bridge substrate to provide chip-to-chip connections between the logic or I/O chiplet 2474 and the memory chiplet 2475. The bridge 2487 may also be referred to as a silicon bridge or an interconnect bridge. For example, the bridge 2487 is an embedded multi-die interconnect bridge (Embedded Multi-die Interconnect Bridge, EMIB). Alternatively, the bridge 2487 may simply be a direct connection from one chiplet to another chiplet.

24D illustrates a package assembly 2494 including interchangeable chiplets 2495 according to an embodiment. Interchangeable chiplets 2495 can be assembled into standardized sockets on one or more base chiplets 2496, 2498. The base chiplets 2496, 2498 can be coupled via a bridge interconnect 2497, which can be similar to other bridge interconnects described herein and can be, for example, EMIB. Memory chiplets can also be connected to logic or I/O chiplets via a bridge interconnect. The I/O and logic chiplets can communicate via an interconnect structure. The base chiplets can each support one or more sockets in a standardized format for one of logic or I/O or memory/cache.

The SRAM and power delivery circuits may be fabricated into one or more of the base chiplets 2496, 2498, which may be fabricated using a different process technology relative to the interchangeable chiplets 2495, which are stacked on top of the base chiplets. For example, the base chiplets 2496, 2498 may be fabricated using a larger process technology while the interchangeable chiplets may be fabricated using a smaller process technology. One or more of the interchangeable chiplets 2495 may be memory (e.g., DRAM) chiplets. Different memory densities may be selected for the package assembly 2494 based on power and/or performance for the product using the package assembly 2494. In addition, logic chiplets with different numbers of types of functional units may be selected at assembly time based on power and/or performance for the product. In addition, chiplets containing IP logic cores of different types may be inserted into interchangeable chiplet sockets, thereby enabling hybrid processor designs that can mix and match IP blocks of different technologies.

Exemplary System-on-Chip Integrated Circuit

Figures 25-26B illustrate exemplary integrated circuits and associated graphics processors that can be manufactured using one or more IP cores. In addition to what is illustrated, other logic and circuits may be included, including additional graphics processors/cores, peripheral interface controllers, or general purpose processor cores. Elements of Figures 25-26B with the same or similar names as elements of any other figure herein describe the same elements as in the other figures, can operate or function in a similar manner as in the other figures, may include the same components, and may be linked to other entities, such as, but not limited to, those described elsewhere herein.

FIG. 25 is a block diagram illustrating an exemplary system-on-chip integrated circuit 2500 that can be manufactured using one or more IP cores. The exemplary integrated circuit 2500 includes one or more application processors 2505 (e.g., CPUs), at least one graphics processor 2510, which can be a variation of the graphics processors 1408, 1508, 2510, or can be any graphics processor described herein and can be used in place of any of the described graphics processors. Therefore, the disclosure of any feature in conjunction with a graphics processor herein also discloses the corresponding combination with the graphics processor 2510, but is not limited thereto. The integrated circuit 2500 may additionally include an image processor 2515 and/or a video processor 2520, either of which can be a modular IP core from the same design facility or multiple different design facilities. The integrated circuit 2500 may include peripheral or bus logic, including a USB controller 2525, a UART controller 2530, a SPI/SDIO controller 2535, and an I2S/I2C controller 2540. In addition, the integrated circuit may include a display device 2545 coupled to one or more of a high-definition multimedia interface (HDMI) controller 2550 and a mobile industry processor interface (MIPI) display interface 2555. Storage may be provided by a flash memory subsystem 2560 (including flash memory and a flash memory controller). A memory interface may be provided via a memory controller 2565 to obtain access to SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 2570.

Figures 26A-26B are block diagrams illustrating an exemplary graphics processor for use within a SoC according to an embodiment described herein. The illustrated graphics processor may be a variant of graphics processor 1408, 1508, 2510, or any other graphics processor described herein. The graphics processor may be used in place of graphics processor 1408, 1508, 2510, or any other graphics processor in the graphics processor described herein. Therefore, the disclosure of any feature in conjunction with graphics processor 1408, 1508, 2510, or any other graphics processor in the graphics processor described herein also discloses the corresponding combination with the graphics processor of Figures 26A-26B, but is not limited thereto. Figure 26A illustrates an exemplary graphics processor 2610 of a system-on-chip integrated circuit that can be manufactured using one or more IP cores according to an embodiment. Figure 26B illustrates an additional exemplary graphics processor 2640 of a system-on-chip integrated circuit that can be manufactured using one or more IP cores according to an embodiment. The graphics processor 2610 of Figure 26A is an example of a low-power graphics processor core. Graphics processor 2640 of Figure 26B is an example of a higher performance graphics processor core. For example, as mentioned at the beginning of this paragraph, each of graphics processors 2610 and graphics processor 2640 may be a variation of graphics processor 2510 of Figure 25 .

As shown in FIG. 26A , the graphics processor 2610 includes a vertex processor 2605 and one or more fragment processors 2615A-2615N (e.g., 2615A, 2615B, 2615C, 2615D, up to 2615N-1 and 2615N). The graphics processor 2610 can execute different shader programs via separate logic, so that the vertex processor 2605 is optimized to perform operations for the vertex shader program, while the one or more fragment processors 2615A-2615N perform fragment (e.g., pixel) shading operations for the fragment or pixel shader program. The vertex processor 2605 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. (One or more) fragment processors 2615A-2615N use the primitive data and vertex data generated by the vertex processor 2605 to generate a frame buffer that is displayed on a display device. The fragment processor(s) 2615A-2615N may be optimized to execute fragment shader programs as provided in the OpenGL API, which may be used to perform similar operations as pixel shader programs as provided in the Direct3D API.

The graphics processor 2610 additionally includes one or more memory management units (MMUs) 2620A-2620B, cache(s) 2625A-2625B, and circuit interconnect(s) 2630A-2630B. The one or more MMUs 2620A-2620B provide virtual to physical address mappings for the graphics processor 2610 (including for the vertex processor 2605 and/or the fragment processor(s) 2615A-2615N), which may reference vertex data or image/texture data stored in memory in addition to vertex data or image/texture data stored in the one or more caches 2625A-2625B. One or more MMUs 2620A-2620B can be synchronized with other MMUs within the system so that each processor 2505-2520 can participate in a shared or unified virtual memory system, and other MMUs within the system include one or more MMUs associated with one or more application processors 2505, image processors 2515, and/or video processors 2520 of Figure 25. The components of the graphics processor 2610 may correspond to the components of other graphics processors described herein. One or more MMUs 2620A-2620B may correspond to the MMU 245 of Figure 2C. The vertex processor 2605 and the fragment processor 2615A-2515N may correspond to the graphics multiprocessor 234. According to an embodiment, one or more circuit interconnects 2630A-2630B enable the graphics processor 2610 to interface with other IP cores within the SoC via the internal bus of the SoC or via a direct connection. One or more circuit interconnects 2630A-2630B may correspond to the data crossbar switch 240 of Figure 2C. Further correspondence may be found between similar components of graphics processor 2610 and the various graphics processor architectures described herein.

As shown in FIG. 26B , graphics processor 2640 includes one or more MMUs 2620A-2620B, caches 2625A-2625B, and circuit interconnects 2630A-2630B of graphics processor 2610 of FIG. 26A . Graphics processor 2640 includes one or more shader cores 2655A-2655N (e.g., 2655A, 2655B, 26555C, 2655D, 2655E, 2655F, all the way to 2655N-1 and 2655N) that provide a unified shader core architecture in which a single core or type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and/or compute shaders. The exact number of shader cores present may vary depending on the embodiment and implementation. In addition, the graphics processor 2640 includes an inter-core task manager 2645 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 2655A-2655N and a tiling unit 2658 for accelerating tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, for example to exploit local spatial coherence within a scene or to optimize the use of internal caches. The shader cores 2655A-2655N may correspond, for example, to the graphics multiprocessor 234 in FIG. 2D, or to the graphics multiprocessors 325, 350 of FIGS. 3A and 3B, respectively, or to the multi-core group 365A of FIG. 3C.

Tensor acceleration logic for graphics and machine learning workloads

FIG27 is a block diagram of a data processing system 2700 according to an embodiment. The data processing system 2700 is a heterogeneous processing system having a processor 2702, a unified memory 2710, and a GPGPU 2720, including machine learning acceleration logic. The processor 2702 and the GPGPU 2720 may be any of the processors and GPGPU/parallel processors described herein. For example, with additional reference to FIG1, the processor 2702 may be a variant of a processor in the illustrated one or more processors 102 and/or share an architecture with the processor, and the GPGPU 2720 may be a variant of a parallel processor in the illustrated one or more parallel processors 112 and/or share an architecture with the parallel processor. With additional reference to FIG4, the processor 2702 may be a variant of a processor in the illustrated (one or more) processors 1402 and/or share an architecture with the processor, and the GPGPU 2720 may be a variant of a graphics processor in the illustrated (one or more) graphics processors 1408 and/or share an architecture with the graphics processor.

The processor 2702 may execute instructions of a compiler 2715 stored in the system memory 2712. The compiler 2715 is executed on the processor 2702 to compile the source code 2714A into the compiled code 2714B. The compiled code 2714B may include instructions that may be executed by the processor 2702 and/or instructions that may be executed by the GPGPU 2720. A shader or compute program compiler (such as, for example, the shader compiler 2327 and/or the shader compiler 2324 in FIG. 23) may be used to facilitate the compilation of instructions to be executed by the GPGPU. During compilation, the compiler 2715 may perform operations of inserting metadata including hints about the level of data parallelism present in the compiled code 2714B and/or hints about data locality associated with threads to be dispatched based on the compiled code 2714B. The compiler 2715 may include the information required to perform such operations, or the operations may be performed with the aid of a runtime library 2716. The runtime library 2716 may also assist the compiler 2715 in compiling the source code 2714A and may also include instructions that are linked with the compiled code 2714B at runtime to facilitate execution of the compiled instructions on the GPGPU 2720. The compiler 2715 may also facilitate register allocation of variables via a register allocator (RA) and generate load and store instructions to move data of a variable between memory and the registers assigned to the variable.

Unified memory 2710 represents a unified address space that is accessible by processor 2702 and GPGPU 2720. Unified memory may include system memory 2712 and GPGPU memory 2718. GPGPU memory 2718 is memory within the address space of GPGPU 2720 and may include some or all of system memory 2712. In one embodiment, compiled code 2714B stored in system memory 2712 may be mapped to GPGPU memory 2718 for access by GPGPU 2720. GPGPU memory 2718 also includes GPGPU local memory 2728 of GPGPU 2720. GPGPU local memory 2728 may include, for example, HBM or GDDR memory.

GPGPU 2720 includes multiple computing blocks 2724A-2724N, which may include one or more of the various processing resources described herein. Processing resources can be or include a variety of different computing resources, such as, for example, execution units, computing units, streaming multiprocessors, graphics multiprocessors, or multi-core groups. In one embodiment, GPGPU 2720 additionally includes a tensor accelerator 2723 (e.g., a matrix accelerator), which may include one or more special function computing units designed to accelerate a subset of matrix operations (e.g., dot products, etc.). Tensor accelerator 2723 may also be referred to as a tensor accelerator or tensor core. In one embodiment, the logic components within tensor accelerator 2723 may be distributed across the processing resources of multiple computing blocks 2724A-2724N.

GPGPU 2720 may also include a collection of resources that may be shared by compute blocks 2724A-2724N and tensor accelerator 2723, including, but not limited to, cache 2727, power and performance module 2726, and a collection of registers 2725. In one embodiment, registers 2725 include directly and indirectly accessible registers, wherein the indirectly accessible registers are optimized for use by tensor accelerator 2723. Power and performance module 2726 may be configured to adjust the power delivery and clock frequency of compute blocks 2724A-2724N to power gate idle components within compute blocks 2724A-2724N. In various embodiments, cache 2727 may include an instruction cache and/or a lower level data cache.

GPGPU 2720 may additionally include an L3 data cache 2730, which may be used to cache data accessed from unified memory 2710 by tensor accelerator 2723 and/or computing elements within compute blocks 2724A-2724N. In one embodiment, L3 data cache 2730 includes shared local memory 2732, which may be shared by computing elements within compute blocks 2724A-2724N and tensor accelerator 2723.

In one embodiment, the GPGPU 2720 includes instruction handling logic, such as a fetch and decode unit 2721 and a scheduler controller 2722. The fetch and decode unit 2721 includes a fetch unit and a decode unit to fetch and decode instructions for execution by one or more of the tensor accelerator 2723 or the compute blocks 2724A-2724N. Instructions can be dispatched to appropriate functional units within the tensor accelerator or the compute blocks 2724A-2724N via the scheduler controller 2722. In one embodiment, the scheduler controller 2722 is an ASIC configurable to perform advanced scheduling operations. In one embodiment, the scheduler controller 2722 is a microcontroller or a low-energy per-instruction processing core capable of executing scheduler instructions loaded from a firmware module.

In one embodiment, some functions to be performed by the computational blocks 2724A-2724N may be directly scheduled or migrated to the tensor accelerator 2723. In various embodiments, the tensor accelerator 2723 includes processing element logic configured to efficiently perform matrix computation operations, such as multiplication and addition operations and dot product operations used by 3D graphics or computational shader programs. In one embodiment, the tensor accelerator 2723 may be configured to accelerate operations used by a machine learning framework. In one embodiment, the tensor accelerator 2723 is a dedicated integrated circuit that is explicitly configured to perform a specific set of parallel matrix multiplication and/or addition operations. In one embodiment, the tensor accelerator 2723 is a field programmable gate array (FPGA) that provides fixed-function logic that can be updated between workloads. In one embodiment, the set of computational operations that can be performed by the tensor accelerator 2723 may be limited relative to the operations that can be performed by the computational blocks 2724A-2724N. However, tensor accelerator 2723 can perform parallel tensor operations at a significantly higher throughput relative to compute blocks 2724A-2724N.

Figures 28A-28B illustrate matrix operations 2805 performed by the instruction pipeline 2800, according to an embodiment. Figure 28A illustrates the instruction pipeline 2800 when configured with a systolic array 2808 within a tensor accelerator 2723. Figure 28B illustrates the instruction pipeline when configured with graphics processor cores 2810A-2810N each including a matrix engine 2812A-2812N.

28A, the instruction pipeline 2800 may be configured to perform a matrix operation 2805, such as but not limited to a dot product operation. The dot product of two vectors is a scalar value that is equal to the sum of the products of the corresponding components of the vectors.

The dot product may be calculated as shown in equation (1) below.

The dot product can be used in the convolution operation of a convolutional neural network (CNN). Although a 2D convolution is shown, an N-dimensional convolution can be performed on an N-dimensional volume using an N-dimensional filter. The receptive field sheet 2802 highlights a portion of the input volume in the input volume buffer 2804. The input volume buffer can be stored in a memory 2830. A dot product matrix operation 2805 can be performed between the data in the receptive field sheet 2802 and the convolution filter to generate data points in the output buffer 2806, which can also be stored in the memory 2830. The memory 2830 can be any of the memories described herein, including the system memory 2712, the GPGPU memory 2718, or one or more cache memories 2727, 2730 as shown in Figure 27.

The combination of data points within the output buffer 2806 represents an activation map generated by the convolution operation. Each point within the activation map is generated by sliding a receptive field slice across the input volume buffer 2804. The activation map data may be input to an activation function to determine an output activation value. In one embodiment, the convolution of the input volume buffer 2804 may be defined within the framework as a high-level matrix operation 2805. The high-level matrix operation can be performed via primitive operations such as basic linear algebra subroutines (BLAS) operations. Primitive operations may be accelerated via hardware instructions executed by the instruction pipeline 2800.

The instruction pipeline 2800 for accelerating hardware instructions may include: an instruction acquisition and decoding unit 2721, which can acquire and decode hardware instructions; and a scheduler controller 2722, which can schedule decoded instructions to one or more processing resources within the tensor accelerator 2723 and/or the computing blocks 2724A-2724N. In one embodiment, the hardware instructions may be scheduled to the computing blocks 2724A-2724N and migrated to the tensor accelerator 2723. One or more hardware instructions and associated data for performing the matrix operation 2805 may be stored in the memory 2830. The output of the hardware instructions may also be stored in the memory 2830.

In one embodiment, the tensor accelerator 2723 can execute one or more hardware instructions to perform matrix operations 2805 using a systolic array 2808 of processing elements. The systolic array 2808 includes a combination of programmable and fixed-function hardware that can be configured to perform matrix-matrix and matrix-vector dot product operations and other operations such as matrix-matrix and matrix-vector fused multiply-add operations. The systolic array 2808 includes an array of matrix engines, each of which can be configured similarly to the matrix engine 1803 of FIG. 18C.

In various embodiments, as an alternative or in addition to the tensor accelerator 2723, matrix acceleration logic may also be included in the processing resources of the computing blocks 2724A-2724N. For example, as shown in FIG. 28B, in one embodiment, each computing block (e.g., computing block 2724N) includes an array of graphics cores 2810A-2810N. Each graphics core in the array of graphics cores 2810A-2810N may include a matrix accelerator 2812A-2812N. In one embodiment, the graphics cores 2810A-2810N are graphics cores 1815A-1815N such as in FIG. 18A, and the matrix accelerators 2812A-2812N include a version of the matrix engine 1803 of FIG. 18C. The scheduler controller 2722 may schedule matrix operations (dot products, fused multiply-adds, etc.) to available matrix accelerators 2812A-2812N within the graphics cores 2810A-2810N of the various compute blocks 2724A-2724N.

While in one embodiment, each of the compute blocks 2724A-2724N includes an array of graphics cores 2810A-2810N, in another embodiment, the compute blocks 2724A-2724N share the architecture of the processing clusters 214A-214N having the array of processing clusters in FIG. 2A. In such embodiments, the compute blocks 2724A-2724N include multiple graphics multiprocessors 234 as in FIG. 2C, which include internal components as illustrated in FIG. 2D. Thus, the graphics multiprocessor within the compute block may include a load/store unit 266, a GPGPU core 262, and a tensor/RT core 263. In one embodiment, the compute blocks 2724A-2724N may include the multi-core group 365A-365N of the GPU 380 of FIG. 3C, and include multiple sets of GFX cores 370, tensor cores 371, and ray tracing cores 372. In such embodiments, the scheduler controller 2722 can schedule instructions to perform matrix operations to the tensor/RT core 263 and/or tensor core 371 within the computing blocks 2724A-2724N. Accelerated matrix operations include dot product operations, matrix multiplication operations, and/or fused multiply-add operations, which can be performed on integer or floating-point matrix elements and various levels of precision. Additionally, in one embodiment, the computing blocks 2724A-2724N may include variants of the computing units 1560A-1560N of FIG. 15C, wherein such variants include matrix acceleration logic (e.g., systolic arrays, tensor cores, systolic tensor cores) as described herein, which can execute integer or floating-point matrix acceleration instructions. In each configuration, the processing elements within each computing block 2724A-2724N can collaborate to execute a cluster of thread blocks of a kernel program.

FIG. 29 illustrates a compute block 2900 including decomposed systolic logic enabled by a codec. In one embodiment, rather than including a systolic array 2808 in a separate tensor accelerator 2723 or a matrix engine 2812A-2812N in each graphics core 2815A-2815N as in FIG. 28A , a decomposed set of systolic arrays 2912A-2912B may be included in a compute block 2900 similar to one of the compute blocks 2724A-2724N of FIG. 27 . The compute block 2900 may include a plurality of interconnected processing resources (PRs 2908A-2908O) that may be similar to any of the processing resource architectures described herein, such as, but not limited to, the processing resources described herein. In one embodiment, the systolic arrays 2912A-2912B include codecs 2924A-2924B that enable encoding and decoding of input and output data received for processing.

The systolic arrays 2912A-2912B include a W-wide and D-deep network of data processing elements that can be used to perform vector or other data parallel operations in a systolic manner, similar to other systolic arrays described herein. In one embodiment, the systolic arrays 2912A-2912B may be configured to perform matrix operations, such as matrix dot product operations. In one embodiment, the systolic arrays 2912A-2912B support 16-bit and 8-bit floating point operations as well as 8-bit and 4-bit integer operations, ternary operations, binary, bipolar binary, ternary, and one-hot bit operations. In one embodiment, the systolic arrays 2912A-2912B may be configured to accelerate machine learning operations. In such embodiments, the systolic arrays 2912A-2912B may be configured with support for the brain float (bfloat) 16-bit floating point format. By including the systolic arrays 2912A-2912B within the compute block 2900 but outside the PRs 2908A-2908O, the size and number of systolic arrays 2912A-2912B can be scaled independently of the number of PRs 2908A-2908O. Additionally, communication bandwidth within the PRs that would otherwise be consumed by systolic array activity can be saved. Furthermore, the systolic arrays 2912A-2912B can be clock/power gated when matrix workloads are not being executed.

The communication between the systolic arrays 2912A-2912B and the PRs 2908A-2908O may be performed via a cache or shared local memory (cache/SLM 2910) and/or a shared register file 2914. In one embodiment, rather than a distinct shared register file 2914, the cache/SLM 2910 may be partitioned for use as a shared register file. The shared register file 2914 may be constructed similarly to other GPGPU register files described herein. The shared register file may also include a set of special registers that are used to configure the interaction between the systolic arrays 2912A-2912B and the PRs 2908A-2908O. The cache/LM 2910 may be a block of an L1 cache, an L2 cache, and/or an explicitly addressable on-die memory.

Matrix data for processing by the systolic arrays 2912A-2912B may be stored in the cache/SLM 2910. Processing commands or instructions can be provided to the systolic arrays 2912A-2912B via the shared register file 2914. Processing results may be read by the PRs 2908A-2908O from the cache/SLM 2910 or from the destination/output registers within the shared register file. During operation, rather than consuming bus/structure bandwidth within the PRs 2908A-2908O, communication traffic may be directed to the systolic arrays 2912A-2912B, the cache/SLM 2910, and/or the shared register file 2914. Any of the PRs 2908A-2908O within the compute block 2900 may migrate the matrix workload to one or both systolic arrays 2912A-2912B. Messages may be sent from the PRs to the systolic arrays using commands that specify the operation to be performed and the operands of the operation. The systolic arrays 2912A-2912B may perform the requested operation (multiply/add, fused multiply/add, multiply/accumulate, dot product, etc.) and output the result to the shared register file 2914. The input, intermediate, and/or output data for the requested operation may be stored in the cache/SLM 2910, and multiple dependent operations may be chained. In one embodiment, when performing operations for training or inference of a neural network, the systolic arrays 2928A-2928B may also perform activation functions including, but not limited to, sigmoid, ReLU, and hyperbolic tangent (TanH) activations. In such embodiments, operations for the neural network may be migrated to the systolic arrays 2912A-2912B at a coarse granularity.

The PRs 2908A-2908O may provide input data to the systolic arrays 2912A-2912B in a compressed format, and the codecs 2924A-2924B may be used to decompress the data. When output data is ready to be provided to the PRs 2908A-2908O, if the PRs will perform operations and data and do not support direct reading of compressed data, the data may remain decompressed. If the PRs 2908A-2908O support reading of compressed data or will not perform additional operations on the data, the output data may be re-encoded. Zero-based encoding may be used, and compression may be enabled or disabled based on the degree of data sparsity. Alternatively, other forms of encoding may be used based on the distribution of the data to be processed or output. For example, the codecs 2924A-2924B may be configured to decode sparse data that is encoded according to zero-based compression or using another form of compression described herein (e.g., one-based, two-based, near-zero, near-one, near-two, etc.). Additional exemplary encoding or compression techniques that may be supported include unique absolute value (UAV) table encoding, significance map (SM) encoding, table encoding (TE), unique value coordinate (UVC) encoding, and mean encoding (ME). The metadata of the encoded data indicates the type of encoding format used for the data. In one embodiment, a specific encoding format may be selected for a specific type of data (such as kernel data or feature data). In one embodiment, a statistical analysis is performed on the data before encoding so that an appropriate encoder can be selected for each block of data. In one embodiment, the data generated during SM encoding may be used to facilitate the supply of compressed data to the systolic arrays 2912A-2912B. In a zero-based SM encoding mode, only non-zero values in a block are encoded. The number of non-zero values in a sample block is indicated in the header, followed by a significance map indicating the mapping of non-zero values within the block. The non-zero values of the samples are then encoded in the order of appearance within the stream.

Time-based frame generation via a time-aware machine learning model

Existing frame generation models are trained based on frame and optical flow data, but are not trained to have a concept of the amount of time that passes between frames. Described herein are techniques that perform the following operations: 1) train an interpolation/extrapolation model on frame data, optical flow data, and rendering timestamps of frames generated at a target frame rate, and 2) use the resulting model to extrapolate or interpolate frames as needed to maintain the target frame rate if the in-progress frame will not be completed before the next frame deadline. Maintaining consistent frame pacing with updated frame data for each display refresh cycle enables a smooth and responsive gameplay experience to be achieved even at lower rendering rates because time-correlated frames can be generated.

Figures 30A-30B illustrate a system for frame extrapolation and frame interpolation using a unified time-aware machine learning model according to an embodiment. Figure 30A illustrates a system 3000 for frame extrapolation based on frame data, optical flow, and rendering timestamps. Figure 30B illustrates a system 3010 for frame interpolation based on frame data, optical flow, and rendering timestamps. In general, frame extrapolation is considered to be a more difficult problem relative to frame interpolation because it predicts future frames from past frames and other inputs related to these past frames (such as optical flow between them). In contrast, frame interpolation is a relatively easier problem because it predicts intermediate frames from past and current frames. However, frame interpolation comes with a higher latency cost and may not be suitable for some use cases. By enabling frame interpolation and extrapolation, users may choose to use frame interpolation for latency-sensitive applications with higher quality requirements, and use frame extrapolation for latency-sensitive but relatively less stringent requirements for perceptible quality. Additionally, by providing rendering timestamps associated with a training frame sequence, the machine learning model is able to learn the concept of the relative amount of time that has passed between rendered frames. Once properly trained, the model can be used to interpolate between input frames or to extrapolate the next frame at a specific time relative to another frame.

30A , a system 3000 configured for frame extrapolation may load a unified neural network 3005 with extrapolation weights 3007 that are generated by training the unified neural network 3005 to extrapolate future frames based on two existing frames. A first frame 3001 (frame 1) and a second frame 3002 (frame 2) may be provided as input to the unified neural network 3005 along with an optical flow 3006 between frame 1 and frame 2. The unified neural network 3005 may then generate an extrapolated frame 3003 (frame 3).

When the unified neural network 3005 is a time-aware neural network that has been trained using training data that includes timestamps indicating the relative amount of time between frames, the unified neural network 3005 can be used to target specific relative timestamps for frame generation. For example, a target timestamp 3004 can be provided that indicates the relative amount of time after the second frame 3002 that should be represented by the extrapolated frame. A low relative timestamp would indicate that the extrapolated frame 3003 will appear closer in time to the second frame 3002 and should appear relatively close to the second frame 3002. A higher relative timestamp would indicate that the extrapolated frame 3003 should show a greater degree of convolution based on the optical flow 3006 because the frame will be displayed for a longer amount of time after the display of the second frame 3002.

30B , a system 3010 configured for frame interpolation may load a unified neural network 3005 with interpolation weights 3017 generated by training the unified neural network 3005 to interpolate an intermediate frame between two existing frames. A first frame 3011 (frame 1) and a third frame 3013 (frame 3) may be provided as input to the unified neural network 3005 along with an optical flow 3016 between frames 1 and 3. The unified neural network 3005 may then generate an interpolated frame 3012 (frame 2) between frames 1 and 3.

When the unified neural network 3005 is a time-aware neural network that has been trained using training data that includes timestamps indicating the relative amount of time between frames, the unified neural network 3005 can be used to generate frames that will be displayed at a specific target time between the first frame 3011 and the third frame 3013. For example, a target timestamp 3014 can be provided that indicates a point in time between the first frame 3011 and the third frame 3013. A low relative timestamp would indicate that the interpolated frame 3012 will appear closer in time to the first frame 3011 and should appear closer to the second frame 3002. A higher relative timestamp would indicate that the interpolated frame 3012 should appear closer to the third frame 3013.

Existing techniques are able to apply adaptive resolution or adaptive quality to hit a frame rate target. Such techniques will reduce the rendering resolution or rendering quality to enable the graphics processor to meet or exceed a predetermined frame rate target. In contrast to adaptive resolution or quality techniques, if a determination is made that an ongoing frame will not be completed in time to meet the next frame display deadline, the embodiments described herein may adaptively perform neural frame generation to meet a target frame rate. In such cases, new frames may be extrapolated based on previously rendered frames in order to be displayed at the next frame display deadline. In the case where a time-aware machine learning model is in use, a specific target timestamp may be provided to the machine learning model to indicate the time at which a generated frame will be displayed relative to the input frame.

The graphics processor may be configured to present frames for display at a predetermined rhythm, which in one embodiment corresponds to the refresh rate of the display to which the output of the graphics processor will be displayed. For example, a display with a refresh rate of 60 Hz will refresh the image 60 times per second and can display a new image every 16.6 milliseconds. A display with a refresh rate of 120 Hz will refresh the image one hundred and twenty times per second and can display a new image every 8.3 milliseconds. When vertical synchronization (Vsync) is enabled, the graphics processor is configured to synchronize the updating of frame data with the refresh rate of the display. This synchronization enables the graphics processor to update the display only when the display is ready to display a new frame (such as during the vertical blanking interval (Vblank), which is the time between the end of the last visible line of the frame and the beginning of the first visible line of the next frame). During the vertical blanking interval, the graphics processor swaps the buffer containing the newly rendered frame with the buffer currently displayed on the screen. When the display begins to refresh from the new buffer, the updated frame is displayed on the screen. This synchronization prevents visual artifacts such as screen tearing. However, if the graphics processor cannot render a new frame in time to meet the next vertical blanking interval, the previously rendered frame will be presented for the next frame. If too many frames pass before new frame data is presented to the display, stuttering may occur.

Adaptive refresh rate technology, Variable Refresh Rate (VRR), allows the display to adjust its refresh rate to match the output of the graphics card, thereby eliminating screen tearing and stuttering without the need for Vsync. While VRR enables the display to adapt to the graphics processor update cadence, it is still best for the graphics processor to meet a target frame cadence to maintain smooth and responsive gameplay. In one embodiment, this frame cadence can be set by the user, or the user can select from a set of available frame cadences supported by the graphics processor.

Figure 31 illustrates a timeline 3100 of end-to-end operation for frame rendering on a graphics processor. A key input frame is a frame corresponding to an input provided by a user of a game application (such as a local execution or a cloud-based game application). The key input 3102 received at time T1 is propagated through a game application 3104. The game application 3104 or a rendering engine associated with the game application 3104 can generate a GPU command 3106 to be placed in a rendering queue. GPU dump clearing 3108 queues the command associated with the key input 3102 behind the previously queued command in the GPU rendering queue, and the previously queued command may include a command for rendering frames F0-F3. The GPU completes rendering (GPU completion 3110) at T5, and presents frame F4 to the display at T7. When the display is timed to a vertical synchronization signal (V-sync signal 3112), the display of the frame corresponding to the key input 3102 is delayed until the V-sync event at T6. Thus, the T7-T1 wait time 3120 between the key input 3102 and the display 3114 of the key input frame is determined based on the rendering time of the key input frame and the frames that were enqueued for rendering in the rendering queue before the key input frame. Additionally note that when a new frame is not ready to be presented in time for the next display update cycle (which can be indicated by the V-sync signal 3112), the previous frame is redisplayed.

Figure 32 illustrates a timeline 3200 in which neural frame generation is used to maintain a target frame rhythm. When the presentation of a new frame by the GPU is timed to the vertical synchronization (V-sync) signal 3112 via a wait V-sync configuration, if the frame is not ready for presentation in time, the display of the frame can be delayed until the next V-sync event. When the new frame is not ready to be presented, the previous frame is redisplayed. For example, for frames in the rendering queue, frame F0 is completed in time to be displayed during the next target display update interval (as determined based on the V-blank or V-sync signal 3112 interval or a predetermined target frame rate). Frame F1 is completed in time for the next target display update interval at time T2.

However, in one embodiment, a determination is made at time T5 that frame F2 will not be completed in time for the next target display update interval. At this time, a frame generation request may be submitted to the queue of GPU/AI commands 3205 to perform neural frame generation to extrapolate frame A1 based on frame F0 and frame F1. The neural frame generation is then performed at a deterministic amount of time and completed at time T6 in time for display at time T7 (AI completion 3206). Frame A1 can be generated based on frame F0, frame F1, and a target display timestamp specifying the amount of time between when frame F1 is completed and when the generated frame A1 will be displayed (e.g., T7-T2). Frame A1 can be generated by warping frame F1 using a predicted optical flow between frame F1 and the generated frame A1, or a direct pixel generation model can be used to extrapolate frame data for frame A1 based on frame F0 and frame F1 and the optical flow between frame F0 and frame F1.

In one embodiment, if frame F2 is actually completed in time to be presented during the next target update interval, frame F2 may be displayed in place of frame A1. In one embodiment, frame data may be discarded and not used. In one embodiment, the ongoing frame F2 is preempted to enable an early start of frame F3, thereby increasing the likelihood that frame F3 will be completed before the next target display update interval. In one embodiment, the data generated for frame 2 can be used in combination with frame A1 and/or frame F1 to generate frame A2 for display during the next target display update interval. For example, given an input including completion timestamps of frames F1 and F2 and a target display time for frame A1, a time-aware machine learning model (e.g., unified neural network 3005) can then generate frame data that should be displayed at the time of the target display update interval when frame A2 will be displayed. In one embodiment, frame A2 can be generated by temporally warping frame F2 based on an estimate of the evolution of the scene at the time when frame A2 will be displayed, frame A1, frame F2 (and optionally frame F1), and the time when frame A2 will be displayed. Additional frame generation may be performed to generate frame A3 for display while rendering frame F3. The combination of generated frame A3 and rendered frame F3 may be used to generate frames A4 and A5 for display while rendering frame F4, which contains scene data responsive to the input received at time T1. Frame F4 may be displayed at the next target display update interval after completion.

Figures 33A-33B illustrate multiple GPU engines with multiple associated command buffers that can implement asynchronous rendering and computing operations. Figure 33A shows a copy engine 3310, a graphics engine 3320, and a computing engine 3330 of a GPU 3360. Figure 33B shows multithreaded inputs to multiple command queues of a GPU 3360. As shown in Figure 33A, the copy engine 3310, the graphics engine 3320, and the computing engine 3330 can independently perform workloads, and can also synchronize when the work of one engine depends on or is related to another engine. For example, the copy engine 3310 can execute a command to perform a copy resource operation 3312 to copy the resources used by the drawing operation 3324 to be performed by the graphics engine 3320. The graphics engine 3320 can perform a wait operation 3322 until a signal 3314 indicating that the copy resource operation 3312 is completed is received from the copy engine 3310. After completing the drawing operation 3324, the graphics engine 3320 may signal 3326 the compute engine 3330, which may perform a compute operation, such as the AI drawing operation 3334, to produce an AI-generated frame based on one or more previous frames. When the AI drawing operation 3334 is complete, the compute engine 3330 may then signal 3336 the graphics engine 3320. In one embodiment, the graphics engine 3320 may continue to perform the drawing operation 3328 to render additional frame data for the upcoming frame.

As shown in FIG. 33B , separate threads 3342A-3342D executed by the CPU can insert workloads into various command queues associated with the GPU 3360. The threads 3342A-3342D can be threads of software executed by other CPUs, such as graphics drivers or management or facilitation of the operation of the GPU 3360. Each thread 3342A-3342D can insert a command list (e.g., command list 3344) into any one of the copy queue 3350, the rendering queue 3352, and the calculation queue 3354. The command list 3344 can include one or more command buffers, which include commands to be executed by various engines. The copy queue 3350 is used to submit commands to the copy engine 3310. The rendering queue 3352 can include commands executed by the graphics engine 3320 and the copy engine 3310. The calculation queue 3354 can include commands executed by the calculation engine 3330, the graphics engine 3320, and the copy engine 3310.

In one embodiment, one of the threads 3342A-3342D (e.g., CPU thread 3342A) may perform workload management operations including workload execution tracking. The progress of workload execution on the various engines may be tracked based on, for example, performance and/or event monitoring circuit modules associated with the replication engine 3310, the graphics engine 3320, and the compute engine 3330. When the workload tracking logic of the thread determines that the drawing command in progress may not meet the next target display update interval, a command may be submitted asynchronously to generate an AI frame based on two or more previously rendered frames and associated optical flows. The command to generate the AI frame may be executed asynchronously on the compute engine 3330 relative to the rendering operation performed on the graphics engine 3320, where the AI frame is generated based on a set of rendered frames, the optical flow between those frames, and the target timestamp for which the generated frame is expected to be displayed.

In one embodiment, the computing engine 3330 is configured to continuously generate new frames via an AI drawing and/or frame generation model based on output from the graphics engine 3320. The rendering queue 3352 may receive a command list to render frames based on API commands submitted by the game engine of the graphics application, while the computing queue 3354 receives commands to asynchronously execute the AI drawing and/or frame generation model via the computing engine 3330 relative to the operation of the graphics engine 3320. In such embodiments, the rendered frame or the AI generated frame may be displayed to the screen, depending on a predetermined frame rhythm adjustment. The predetermined frame rhythm adjustment may, for example, be bound to a display refresh cycle while considering motion increments between frames based on real GPU timestamps rather than frame-based motion increments. In one embodiment, timestamp-based generation may be used to continuously generate new frames at a frequency synchronized with a high-frequency adaptive refresh rate. AI frame generation can be executed at a fixed ML execution cost with a deterministic execution time. AI frame generation may be configured to generate all frames for display based on a sliding window of source frames generated by the graphics engine 3320 based on commands from a game application.

In one embodiment, at least a portion of the workload execution tracking and/or asynchronous AI frame generation may be managed by the hardware, firmware, or kernel program of the GPU. For example, a permanent program code configured for execution on the GPU (such as GPU firmware executed on a graphics microcontroller or a GPGPU program executed on a dedicated GPU hardware thread) may be configured to automatically trigger the execution of an AI drawing routine based on data stored in a preconfigured memory location designed to store the most recently rendered frame and a history buffer containing one or more previous frames that have been warped and aligned based on optical flow data. In such embodiments, the most recent frame and one or more previously rendered frames are used as continuously updated source data for the AI drawing and/or frame generation model. The permanent program code can then use a timestamp-aware AI model to continuously generate frames based on the configured refresh cycle of the display to which the GPU is attached.

34 illustrates a method 3400 for generating a time-aware machine learning model, in accordance with an embodiment. The model may be generated by performing operations to train an interpolation/extrapolation frame generation model using frame data, optical flow, and timestamps associated with the frame data to generate interpolation weights for the model (3402). Further operations may be performed to train the interpolation/extrapolation frame generation model using frame data, optical flow, and timestamps associated with the frame data to generate extrapolation weights for the model (3404). The model may be deployed as an interpolation/extrapolation frame generation model capable of interpolating or extrapolating a target timestamp relative to an input frame (3406).

FIG35 illustrates a method 3500 for time-based frame generation via a time-aware machine learning model in accordance with an embodiment. A graphics processor may receive a workload to render frame data based on an API command to render a frame received from an application (3502). The workload may be received from a graphics driver associated with the application. The graphics processor may then process the workload in a command queue of a graphics engine (3504). The workload may be submitted to the command queue by the graphics driver based on the API command received from the application. During rendering, a workload management logic within the graphics processor or graphics driver may track the rendering progress of the submitted workload for the frame (3506). The workload management logic of the graphics processor may determine whether the frame in progress will meet the target display update deadline (3507). If the frame will meet the deadline (“yes” of 3507), the graphics processor may continue to execute the workload of the frame (3508), and then display the rendered frame based on the processed workload (3509). If the frame will not meet the deadline ("No" of 3507), the graphics processor may trigger neural frame generation (3510) via the graphics processor's compute engine. The graphics processor may then display the generated frame (3511).

Figure 36 illustrates a method 3600 for time-based frame generation asynchronous with a rendering rate according to an embodiment. A graphics processor can render a frame via a graphics engine based on an API command (3602). The API command associated with the 3D API can be received by a graphics driver and used to render a frame of a 3D scene associated with an application (such as a 3D game application). The graphics processor can then generate optical flow data (3604) based on the frame data, the frame data including the currently rendered frame and at least one previously rendered frame. The graphics processor can then store the frame data and the optical flow data to a predetermined location in a device memory (3606). The predetermined location is at a memory address that is known and accessible to both graphics and computing resources. Asynchronously with the rendering of a new frame via the graphics engine, frame generation logic can read the frame data and the optical flow data from the device memory (3608). The frame generation logic can be executed via a computing engine of the graphics processor. The frame generation logic can then generate a frame for display via the computing engine based on a timestamp corresponding to the next display update (3610). In this way, new frames can be generated for display at each frame update cycle based on the optical flow data and the most recently available set of frame data using a time-aware machine learning model.

FIG37 illustrates a system 3700 that maintains consistent frame pacing via time-aware frame generation. The system 3700 includes a GPU 3360 coupled to a display 3720 via a display controller 3710. The display controller is configured to provide frame data to the display 3720 at a rate determined by or proportional to the refresh rate of the display 3720. New frames can be generated via the graphics engine 3320 based at least in part on shader programs executed via graphics processing resources within the compute blocks 2900A-2900N. To increase the frame rate and provide the appearance of smooth gameplay, additional frames can be interpolated or extrapolated using a neural frame generation model that is executed via a matrix or tensor accelerator (e.g., the systolic array 2912A-2912B of FIG29) within the compute blocks 2900A-2900N. In a conventional GPU, when a new frame is not ready in time for the next update, the previously rendered frame will be re-rendered.

The system 3700 is configured to attempt to present a new frame for display at each display update interval (up to a predetermined maximum refresh rate). In one embodiment, if the rendered frame data 3702 is ready for display, the newly rendered frame is presented, otherwise the generated frame data 3708 may be displayed. For example, if a determination is made that the newly rendered frame will not be ready in time for the next display update, neural frame generation may be triggered to generate a new frame using the time-aware machine learning model described herein. In various embodiments, this determination may be made by the CPU executing workload management logic 3705A, the GPU executing workload management logic 3705B, or workload management logic 3705A-3705B (which executes on both the CPU and GPU). In one embodiment, the GPU executing workload management logic 3705B is executed via the graphics microcontroller 1533 of FIG. 15B. The determination that the newly rendered frame will not be ready in time for the next display update may be made via the graphics engine 3320 based on an estimated time for frame completion (compared to an estimated completion time for time-aware frame generation).

Since the machine learning model for frame generation is time-aware, a timestamp corresponding to the time at which the generated frame will be displayed is provided as an input to the frame generation process, allowing the machine learning model to evolve the optical flow data 3704 generated between the set of rendered frames to target a specific time between the input frames from the rendered frame data 3702 or outside the most recently rendered frame. The optical flow data 3704 can be generated using a media/OFA engine 3730 that performs media encoding/decoding operations, generates dense optical flow between input frames, or generates sparse motion vectors between input frames, where these sparse motion vectors can be expanded using motion vector expansion models that are executed via matrix or tensor accelerators within the computation blocks 2900A-2900N. A history buffer 3706 (where previous frames are warped and accumulated in time) can also be maintained to provide an additional sampling source for anti-aliasing, supersampling, or frame generation models that utilize temporal accumulated data.

In one embodiment, the system 3700 may be configured in a mode in which strict frame timing is maintained by rendering primarily or entirely from generated frame data 3708. The generated frame data 3708 is presented to the display 3720 via a display controller at predetermined intervals that can be synchronized or correlated with the update rate of the display 3720. In this mode, the time-aware machine learning model executed via computation blocks 2900A-2900N may generate new frames by warping the rendered frames according to the optical flow data evolved to a specific timestamp corresponding to the target time for display of the generated frames.

Additional Exemplary Computing Devices

38 is a block diagram of a computing device 3800 including a graphics processor 3804, according to an embodiment. A version of the computing device 3800 may be or be included in a communication device such as a set-top box (e.g., an Internet-based cable TV set-top box, etc.), a device based on a global positioning system (GPS), etc. The computing device 3800 may also be or be included in a mobile computing device such as a cellular phone, a smart phone, a personal digital assistant (PDA), a tablet computer, a laptop computer, an e-reader, a smart TV, a TV platform, a wearable device (e.g., glasses, watches, bracelets, smart cards, jewelry, clothing items, etc.), a media player, etc. For example, in one embodiment, the computing device 3800 includes a mobile computing device that employs an integrated circuit ("IC") that integrates various hardware and/or software components of the computing device 3800 on a single chip, such as a system on a chip ("SoC" or "SOC").

The computing device 3800 includes a graphics processor 3804. The graphics processor 3804 represents any graphics processor described herein. In one embodiment, the graphics processor 3804 includes a cache 3814, which can be a single cache or divided into multiple segments of cache memory, including but not limited to any number of L1, L2, L3 or L4 caches, rendering caches, depth caches, sampler caches and/or shader unit caches. In one embodiment, the cache 3814 can be a last level cache shared with the application processor 3806. In one embodiment, the computing device 3800 includes CSL logic 3812 to facilitate the sharing and transmission of data between the application processor 3806 and the graphics processor 3804. The computing device 3800 may also include hardware and software logic 3813 to enable scalable I/O virtualization (S-IOV) or single root I/O virtualization (SRIOV) to provide a virtual instance of the graphics processor 3804 to the software domain executed by the application processor 3806.

In one embodiment, the graphics processor 3804 includes a graphics microcontroller that implements the control and scheduling logic of the graphics processor. The control and scheduling logic may be firmware executed by the graphics microcontroller 3815. The firmware may be loaded at the root by the graphics driver logic 3822. The firmware may also be programmed into an electrically erasable programmable read-only memory or loaded from a flash memory device within the graphics microcontroller 3815. The firmware may be capable of including a GPU OS 3816, which includes device management logic 3817 and driver logic 3818 and a scheduler 3819. The GPU OS 3816 may also include a graphics memory manager 3820, which may supplement or replace the graphics memory manager 3821 within the graphics driver logic 3822.

The graphics processor 3804 also includes a GPGPU engine 3844, which includes one or more graphics engines, a graphics processor core, and other graphics execution resources as described herein. Such graphics execution resources can be presented in the form of, but not limited to, execution units, shader engines, fragment processors, vertex processors, graphics multiprocessors, streaming multiprocessors, graphics processor clusters, or any collection of computing resources suitable for processing graphics resources or image resources or performing general computing operations in a heterogeneous processing system including integrated or discrete graphics and/or parallel processing elements. The processing resources of the GPGPU engine 3844 may be included in multiple slices of hardware logic connected to the substrate. The GPGPU engine 3844 may include GPU slices 3845, which include graphics processing and execution resources, caches, samplers, etc. The GPU slice 3845 may also include local volatile memory, or may be coupled to one or more memory slices.

The GPGPU engine 3844 may also include one or more special slices 3846, which include, for example, a non-volatile memory slice 3856, a network processor slice 3857, and/or a general computing slice 3858. The GPGPU engine 3844 also includes a matrix multiplication accelerator 3860. The general computing slice 3858 may also include logic to accelerate matrix multiplication operations. The non-volatile memory slice 3856 may include a non-volatile memory unit and controller logic. The controller logic of the non-volatile memory slice 3856 may be managed by one of the device management logic 3817 or the driver logic 3818. The network processor slice 3857 may include network processing resources that are coupled to physical interfaces within the input/output (I/O) resources 3810 of the computing device 3800. The network processor slice 3857 may be managed by one or more of the device management logic 3817 or the driver logic 3818.

In one embodiment, the matrix multiplication accelerator 3860 is a modular scalable sparse matrix multiplication accelerator. The matrix multiplication accelerator 3860 may include multiple processing paths, each of which includes multiple pipeline stages. Each processing path can execute a separate instruction. In various embodiments, the matrix multiplication accelerator 3860 may have any one or more of the architectural features of the matrix multiplication accelerators described herein. For example, in one embodiment, the matrix multiplication accelerator 3860 is a systolic array, which can be configured to cooperate with multiples of four logical stages (e.g., four, eight, twelve, sixteen, etc.). In one embodiment, the matrix multiplication accelerator 3860 includes one or more instances of a two-path matrix multiplication accelerator with a four-stage pipeline or a four-path matrix multiplication accelerator with a two-stage pipeline. In one embodiment, the matrix multiplication accelerator 3860 includes a processing element configured as a scalable sparse matrix multiplication accelerator. The matrix multiplication accelerator 3860 can be used to accelerate the matrix operations performed via the XMX extension or promote another computing library of matrix calculation operations. As an example, the matrix multiplication accelerator 3860 may be used to perform operations associated with convolution and upconvolution/transposed convolution layers for the optical flow estimation, frame generation, and neural super-resolution networks described herein, which may be included in a time-based frame generator 3823 used by the computing device 3800. The time-based frame generator 3823 may include one or more time-aware neural networks as described herein, such as the unified neural network 3005 of FIGS. 30A-30B .

As illustrated, in one embodiment, and in addition to the graphics processor 3804, the computing device 3800 may further include any number and type of hardware components and/or software components, including but not limited to an application processor 3806, a memory 3808, and an input/output (I/O) source 3810. The application processor 3806 may interact with the hardware graphics pipeline to share the graphics pipeline functionality. The processed data is stored in a buffer in the hardware graphics pipeline, and the state information is stored in the memory 3808. The generated data may be transmitted to the display controller via a display device for output via the display device. The display device may be of various types, such as a cathode ray tube (CRT), a thin film transistor (TFT), a liquid crystal display (LCD), an organic light emitting diode (OLED) array, etc., and may be configured to display information to a user via a graphical user interface.

The application processor 3806 may include one or more processors, such as the processor(s) 102 of FIG. 1 , and may be a central processing unit (CPU) used at least in part to execute an operating system (OS) 3802 of the computing device 3800. The OS 3802 may serve as an interface between the hardware and/or physical resources of the computing device 3800 and one or more users. The OS 3802 may include driver logic for various hardware devices in the computing device 3800. The driver logic may include graphics driver logic 3822, which may include a user mode graphics driver and/or a kernel mode graphics driver. The graphics driver logic may include a graphics memory manager 3821 to manage the virtual memory address space of the graphics processor 3804. The graphics memory manager 3821 may facilitate a unified virtual address space that is accessible by the application processor 3806 and the graphics processor 3804.

It is contemplated that in some embodiments, graphics processor 3804 may exist as part of application processor 3806 (such as part of a physical CPU package), in which case at least a portion of memory 3808 may be shared by application processor 3806 and graphics processor 3804, but at least a portion of memory 3808 may be exclusive to graphics processor 3804, or graphics processor 3804 may have a separate storage location for memory. Memory 3808 may also be shared with a discrete version of graphics processor 3804 via CXL logic 3812.

Memory 3808 may include a pre-allocated area of a buffer (e.g., a frame buffer); however, it should be understood by those skilled in the art that embodiments are not limited thereto, and any memory accessible to a lower graphics pipeline may be used. Memory 3808 may include various forms of random access memory (RAM) (e.g., SDRAM, SRAM, etc.), including applications that utilize graphics processor 3804 to render a desktop or 3D graphics scene. The memory controller hub may access data in memory 3808 and forward it to graphics processor 3804 for graphics pipeline processing. Memory 3808 may be made available to other components within computing device 3800. For example, any data (e.g., input graphics data) received from various I/O sources 3810 of computing device 3800 may be temporarily queued in memory 3808 before being operated by one or more processors (e.g., application processor 3806) in an implementation of a software program or application. Similarly, data determined by the software program to be sent from computing device 3800 to an external entity through one of the computing system interfaces, or stored in an internal storage element, is typically queued temporarily in memory 3808 prior to being transmitted or stored.

The I/O sources may include devices such as a touch screen, a touch panel, a touch pad, a virtual or conventional keyboard, a virtual or conventional mouse, a port, a connector, a network device, or the like, and may be attached via a platform controller hub. Additionally, the I/O source 3810 may include one or more I/O devices (e.g., a networking adapter) that are implemented to transfer data to and/or from the computing device 3800; or for large-scale non-volatile storage devices (e.g., SSD/HDD) within the computing device 3800. User input devices (including alphanumeric and other keys) may be used to pass information and command selections to the graphics processor 3804. Another type of user input device is a cursor control, such as a mouse, trackball, touch screen, touch pad, or cursor direction keys to pass direction information and command selections to the GPU and control cursor movement on the display device. The camera and microphone array of the computing device 3800 may be used to observe gestures, record audio and video, and receive and transmit visual and audio commands.

The I/O source 3810 may include one or more network interfaces. The network interface may include associated network processing logic, and/or be coupled to a network processing slice 3857. The one or more network interfaces may provide access to a LAN, a wide area network (WAN), a metropolitan area network (MAN), a personal area network (PAN), Bluetooth, a cloud network, a cellular or mobile network (e.g., 3rd generation (3G), 4th generation (4G), 5th generation (5G), etc.), an intranet, the Internet, etc.). The (one or more) network interfaces may include, for example, a wireless network interface having one or more antennas. The (one or more) network interfaces may also include, for example, a wired network interface to communicate with a remote device via a network cable, which may be, for example, an Ethernet cable, a coaxial cable, a fiber optic cable, a serial cable, or a parallel cable.

The network interface(s) may provide access to a LAN, for example, by complying with the IEEE 802.11 standard, and/or the wireless network interface may provide access to a personal area network, for example, by complying with the Bluetooth standard. Other wireless network interfaces and/or protocols may also be supported, including previous and subsequent versions of the standards. In addition to or in lieu of communication via the wireless LAN standard, the network interface(s) may provide wireless communication using, for example, a time division multiple access (TDMA) protocol, a global system for mobile communications (GSM) protocol, a code division multiple access (CDMA) protocol, and/or any other type of wireless communication protocol.

It is to be appreciated that the system less or more equipped than in the above-described example may be preferred for some implementations.Therefore, the configuration of the computing device described herein may vary from implementation to implementation according to many factors, such as price constraints, performance requirements, technical improvements or other environments.Examples (without limitation) include mobile devices, personal digital assistants, mobile computing devices, smart phones, cellular phones, mobile phones, one-way pagers, two-way pagers, messaging devices, computers, personal computers (PCs), desktop computers, laptop computers, notebook computers, handheld computers, tablet computers, servers, server arrays or server farms, web servers, network servers, Internet servers, workstations, microcomputers, mainframe computers, supercomputers, network appliances, web appliances, distributed computing systems, multiprocessor systems, systems based on processors, consumer electronics, programmable consumer electronics, television sets, digital television sets, set-top boxes, wireless access points, base stations, subscriber stations, mobile subscriber centers, radio network controllers, routers, hubs, gateways, bridges, switches, machines or combinations thereof.

Embodiments may be provided, for example, as a computer program product that may include one or more machine-readable media having machine-executable instructions stored thereon that, when executed by one or more machines (such as a computer, a network of computers, or other electronic devices), may cause the one or more machines to perform operations according to the embodiments described herein. Machine-readable media may include, but are not limited to, floppy disks, optical disks, CD-ROMs (compact disk read-only memory) and magneto-optical disks, ROMs, RAMs, EPROMs (erasable programmable read-only memory), EEPROMs (electrically erasable programmable read-only memory), magnetic or optical cards, flash memory, or other types of media/machine-readable media suitable for storing machine-executable instructions.

In addition, embodiments may be downloaded as a computer program product, wherein the program may be transmitted from a remote computer (e.g., a server) to a requesting computer (e.g., a client) via a communication link (e.g., a modem and/or a network connection) by one or more data signals embodied in and/or modulated by a carrier wave or other propagation medium.

In this document, the term "user" may be referred to interchangeably as "viewer," "observer," "person," "individual," "end-user," and/or the like throughout. Note that in this document, terms like "graphics domain" may be referred to interchangeably as "graphics processing unit," "graphics processor," or simply "GPU" throughout, and similarly, "CPU domain" or "host domain" may be referred to interchangeably as "computer processing unit," "application processor," or simply "CPU."

It is to be noted that terms like "node", "computing node", "server", "server device", "cloud computer", "cloud server", "cloud server computer", "machine", "host machine", "device", "computing device", "computer", "computing system" and the like may be used interchangeably throughout this document. It is to be further noted that terms like "application", "software application", "program", "software program", "package", "software package" and the like may be used interchangeably throughout this document. In addition, terms like "job", "input", "request", "message" and the like may be used interchangeably throughout this document.

It is contemplated that terms such as "request,""query,""job,""work,""workitem," and "workload" may be referred to interchangeably throughout this document. Similarly, an "application" or "agent" may refer to or include a computer program, software application, game, workstation application, etc., provided through an application programming interface (API), such as a free rendering API, such as the Open Graphics Library. Open Computing Language 11. 12, etc., where "dispatches" may be interchangeably referred to as "work units" or "renderings," and similarly, "applications" may be interchangeably referred to as "workflows" or simply "agents." For example, a workload such as a three-dimensional (3D) game workload may include and emit any number and type of "frames," where each frame may represent an image (e.g., a sailboat, a person's face). Further, each frame may include and provide any number and type of work units, where each work unit may represent a portion (e.g., a mast of a sailboat, a forehead of a person's face) of the image (e.g., a sailboat, a person's face) represented by its corresponding frame. However, for the sake of consistency, each item may be referred to throughout this document by a single term (e.g., "dispatches,""agents," etc.).

References herein to "one embodiment," "an embodiment," "an example embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment may include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is considered to be within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

Described herein is a graphics processor comprising a memory interface, a processing cluster, and a first circuit module. The graphics processing cluster comprises a plurality of processing resources connected by a data interconnect. The graphics processor comprises a first circuit module that receives workload requests from an application to render frames through programming interface calls and processes these requests using a command queue of a graphics engine. The graphics processor also tracks the progress of the workload to determine whether the frame will meet its target display update deadline and continues to execute the workload if the frame will meet the deadline. If the frame will not meet the deadline, the graphics processor will also request neural frame generation. The graphics processor will then display the rendered frame or the generated frame at the target display update deadline. The graphics processor comprises a second circuit module for performing neural frame generation of a frame. The second circuit module comprises a computing engine associated with the processing resource, and the processing resource comprises a matrix accelerator for performing matrix multiplication operations on behalf of the computing engine. The second circuit module is configured to perform operations associated with a time-aware machine learning model via the computing engine to perform neural frame generation of a frame. A time-aware machine learning model is trained to estimate optical flow at a target timestamp based on a plurality of input frames, and timestamps associated with the plurality of input frames and the optical flow between the plurality of input frames are rendered. A second circuit module may estimate the optical flow at the target timestamp using the time-aware machine learning model, and warp a previously rendered frame based on the estimated optical flow at the target timestamp. The estimated optical flow at the target timestamp is an extrapolated optical flow, and the previously rendered frame is warped to a frame generated by the extrapolation.

One embodiment provides a method, including receiving a workload to render frame data for a frame to be rendered based on a programming interface call received from an application, processing the workload submitted to a command queue of a graphics engine configured to render the frame data for the application, tracking progress of the submitted workload for the frame, determining whether the frame will meet a target display update deadline, continuing to execute the workload to render the frame data in response to determining that the frame will meet the target display update deadline, requesting neural frame generation for the frame in response to determining that the frame will not meet the target display update deadline, and displaying the rendered or generated frame at the target display update deadline. The method additionally includes performing neural frame generation for the frame via a compute engine, which includes performing matrix multiplication operations via a matrix engine associated with the compute engine. Performing neural frame generation for the frame includes performing operations associated with a time-aware machine learning model via the compute engine. The time-aware machine learning model is trained to estimate optical flow based on multiple input frames at target timestamps, rendering timestamps associated with the multiple input frames and optical flow between the multiple input frames. The method additionally includes estimating optical flow at a target timestamp via a time-aware machine learning model, and warping a previously rendered frame based on the estimated optical flow at the target timestamp. The estimated optical flow at the target timestamp is an extrapolated optical flow, and the previously rendered frame is warped to a frame generated by the extrapolation.

One embodiment provides a graphics processing system, which includes a memory device and a graphics processor associated with the memory device. The graphics processor includes a processing cluster having a plurality of processing resources coupled via a data interconnect. The data interconnect enables the plurality of processing resources to collaboratively execute thread blocks of a workload submitted to the graphics processor. The graphics processor also includes a first circuit module for processing input data via a processing resource in the plurality of processing resources. The first circuit module is configured to receive a workload to render frame data for a frame to be rendered based on a programming interface call received from an application, and execute the workload submitted to a command queue of a graphics engine to render the frame data.

In response to a determination that the workload execution of the frame will meet the target display update deadline, the first circuit module will continue to execute the workload to render the frame data. In response to a determination that the workload execution of the frame will not meet the target display update deadline, the first circuit module will instead display the frame created via neural frame generation. The graphics processing system includes a second circuit module that tracks the progress of the submitted workload for the frame and determines whether the frame will meet the target display update deadline. The second circuit module will signal the first circuit module in response to the determination that the frame will not meet the target display update deadline, and then initiate a request for neural frame generation of the frame. The graphics processing system also includes a third circuit module for performing neural frame generation of the frame. The third circuit module includes a computing engine associated with a processing resource. The computing engine performs matrix multiplication operations via a matrix accelerator of the processing resource to perform operations associated with a time-aware machine learning model trained to estimate optical flow at a target timestamp. The time-aware machine learning model is trained to estimate optical flow at a target timestamp based on a plurality of input frames, rendering timestamps associated with the plurality of input frames and optical flow between the plurality of input frames. The third circuit module may estimate the extrapolated optical flow at the target time stamp, and warp the previously rendered frame based on the estimated optical flow at the target time stamp to extrapolate the generated frame.

One embodiment provides a method for generating a frame for display via a graphics processor. The method includes rendering a frame based on a programming interface command via a graphics engine, generating optical flow data based on frame data including a currently rendered frame and a previously rendered frame, storing the frame data and the optical flow data to a predetermined location of a device memory of the graphics processor, and executing frame generation logic via a compute engine of the graphics processor to generate a frame for display based on a timestamp corresponding to a next display update. The method additionally includes rendering additional frame data asynchronously with executing the frame generation logic, reading the optical flow data and the most recently available set of frame data stored to the predetermined location in the device memory, and generating a frame for display based on a timestamp corresponding to a next display update.

In the various embodiments described above, unless specifically noted otherwise, disjunctive language such as the phrase "at least one of A, B, or C" is intended to be understood to mean A, B, or C, or any combination thereof (e.g., A, B, and/or C). Thus, disjunctive language is not intended to, and should not be understood to, imply that a given embodiment requires that at least one of A, at least one of B, or at least one of C each be present. Similarly, items listed in the form of "at least one of A, B, or C" may mean (A), (B), (C), (A and B), (B and C), or (A, B, and C).

Some aspects of the technology provided herein include logic and associated operations described in the form of an algorithm or relative to an algorithm. It should be noted that such logic can be implemented in software, firmware and/or hardware. When logic is implemented in software, such logic can be downloaded to reside on different platforms used by a variety of operating systems and operated from different platforms, and executed by a processor to perform associated operations. The logic implemented in firmware can be executed on a microcontroller or processor device described in this article. When logic is implemented in hardware, such logic can be in the form of digital logic. Such digital logic can also be associated with an analog circuit module.

In some embodiments, terms like "display screen" and "display surface" may be used interchangeably to refer to the visible portion of the display device, while the remainder of the display device may be embedded in a computing device (such as a smart phone, wearable device, etc.). It is contemplated and noted that embodiments are not limited to any particular computing device, software application, hardware component, display device, display screen or surface, protocol, standard, etc. For example, embodiments may be applied to and used with any number and type of real-time applications on any number and type of computers, such as desktops, laptops, tablet computers, smart phones, head-mounted displays and other wearable devices, and/or the like. Further, for example, rendering scenarios using the efficient performance of this new technology may range from simple scenarios such as desktop composition to complex scenarios such as 3D games, augmented reality applications, etc.

The foregoing description and drawings are to be regarded in an illustrative rather than a restrictive sense. It will be appreciated by those skilled in the art that various modifications and changes may be made to the embodiments described herein without departing from the broader spirit and scope of the features as set forth in the appended claims.

Claims (25)

1. A graphics processor, comprising:

A memory interface;

A processing cluster coupled with the memory interface, the processing cluster comprising a plurality of processing resources coupled via a data interconnect; and

A first circuit module for processing input data via a processing resource of the plurality of processing resources, the first circuit module for:

Receiving a workload for rendering frame data for a frame to be rendered based on a programming interface call received from an application;

processing the workload submitted to the command queue of the graphics engine to render the frame data;

tracking progress of the submitted workload for the frame;

Determining whether the frame will meet a target display update deadline;

continuing to execute the workload to render the frame data in response to a determination that the frame will meet the target display update deadline;

requesting neural frame generation of the frame in response to a determination that the frame will not meet the target display update deadline; and

The rendered or generated frame is displayed at the target display update deadline.

2. The graphics processor of claim 1, comprising a second circuit module to perform neural frame generation of the frame, the second circuit module comprising a computing engine associated with the processing resource.

3. The graphics processor of claim 2, the processing resource comprising a matrix accelerator to perform matrix multiplication operations on behalf of the compute engine.

4. The graphics processor of claim 3, the second circuit module configured to perform operations associated with a time-aware machine learning model trained to estimate optical flow at a target timestamp via the computing engine to perform the neural frame generation of the frame.

5. The graphics processor of claim 4, the time-aware machine learning model trained to estimate the optical flow based on a plurality of input frames at the target timestamp, render timestamps associated with the plurality of input frames and optical flow between the plurality of input frames.

6. The graphics processor of claim 5, the second circuit module to:

Estimating optical flow at the target timestamp; and

Previously rendered frames are warped based on the optical flow estimated at the target timestamp.

7. The graphics processor of claim 6, wherein the optical flow estimated at the target timestamp is an extrapolated optical flow and the previously rendered frame is warped to extrapolate the generated frame.

8. A method, comprising:

Receiving a workload for rendering frame data for a frame to be rendered based on a programming interface call received from an application;

processing a workload submitted to a command queue of a graphics engine configured to render the frame data for the application;

tracking progress of the submitted workload for the frame;

Determining whether the frame will meet a target display update deadline;

continuing to execute the workload to render the frame data in response to determining that the frame will meet the target display update deadline;

requesting neural frame generation of the frame in response to determining that the frame will not meet the target display update deadline; and

And displaying the rendered or generated frame at the target display update deadline.

9. The method of claim 8, comprising performing, via a computing engine, neural frame generation of the frame.

10. The method of claim 9, comprising performing a matrix multiplication operation via a matrix engine associated with the computing engine to perform the neural frame generation.

11. The method of claim 10, performing, via the computing engine, operations associated with a time-aware machine learning model trained to estimate optical flow at a target timestamp to perform the neural frame generation of the frame.

12. The method of claim 11, the time-aware machine learning model trained to estimate the optical flow based on a plurality of input frames at the target timestamp, render timestamps associated with the plurality of input frames and optical flow between the plurality of input frames.

13. The method of claim 12, comprising:

Estimating optical flow at the target timestamp; and

Previously rendered frames are warped based on the optical flow estimated at the target timestamp.

14. The method of claim 13, wherein the optical flow estimated at the target timestamp is an extrapolated optical flow and the previously rendered frame is warped to extrapolate the generated frame.

15. A graphics processing system, comprising:

A memory device;

A graphics processor coupled with the memory device, the graphics processor comprising a processing cluster including a plurality of processing resources coupled via a data interconnect; and

A first circuit module for processing input data via a processing resource of the plurality of processing resources, the first circuit module for:

Receiving a workload for rendering frame data for a frame to be rendered based on a programming interface call received from an application;

executing a workload submitted to a command queue of a graphics engine to render the frame data;

continuing to execute the workload to render the frame data in response to the workload of the frame executing a determination that a target display update deadline is to be met; and

The display generates the created frame via a neural frame in response to the workload of the frame performing a determination that the target display update deadline will not be met.

16. The graphics processing system of claim 15, comprising a second circuit module to:

tracking progress of the submitted workload for the frame;

determining whether the frame will meet the target display update deadline; and

In response to a determination that the frame will not meet the target display update deadline, the first circuit module is signaled and a request for nerve frame generation of the frame is initiated.

17. The graphics processing system of claim 16, comprising a third circuit module for performing neural frame generation of the frame, the third circuit module comprising a computing engine associated with the processing resource.

18. The graphics processing system of claim 17, the processing resource comprising a matrix accelerator to perform matrix multiplication operations on behalf of the compute engine.

19. The graphics processing system of claim 18, the second circuit module configured to perform operations associated with a time-aware machine learning model, trained to estimate optical flow at a target timestamp, via the computing engine to perform the neural frame generation of the frame.

20. The graphics processing system of claim 19, the time-aware machine learning model is trained to estimate the optical flow based on a plurality of input frames at the target timestamp, rendering timestamps associated with the plurality of input frames and optical flow between the plurality of input frames.

21. The graphics processing system of claim 20, the third circuit module to:

Estimating optical flow at the target timestamp; and

Previously rendered frames are warped based on the optical flow estimated at the target timestamp.

22. The graphics processing system of claim 21, wherein the optical flow estimated at the target timestamp is an extrapolated optical flow and the previously rendered frame is warped to extrapolate the generated frame.

23. A method of generating a frame for display, comprising:

rendering, via a graphics engine of a graphics processor, the frame based on the programming interface command;

Generating optical flow data based on frame data including a current rendered frame and a previous rendered frame;

Storing the frame data and the optical flow data to predetermined locations in a device memory of the graphics processor; and

Executing, via a computing engine of the graphics processor, frame generation logic to generate a frame for display based on a timestamp corresponding to a next display update, wherein the frame generation logic uses a time-aware machine learning model to generate the frame for display based on a set of optical flow data and rendered frame data read from the predetermined location in the device memory.

24. The method of claim 23, comprising:

rendering additional frame data via the graphics engine based on the programming interface command asynchronously with execution of the frame generation logic via the computing engine;

Reading a most recently available set of optical flow data and frame data stored to the predetermined location in the device memory; and

The frame for display is generated based on a timestamp corresponding to a next display update.

25. A system comprising means for performing the method as in claim 23 or 24.