CN118502717A - Arithmetic logic unit, processor, computing chip, and computing device - Google Patents
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- G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
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- G06F7/46—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using electromechanical counter-type accumulators
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Abstract
本公开涉及算术逻辑单元、处理器、计算芯片和计算设备。公开了一种算术逻辑单元，用于接收两个二进制整数，能够实现针对其中至少一者的两种或更多种运算，算术逻辑单元包括：加法器，用于接收第一输入、第二输入和进位输入，并且输出第一输入、第二输入和进位输入的和，进位输入为1或0；第一输入选择模块，包括至少一个输入端，和耦合到加法器的第一输入的输出端；第二输入选择模块，包括至少两个输入端，和耦合到加法器的第二输入的输出端；进位输入选择模块，包括至少一个输入端，和耦合到加法器的进位输入的输出端；输出选择模块，包括至少三个输入端，和耦合到算术逻辑单元的输出端的输出端，至少一个输入端耦合到加法器输出的和。
The present disclosure relates to an arithmetic logic unit, a processor, a computing chip and a computing device. An arithmetic logic unit is disclosed, which is used to receive two binary integers and can implement two or more operations for at least one of them. The arithmetic logic unit includes: an adder, which is used to receive a first input, a second input and a carry input, and output the sum of the first input, the second input and the carry input, and the carry input is 1 or 0; a first input selection module, which includes at least one input terminal and an output terminal coupled to the first input of the adder; a second input selection module, which includes at least two input terminals and an output terminal coupled to the second input of the adder; a carry input selection module, which includes at least one input terminal and an output terminal coupled to the carry input of the adder; an output selection module, which includes at least three input terminals and an output terminal coupled to the output terminal of the arithmetic logic unit, and at least one input terminal is coupled to the sum of the adder output.
Description
Technical Field
The present invention relates to the field of computers. In particular, the present invention relates to a processor, and a computing chip and a computing device including the processor, particularly suitable for neural network related computation.
Background
In various application scenarios related to the computer field (such as neural networks, etc.), a large number of operations are generally required to be performed by a processor. An Arithmetic Logic Unit (ALU) is a unit for performing arithmetic operations in a processor that is typically capable of performing a variety of operations, such as addition, subtraction, absolute value, maximum value, minimum value, and the like. The power consumption and area of the arithmetic logic unit are critical to the efficiency and cost of the processor and the overall computing device. It is desirable to implement an arithmetic logic unit with lower power consumption and smaller area, thereby improving the computational efficiency of the processor and reducing the production and operating costs.
Thus, there is a need for new technologies.
Disclosure of Invention
It is an object of the present disclosure to provide an improved arithmetic logic unit.
According to one aspect of the present invention, there is provided an arithmetic logic unit for receiving two binary integers a and b, capable of implementing two or more operations for at least one of a and b, the arithmetic logic unit comprising: an adder for receiving a first input a, a second input B and a carry input Ci and outputting a sum S of the first input a, the second input B and the carry input Ci, wherein the carry input Ci is 1 or 0; a first input selection module comprising at least one input and an output coupled to a first input a of the adder; a second input selection module comprising at least two inputs and an output coupled to a second input B of the adder; a carry input selection module comprising at least one input and an output coupled to a carry input Ci of the adder; an output selection module comprising at least three inputs and an output coupled to an output of the arithmetic logic unit, wherein at least one input is coupled to the sum S of the adder outputs.
According to another aspect of the present invention there is provided a processor comprising one or more of the above arithmetic logic units.
According to yet another aspect of the present invention, there is provided a computing chip comprising one or more of the above processors.
According to yet another aspect of the present invention, there is provided a computing device comprising one or more of the above-described computing chips.
Other characteristic features and advantages of the invention will become apparent from the following description with reference to the accompanying drawings.
Drawings
The drawings are included for illustrative purposes and are merely to provide examples of possible structures and arrangements of the inventive apparatus disclosed herein and methods of applying same to a computing device. The figures in no way limit any changes in form and detail that may be made to the embodiments by those skilled in the art without departing from the spirit and scope of the embodiments. The embodiments will be more readily understood from the following detailed description taken in conjunction with the accompanying drawings, in which like reference numerals designate like structural elements.
Fig. 1 shows a schematic diagram of a prior art arithmetic logic unit.
Fig. 2 shows a schematic diagram of an arithmetic logic unit according to one embodiment of the invention.
Fig. 3 shows a schematic diagram of a comparison module in an output selection module of an arithmetic logic unit according to one embodiment of the invention.
Note that in the embodiments described below, the same reference numerals are used in common between different drawings to denote the same parts or parts having the same functions, and a repetitive description thereof may be omitted. In this specification, like reference numerals and letters are used to designate like items, and thus once an item is defined in one drawing, no further discussion thereof is necessary in subsequent drawings.
For ease of understanding, the positions, dimensions, ranges, etc. of the respective structures shown in the drawings and the like may not represent actual positions, dimensions, ranges, etc. Accordingly, the disclosed invention is not limited to the disclosed positions, dimensions, ranges, etc. as illustrated in the drawings. Moreover, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components.
Detailed Description
Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless it is specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. That is, the hash engine herein is shown by way of example to illustrate different embodiments of the circuitry in this disclosure and is not intended to be limiting. Those skilled in the art will appreciate that they are merely illustrative of exemplary ways in which the invention may be practiced, and not exhaustive.
Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but should be considered part of the specification where appropriate.
Fig. 1 shows a schematic diagram of a prior art arithmetic logic unit 100. The arithmetic logic unit 100 is configured to receive two numbers a and b, and is capable of performing a plurality of operations for at least one of a and b, such as addition, subtraction, absolute value, maximum value, minimum value, and the like. Wherein a and b are binary integers.
The arithmetic logic unit 100 includes a plurality of operator subunits 111, 112, 113, 114, 115, and an output selection module 120. Wherein each of the operation subunits receives two numbers a and b, respectively, for performing an operation (e.g., one of addition, subtraction, absolute value, maximum value, minimum value) and outputting the operation result to the output selection module 120.
The output selection module 120 receives the output of each operation subunit and receives a flag indicating an operation to be implemented by the arithmetic logic unit 100. The flags are denoted by reference numeral 1100 and include, for example, a flag ADD indicating that the arithmetic logic unit 100 is to implement an a plus b operation, a flag SUB indicating that the arithmetic logic unit 100 is to implement an a minus b operation, a flag ABS indicating that the arithmetic logic unit 100 is to implement an absolute value operation of a, a flag MAX indicating that the arithmetic logic unit 100 is to implement a maximum value operation of a and b, and a flag MIN indicating that the arithmetic logic unit 100 is to implement a minimum value operation of a and b. The output selection module 120 selects the output of an operator unit for performing a corresponding operation among the plurality of operator units 111, 112, 113, 114, 115 as the output x of the arithmetic logic unit 100 based on the above-described flag 1100. For example, when ADD is 1 and the other flags are all 0, indicating that the arithmetic logic unit 100 is to implement an a-plus-b operation, the output selection module 120 selects the output of an operator unit (e.g., the ADD operator unit 111) for performing the ADD operation as the output x of the arithmetic logic unit 100. Wherein the addition operator unit 111 may be implemented by an adder for calculating the sum of a plus b.
The arithmetic logic unit 100 of the prior art has some problems. When the arithmetic logic unit 100 operates, each operation subunit performs an operation, but only one operation result is selected and outputted by the output selection module 120. In other words, the arithmetic logic unit 100 performs a large number of invalidation operations, so that its power consumption is large and the occupied area is also large.
The present disclosure is directed to an arithmetic logic unit with lower power consumption and smaller area, thereby improving the computing efficiency of a processor and reducing the production cost and the operation cost.
Fig. 2 shows a schematic diagram of an arithmetic logic unit 200 according to one embodiment of the invention. The arithmetic logic unit 200 is configured to receive two numbers a and b, and is capable of implementing a plurality of operations for at least one of a and b. Wherein a and b are binary integers.
The arithmetic logic unit 200 includes an adder 210, a first input selection module 220, a second input selection module 230, a carry input selection module 240, and an output selection module 250.
The adder 210 is configured to receive a first input a, a second input B, and a carry input Ci, and output a sum S of the first input a, the second input B, and the carry input Ci, wherein the carry input Ci is 1 or 0. As will be described in detail below, the arithmetic logic unit 200 is capable of implementing a variety of operations with the adder 210, including a plus b, a minus b, taking absolute values of a, taking maximum values of a and b, taking minimum values of a and b, taking comparison results of a and b, and the like.
Adder 210 may be implemented similarly to the adder in addition operator unit 111 in prior art arithmetic logic unit 100 shown in fig. 1, except that the adder in prior art addition operator unit 111 is used to calculate the sum of two N-bit binary numbers a and B, and adder 210 is used to calculate the sum of two N-bit binary numbers (first input a, second input B) and a 1-bit carry input (carry input Ci). It will be appreciated by those skilled in the art that in implementing an adder for calculating the sum of two N-bit binary numbers a and b, only the sum of the lowest bit of a and the lowest bit of b need to be calculated at the lowest bit, while the sum of the corresponding bit of a, the corresponding bit of b and the carry of the previous bit need to be calculated at each of the other bits. Thus, in implementing an adder for calculating the sum of two N-bit binary numbers a and b and a 1-bit carry input, a similar implementation as an adder for calculating the sum of two N-bit binary numbers a and b may be employed, with only the lowest-order calculation block being modified adaptively (i.e., to the sum of the lowest order bits of a, b and 1-bit carry input) while the other-order calculation blocks remain unchanged.
That is, the specific circuit of the adder 210 for calculating the sum of the two N-bit binary numbers a and b and the 1-bit carry input may be substantially the same as that for calculating the two N-bit binary numbers a and b, with only the lowest order calculation block slightly different. In practical applications, N is typically large (e.g., 32 or 64), and therefore, the slight increase in computational power consumption and area caused by the slight complexity of the 1-bit computation module is almost negligible relative to the total power consumption and total area of the adder. That is, the power consumption and area of the adder 210 used by the arithmetic logic unit 200 of the present disclosure are substantially the same as those used in the addition operator unit 111 in the arithmetic logic unit 100 of the related art.
The arithmetic logic unit 200 of the present disclosure implements various operations only with the adder 210, and omits other multiple operator units (operator units 112, 113, 114, 115) used in the arithmetic logic unit 100 of the related art, thereby significantly reducing the calculation power consumption and area of the arithmetic logic unit 200, improving the calculation efficiency of the processor, and reducing the production cost and the operation cost, relative to the related art.
The first input selection module 220 may selectively output a value as the first input a of the adder 210 according to an operation to be implemented by the arithmetic logic unit 200. The first input selection module 220 includes at least one input and an output coupled to a first input a of the adder 210. In particular, at least one input of the first input selection module 220 may receive a.
Fig. 2 schematically shows that the two inputs of the first input selection module 220 receive a and 0, respectively, and that the first input selection module 220 selects the value received at one input (i.e. a or 0) as the first input a of the adder 210, depending on the operation to be implemented by the arithmetic logic unit 200. It should be understood that the implementation of the first input selection module 220 shown in fig. 2 is only for illustrative purposes of illustrating the principle of operation thereof, and that this module may be implemented in a more simple and efficient manner.
In an exemplary embodiment, the arithmetic logic unit 200 is capable of implementing the following operations: a plus b, a minus b, taking absolute values of a, taking maximum values of a and b, taking minimum values of a and b, etc. In particular, the first input selection module 220 may be configured to: when the arithmetic logic unit 200 is to perform any one of operations of a plus b, a minus b, taking the maximum values of a and b, taking the minimum values of a and b, outputting a as a first input a of the adder 210; when the arithmetic logic unit 200 is to implement the absolute value operation of claim a, 0 is output as the first input a of the adder 210.
In an exemplary embodiment, as shown in FIG. 2, the first input selection module 220 may receive a flag indicating an operation to be performed by the arithmetic logic unit 200. This flag is denoted by reference numeral 2100 and includes, for example, a flag ADD indicating that the arithmetic logic unit 200 is to implement an a plus b operation, a flag SUB indicating that the arithmetic logic unit 200 is to implement an a minus b operation, a flag ABS indicating that the arithmetic logic unit 200 is to implement an absolute value operation of a, a flag MAX indicating that the arithmetic logic unit 200 is to implement a maximum value operation of a and b, and a flag MIN indicating that the arithmetic logic unit 200 is to implement a minimum value operation of a and b. For example, a flag of 1 indicates that the arithmetic logic unit 200 is to implement a corresponding operation, wherein at most one of all flags ADD, SUB, ABS, MAX, MIN, etc. is 1. As such, the first input selection module 220 may be configured to: when any of the received flags ADD, SUB, MAX, MIN is 1, output a is taken as the first input a of adder 210; when the received flag ABS is 1, 0 is output as the first input a of adder 210.
In a preferred embodiment, the first input selection module 220 may be implemented by N and gates including two inputs, where N is the number of bits of binary numbers a and b. Where one input of each and gate receives a corresponding one bit of a and the other input may receive a 0 or 1 in response to an operation to be implemented by arithmetic logic unit 200. In particular, the other input may receive 1 when the arithmetic logic unit is to perform any one of operations a plus b, a minus b, maximum values of a and b, minimum values of a and b, and 0 when the arithmetic logic unit is to perform an absolute value operation of a. For example, in an embodiment where a flag of 1 indicates that arithmetic logic unit 200 is to perform a corresponding operation, the other input of each AND gate may receive the result of the OR operation by flag ADD, SUB, MAX, MIN.
The second input selection module 230 may selectively output a value as the second input B of the adder 210 according to an operation to be implemented by the arithmetic logic unit 200. The second input selection module 230 may include at least two inputs and an output coupled to the second input B of the adder 210. In particular, at least one input of the second input selection module 230 may receive a or a value related thereto, and at least one input may receive b or a value related thereto. Here, the value related to a or b refers to a value of a or b after simple processing, for example, _a or _b, where the symbol _represents a bit-wise inversion.
Fig. 2 schematically shows that three inputs of the second input selection module 230 receive B, -, a, and-, respectively, and that the second input selection module 230 selects the value received at one input (i.e., B, -, a, or-, B) as the second input B of the adder 210, depending on the operation to be implemented by the arithmetic logic unit 200. It should be understood that the implementation of the second input selection module 230 shown in fig. 2 is only for illustrative purposes of illustrating the principle of operation thereof, and that this module may be implemented in a more simple and efficient manner.
In particular, in an exemplary embodiment, the second input selection module 230 may be configured to: when the arithmetic logic unit 200 is to implement an a-plus-B operation, the output B is taken as the second input B of the adder 210; when the arithmetic logic unit 200 is to implement the absolute value operation of claim a, output a is the second input B of adder 210; when the arithmetic logic unit 200 is to perform any one of operations a minus B, maximum values of a and B, minimum values of a and B, output B is taken as the second input B of the adder 210.
In an exemplary embodiment, as shown in FIG. 2, the second input selection module 230 may receive a flag 2100 representing an operation to be performed by the arithmetic logic unit 200. For example, in an embodiment where a flag of 1 indicates that the arithmetic logic unit 200 is to implement a corresponding operation, the second input selection module 230 may be configured to: when the received flag ADD is 1, output B is taken as a second input B of adder 210; when the received flag ABS is 1, output-a is the second input B of adder 210; when any of the received flags SUB, MAX, MIN is 1, output B is taken as the second input B of adder 210.
In a preferred embodiment, the second input selection module 230 may be implemented by a three-control-side selector ao222 comprising three inputs, wherein three input terminals respectively receive b b-a.
The carry-in selection block 240 may selectively output 0 or 1 as the carry-in Ci of the adder 210 according to an operation to be implemented by the arithmetic logic unit 200. Carry-in selection module 240 may include at least one input and an output coupled to carry-in Ci of adder 210.
Fig. 2 schematically shows that the two inputs of the carry-in selection block 240 receive 0 and 1, respectively, and that the carry-in selection block 240 selects the value received at one input (i.e. 0 or 1) as the carry-in Ci of the adder 210, depending on the operation to be implemented by the arithmetic logic unit 200. It should be appreciated that the implementation of carry-in selection module 240 shown in fig. 2 is merely for illustrative purposes of illustrating the principle of operation thereof, and that this module may be implemented in a more simple and efficient manner.
In particular, in an exemplary embodiment, carry-in selection module 240 may be configured to: when the arithmetic logic unit 200 is to implement an a-plus-b operation, 0 is output as the carry input Ci of the adder; when the arithmetic logic unit 200 is to perform any one of operations of a minus b, calculating the absolute value of a, calculating the maximum values of a and b, and calculating the minimum values of a and b, output 1 is used as the carry input Ci of the adder.
In an exemplary embodiment, as shown in FIG. 2, carry-in select module 240 may receive a flag 2100 for an operation to be performed by arithmetic logic unit 200. For example, in an embodiment where a flag of 1 indicates that arithmetic logic unit 200 is to implement a corresponding operation, carry-in selection module 240 may be configured to: when the received flag ADD is 1,0 is output as the carry input Ci of the adder 210; when any of the received flags SUB, ABS, MAX, MIN is 1, output 1 is taken as the carry input Ci of adder 210.
In a preferred embodiment, carry-in selection module 240 may be implemented by an OR gate that includes a plurality of inputs that respectively receive at least a portion of the flags representing the operations to be implemented by arithmetic logic unit 200. For example, the OR gate may have at least four inputs, each receiving a flag SUB, ABS, MAX, MIN, etc.
The output selection module 250 may selectively output a value as the output x of the arithmetic logic unit 200 according to an operation to be implemented by the arithmetic logic unit 200. The output selection module 250 may include at least three inputs and an output coupled to an output of the arithmetic logic unit 200. In particular, at least one input of the output selection module 250 may be coupled to the sum S of the adder 210 outputs, further at least one input may receive a, further at least one input may receive b.
Fig. 2 schematically shows that three inputs of the output selection module 250 receive a, b and S, respectively, and that the output selection module 250 may select a value received at one input (i.e. a, b or S) as the output x of the arithmetic logic unit 200, depending on the operation to be implemented by the arithmetic logic unit 200. It should be understood that the implementation of the output selection module 250 shown in fig. 2 is merely for illustrative purposes of illustrating the principles of operation thereof, and that the module may be implemented in a more simple and efficient manner.
Specifically, in an exemplary embodiment, the output selection module 250 may be configured to: when the arithmetic logic unit 200 is to implement any one of operations a plus b, a minus b, the output sum S is taken as the output x of the arithmetic logic unit 200; when the arithmetic logic unit 200 is to implement the absolute value operation of a, either S or a is selected as the output x of the arithmetic logic unit 200 based on the sign bit of a; when the arithmetic logic unit 200 is to perform any one of operations of obtaining the maximum values of a and b and obtaining the minimum values of a and b, a or b is selected as the output x of the arithmetic logic unit 200 based on the sign bit of the sum S.
In particular, the output selection module 250 may be configured to: when the arithmetic logic unit 200 is to implement the absolute value operation of a, a is selected as an output of the arithmetic logic unit 200 in response to the sign bit of a being 0, and sum S is selected as an output of the arithmetic logic unit 200 in response to the sign bit of a being 1; when the arithmetic logic unit 200 is required to implement the maximum value operation of the requirements a and b, a is selected as the output of the arithmetic logic unit 200 in response to the sign bit of the sum S being 0, and b is selected as the output of the arithmetic logic unit 200 in response to the sign bit of the sum S being 1; when the arithmetic logic unit 200 is to implement the minimum value operation of the requirements a and b, b is selected as the output of the arithmetic logic unit 200 in response to the sign bit of the sum S being 0, and a is selected as the output of the arithmetic logic unit 200 in response to the sign bit of the sum S being 1. It will be appreciated by those skilled in the art that a sign bit of a binary integer of 0 indicates that the number is a non-negative number and a sign bit of a binary integer of 1 indicates that the number is a negative number.
In an exemplary embodiment, as shown in FIG. 2, the output selection module 250 may receive a flag 2100 for an operation to be performed by the arithmetic logic unit 200. For example, in an embodiment where a flag of 1 indicates that arithmetic logic unit 200 is to implement a corresponding operation, output selection module 250 may be configured to: when either of the received flags ADD, SUB is 1, the sum S is output as the arithmetic logic unit 200; when the received flag ABS is 1, a is selected as an output of the arithmetic logic unit 200 in response to the sign bit of a being 0, and sum S is selected as an output of the arithmetic logic unit 200 in response to the sign bit of a being 1; when the received flag MAX is 1, a is selected as the output of the arithmetic logic unit 200 in response to the sign bit of the sum S being 0, and b is selected as the output of the arithmetic logic unit 200 in response to the sign bit of the sum S being 1; when the received flag MIN is 1, b is selected as the output of the arithmetic logic unit 200 in response to the sign bit of the sum S being 0, and a is selected as the output of the arithmetic logic unit 200 in response to the sign bit of the sum S being 1.
In a preferred embodiment, the arithmetic logic unit 200 may be further adapted to implement the comparison result operations for a and b. Specifically, the arithmetic logic unit 200 may output at least one of flags indicating whether a is equal to b, whether a is greater than b, and whether a is less than b as the output x of the arithmetic logic unit 200. For example, the arithmetic logic unit 200 may simultaneously output a flag indicating that a is equal to b, a is not greater than b, a is not less than b as the output x of the arithmetic logic unit 200.
In particular, the first input selection module 220 may be configured to output a as the first input a of the adder 210 when the arithmetic logic unit 200 is required to implement the comparison result operation of the requirements a and b; the second input selection module 230 may be configured to output-B as the second input B of the adder 210 when the arithmetic logic unit 200 desires to implement the comparison result operation of the requirements a and B; the carry-in selection module 240 may be configured to output 1 as the carry-in Ci of the adder 210 when the arithmetic logic unit 200 is required to implement the comparison result operation of the requirements a and b; the output selection module 250 may be configured to output one of flags indicating that a is equal to b, a is greater than b, a is less than b as the output x of the arithmetic logic unit 200 based on whether a and b are equal and sign bits of sum S when the arithmetic logic unit 200 is required to implement the comparison result operation of a and b.
In an exemplary embodiment, the first input selection module 220, the second input selection module 230, the carry input selection module 240, and the output selection module 250 may receive a flag (not shown in fig. 2) indicating that the arithmetic logic unit 200 requires the comparison result operation of the requirements a and b to be implemented. For example, the first input selection module 220, the second input selection module 230, the carry input selection module 240, and the output selection module 250 may output one of a as a first input a of the adder 210, B as a second input B of the adder 210, 1 as a carry input Ci of the adder 210, and a flag indicating a is equal to B, a is greater than B, a is less than B as an output x of the arithmetic logic unit 200, respectively, in response to the flag being 1.
The output selection module 250 may include a comparison module 350 for performing a comparison result operation for a and b. Specifically, the comparison module 350 is configured to output one of the flags indicating that a is equal to b, a is greater than b, and a is less than b as the output x of the arithmetic logic unit 200 based on whether a and b are equal and the sign bit of S.
Fig. 3 shows a schematic diagram of a comparison module 350 in the output selection module 250 of the arithmetic logic unit 200 according to one embodiment of the invention.
As shown in fig. 3, the comparison module 350 may include an equality determination module 351, a sign bit determination module 352, and a greater than determination module 353.
The equality judgment module 351 is configured to judge whether a and b are equal. The equality determination module 351 receives a and b and outputs a flag indicating that a and b are equal (e.g., outputs 1 when a and b are equal). The comparison module 350 is configured to output a flag EQ indicating that a is equal to b as an output x of the arithmetic logic unit 200 in response to the equality determination module 351 outputting a flag (for example, output 1) indicating that a and b are equal when the arithmetic logic unit 200 is required to implement the comparison result operation of the requirements a and b. In particular, as shown in fig. 3, the output of the equality determination module 351 may be directly coupled to the output of the comparison module 350.
In a preferred embodiment, the equality determination module 351 may be implemented by a combination of a plurality of exclusive nor gates and one or more and gates. For example, the equality determination module 351 may be implemented by a combination of N exclusive or gates and an N terminal and gate, where N is the number of bits of binary numbers a and b. Wherein one input of each exclusive nor gate receives a bit and the other input receives a corresponding bit of b, and the outputs are coupled to corresponding ones of the N-terminal and gates. If and only if a and b are equal, all exclusive nor gates output 1, and the N terminal and gate output 1. In a preferred implementation, the N-terminal and gate may be replaced by a combination of a plurality of and gates with a smaller number of terminals.
The sign bit determination module 352 is configured to determine a sign bit of the sum S. The sign bit determination module 352 receives the sum S and outputs a sign bit of the sum S (e.g., outputs 1 when the sign bit of the sum S is 1, and conversely outputs 0). The comparison module 350 is configured to output a flag LT indicating that a is smaller than b as an output x of the arithmetic logic unit 200 in response to a sign bit of S being 1 when the arithmetic logic unit 200 is required to implement the comparison result operation of the requirements a and b. In particular, as shown in FIG. 3, the output of the sign bit determination module 352 may be directly coupled to the output of the comparison module 350.
The greater than determination module 353 is configured to determine whether a is greater than b. The greater than decision block 353 includes two inputs coupled to the outputs of the equal decision block 351 and the sign bit decision block 352, respectively. The greater than judging module 353 is configured to output a flag GT indicating that a is greater than b as an output x of the arithmetic logic unit 200 in response to the sign bit of the sum S being 0 and the equality judging module outputting a flag indicating that a and b are not equal when the arithmetic logic unit 200 is required to implement the comparison result operation of the requirements a and b. In particular, the greater than determination module 353 may be implemented by a nor gate.
In one implementation, a processor may include one or more of the arithmetic logic units described above. In one implementation, a computing chip may include one or more of the processors described above. In one implementation, a computing device may include one or more computing chips. Multiple computing chips may perform computing tasks in parallel.
In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of the exemplary embodiments may have different values.
It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, and/or components, and/or groups thereof.
While certain specific embodiments of the invention have been illustrated in detail by way of example, it will be appreciated by those skilled in the art that the foregoing examples are intended to be illustrative only and not to limit the scope of the invention. It will be appreciated by those skilled in the art that changes could be made to the embodiments described above without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (20)
1. An arithmetic logic unit for receiving two binary integers a and b, capable of implementing two or more operations on at least one of a and b, the arithmetic logic unit comprising:
An adder for receiving a first input a, a second input B and a carry input Ci and outputting a sum S of the first input a, the second input B and the carry input Ci, wherein the carry input Ci is 1 or 0;
a first input selection module comprising at least one input and an output coupled to a first input a of the adder;
A second input selection module comprising at least two inputs and an output coupled to a second input B of the adder;
A carry input selection module comprising at least one input and an output coupled to a carry input Ci of the adder;
An output selection module comprising at least three inputs and an output coupled to an output of the arithmetic logic unit, wherein at least one input is coupled to the sum S of the adder outputs.
2. The arithmetic logic unit of claim 1 wherein at least one input of the first input selection module receives a.
3. The arithmetic logic unit of claim 2, wherein the first input selection module is configured to:
when the arithmetic logic unit is to perform any one of operations of a plus b, a minus b, maximum values of a and b, minimum values of a and b, output a as a first input a of the adder;
when the arithmetic logic unit is to implement the absolute value operation of claim a, 0 is output as the first input a of the adder.
4. An arithmetic logic unit as claimed in claim 3, wherein the first input selection module is implemented by N and gates comprising two inputs, wherein one input of each and gate receives a respective one bit of a, the other input receives 1 when the arithmetic logic unit is to implement any one of a plus b, a minus b, a maximum of a and b, a minimum of a and b, and receives 0 when the arithmetic logic unit is to implement an absolute value operation of a, where N is the number of bits of binary numbers a and b.
5. The arithmetic logic unit of claim 1 wherein at least one of the at least two inputs of the second input selection module receives a or-a and at least one other input receives b or-b, wherein the symbol-represents a bit-wise negation.
6. The arithmetic logic unit of claim 5 wherein the second input selection module is configured to:
When the arithmetic logic unit is to implement an a-plus-B operation, outputting B as a second input B of the adder;
outputting a as a second input B of the adder when the arithmetic logic unit is to implement the absolute value operation of a;
When the arithmetic logic unit is to perform any one of operations a minus B, maximum values of a and B, minimum values of a and B, output-B is taken as the second input B of the adder.
7. The arithmetic logic unit of claim 6 wherein the second input selection module is implemented by a three control terminal selector ao222 comprising three inputs, wherein three input terminals respectively receive b b-a.
8. The arithmetic logic unit of claim 1, wherein the carry-in selection module is configured to:
when the arithmetic logic unit is to implement an a-plus-b operation, outputting 0 as the carry input Ci of the adder;
When the arithmetic logic unit is to perform any one of operations of a minus b, calculating an absolute value of a, calculating a maximum value of a and b, and calculating a minimum value of a and b, output 1 is used as carry input Ci of the adder.
9. The arithmetic logic unit of claim 8, wherein the carry-in selection module is implemented by an or gate comprising a plurality of inputs that respectively receive at least a portion of the flags representing the operations to be implemented by the arithmetic logic unit.
10. The arithmetic logic unit of claim 1 wherein a further at least one of the at least three inputs of the output selection module receives a and a further at least one input receives b.
11. The arithmetic logic unit of claim 10, wherein the output selection module is configured to:
when the arithmetic logic unit is to realize any one of operations a plus b, a minus b, outputting sum S as an output of the arithmetic logic unit;
when the arithmetic logic unit is to implement the absolute value operation of a, selecting either S or a as the output of the arithmetic logic unit based on the sign bit of a;
when the arithmetic logic unit is to perform any one of operations of maximum values of a and b, minimum values of a and b, a or b is selected as an output of the arithmetic logic unit based on sign bits of sum S.
12. The arithmetic logic unit of claim 11, wherein the output selection module is configured to select a as the output of the arithmetic logic unit in response to the sign bit of a being 0 and to select and S as the output of the arithmetic logic unit in response to the sign bit of a being 1 when the arithmetic logic unit is to implement the absolute value operation of a.
13. The arithmetic logic unit of claim 11, wherein the output selection module is configured to:
When the arithmetic logic unit is to implement the maximum value operation of the claims a and b, a is selected as an output of the arithmetic logic unit in response to the sign bit of the sum S being 0, and b is selected as an output of the arithmetic logic unit in response to the sign bit of the sum S being 1;
when the arithmetic logic unit is to implement the minimum value operation of the requirements a and b, b is selected as an output of the arithmetic logic unit in response to the sign bit of the sum S being 0, and a is selected as an output of the arithmetic logic unit in response to the sign bit of the sum S being 1.
14. The arithmetic logic unit of claim 10 wherein the output selection module includes an equality determination module for determining whether a and b are equal.
15. The arithmetic logic unit of claim 14 wherein:
the first input selection module is configured to output a as a first input a of the adder when the arithmetic logic unit is to implement a comparison result operation of the requirements a and b;
the second input selection module is configured to output-B as a second input B of the adder when the arithmetic logic unit is to implement the comparison result operation of the requirements a and B;
The carry-in selection module is configured to output 1 as carry-in Ci of the adder when the arithmetic logic unit is to implement the comparison result operation of the requirements a and b; and
The output selecting module is configured to output, as an output of the arithmetic logic unit, one of flags indicating that a is equal to b, a is greater than b, and a is less than b, based on an output of the equality judging module and a sign bit of sum S, when the arithmetic logic unit is to implement a comparison result operation of the requirements a and b.
16. The arithmetic logic unit of claim 15, wherein the output selection module is configured, when the arithmetic logic unit is to implement the compare result operation of the requirements a and b:
Outputting a flag indicating that a is equal to b as an output of the arithmetic logic unit in response to the equality judgment module outputting the flag indicating that a and b are equal;
outputting a flag indicating that a is smaller than b as an output of the arithmetic logic unit in response to the sign bit of the sum S being 1; and
In response to the sign bit of the sum S being 0 and the equality judgment module outputting a flag indicating that a and b are not equal, a flag indicating that a is greater than b is output as an output of the arithmetic logic unit.
17. The arithmetic logic unit of claim 14 wherein the equality determination module is implemented by a combination of N exclusive nor gates and one or more and gates, where N is the number of bits of binary numbers a and b.
18. A processor comprising one or more arithmetic logic units as claimed in any one of claims 1 to 17.
19. A computing chip comprising one or more processors as recited in claim 18.
20. A computing device comprising one or more computing chips as claimed in claim 19.
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| CN1916886A (en) * | 2006-08-29 | 2007-02-21 | 中国航天时代电子公司第七七一研究所 | Circuit struction of reverse order / circulation address generater |
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| CN117157880A (en) * | 2021-05-21 | 2023-12-01 | 微芯片技术股份有限公司 | Logic cell for programmable gate array |
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| US7818361B1 (en) * | 2005-11-07 | 2010-10-19 | Tabula, Inc. | Method and apparatus for performing two's complement multiplication |
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