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CN118366507A - Method and device for checking voltage calibration function test circuit of input buffer - Google Patents

Method and device for checking voltage calibration function test circuit of input buffer Download PDF

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Publication number
CN118366507A
CN118366507A CN202310064942.5A CN202310064942A CN118366507A CN 118366507 A CN118366507 A CN 118366507A CN 202310064942 A CN202310064942 A CN 202310064942A CN 118366507 A CN118366507 A CN 118366507A
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China
Prior art keywords
output
voltage
comparator
signal
circuit
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CN202310064942.5A
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Chinese (zh)
Inventor
史腾
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202310064942.5A priority Critical patent/CN118366507A/en
Publication of CN118366507A publication Critical patent/CN118366507A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

The disclosure provides a voltage calibration function test circuit inspection method and equipment of an input buffer, and relates to the technical field of semiconductor test, wherein the method comprises the following steps: the voltage calibration function test circuit comprises a reference voltage generation circuit, a comparator and a combinational logic circuit; establishing a substitute model of the comparator, wherein the substitute model is used for outputting a corresponding output signal according to an excitation signal input by the trimming voltage input end; replacing the comparator with the replacement model so that the positive phase input end and the negative phase input end are both connected to the output end of the reference voltage generating circuit; the excitation signal is input through the trimming voltage input end, and the calibration output signal generated by the combinational logic circuit is monitored so as to compare the calibration output signal with a preset expected output. The present disclosure may use the surrogate model as a digital model of the comparator to enable testing of the voltage calibration function through digital simulation, which may reduce inspection complexity and time consumption of the voltage calibration function as compared to analog simulation.

Description

Method and device for checking voltage calibration function test circuit of input buffer
Technical Field
The present disclosure relates to, but is not limited to, a voltage calibration functional test circuit inspection method and apparatus for an input buffer.
Background
The memory is a semiconductor device for storing data, and has an input buffer connected to an input pin of the memory to transmit an input signal received by the input pin into the input buffer for processing. Under the influence of factors such as different operating temperatures, the input signal may output a comparison value which is inconsistent with the expected value after being compared with the reference voltage in the input buffer, and at the moment, the input buffer needs to have certain calibration compensation capability, and reasonable offset compensation is set after recalibration for different signal paths.
In the prior art, the voltage calibration function test circuit is designed to calibrate the voltage of the input buffer, so that the reasonable configuration of the compensation circuit is tested. In the design stage, since the core unit of the input buffer is an analog circuit, when verifying whether the voltage calibration function test circuit meets the design requirement, the whole circuit is generally verified in an analog simulation mode, however, the analog simulation has high complexity and takes a long time.
Disclosure of Invention
The embodiment of the disclosure provides a method and equipment for checking a voltage calibration function test circuit of an input buffer, so as to reduce the checking complexity and time consumption of the voltage calibration function test circuit of the input buffer.
In a first aspect, embodiments of the present disclosure provide a voltage calibration functional test circuit inspection method of an input buffer, the method comprising:
The method comprises the steps of obtaining a voltage calibration function test circuit of the input buffer, wherein the voltage calibration function test circuit comprises a reference voltage generation circuit, a comparator and a combinational logic circuit; the reference voltage generation circuit is used for providing a reference voltage signal to the comparator, and the combinational logic circuit is used for generating a calibration output signal based on the output signal of the comparator;
Establishing a substitution model of the comparator; the substitution model comprises a positive phase input end, a negative phase input end, an output end and a trimming voltage input end, and is used for outputting an output signal corresponding to the excitation signal according to the excitation signal input by the trimming voltage input end;
Replacing the comparator in the voltage calibration function test circuit with the replacement model so that the positive phase input end and the negative phase input end are both connected to the output end of the reference voltage generation circuit, and the output end of the replacement model is connected with the input end of the combinational logic circuit;
And inputting the excitation signal through the trimming voltage input end, and monitoring a calibration output signal generated by the combinational logic circuit to compare the calibration output signal with a preset expected output.
In some embodiments, the excitation signal is a digital signal, the output of the surrogate model is a digital signal, and the output of the combinational logic circuit is a digital signal.
In some embodiments, the stimulus signal includes a plurality of test sequences, the inputting the stimulus signal through the trimming voltage input terminal, and monitoring a calibration output signal generated by the combinational logic circuit to compare the calibration output signal with a preset desired output includes:
And respectively inputting a plurality of test sequences into the trimming voltage input end to obtain a plurality of corresponding calibration output signals, comparing the calibration output signals with preset expected output, and determining that the voltage calibration function test circuit passes the inspection when all the calibration output signals are consistent with the preset expected output.
In some embodiments, the test sequence consists of binary numbers of a preset length.
In some embodiments, the preset length is 3.
In a second aspect, embodiments of the present disclosure provide a voltage calibration function test circuit inspection apparatus of an input buffer, the apparatus comprising:
The circuit acquisition module is used for acquiring a voltage calibration function test circuit of the input buffer, and the voltage calibration function test circuit comprises a reference voltage generation circuit, a comparator and a combinational logic circuit; the reference voltage generation circuit is used for providing a reference voltage signal to the comparator, and the combinational logic circuit is used for generating a calibration output signal based on the output signal of the comparator;
the substitute model building module is used for building a substitute model of the comparator; the substitution model comprises a positive phase input end, a negative phase input end, an output end and a trimming voltage input end, and is used for outputting an output signal corresponding to the excitation signal according to the excitation signal input by the trimming voltage input end;
A model replacement module, configured to replace the comparator in the voltage calibration function test circuit with the replacement model, so that the positive phase input terminal and the negative phase input terminal are both connected to the output terminal of the reference voltage generating circuit, and the output terminal of the replacement model is connected to the input terminal of the combinational logic circuit;
and the checking module is used for inputting the excitation signal through the trimming voltage input end and monitoring a calibration output signal generated by the combinational logic circuit so as to compare the calibration output signal with a preset expected output.
In some embodiments, the excitation signal is a digital signal, the output of the surrogate model is a digital signal, and the output of the combinational logic circuit is a digital signal.
In some embodiments, the excitation signal comprises a plurality of test sequences, the inspection module further configured to:
And respectively inputting a plurality of test sequences into the trimming voltage input end to obtain a plurality of corresponding calibration output signals, comparing the calibration output signals with preset expected output, and determining that the voltage calibration function test circuit passes the inspection when all the calibration output signals are consistent with the preset expected output.
In some embodiments, the test sequence consists of binary numbers of a preset length.
In some embodiments, the preset length is 3.
In a third aspect, an embodiment of the present disclosure further provides an electronic device, including: at least one processor and memory;
The memory stores computer-executable instructions;
The at least one processor executes computer-executable instructions stored in the memory to cause the electronic device to implement the method as described in the first aspect.
In a fourth aspect, embodiments of the present disclosure also provide a computer-readable storage medium having stored therein computer-executable instructions for implementing the method of the first aspect when the computer-executable instructions are executed by an electronic device.
In a fifth aspect, embodiments of the present disclosure further provide a computer program for implementing the method of the first aspect.
The embodiment of the disclosure provides a voltage calibration function test circuit inspection method and equipment of an input buffer, comprising the following steps: the method comprises the steps of acquiring a voltage calibration function test circuit of an input buffer, wherein the voltage calibration function test circuit comprises a reference voltage generation circuit, a comparator and a combinational logic circuit; the reference voltage generating circuit is used for providing a reference voltage signal for the comparator, and the combinational logic circuit is used for generating a calibration output signal based on the output signal of the comparator; establishing a replacement model of the comparator; the substitution model comprises a positive phase input end, a negative phase input end, an output end and a trimming voltage input end, and is used for outputting an output signal corresponding to the excitation signal according to the excitation signal input by the trimming voltage input end; replacing a comparator in the voltage calibration function test circuit with a replacement model so that a positive phase input end and a negative phase input end are both connected to the output end of the reference voltage generation circuit, and the output end of the replacement model is connected with the input end of the combination logic circuit; the excitation signal is input through the trimming voltage input end, and the calibration output signal generated by the combinational logic circuit is monitored so as to compare the calibration output signal with a preset expected output. The embodiment of the disclosure can establish a substitute model for the comparator to realize the inspection of the voltage calibration function test circuit of the input buffer through digital simulation, and compared with analog simulation, the inspection complexity and time consumption of the voltage calibration function test circuit of the input buffer can be reduced.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.
FIGS. 1 and 2 are schematic diagrams of a voltage calibration function test circuit for two input buffers according to embodiments of the present disclosure;
FIG. 3 is a schematic diagram of a digital simulation model of a voltage calibration functional test circuit of an input buffer according to an embodiment of the present disclosure;
FIG. 4 is a flow chart of steps of a method for checking a voltage calibration function test circuit of an input buffer according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a voltage calibration function test circuit inspection device for an input buffer according to an embodiment of the present disclosure;
Fig. 6 is a block diagram of an electronic device according to an embodiment of the present disclosure.
Specific embodiments of the present disclosure have been shown by way of the above drawings and will be described in more detail below. These drawings and the written description are not intended to limit the scope of the disclosed concepts in any way, but rather to illustrate the disclosed concepts to those skilled in the art by reference to specific embodiments.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present disclosure as detailed in the accompanying claims.
In the field of semiconductor technology, integrated circuit chips, such as DRAMs (dynamic random accessing memory, dynamic random access memories), are often provided with built-in self-test (BIST) circuits. Such BIST circuits may assist in the execution of certain tests for the integrated circuit chip during the entry of the integrated circuit chip into a test mode. After the integrated circuit chip design is completed, the various functions of the integrated circuit chip need to be checked to determine if they are normal. For example, the BIST circuit described above needs to be checked to determine whether the BIST circuit is normal.
When the integrated circuit chip is a DRAM, the voltage calibration function test circuit of the input buffer in the DRAM serves as a BIST circuit, and the embodiments of the present disclosure are used to check the voltage calibration function test circuit to determine whether the voltage calibration function test circuit of the input buffer is normal. Fig. 1 and 2 are schematic diagrams of a voltage calibration function test circuit of two input buffers according to an embodiment of the present disclosure.
Referring to fig. 1, the voltage calibration function test circuit of the input buffer includes a reference voltage generation circuit, a multiplexer, a comparator, and a combinational logic circuit.
The reference voltage generation circuit is configured to generate a reference voltage signal VrefCa to provide the reference voltage signal VrefCa to the multiplexer and the comparator.
The multiplexer has two data inputs D1 and D2 and a control input C. The data input D1 may receive the test data signal CaPd, the data input D2 is connected to the output of the reference voltage generating circuit for receiving the reference voltage signal VrefCa, and the control input C is for receiving the selection control signal SS. The multiplexer may output the test data signal CaPd or the reference voltage signal VrefCa to the comparator according to the selection control signal SS. For example, when the input buffer is in the normal operation mode, the control signal SS is selected to be at the first level, so that the multiplexer outputs the test data signal CaPd to the comparator; when the input buffer is in the test mode, the control signal SS is selected to be at the second level, so that the multiplexer outputs the reference voltage signal CaPd to the comparator.
The comparator is provided with an enabling end E, a positive input end P, a negative input end N and a trimming voltage input end T, wherein the enabling end E is used for receiving an enabling signal EN, when the enabling signal EN is at a first level, the comparator normally works, and when the enabling signal EN is at a second level, the comparator stops working.
The positive input end P of the comparator is connected with the output end of the multiplexer to receive the output signal of the comparator, and the negative input end N of the comparator is connected with the output end of the reference voltage generating circuit to receive the reference voltage signal VrefCa. When the voltage received by the forward input end P is greater than the voltage received by the reverse input end N, the comparator outputs a high level; the comparator outputs a low level when the voltage received at the forward input P is less than the voltage received at the reverse input N.
The trimming voltage input terminal T of the comparator is used for receiving the excitation signal tm_trim to calibrate the comparator. In an ideal case, the comparator can accurately identify the voltage level between the positive input P and the negative input N. However, since the input pin receives an analog signal, when the analog signal is interfered by various factors (such as intersymbol interference, operating temperature, etc.), the comparator may deviate, that is, the comparator may be out of order.
When the comparator deviates, the comparator cannot accurately identify the voltage between the positive input end P and the negative input end N, and at this time, calibration can be performed through the excitation signal TM_trim. For example, when the voltage difference between the positive input terminal P and the negative input terminal N identified by the comparator is smaller, the excitation signal tm_trim may be a voltage signal greater than 0 to increase the voltage difference, so that the comparator may accurately output the voltage magnitude relationship between the positive input terminal P and the negative input terminal N. When the voltage difference between the positive input terminal P and the negative input terminal N identified by the comparator is larger, the excitation signal tm_trim may be a voltage signal smaller than 0, so as to reduce the voltage difference, so that the comparator can accurately output the voltage magnitude relationship between the positive input terminal P and the negative input terminal N. The excitation signal tm_trim may thus also be referred to as a compensation voltage signal or a trimming voltage signal.
The input end of the combinational logic circuit is connected to the output end of the comparator to carry OUT combinational logic judgment on the output signals of the comparator, so as to obtain a calibration output signal OUT, and the excitation signal TM_trim of the comparator is determined according to the calibration output signal OUT.
Referring to fig. 2, the voltage calibration function test circuit of the input buffer includes a reference voltage generation circuit, a comparator, and a combinational logic circuit. The voltage calibration function test circuit shown in fig. 2 can be understood as a result of removing the multiplexer in the voltage calibration function test circuit shown in fig. 1.
Referring to fig. 2, an output terminal of the reference voltage generating circuit is connected to a negative input terminal N of the comparator to input the reference voltage signal VrefCa to the negative input terminal N of the comparator. The positive input end P of the comparator is used for receiving the test data signal CaPd, the enabling input end E of the comparator is used for receiving the enabling signal EN, the trimming voltage input end of the comparator is used for receiving the excitation signal TM_trim, and the output end of the comparator is connected with the input end of the combinational logic circuit.
Since the comparator in fig. 1 or 2 is an analog circuit, the voltage calibration function test circuit of the input buffer in fig. 1 or 2 described above needs to be checked by analog simulation. However, the complexity of analog simulation is higher than that of digital simulation, resulting in higher inspection complexity and higher time consumption of the voltage calibration function test circuit of the input buffer.
In order to achieve a digital simulation of the voltage calibration function test circuit of the input buffer, a digital model needs to be built for the comparator. Since the comparator is an analog circuit, when a digital model is built, the positive input terminal P and the negative input terminal N of the comparator need to be input with the same reference voltage signal, in which case the output signal of the comparator depends only on the excitation signal tm_trim received by the trimming voltage input terminal T, so as to obtain the digital model of the comparator, which is called as a substitute model of the comparator.
Fig. 3 is a schematic diagram of a digital simulation model of a voltage calibration function test circuit of an input buffer according to an embodiment of the disclosure. Referring to fig. 3, a digital simulation model of a voltage calibration function test circuit includes a reference voltage generation circuit, an alternative model, and a combinational logic circuit. The surrogate model is a digital model of the comparator, which is constructed in a state where both the positive input terminal P and the negative input terminal N of the comparator receive the reference voltage signal VrefCa. Therefore, the embodiment of the disclosure can realize the inspection of the voltage calibration function test circuit of the input buffer through digital simulation, and compared with analog simulation, the inspection complexity and time consumption of the voltage calibration function test circuit of the input buffer can be reduced.
Fig. 4 is a flowchart illustrating a step of a method for checking a voltage calibration function test circuit of an input buffer according to an embodiment of the present disclosure. Referring to fig. 4, the above-described method includes S201 to S204.
S201: the method comprises the steps of acquiring a voltage calibration function test circuit of an input buffer, wherein the voltage calibration function test circuit comprises a reference voltage generation circuit, a comparator and a combinational logic circuit; the reference voltage generation circuit is used for providing a reference voltage signal to the comparator, and the combinational logic circuit is used for generating a calibration output signal based on the output signal of the comparator.
It is understood that the obtained voltage calibration function test circuit is a designed circuit, and it is understood that the voltage calibration function test circuit according to the embodiments of the present disclosure may further include the multiplexer shown in fig. 1 on the basis of including the reference voltage generating circuit, the comparator, and the combinational logic circuit. That is, the voltage calibration function test circuit may have the structure shown in fig. 1 or the structure shown in fig. 2.
The reference voltage signal may be an accessible common voltage, such as VDD, or the like. The output end of the reference voltage generating circuit is connected to the negative input end N of the comparator so as to provide a reference voltage signal for the comparator.
The combinational logic circuit may include one or more logic gates for implementing the processing and conversion of the digital signals. For example, when the input of the combinational logic circuit is 1, the output is 0, and when the input of the combinational logic circuit is 0, the output is 1. That is, the combinational logic circuit corresponds to a set of input-output relationships, and for an input signal, the calibration output signal generated by the combinational logic circuit corresponds to a preset desired output. If the calibration output signal generated by the combinational logic circuit is inconsistent with the preset expected output, an anomaly is represented by the combinational logic circuit. If the calibration output signal generated by the combinational logic circuit is consistent with the preset desired output, it is indicative that the combinational logic circuit is normal.
S202: establishing a replacement model of the comparator; the substitution model comprises a positive phase input end, a negative phase input end, an output end and a trimming voltage input end, and is used for outputting an output signal corresponding to the excitation signal according to the excitation signal input by the trimming voltage input end.
The comparator of the embodiments of the present disclosure may be understood as an analog-to-digital converter, which is configured to perform analog-to-digital conversion on an analog signal received by an input pin, to obtain a digital signal of 0 or 1. When the positive input terminal and the negative input terminal of the comparator receive the same reference voltage signal, the output signal of the comparator is only determined by the excitation signal of the trimming voltage input terminal. Thus, the surrogate model describes the correspondence between the excitation signal and the output signal of the comparator, both of which are digital signals.
The above-mentioned substitution pattern is shown with reference to fig. 3, in which the enable input terminal E of the substitution pattern in fig. 3 corresponds to the enable input terminal E of the comparator in fig. 1or 2, the positive input terminal P of the substitution pattern in fig. 3 corresponds to the non-inverting input terminal P of the comparator in fig. 1or 2, the negative input terminal N of the substitution pattern in fig. 3 corresponds to the negative input terminal N of the comparator in fig. 1or 2, the trimming voltage input terminal T of the substitution pattern in fig. 3 corresponds to the trimming voltage input terminal T of the comparator in fig. 1or 2, and the output terminal of the substitution pattern in fig. 3 corresponds to the output terminal of the comparator in fig. 1or 2.
S203: and replacing the comparator in the voltage calibration function test circuit with the replacement model so that the positive phase input end and the negative phase input end are both connected to the output end of the reference voltage generation circuit, and the output end of the replacement model is connected with the input end of the combination logic circuit.
Referring to fig. 3, the positive input terminal P and the negative input terminal N of the substitution model are both connected to the reference voltage generating circuit to receive the reference voltage signal VrefCa provided by the reference voltage generating circuit, so that the voltage signals received by the positive input terminal P and the negative input terminal N of the substitution model are the same, and the output signal of the substitution model is determined only by the excitation signal tm_trim received by the trimming voltage input terminal T. Therefore, the substitution model and the combinational logic circuit constitute a digital simulation model of the voltage calibration function circuit, and the inspection of the voltage calibration function test circuit can be realized through digital simulation.
S204: the excitation signal is input through the trimming voltage input end, and the calibration output signal generated by the combinational logic circuit is monitored so as to compare the calibration output signal with a preset expected output.
It can be seen that the relationship between the stimulus signal input into the surrogate model and the calibration output signal output by the combinational logic circuit can reflect whether the comparator and combinational logic circuit are abnormal, enabling inspection of the voltage calibration functional test circuit.
The excitation signal is a digital signal, the output of the substitution model is a digital signal, and the output of the combination logic circuit is a digital signal, so that the voltage calibration function test circuit is checked through digital simulation.
In some embodiments, the stimulus signal includes one or more test sequences, each test sequence corresponding to a calibration output signal and a preset desired output. For each test sequence, the test sequence is input into the surrogate model and the combinational logic circuit may generate a calibration output signal corresponding to the test sequence. The preset desired output for the test sequence is determined at circuit design time.
Wherein each test sequence may be a binary number, i.e. a digital signal. The predetermined length of the binary number is greater than or equal to 1, that is to say the test sequence is a sequence comprising at least one bit binary. The preset length may be flexibly set, and is generally greater than 1, for example, the preset length may be 3, and the test sequence may be 000, 111, etc.
When the excitation signal comprises a test sequence, comparing a calibration output signal corresponding to the test sequence with a preset expected output. When the calibration output signal of the test sequence is consistent with the preset expected output, determining that the voltage calibration function test circuit of the input buffer is normal; and when the calibration output signal of the test sequence is inconsistent with the preset expected output, determining that the voltage calibration function test circuit of the input buffer is abnormal. For example, the preset expected output of the test sequence is 1, and when the calibration output signal of the test sequence is 1, it may be determined that the voltage calibration function test circuit is normal. When the calibration output signal of the test sequence is 0, it may be determined that the voltage calibration function test circuit is abnormal.
It should be noted that, the inspection performed by the above-mentioned one test sequence cannot cover all scenes, and has a problem of low inspection coverage. In order to improve inspection coverage, embodiments of the present disclosure may be tested through multiple test sequences.
When the excitation signal comprises a plurality of test sequences, the plurality of test sequences may comprise all the desired binary numbers of the predetermined length, such that the number of test sequences comprised by the excitation signal is associated with the predetermined length of the test sequences. When the preset length of the test sequence is N, the number of test sequences may be N to the power of 2. For example, the predetermined length may be 3, and all the possible values of the three-bit binary numbers are 000, 001, 010, 011, 100, 101, 110, 111, so that the stimulus signal may include 8 test sequences 000, 001, 010, 011, 100, 101, 110, 111.
When the test sequence is 000, the corresponding preset expected output may be 0. When the test sequence is 001, the corresponding preset expected output may be 0. When the test sequence is 010, the corresponding preset expected output may be 0. When the test sequence is 011, the corresponding preset expected output may be 0. When the test sequence is 100, the corresponding preset expected output may be 0. When the test sequence is 101, the corresponding preset expected output may be 1. When the test sequence is 110, the corresponding preset expected output may be 1. When the test sequence is 111, the corresponding preset expected output may be 1.
Accordingly, the step S204 may include: and respectively inputting the test sequences into the trimming voltage input end to obtain a plurality of corresponding calibration output signals so as to compare the calibration output signals with preset expected output. And when all the calibration output signals are consistent with the corresponding preset expected output, determining that the voltage calibration function test circuit passes the check. When at least one calibration output signal is inconsistent with a corresponding preset expected output, the voltage calibration function test circuit is determined to check for failure. For example, when the calibration output signals corresponding to the 8 test sequences 000, 001, 010, 011, 100, 101, 110, 111 are 0, 1, and 1, respectively, it may be determined that the voltage calibration function test circuit of the input buffer is normal; otherwise, it may be determined that the voltage calibration function test circuit of the input buffer is abnormal.
The method of the embodiment of the disclosure can be used for checking a voltage calibration function test circuit of an input buffer of a memory, wherein the memory can be a semiconductor device with the input buffer, such as a DRAM (dynamic random access memory), an SRAM (static random accessing memory, static random access memory), a flash memory and the like. The methods of the embodiments of the present disclosure may be implemented in verilog language, i.e., the digital comparison model and the combinational logic model may be represented in verilog language. The Verilog language is a language in which the structure and behavior of digital system hardware is described in text form, and may represent logic circuit diagrams, logic expressions, logic functions performed by a digital logic system, and the like.
Verilog may describe a circuit or system from five levels, including: system level, algorithm level, register transfer level (RTL, REGISTER TRANSFER LEVEL), gate level, switching level. The most commonly used is the RTL level, and thus Verilog code is also often referred to as RTL code. The methods of the embodiments of the present disclosure may be implemented using gate level verilog.
In summary, the embodiments of the present disclosure may construct a surrogate model for the positive and negative inputs of the comparator in a state in which they both receive the reference voltage signal. The constructed substitution model and the combined logic circuit form a digital simulation model of the voltage calibration function test circuit, and the voltage calibration function test circuit is a digital simulation model, so that the voltage calibration function test circuit can be checked through digital simulation. The inspection complexity and time consumption of the voltage calibration function test circuit of the input buffer can be reduced compared to analog simulation.
Fig. 5 is a schematic structural diagram of a voltage calibration function test circuit inspection device for an input buffer according to an embodiment of the disclosure. Referring to fig. 5, the above-described apparatus includes a circuit acquisition module 401, a substitute model creation module 402, a model replacement module 403, and a check module 404.
A circuit acquisition module 401, configured to acquire a voltage calibration function test circuit of the input buffer, where the voltage calibration function test circuit includes a reference voltage generating circuit, a comparator, and a combinational logic circuit; the reference voltage generation circuit is configured to provide a reference voltage signal to the comparator, and the combinational logic circuit is configured to generate a calibration output signal based on an output signal of the comparator.
A surrogate model building module 402 for building a surrogate model of the comparator; the substitution model comprises a positive phase input end, a negative phase input end, an output end and a trimming voltage input end, and is used for outputting an output signal corresponding to the excitation signal according to the excitation signal input by the trimming voltage input end.
A model replacing module 403, configured to replace the comparator in the voltage calibration function test circuit with the replacement model, so that the positive phase input terminal and the negative phase input terminal are both connected to the output terminal of the reference voltage generating circuit, and the output terminal of the replacement model is connected to the input terminal of the combinational logic circuit.
And the checking module 404 is configured to input the excitation signal through the trimming voltage input terminal, and monitor a calibration output signal generated by the combinational logic circuit, so as to compare the calibration output signal with a preset expected output.
In some embodiments, the excitation signal is a digital signal, the output of the surrogate model is a digital signal, and the output of the combinational logic circuit is a digital signal.
In some embodiments, the excitation signal comprises a plurality of test sequences, the inspection module further configured to:
And respectively inputting a plurality of test sequences into the trimming voltage input end to obtain a plurality of corresponding calibration output signals, comparing the calibration output signals with preset expected output, and determining that the voltage calibration function test circuit passes the inspection when all the calibration output signals are consistent with the preset expected output.
In some embodiments, the test sequence consists of binary numbers of a preset length.
In some embodiments, the preset length is 3.
In summary, the embodiments of the present disclosure may construct a surrogate model for the positive and negative inputs of the comparator in a state in which they both receive the reference voltage signal. The constructed substitution model and the combined logic circuit form a voltage calibration function test circuit which is a digital simulation model, so that the voltage calibration function test circuit can be checked through digital simulation. The inspection complexity and time consumption of the voltage calibration function test circuit of the input buffer can be reduced compared to analog simulation.
The voltage calibration function test circuit inspection device of the input buffer is a device embodiment corresponding to the method embodiment, and has the same implementation principle as the method embodiment, and the detailed description may refer to the method embodiment and will not be repeated herein.
Fig. 6 is a block diagram of an electronic device according to an embodiment of the present disclosure. Referring to fig. 6, the electronic device 600 includes a memory 602 and at least one processor 601.
Wherein the memory 602 stores computer-executable instructions.
At least one processor 601 executes computer-executable instructions stored in memory 602 to cause electronic device 600 to implement the method of fig. 4 described above.
The electronic device 600 may further comprise a receiver 603 for receiving information from the remaining apparatus or device and forwarding to the processor 601, and a transmitter 604 for transmitting information to the remaining apparatus or device.
The electronic device 600 is an embodiment of a device corresponding to the method shown in fig. 4, and specific reference may be made to the detailed description of the embodiment of the method shown in fig. 4, which is not repeated herein.
The disclosed embodiments also provide a computer-readable storage medium having stored therein computer-executable instructions for performing a method as shown in fig. 4 when the computer-executable instructions are executed by the electronic device 600.
The computer readable storage medium is an embodiment of an apparatus corresponding to the method shown in fig. 4, and specific reference may be made to the detailed description of the embodiment of the method shown in fig. 4, which is not repeated herein.
The embodiment of the disclosure also provides a computer program for implementing the method shown in fig. 4.
The computer program is an embodiment of an apparatus corresponding to the method shown in fig. 4, and specifically, reference may be made to the detailed description of the embodiment of the method shown in fig. 4, which is not repeated herein.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This disclosure is intended to cover any adaptations, uses, or adaptations of the disclosure following the general principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It is to be understood that the present disclosure is not limited to the precise arrangements and instrumentalities shown in the drawings, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims (10)

1. A method of checking a voltage calibration functional test circuit of an input buffer, the method comprising:
The method comprises the steps of obtaining a voltage calibration function test circuit of the input buffer, wherein the voltage calibration function test circuit comprises a reference voltage generation circuit, a comparator and a combinational logic circuit; the reference voltage generation circuit is used for providing a reference voltage signal to the comparator, and the combinational logic circuit is used for generating a calibration output signal based on the output signal of the comparator;
Establishing a substitution model of the comparator; the substitution model comprises a positive phase input end, a negative phase input end, an output end and a trimming voltage input end, and is used for outputting an output signal corresponding to the excitation signal according to the excitation signal input by the trimming voltage input end;
Replacing the comparator in the voltage calibration function test circuit with the replacement model so that the positive phase input end and the negative phase input end are both connected to the output end of the reference voltage generation circuit, and the output end of the replacement model is connected with the input end of the combinational logic circuit;
And inputting the excitation signal through the trimming voltage input end, and monitoring a calibration output signal generated by the combinational logic circuit to compare the calibration output signal with a preset expected output.
2. The method of claim 1, wherein the stimulus signal is a digital signal, the output of the surrogate model is a digital signal, and the output of the combinational logic circuit is a digital signal.
3. The method of claim 2, wherein the stimulus signal comprises a plurality of test sequences, the inputting the stimulus signal through the trimming voltage input and monitoring the calibration output signal generated by the combinational logic circuit to compare the calibration output signal with a preset desired output, comprising:
And respectively inputting a plurality of test sequences into the trimming voltage input end to obtain a plurality of corresponding calibration output signals, comparing the calibration output signals with preset expected output, and determining that the voltage calibration function test circuit passes the inspection when all the calibration output signals are consistent with the preset expected output.
4. A method according to claim 3, wherein the test sequence consists of binary numbers of a preset length.
5. The method of claim 4, wherein the predetermined length is 3.
6. A voltage calibration function test circuit inspection device for an input buffer, the device comprising:
The circuit acquisition module is used for acquiring a voltage calibration function test circuit of the input buffer, and the voltage calibration function test circuit comprises a reference voltage generation circuit, a comparator and a combinational logic circuit; the reference voltage generation circuit is used for providing a reference voltage signal to the comparator, and the combinational logic circuit is used for generating a calibration output signal based on the output signal of the comparator;
the substitute model building module is used for building a substitute model of the comparator; the substitution model comprises a positive phase input end, a negative phase input end, an output end and a trimming voltage input end, and is used for outputting an output signal corresponding to the excitation signal according to the excitation signal input by the trimming voltage input end;
A model replacement module, configured to replace the comparator in the voltage calibration function test circuit with the replacement model, so that the positive phase input terminal and the negative phase input terminal are both connected to the output terminal of the reference voltage generating circuit, and the output terminal of the replacement model is connected to the input terminal of the combinational logic circuit;
and the checking module is used for inputting the excitation signal through the trimming voltage input end and monitoring a calibration output signal generated by the combinational logic circuit so as to compare the calibration output signal with a preset expected output.
7. The apparatus of claim 6, wherein the stimulus signal is a digital signal, the output of the surrogate model is a digital signal, and the output of the combinational logic circuit is a digital signal.
8. The apparatus of claim 7, wherein the stimulus signal comprises a plurality of test sequences, the inspection module further to:
And respectively inputting a plurality of test sequences into the trimming voltage input end to obtain a plurality of corresponding calibration output signals, comparing the calibration output signals with preset expected output, and determining that the voltage calibration function test circuit passes the inspection when all the calibration output signals are consistent with the preset expected output.
9. An electronic device, comprising: at least one processor and memory;
The memory stores computer-executable instructions;
the at least one processor executing computer-executable instructions stored in the memory causes the electronic device to implement the method of any one of claims 1 to 5.
10. A computer readable storage medium having stored therein computer executable instructions for implementing the method of any of claims 1 to 5 when the computer executable instructions are executed by an electronic device.
CN202310064942.5A 2023-01-11 2023-01-11 Method and device for checking voltage calibration function test circuit of input buffer Pending CN118366507A (en)

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