CN118231316A - Support substrate, method for manufacturing the same, and method for processing semiconductor substrate - Google Patents
Support substrate, method for manufacturing the same, and method for processing semiconductor substrate Download PDFInfo
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- CN118231316A CN118231316A CN202211642631.4A CN202211642631A CN118231316A CN 118231316 A CN118231316 A CN 118231316A CN 202211642631 A CN202211642631 A CN 202211642631A CN 118231316 A CN118231316 A CN 118231316A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/18, H10D48/04 and H10D48/07, with or without impurities, e.g. doping materials
- H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
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Abstract
The invention provides a support substrate, a preparation method thereof and a processing method of a semiconductor substrate, wherein a pit structure in the support substrate forms a hollowed-out design, so that only the edge of the semiconductor substrate is attached to the annular peripheral part of the support substrate when the semiconductor substrate is bonded, and the semiconductor substrate, particularly the central area of a manufactured device, is not damaged. The contact surface is reduced, so that damage to the surface of the semiconductor substrate is reduced. Furthermore, the grooves are formed in the peripheral portion, so that gas generated at the interface during bonding can be well diffused to the external environment, defects such as bubbles are avoided, and in addition, the grooves are beneficial to releasing stress generated during bonding and improving bonding strength. Meanwhile, in the process of removing the bonding layer to be de-bonded, the bonding interface between the semiconductor substrate and the support substrate is easily accessed by corrosive liquid, gas or plasma due to the existence of the groove, so that the bonding layer can be removed more effectively.
Description
Technical Field
The present invention relates to the field of semiconductor and microelectromechanical systems technology, and more particularly, to a support substrate for use in semiconductor processing. Background art in the process of manufacturing semiconductor devices and MEMS (Micro Electro MECHANICAL SYSTEMS: microelectromechanical systems) devices from semiconductor substrates, it is often necessary to process a processed semiconductor substrate (hereinafter simply referred to as a "processed substrate") to a very thin thickness, for example, a thickness of less than 400 μm; many times, a through hole penetrating through the substrate needs to be machined in the processed substrate; many times the substrate being processed is severely warped due to stress. Such processed substrates, whether too thin or having through holes or being severely warped, often cannot be normally adsorbed or gripped by the transfer arm of the processing apparatus, or cannot be normally adsorbed or cooled by the workpiece tray (e.g., e-chuck) of the processing apparatus, or are damaged or even chipped during processing (e.g., ion implantation, or spin-drying) requiring high-speed rotation during semiconductor manufacturing. The above problems become more prominent when the size of the substrate to be processed reaches 6 inches or more.
In order to avoid the above-mentioned problems, a common solution is to bond the substrate to be processed to a supporting substrate, and to detach the substrate to be processed from the supporting substrate by performing debonding after the desired processing is completed. This process is called temporary bonding. The existing temporary bonding is often temporary bonding by using bonding glue. However, such temporary bonding often requires that the entire bonding surface of the semiconductor substrate is in contact with the bonding adhesive, and the entire bonding surface of the semiconductor substrate is often subjected to a certain degree of shearing force or impact force during the debonding, which may cause damage to the semiconductor device. Further, after temporary bonding using a bonding paste, the processing of the semiconductor substrate needs to be performed at a temperature not higher than the debonding temperature or the degradation temperature of the bonding paste, nor chemicals corrosive to the bonding paste can be used; this places a great limitation on the processing of the semiconductor substrate. On the other hand, although the permanent bonding without using the bonding adhesive can have higher bonding strength and can withstand higher process temperatures, the fine structure on the bonding surface of the processed substrate may be damaged when the supporting substrate is bonded or removed because the bonding surface of the processed substrate needs to be directly adhered and bonded to the supporting substrate.
Therefore, there is a need to propose a solution to optimize and improve the structure of the existing support substrate.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a supporting substrate for solving the problem that the semiconductor wafer is easily damaged during the process of using the supporting substrate in the prior art.
To achieve the above and other related objects, the present invention provides a support substrate comprising:
A substrate divided into a central portion and a peripheral portion surrounding the central portion, the central portion being recessed downward relative to the peripheral portion to form a pit;
And the bonding layer covers the upper surface of the peripheral part and is used for bonding the semiconductor substrate, and the material of the bonding layer is different from that of the substrate.
Preferably, the bonding layer also covers the bottom and sidewalls of the pit.
Preferably, grooves arranged in the radial direction are distributed on the upper surface of the peripheral part, and the grooves are communicated with or not communicated with the pits.
Preferably, the depth of the groove is the same as or different from the depth of the pit.
Preferably, the thickness t of the substrate is 400-1000 micrometers, the depth d of the pit is 1-1000 micrometers, and the width l of the peripheral part is 100-20000 micrometers.
The invention also provides a preparation method of the support substrate, which comprises the following steps:
S1: providing a substrate, dividing the substrate into a central part and a peripheral part surrounding the central part;
s2: etching the substrate so that the central portion is recessed downward relative to the peripheral portion to form a pit;
S3: and forming a bonding layer on the surface of the peripheral part.
Preferably, the bonding layer has a thickness of 0.1 to 10 microns.
Preferably, in step S2, grooves disposed in the radial direction are also etched in the peripheral portion, and the grooves are in communication with or not in communication with the pits.
The invention also provides a processing method of the semiconductor substrate, which comprises the following steps:
S1: providing the support substrate according to any one of claims 1 to 5, bonding the support substrate to the semiconductor substrate through a bonding layer on the peripheral portion to obtain a bonded body;
S2: processing the semiconductor substrate through the bonding body;
s3: and removing the bonding layer to separate the semiconductor substrate from the support substrate.
Preferably, the bonding layer includes one of a bonding paste, a silicon compound, and a metal material.
As described above, the present invention provides a support substrate, a method of manufacturing the same, and a method of processing a semiconductor substrate, in which a pit structure in the support substrate is formed in a hollowed-out design so that only an edge of the semiconductor substrate is bonded to an annular peripheral portion of the support substrate without damaging the semiconductor substrate, particularly a central region of a device being fabricated, when the semiconductor substrate is bonded. The contact surface is reduced, so that damage to the surface of the semiconductor substrate is reduced. Furthermore, the grooves are formed in the peripheral portion, so that gas generated at the interface during bonding can be well diffused to the external environment, defects such as bubbles are avoided, and in addition, the grooves are beneficial to releasing stress generated during bonding and improving bonding strength. Meanwhile, in the process of removing the bonding layer to be de-bonded, the bonding interface between the semiconductor substrate and the support substrate is easily accessed by corrosive liquid, gas or plasma due to the existence of the groove, so that the bonding layer can be removed more effectively.
The whole process from bonding to unbinding is only performed at the outermost periphery of the semiconductor wafer, and devices in the central area of the semiconductor wafer are not affected. When the semiconductor substrate is processed after bonding, even if the semiconductor substrate becomes thin or has a through hole, the semiconductor substrate is normally processed by the semiconductor manufacturing equipment without abnormality such as equipment failure, chipping, and the like. In addition, the support substrate is easy to process, can be reused and is easy for mass production.
Drawings
Fig. 1 (a) is a schematic top view of a support substrate according to the first embodiment.
Fig. 1 (b) shows a schematic cross-sectional structure along line AA' in fig. 1 (a).
Fig. 2 (a) is a schematic top view of the bonding layer covering the entire substrate surface in the first embodiment.
Fig. 2 (b) shows a schematic cross-sectional structure along the line BB' in fig. 2 (a).
Fig. 3 (a) is a schematic top view showing a structure in which grooves and pits of the support substrate communicate in the second embodiment.
Fig. 3 (b) shows a schematic cross-sectional structure along line CC' in fig. 3 (a).
Fig. 4 (a) is a schematic top view of the bonding layer covering the entire substrate surface in the second embodiment.
Fig. 4 (b) shows a schematic cross-sectional structure along line DD' in fig. 4 (a).
Fig. 5 (a) is a schematic top view showing a structure in which the grooves of the support substrate do not communicate with the pits in the third embodiment.
Fig. 5 (b) shows a schematic cross-sectional structure along line EE' in fig. 5 (a).
Fig. 6 (a) is a schematic top view of the bonding layer covering the entire substrate surface in the third embodiment.
Fig. 6 (b) is a schematic cross-sectional structure along FF' in fig. 6 (a).
Fig. 7 (a) to 7 (c) are schematic views showing a process for preparing a support substrate in the third embodiment.
Fig. 8 (a) to 8 (f) are schematic views showing a process of manufacturing a semiconductor substrate.
Description of element reference numerals
1. Substrate
11. Center portion
12. Peripheral portion
13. Virtual ring
14. Pit
15. Bonding layer
16. Groove(s)
20. Semiconductor substrate
23. Through hole
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
As described in detail in the embodiments of the present invention, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present. As used herein, "between … …" is meant to include both endpoints.
In the context of the present application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be changed at will, and the layout of the components may be more complex.
Example 1
As shown in fig. 1 (a) -1 (b), the present embodiment provides a support substrate including:
A base 1, the base 1 is divided into a central part 11 and a peripheral part 12 surrounding the central part 11, the central part 11 is recessed downwards relative to the peripheral part 12 to form a pit 14; the central portion 11 is separated from the peripheral portion 12 by a virtual ring 13.
And a bonding layer 15, wherein the bonding layer 15 covers the upper surface of the peripheral portion 12 for bonding the semiconductor substrate 20, and the bonding layer 15 is made of a material different from that of the base 1.
Specifically, the material of the substrate 1 may be one of a conductive substrate such as a silicon substrate and a metal substrate, or may be one of an insulating substrate such as a glass substrate, a quartz substrate, a sapphire substrate, a polymer substrate, and a ceramic substrate. Other material layers may be further disposed on the upper surface of the substrate 1. The semiconductor substrate 20 may be made of various common materials, such as silicon (Si), germanium (Ge), or semiconductor materials including silicon germanium (GeSi), silicon carbide (SiC); silicon On Insulator (SOI), germanium On Insulator (GOI); or may be other materials such as III-V compounds such as gallium arsenide.
The thickness t of the substrate 1 is 400-1000 micrometers, the depth d of the pit 14 is 1-1000 micrometers, and the width l of the peripheral part 12 is 100-20000 micrometers; the diameter of the substrate 1 may be a value of 100mm, 200mm, etc., without being excessively limited thereto.
Specifically, when the depth d of the pit 14 is the same as the thickness of the base 1, this means that the pit 14 penetrates the base 1, and the support substrate at this time is of a ring-shaped structure.
Specifically, the pit 14 structure in the support substrate forms a hollowed-out design so that only the edge of the semiconductor substrate is attached to the annular peripheral portion of the support substrate during bonding of the semiconductor substrate without damaging the semiconductor substrate, particularly the central region of the device being fabricated. The contact surface is reduced, so that damage to the surface of the semiconductor substrate is reduced. The whole process from bonding to unbinding is only performed at the outermost periphery of the semiconductor wafer, and devices in the central area of the semiconductor wafer are not affected. In addition, the support substrate is easy to process, can be reused and is easy for mass production. The bonding layer adopts bonding glue or a silicon compound (such as silicon oxide, silicon nitride and silicon oxynitride) or a metal material (such as one or a combination of copper, nickel, tin, aluminum, silver and titanium), the bonding mode can be flexibly and variously selected according to actual requirements, and the semiconductor substrate can be easily separated from the supporting substrate, so that the process is simple and the production cost is reduced. In addition, even if the semiconductor substrate becomes thin or has a through hole at the time of processing the semiconductor substrate after bonding, the semiconductor substrate is normally processed by the semiconductor manufacturing apparatus without abnormality such as equipment failure, chipping, and the like.
Further, as shown in fig. 2 (a) -2 (b), the bonding layer 15 also covers the bottom and the side walls of the pit 14. The bonding layer 15 may not be controlled in terms of its coverage area when deposited or coated, and thus the bonding layer 15 may also cover the surface of the pit 14, it being understood that the bonding layer 15 on the surface of the pit 14 is not necessary for supporting the substrate and the bonding process, and thus does not require continuity or flatness. The bonding layer 15 on the peripheral portion 12 is required to have continuity and a flat surface morphology.
Further, the shape of the pit 14 shown in the present embodiment is cylindrical, and besides, the shape of the pit 14 may be various shapes such as a cone, a hemisphere, a truncated cone, and the like.
Example two
On the basis of the first embodiment, this embodiment also provides a support substrate, unlike the support substrate in the first embodiment, as shown in fig. 3 (a) -3 (b), grooves 16 are distributed on the upper surface of the support substrate peripheral portion 12 in this embodiment, and the grooves 16 communicate with the pits 14.
Specifically, the depth z of the groove 16 may be the same as or different from the depth d of the pit 14. According to practical needs, as shown in fig. 4 (a) -4 (b), the bonding layer 15 may be covered in the trench 16, or the bonding layer 15 may be absent. The number of grooves 16 is more than two, preferably symmetrically distributed.
Specifically, the grooves 16 are disposed on the peripheral portion 12, so that gas generated at the interface during bonding can be better diffused to the external environment, defects such as bubbles are avoided, and in addition, the grooves 16 are beneficial to releasing stress generated during bonding, so that bonding strength is improved. Meanwhile, in the process of removing the bonding layer 15, the bonding interface of the semiconductor substrate 20 and the support substrate is relatively easily accessed by the etching liquid, gas or plasma due to the presence of the grooves 16, so that the bonding layer 15 can be removed more effectively.
Example III
On the basis of the second embodiment, the present embodiment also provides a support substrate, unlike the support substrate in the second embodiment, the grooves 16 of the upper surface of the support substrate peripheral portion 12 in the present embodiment are not communicated with the pits 14 as shown in fig. 5 (a) to 5 (b).
Specifically, the depth z of the groove 16 may be the same as or different from the depth d of the pit 14. According to practical needs, as shown in fig. 6 (a) -6 (b), the bonding layer 15 may be covered in the trench 16, or the bonding layer 15 may be absent.
Compared with the structure in the second embodiment, the grooves 16 in the second embodiment are not communicated with the inner pits 14, and on the basis of the beneficial effects of the second embodiment, the supporting substrate can be bonded with the semiconductor substrate 20, so that the central area of the semiconductor substrate 20 surrounded by the peripheral portion 12 is ensured not to be in contact with the outside, a sealing effect is formed, and the protection of the surface of the substrate wafer is facilitated. In addition, in the support substrate, grooves communicating with the pits and grooves not communicating with the pits may be present at the same time.
Example IV
The embodiment provides a preparation method of a support substrate, which includes the following steps:
S1: providing a substrate 1, dividing the substrate 1 into a central portion 11 and a peripheral portion 12 surrounding the central portion 11;
s2: etching the substrate 1 such that the central portion 11 is recessed downward relative to the peripheral portion 12 to form a pit 14;
S3: a bonding layer 15 is formed on the surface of the peripheral portion 12.
Through the above steps, the support substrate in the first embodiment is formed.
Specifically, the substrate 1 is selected to be a silicon wafer with a diameter of 200mm. The base 1 is divided into a central portion 11 and a peripheral portion 12 surrounding the central portion 11 by a virtual ring 13. The thickness of the substrate 1 is 600 μm and the width l of the peripheral portion 12, i.e. the distance from the virtual ring 13 to the edge of the substrate 1, is about 4mm.
The depth d of the pit 14 may be uniform throughout or may be non-uniform. For example, d is uniform throughout and d is 10 microns. Pit 14 may be formed by a dry etching process of silicon, which is common in semiconductor manufacturing processes.
The bonding layer 15 is made of bonding glue, or a silicon compound (such as silicon oxide, silicon nitride, silicon oxynitride) or a metal material, and the bonding layer 15 can be formed by a physical vapor deposition process, a chemical vapor deposition process, an evaporation process, a sputtering process, an electroplating process, or the like according to material selection. The bonding layer 15 is made of a material different from that of the substrate 1, for example, the substrate 1 is made of monocrystalline silicon, and the bonding layer 15 is made of silicon oxide. The bonding layer 15 has a thickness of 0.1-10 microns, for example, the bonding layer 15 has a thickness of 1 micron.
Further, in step S2, grooves 16 disposed in the radial direction are also etched in the peripheral portion 12, and the grooves 16 are in communication with the pits 14 (corresponding to the support substrate in the second embodiment) or not (corresponding to the support substrate in the third embodiment). The method for preparing the support substrate in the third embodiment corresponds to the method for preparing the support substrate in the third embodiment shown in fig. 7 (a) -7 (c), wherein the left side is a top view and the right side is a cross-sectional view.
Specifically, the depth of the groove 16 formed in the peripheral portion 12 is z. The depth z of the grooves 16 may or may not be uniform throughout. The depth z of the groove 16 may be the same as or different from the depth d of the pit 14. For example, z is approximately the same as d, i.e., z is also 10 microns. The length p of the groove 16 is approximately 2mm. The grooves 16 may be machined in the same manner as the pits 14. When z is the same as d, the trench 16 may be formed by machining in a synchronous etch with the pit 14.
The bonding layer 15 may be formed only on the surface of the peripheral portion 12, may be formed simultaneously on the surfaces of the pits 14 and the grooves 16, or may be further formed simultaneously on all the surfaces of the substrate 1.
Example five
The present embodiment provides a processing method of a semiconductor substrate, as shown in fig. 8 (a) -8 (f), including the steps of:
S1: providing the support substrate of any one of the first to third embodiments, bonding the support substrate to the semiconductor substrate 20 through the bonding layer 15 on the peripheral portion 12 to obtain a bonded body, as shown in fig. 8 (a) -8 (c);
Specifically, the semiconductor substrate 20 is a processed substrate, and the semiconductor substrate 20 may be made of various common materials, such as silicon (Si), germanium (Ge), or semiconductor materials including silicon germanium (GeSi), silicon carbide (SiC), etc.; silicon On Insulator (SOI), germanium On Insulator (GOI); or may be other materials such as III-V compounds such as gallium arsenide. The semiconductor substrate 20 in this embodiment is a monocrystalline silicon substrate, and has a diameter of about 200mm and a thickness of about 750 μm. The upper and lower surfaces of the semiconductor substrate 20 may be formed with various thin films or device structures, respectively, for example, the surface of the semiconductor substrate 20 is a monocrystalline silicon layer.
The support substrate is the support substrate described in the third embodiment. A pit 14 having a depth d of approximately 10 μm is formed in the central portion 11 of the support substrate, a groove 16 having a depth z of approximately 10 μm is formed in the peripheral portion 12, and silicon oxide having a thickness of approximately 1 μm is formed on the surface thereof as the bonding layer 15. Of course, the bonding layer 15 may be a bonding adhesive if the temperature of the subsequent processing of the semiconductor substrate 20 is sufficiently low.
In the bonding process of the support substrate and the semiconductor substrate 20, the bonding surfaces of the support substrate and the semiconductor substrate may be subjected to planarization and activation, and then subjected to annealing at a temperature of 200 ℃ or higher after being bonded at room temperature, so that the bonding strength reaches the level required for subsequent processing. For example, the annealing treatment is performed at a temperature of 250℃for 2 hours. After bonding, a bonded body is obtained.
Next, step S2 is performed: the semiconductor substrate 20 is thinned and subjected to a via hole processing as shown in fig. 8 (d) -8 (e).
The semiconductor substrate 20 was thinned and polished to obtain a semiconductor substrate 20 having a thickness of 100 μm. The thinned semiconductor substrate 20 can be processed in various semiconductor processing apparatuses without occurrence of abnormality such as chipping and chipping due to the support of the support substrate. Then, a through hole 23 is processed on the thinned semiconductor substrate 20 to obtain a pattern. The semiconductor substrate 20 is etched through by the support of the support substrate, and thus the through hole 23 is formed, and the semiconductor substrate can be processed in various semiconductor processing apparatuses without any abnormality such as chipping or chipping.
Next, step S3 is performed: the bonding layer 15 is removed to separate the semiconductor substrate 20 from the support substrate, as shown in fig. 8 (f).
After the processing of the semiconductor substrate 20 is completed, the semiconductor substrate 20 and the support substrate may be separated by removing the bonding layer, that is, the debonding is completed. The surface of the unbuckled support substrate is free of a bonding layer, and the support substrate without a bonding layer may be reused by forming a bonding layer on the surface thereof. When the bonding layer is silicon oxide, the bonding layer may be removed using a conventional BOE solution (Buffered Oxide Etch, i.e., buffered oxide etchant).
In the process of removing the bonding layer, etching liquid, gas or plasma is relatively easy to access to the bonding interface of the peripheral portions of the semiconductor substrate and the support substrate due to the presence of the trench. In this way, the bonding layer can be effectively removed. Of course, in the processing of the semiconductor substrate, if the grooves communicate with the pits of the support substrate, damage is not generated to the surface of the semiconductor substrate close to the support substrate. That is, the supporting substrate according to the second embodiment is adopted, since the grooves are communicated with the pits of the supporting substrate, the etching liquid, gas or plasma can be filled at both the inner side and the outer side of the peripheral portion, so that the bonding interface between the semiconductor substrate and the supporting substrate is more easily accessed, and the bonding layer can be removed more effectively.
As described above, the present invention provides a support substrate, a method of manufacturing the same, and a method of processing a semiconductor substrate, in which a pit structure in the support substrate is formed in a hollowed-out design so that only an edge of the semiconductor substrate is bonded to an annular peripheral portion of the support substrate without damaging the semiconductor substrate, particularly a central region of a device being fabricated, when the semiconductor substrate is bonded. The contact surface is reduced, so that damage to the surface of the semiconductor substrate is reduced. Furthermore, the grooves are formed in the peripheral portion, so that gas generated at the interface during bonding can be well diffused to the external environment, defects such as bubbles are avoided, and in addition, the grooves are beneficial to releasing stress generated during bonding and improving bonding strength. Meanwhile, in the process of removing the bonding layer to be de-bonded, the bonding interface between the semiconductor substrate and the support substrate is easily accessed by corrosive liquid, gas or plasma due to the existence of the groove, so that the bonding layer can be removed more effectively.
The whole process from bonding to unbinding is only performed at the outermost periphery of the semiconductor wafer, and devices in the central area of the semiconductor wafer are not affected. When the semiconductor substrate is processed after bonding, even if the semiconductor substrate becomes thin or has a through hole, the semiconductor substrate is normally processed by the semiconductor manufacturing equipment without abnormality such as equipment failure, chipping, and the like. In addition, the support substrate is easy to process, can be reused and is easy for mass production.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. A support substrate, the support substrate comprising:
A substrate divided into a central portion and a peripheral portion surrounding the central portion, the central portion being recessed downward relative to the peripheral portion to form a pit;
And the bonding layer covers the upper surface of the peripheral part and is used for bonding the semiconductor substrate, and the material of the bonding layer is different from that of the substrate.
2. The support substrate according to claim 1, wherein: the bonding layer also covers the bottom and sidewalls of the pit.
3. The support substrate according to claim 1, wherein: grooves which are arranged along the radial direction are distributed on the upper surface of the peripheral part, and the grooves are communicated or not communicated with the pits.
4. A support substrate according to claim 3, wherein: the depth of the groove is the same as or different from the depth of the pit.
5. The support substrate according to claim 1, wherein: the thickness t of the substrate is 400-1000 micrometers, the depth d of the pit is 1-1000 micrometers, and the width l of the peripheral part is 100-20000 micrometers.
6. A method of preparing a support substrate, comprising the steps of:
S1: providing a substrate, dividing the substrate into a central part and a peripheral part surrounding the central part;
s2: etching the substrate so that the central portion is recessed downward relative to the peripheral portion to form a pit;
S3: and forming a bonding layer on the surface of the peripheral part.
7. The method of manufacturing according to claim 6, wherein: the bonding layer has a thickness of 0.1-10 microns.
8. The method of manufacturing according to claim 6, wherein: in step S2, grooves disposed in the radial direction are also etched in the peripheral portion, and the grooves are in communication with or not in communication with the pits.
9. A method for processing a semiconductor substrate, comprising the steps of:
S1: providing the support substrate according to any one of claims 1 to 5, bonding the support substrate to the semiconductor substrate through a bonding layer on the peripheral portion to obtain a bonded body;
S2: processing the semiconductor substrate through the bonding body;
s3: and removing the bonding layer to separate the semiconductor substrate from the support substrate.
10. The processing method according to claim 9, characterized in that: the bonding layer comprises one of bonding glue, a silicon compound and a metal material.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211642631.4A CN118231316A (en) | 2022-12-20 | 2022-12-20 | Support substrate, method for manufacturing the same, and method for processing semiconductor substrate |
| PCT/CN2023/123923 WO2024131215A1 (en) | 2022-12-20 | 2023-10-11 | Support substrate and preparation method therefor, and processing method for semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211642631.4A CN118231316A (en) | 2022-12-20 | 2022-12-20 | Support substrate, method for manufacturing the same, and method for processing semiconductor substrate |
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| Publication Number | Publication Date |
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| CN118231316A true CN118231316A (en) | 2024-06-21 |
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| CN202211642631.4A Pending CN118231316A (en) | 2022-12-20 | 2022-12-20 | Support substrate, method for manufacturing the same, and method for processing semiconductor substrate |
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| Country | Link |
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| CN (1) | CN118231316A (en) |
| WO (1) | WO2024131215A1 (en) |
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| CN120749074B (en) * | 2025-09-04 | 2025-12-05 | 芯联集成电路制造股份有限公司 | Stress isolation structure and preparation method thereof, semiconductor device and preparation method thereof, and stress isolation wafer |
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| CN101854578B (en) * | 2010-06-01 | 2013-03-27 | 无锡芯感智半导体有限公司 | Miniature microphone manufacturing method based on Si-Si bonding process |
| JP5501899B2 (en) * | 2010-08-26 | 2014-05-28 | 三菱電機株式会社 | Substrate support plate and temporary wafer fixing method to substrate support plate |
| JP2019198913A (en) * | 2018-05-15 | 2019-11-21 | 株式会社デンソー | Manufacturing method of semiconductor device |
| CN114420621A (en) * | 2021-11-17 | 2022-04-29 | 武汉新芯集成电路制造有限公司 | Bonding method and semiconductor structure |
| CN115274537A (en) * | 2022-08-30 | 2022-11-01 | 长鑫存储技术有限公司 | Temporary bonding structure, temporary carrier and temporary bonding method |
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- 2022-12-20 CN CN202211642631.4A patent/CN118231316A/en active Pending
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| WO2024131215A1 (en) | 2024-06-27 |
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