CN118235325A

CN118235325A - Doherty power amplifier and electronic equipment

Info

Publication number: CN118235325A
Application number: CN202280077297.4A
Authority: CN
Inventors: 丁瑶; 汤岑
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-03-25
Filing date: 2022-03-25
Publication date: 2024-06-21
Also published as: WO2023178682A1

Abstract

The present application provides a Doherty power amplifier and electronic equipment, which relates to the field of power amplifiers and can reduce the number of bare chips (die) used in Doherty power amplifiers. In the Doherty power amplifier, the main power amplifier circuit includes a first amplifier tube, the first auxiliary power amplifier circuit includes a second amplifier tube, and the second auxiliary power amplifier circuit includes a third amplifier tube. The Doherty power amplifier includes a high electron mobility transistor; the transistor includes a source, a gate, a first channel layer, a second channel layer, a first drain, and a second drain; the first drain is electrically connected to the first channel layer, and the second drain is electrically connected to the second channel layer. The first amplifier tube and the third amplifier tube reuse the source of the high electron mobility transistor. The first amplifier tube and the third amplifier tube reuse the gate of the high electron mobility transistor. The first drain of the high electron mobility transistor serves as the drain of the first amplifier tube. The second drain of the high electron mobility transistor serves as the drain of the third amplifier tube.

Description

Doherty power amplifier and electronic equipment

Technical Field

The application relates to the field of power amplifiers, in particular to a Doherty power amplifier and electronic equipment.

Background

A Doherty (Doherty) power amplifier is a high power amplifier that is currently widely used in wireless communication systems. The 3-way Doherty power amplifier has a larger rollback range compared with a 2-way Doherty power amplifier, but in the Doherty power amplifier at present, different bare chips (die) are required to be arranged for amplifying tubes in different power amplifying circuits, and grid voltages are required to be configured independently, so that a series of problems of complex peripheral circuits, poor mass production consistency, high cost and the like are caused, and the 3-way-Doherty power amplifier is difficult to apply in actual products.

Disclosure of Invention

The embodiment of the application provides a Doherty power amplifier and electronic equipment, which can reduce the number of bare chips (die) adopted by the Doherty power amplifier.

The application provides a Doherty power amplifier which comprises a main power amplifier circuit, a first auxiliary power amplifier circuit and a second auxiliary power amplifier circuit. The main power amplifier circuit comprises a first amplifying tube which is used for amplifying signals input to the main power amplifier circuit. The first auxiliary power amplifier circuit includes a second amplifying tube for amplifying a signal input to the first auxiliary power amplifier circuit. The second auxiliary power amplifier circuit comprises a third amplifying tube which is used for amplifying the signal input to the second auxiliary power amplifier circuit. The Doherty power amplifier includes a high electron mobility transistor (first high electron mobility transistor); the high electron mobility transistor includes a source, a gate, a first channel layer, a second channel layer, a first drain, and a second drain. The first drain is electrically connected to the first channel layer, and the second drain is electrically connected to the second channel layer. The source of the first amplifier is the same as the source of the third amplifier, multiplexing the source of the high electron mobility transistor. The gate of the first amplifying tube is the same as the gate of the third amplifying tube, and the gates of the high electron mobility transistors are multiplexed. The first drain of the high electron mobility transistor serves as the drain of the first amplifier tube. The second drain of the high electron mobility transistor serves as the drain of the third amplifier.

In the Doherty power amplifier provided by the embodiment of the application, the multi-channel high electron mobility transistor is adopted as the two amplifying tubes in the main power amplifying circuit and the second auxiliary power amplifying circuit, in this case, the amplifying tubes in the main power amplifying circuit and the second auxiliary power amplifying circuit can meet the requirement by adopting one bare chip, and the first auxiliary power amplifying circuit can meet the requirement by adopting one bare chip; meanwhile, the grid voltage is prevented from being configured for the first amplifying tube and the third amplifying tube independently, so that the circuit complexity of the Doherty power amplifier is simplified, and the cost is reduced.

In some possible implementations, the turn-on voltage of the second amplification tube is greater than the turn-on voltage of the third amplification tube.

In some possible implementations, the source of the high electron mobility transistor is connected to ground; the input signal of the grid electrode of the high electron mobility transistor is amplified by the first amplifying tube and the third amplifying tube and then is output through the first drain electrode and the second drain electrode respectively.

In some possible implementations, the Doherty power amplifier further includes: the power divider comprises a first microstrip line, a second microstrip line, a third microstrip line, a fourth microstrip line, a fifth microstrip line and a power divider. The power divider includes a first output and a second output. The first output terminal is connected to the gate of the high electron mobility transistor through a first microstrip line. The second output end is connected with the grid electrode of the second amplifying tube. The first drain electrode is connected to the combining point through a second microstrip line; the drain electrode of the second amplifying tube is connected to the combining point through a third microstrip line and a fourth microstrip line in sequence; the second drain electrode is connected between the third microstrip line and the fourth microstrip line; the combining point is connected to the output end of the Doherty power amplifier through a fifth microstrip line. Under the condition, the phase compensation is carried out on the output signal of the first output end through the first microstrip line so as to ensure that the total phase of the main power amplifier circuit, the total phase of the first auxiliary power amplifier circuit and the total phase of the second auxiliary power amplifier circuit are basically the same; the second microstrip line, the third microstrip line, the fourth microstrip line and the fifth microstrip line are used for carrying out impedance transformation so as to realize the function of Doherty impedance traction.

In some possible implementations, the high electron mobility transistor includes a substrate; a first channel layer and a first barrier layer are stacked on a substrate, the first barrier layer being located on a side of the first channel layer remote from the substrate. And a second channel layer and a second barrier layer are stacked on the first barrier layer, wherein the second barrier layer is positioned on one side of the second channel layer away from the substrate. And a cap layer disposed on a side of the second barrier layer remote from the substrate. The first drain electrode is disposed on the first channel layer and electrically connected to the first channel layer. The source electrode, the grid electrode and the second drain electrode are arranged on the cap layer, the second drain electrode is electrically connected with the second channel layer, and the source electrode is electrically connected with the first channel layer and the second channel layer.

In some possible implementations, the first drain electrode is in ohmic contact with the first channel layer; the second drain electrode is in ohmic contact with the second channel layer, and the source electrode is in ohmic contact with the first channel layer and the second channel layer. The ohmic contact mode may be etching ohmic contact, injecting ohmic contact, high-temperature metal ohmic contact, etc.

In some possible implementations, a first insertion layer is disposed between the first channel layer and the first barrier layer; a second insertion layer is disposed between the second channel layer and the second barrier layer. The electron mobility of the two-dimensional electron gas generated at the channel can be improved by the arrangement of the insertion layer.

In some possible implementations, a nucleation layer, a buffer layer, are disposed between the substrate and the first channel layer; the nucleation layer is adjacent to the substrate relative to the buffer layer.

In some possible implementations, the high electron mobility transistor includes a plurality of transistor cells arranged in parallel and in series. The plurality of transistor units comprise a first transistor unit, a second transistor unit and a third transistor unit which are sequentially and adjacently arranged. The first transistor unit and the second transistor unit share the same source, and the first transistor unit and the second transistor unit are symmetrically arranged along the source. The second transistor unit and the third transistor unit share the same first drain, and the second transistor unit and the third transistor unit are symmetrical along the first drain. In each transistor cell, the second drain is located in a region between the source and the first drain, and the gate is located in a region between the source and the second drain.

In some possible implementations, the high electron mobility transistor is a GaNHEMT.

The embodiment of the application also provides electronic equipment, which comprises a transmitter; the Doherty power amplifier provided in any one of the possible implementations described above is employed in the transmitter.

Drawings

Fig. 1 is a schematic circuit diagram of a Doherty power amplifier according to an embodiment of the present application;

Fig. 2 is a schematic circuit diagram of a Doherty power amplifier according to an embodiment of the present application;

FIG. 3 is a graph of the operating efficiency of the Doherty power amplifier of FIG. 1;

FIG. 4 is a schematic diagram of a high electron mobility transistor according to the prior art;

fig. 5 is a schematic structural diagram of a high electron mobility transistor according to an embodiment of the present application;

Fig. 6 is a schematic structural diagram of a high electron mobility transistor according to an embodiment of the present application;

fig. 7 is a schematic diagram of layout design of a high electron mobility transistor used in a Doherty power amplifier according to an embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The terms "first," "second," and the like in the description and in the claims and drawings are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or order. "and/or" for describing the association relationship of the association object, the representation may have three relationships, for example, "a and/or B" may represent: only a, only B and both a and B are present, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one" means one or more, and "a plurality" means two or more. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural. "mounted," "connected," and the like are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected; either directly or indirectly through intermediaries, or through communication between two elements. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion, such as a series of steps or elements. The method, system, article, or apparatus is not necessarily limited to those explicitly listed but may include other steps or elements not explicitly listed or inherent to such process, method, article, or apparatus. "upper", "lower", "left", "right", "top", "bottom", etc. are used merely with respect to the orientation of the components in the drawings, these directional terms are relative concepts which are used for descriptive and clarity with respect thereto and which may be varied accordingly with respect to the orientation in which the components are placed in the drawings.

The embodiment of the application provides electronic equipment, wherein a transmitter is arranged in the electronic equipment, and a Doherty power amplifier is arranged in the transmitter and comprises at least three paths of power amplifying circuits, wherein the Doherty power amplifier replaces an amplifying tube in a multi-path power amplifying circuit by a novel multi-channel high electron mobility transistor (high electron mobility transistor, HEMT), which is equivalent to adopting one bare chip to meet the requirements of a plurality of amplifying tubes, and meanwhile, the situation that grid voltages are independently configured for the amplifying tubes is avoided, so that the circuit complexity of the Doherty power amplifier is simplified, and the cost is reduced.

The present application is not limited to the arrangement form of the above-described electronic device. The electronic equipment can be electronic products such as mobile phones, tablet computers, notebooks, vehicle-mounted computers, intelligent watches, intelligent bracelets, radars, base stations and the like.

The following describes schematically the specific structure of the Doherty power amplifier provided in the embodiment of the present application.

Fig. 1 is a schematic circuit diagram of a 3way-Doherty power amplifier according to an embodiment of the present application. As shown in fig. 1, the 3way-Doherty power amplifier includes a main power amplifier circuit 1 (main), a first auxiliary power amplifier circuit 2 (peak 1), and a second auxiliary power amplifier circuit 3 (peak 2). The main power amplifier circuit 1 includes a first amplifying tube d_1, and the signal input to the main power amplifier circuit can be amplified by the first amplifying tube d_1. The first auxiliary power amplifier circuit 2 includes a second amplifying tube d_2, and the signal input to the first auxiliary power amplifier circuit 2 can be amplified by the second amplifying tube d_2. The second auxiliary power amplifier circuit 2 includes a third amplifying tube d_3, and the signal input to the second auxiliary power amplifier circuit 3 can be amplified by the third amplifying tube d_3.

It will be appreciated herein that the multiple power amplifier circuit in the Doherty power amplifier generally includes a main power amplifier circuit (main) and at least one auxiliary power amplifier circuit (peak) other than the main power amplifier circuit (main). The embodiment of the application is illustrated by taking a main power amplifier circuit (main) and two auxiliary power amplifier circuits 2 as examples. In other possible implementations, the Doherty power amplifier may include 3 or more auxiliary power amplifier circuits (peak).

Based on this, the present application also provides a novel dual channel High Electron Mobility Transistor (HEMT), and the specific structure can be referred to in fig. 5 and the following related description. As shown in fig. 1, 2 and 5, the first amplifying tube d_1 and the third amplifying tube d_3 are replaced by the double channel transistor (HEMT), that is, the first amplifying tube d_1 and the third amplifying tube d_3 multiplex the double channel transistor (HEMT). The double channel transistor (HEMT) includes a gate G, a source S, a first channel layer 21, a second channel layer 22, a first drain D1, and a second drain D2. The first drain D1 is electrically connected to the first channel layer 21 and the second drain D2 is electrically connected to the second channel layer 22, i.e. the first drain D1 and the second drain D2 are connected to two different channels (101, 102), respectively. A first drain D1 of the double channel transistor (HEMT) as a drain of the first amplifying transistor d_1; the second drain D2 of the double channel transistor (HEMT) serves as the drain of the third amplifier tube d_3. The gate G of the double-channel transistor (HEMT) is used as the gates of the first amplifying tube D_1 and the third amplifying tube D_3, and the source S of the double-channel transistor (HEMT) is used as the sources of the first amplifying tube D_1 and the third amplifying tube D_3; that is, the gate of the first amplifying transistor d_1 and the gate of the third amplifying transistor d_3 are the same, and the gates of the double channel transistors (HEMTs) are multiplexed; the source of the first amplification tube d_1 and the source of the third amplification tube d_3 are the same, and the source of the double channel transistor (HEMT) is multiplexed.

Illustratively, IN the Doherty power amplifier, a source of a double channel transistor (HEMT) may be connected to a ground terminal, a gate is connected to an input terminal IN of the Doherty power amplifier, and a first drain D1 and a second drain D2 are connected to an output terminal OUT of the Doherty power amplifier through related circuits. IN this way, the signal input from the input terminal IN is amplified by the first amplifying tube d_1 and the third amplifying tube d_3, and then output to the output terminal OUT through the first drain D1 and the second drain D2, respectively.

In summary, compared to the prior art, in the Doherty power amplifier provided in the embodiment of the application, as shown in fig. 1 and 2, the first HEMT1 (multi-channel HEMT) is used as the two amplifiers (d_1 and d_3) in the main power amplifier circuit 1 and the second auxiliary power amplifier circuit 3, and in this case, the requirement can be met by using one die (HEMT 1) for the amplifiers in the main power amplifier circuit 1 and the second auxiliary power amplifier circuit 3, and the requirement can be met by using one die (HEMT 2) for the first auxiliary power amplifier circuit 2; meanwhile, the situation that grid voltages are independently configured for the first amplifying tube D_1 and the third amplifying tube D_3 is avoided, so that the circuit complexity of the Doherty power amplifier is simplified, and the cost is reduced.

Of course, the second amplifying tube d_2 in the second auxiliary power amplifying circuit 3 may use a single channel second high electron mobility transistor HEMT2, in which case, the requirement of 3 paths of power amplifying circuits (1, 2, 3) can be realized by using 2 dies.

In addition, it can be understood that in the multi-path power amplifier circuits (1, 2, 3) of the Doherty power amplifier, the starting sequence of the amplifying tubes is different, and the amplifying tubes in the main power amplifier circuit (main) can be started first, and the amplifying tubes in the auxiliary power amplifier circuit (peak) can be started later.

In this embodiment of the present application, the first amplifying tube d_1, the second amplifying tube d_2, and the third amplifying tube d_3 may be turned on sequentially, that is, the turn-on voltage of the third amplifying tube d_3 (that is, the gate-source voltage vgs_main) is greater than the turn-on voltage (vgs_peak2) of the second amplifying tube d_2, and the turn-on voltage of the second amplifying tube d_2 is greater than the turn-on voltage (vgs_peak1) of the first amplifying tube d_1, that is, vgs_main > vgs_peak1 > vgs_peak2. The following examples are given by way of illustration.

The following is a brief description of the operation state of the Doherty power amplifier.

Referring to fig. 1, 2 and 3, in some possible implementations, the first amplifying tube d_1 is biased in the class AB state, the second amplifying tube d_2 and the third amplifying tube d_3 are biased in the class C state, and the working states of the three-way power amplifier circuits (1, 2 and 3) are changed according to different input powers.

Referring to fig. 1 and 3 (corresponding to the working efficiency curve of fig. 1), in the state 1, the input power is small, only the first amplifying tube d_1 is turned on to work, the circuit matching is designed to make the first amplifying tube d_1 work in a high-resistance and high-efficiency state, at this time, the second amplifying tube d_2 and the third amplifying tube d_3 are not turned on under the bias of class C due to the too small input power, and the impedance presents an open state. As the input power gradually increases, when reaching the saturation point of the first amplifying tube d_1 in the high-resistance state, the efficiency of the first amplifying tube d_1 reaches the maximum value, and by reasonably setting the gate voltage bias of the second amplifying tube d_2, the second amplifying tube d_2 is critical on at this time, and the third amplifying tube d_3 is still in the off state. At this time, the circuit has a value α2=20×log { p_main/(p_main+p_peak1+p_peak2) } with respect to the saturation state. In state 2, the second amplifying tube d_2 (peak 1) is gradually turned on, and pulls the impedance of the first amplifying tube d_1 (main). When the second amplifying tube D_2 (peak 1) reaches the maximum efficiency value, the circuit reaches a second peak efficiency point, and the gate voltage bias of the third amplifying tube D_3 (peak 2) is reasonably set so that the third amplifying tube D_3 (peak 2) is critically started. At this time, the circuit is set to have a value α1=20×log { p_peak1/(p_peak1+p_peak2) } with respect to the saturation state. In state 3, the third amplifying tube d_3 (peak 2) is gradually turned on, and as the third amplifying tube d_3 (peak 2) is turned on, the impedances of the second amplifying tube d_2 (peak 1) and the first amplifying tube d_1 (main) are pulled, and when the third amplifying tube d_3 (peak 2) reaches the saturation point, the second amplifying tube d_2 (peak 1) and the first amplifying tube d_1 (main) also reach the power saturation point, and the full circuit reaches the saturated power and the third peak efficiency point.

The foregoing embodiments are only schematically illustrated by taking the first HEMT1 as a dual channel transistor as an amplifying tube in the two-way power amplifier circuits (1, 3), but the present application is not limited thereto, and in some possible implementations, the Doherty power amplifier may further include a fourth power amplifier circuit, a fifth power amplifier circuit, and so on; the first high electron mobility transistor HEMT1 may also include three or more channels to enable substitution of multiple amplification tubes with in-phase input signals in the Doherty power amplifier. In the embodiment of the application, a 3way-Doherty power amplifier is taken as an example for schematic illustration.

The specific architecture of the 3way-Doherty power amplifier is not limited in the application. As shown in fig. 1 and 2, in some possible implementations, the Doherty power amplifier further includes, in addition to the three amplifying tubes (d_1, d_2, d_3) described above: a first microstrip line 10, a second microstrip line 20, a third microstrip line 30, a fourth microstrip line 40, a fifth microstrip line 50, and a power divider 100. Wherein the power divider 100 comprises a first output out1 and a second output. The first output terminal out1 is connected to the gates of the first high electron mobility transistor HEMT1 (i.e., the gates of the first and third amplification transistors d_1 and d_3) through the first microstrip line 10, and the second output terminal out2 is connected to the gate of the second high electron mobility transistor HEMT2 (i.e., the gate of the second amplification transistor d_2). The drain (i.e., the first drain) of the first amplifying tube d_1 is connected to the combining point O through the second microstrip line 20. The drain electrode of the second amplifying tube d_2 is connected to the combining point O through the third microstrip line 30 and the fourth microstrip line 40 in sequence. The drain (i.e., the second drain) of the third amplification tube d_3 is connected between the third microstrip line 30 and the fourth microstrip line 40. The combining point O is connected to the output terminal OUT of the Doherty power amplifier through the fifth microstrip line 50. The sources of the gates of the first high electron mobility transistor HEMT1 and the second high electron mobility transistor HEMT2 are both connected to ground.

It will be appreciated here that for the input (gate) and output (drain) connections of the above-mentioned amplifiers (d_1, d_2, d_3), the input may be the relevant circuit connection via the input matching circuit and the output may be the relevant circuit connection via the output matching circuit.

It can also be appreciated here that in the Doherty power amplifier described above, the first amplifying tube d_1 and the third amplifying tube d_3 should have input signals with in-phase phases, so as to ensure that the requirement of the input signals for the two amplifying tubes (d_1, d_3) can be satisfied by using the first high electron mobility transistor HEMT 1. In this case, the gate of the first high electron mobility transistor HEMT1 is connected to the same output terminal (first output terminal out 1) of the power divider 100, and the gate of the second high electron mobility transistor HEMT2 is connected to the other output terminal (second output terminal out 2) of the power divider 100.

In the Doherty power amplifier, the phase compensation is performed on the output signal of the first output end out1 through the first microstrip line 10, so as to ensure that the total phase of the main power amplifier circuit 1, the total phase of the first auxiliary power amplifier circuit 2 and the total phase of the second auxiliary power amplifier circuit 3 are basically the same; the second microstrip line 20, the third microstrip line 30, the fourth microstrip line 40 and the fifth microstrip line 50 are used for performing impedance transformation to realize the Doherty impedance pulling function.

The specific structure of the multi-channel high electron mobility transistor provided by the embodiment of the application is further described below with reference to the 3way-Doherty power amplifier.

Fig. 4 is a schematic structural diagram of a conventional single channel electron mobility transistor (HEMT). Referring to fig. 4, one channel layer and one barrier layer are provided in a single channel HEMT, and a two-dimensional electron gas (2-dimension electron gas,2 DEG) is generated at an interface between the channel layer and the barrier layer (i.e., heterojunction interface) to form a channel 100.

In contrast, referring to fig. 5, the dual-channel HEMT adopted in the embodiment of the application forms a plurality of channels (e.g. 101, 102) by repeatedly growing the channel layer and the barrier layer in the epitaxial structure, thereby breaking through the theoretical limit of a single-channel device, and increasing the two-dimensional electron gas (2 DEG) surface density in the channel while maintaining high electron mobility.

Schematically, as shown in fig. 5, an embodiment of the present application provides a dual channel HEMT (i.e., a first HEMT 1) comprising a substrate 11 (substrate), and a nucleation layer 12 (nucleation), a buffer layer 13 (buffer), a first channel layer 21 (channel), a first barrier layer 31 (barrier), a second channel layer 22 (channel), a second barrier layer 32 (barrier), and a cap layer 40 (cap) sequentially disposed on the substrate 11. Wherein an interface between the first channel layer 21 and the first barrier layer 31 forms a first channel 101 and an interface between the second channel layer 22 and the second barrier layer 32 forms a second channel 102.

On the basis, the transistor also comprises a grid electrode G, a source electrode S, a first drain electrode D1 and a second drain electrode D2. The first drain D1 is electrically connected to the first channel layer 21, and the second drain D2 is electrically connected to the second channel layer 22. The first drain electrode D1 may be disposed on the first channel layer 21 to form an electrical connection with the first channel layer 21. The gate electrode G, the source electrode S, and the second drain electrode D2 may be disposed on the cap layer 40, and an electrical connection is formed between the second drain electrode D2 and the second channel layer 22 by means of ion implantation. The source S is electrically connected to the first channel layer 21 and the second channel layer 22 by ion implantation.

The working principle of the double-channel HEMT is as follows: the voltage between the two drains (D1, D2) and the source S (i.e. the drain-source voltage V _D1S、V _D2S) is such that a lateral electric field is generated in the two channels (101, 102), and under the action of the lateral electric field, the two-dimensional electron gas (2 DEG) is transported along the two heterojunction interfaces to form a drain output current (as indicated by the arrow in fig. 5). The depth of a potential well in the heterojunction can be controlled by controlling the voltage input by the grid electrode G, and the surface density of two-dimensional electron gas (2 DEG) in the channels (101 and 102) is changed, so that the output currents of the two drain electrodes (D1 and D2) are controlled.

In this case, when the above-mentioned dual channel HEMT is applied to the 3way-Doherty power amplifier of the present application, the first drain D1 corresponds to the drain of the first amplifying transistor d_1, the second drain D2 corresponds to the drain of the third amplifying transistor d_3, and the dual channel HEMT can convert the conventional planar layout into the vertical layout, and the replacement of the two amplifying transistors (d_1, d_3) is realized by the dual channel HEMT, so that the requirement of the two amplifying transistors (d_1, d_3) can be satisfied by using one die, and simultaneously, the single configuration of the gate voltage for the two power amplifying circuits is avoided, the circuit complexity of the Doherty power amplifier is simplified, and the manufacturing cost is reduced.

In the aforementioned 3way-Doherty power amplifier, the first amplifying transistor d_1 in the main power amplifying circuit 1 is turned on before the third amplifying transistor d_3 in the second auxiliary power amplifying circuit 3, so that for the first HEMT1, the first drain D1 is electrically connected to the first channel 101 (i.e. the lower channel) and the second drain D2 is electrically connected to the second channel 102 (the upper channel), the first channel is turned on before the second channel, and the distance between the adjacent channels is reasonably set, so that the requirements of the main power amplifying circuit 1 (main) and the second auxiliary power amplifying circuit 3 (peak 2) can be satisfied. In practice, the starting voltage of the second auxiliary power amplifier circuit 3 (peak 2) can be adjusted by reasonably setting the distance between the first channel and the second channel, so that two signal paths which are not interfered with each other are formed, and the requirements of the main power amplifier circuit 1 (main) and the second auxiliary power amplifier circuit 3 (peak 2) are met.

The present application is not limited to the manner of electrically connecting the first drain electrode D1 and the first channel layer 21. Illustratively, in some possible implementations, the first drain electrode D1 may be disposed in ohmic contact with the first channel layer 21, thereby ensuring electrical connection between the first drain electrode D1 and the first channel 101. Similarly, the second drain electrode D2 may be disposed to form ohmic contact with the second channel layer 22, and the source electrode S may be disposed to form ohmic contact with the first and second channel layers 21 and 22. Among them, the ohmic contact manner between the source electrode S, the drain electrode (D1, D2) and the channel layer (21, 22) may include, but is not limited to, etching ohmic, injection ohmic, high temperature metal ohmic, and the like.

Schematically, in some possible implementations, as shown in fig. 5, the first drain D1 may be connected to the surface of the first channel layer 21 by etching ohmic contact, the second drain D2 may be connected to the surface of the second channel layer 22 by injecting ohmic contact, and the source S may be connected to the first channel layer 21 and the second channel layer 22 by injecting ohmic contact. In this case, an etching process may be used to remove the film layer above the first channel layer 21, thereby leaking the surface of the first channel layer 21, and making the first drain D1 in the leaking region of the first channel layer 21, so as to ensure ohmic contact between the first drain D1 and the surface of the first channel layer 21. An implantation process is used to perform ion implantation at a position below the source electrode S to form an implantation region a1, and the source electrode S forms ohmic contact with the first channel layer 21 and the second channel layer 22 in the implantation region a 1. An implantation process is used to perform ion implantation at a position below the second drain electrode D2 to form an implantation region a2, and the second drain electrode D2 forms ohmic contact with the second channel layer 22 through the implantation region a 2.

In addition, as shown in fig. 6, in some possible implementations, a first insertion layer n1 may be provided between the first channel layer 21 and the first barrier layer 31, and a second insertion layer n2 may be provided between the second channel layer 22 and the second barrier layer 32, and the electron mobility of the 2DEG generated at the channel (101, 102) may be improved by the provision of the insertion layers (n 1, n 2).

In addition, the materials used for the substrate 11 and other relevant film layers in the transistor are not limited, and may be actually set according to needs.

Illustratively, the substrate 11 may be of a material including, but not limited to, siC, si, gaN, gaAs, inP, and the like.

Illustratively, the nucleation layer 12 may be a material including, but not limited to AlN, inAlN, inGaN, scAlN.

Illustratively, the buffer layer 13 may be formed of materials including, but not limited to AlN, gaN, inAlN, inGaN, scAlN.

Illustratively, the channel layers (21, 22) may be formed from materials including, but not limited to AlN, gaN, inAlN, inGaN, scAlN. For example, in some embodiments, the high electron mobility transistors (HEMT 1, HEMT 2) involved in the foregoing embodiments may both be GaNHEMT, and the channel layers (21, 22) may employ GaN.

Illustratively, the barrier layers (31, 32) may be formed from materials including, but not limited to AlN, gaN, inAlN, inGaN, scAlN.

Illustratively, the intervening layers (n 1, n 2) may be of a material including, but not limited to AlN, gaN, inAlN, inGaN, scAlN.

Illustratively, the cap layer 40 may be formed from materials including, but not limited to SiN, gaN, alN, inAlN, inGaN, scAlN.

The aforementioned second high electron mobility transistor HEMT2 may employ the single channel HEMT shown in fig. 4, but the present application is not limited thereto.

Furthermore, it should be understood by those skilled in the art that in actual layout design (layout), a single HEMT structure may employ a plurality of transistor cells (cells) arranged in parallel, and the distribution of the plurality of transistor cells (i.e., cell structures) arranged in parallel is not limited in the present application.

Illustratively, the layout design of the plurality of transistor cells in the first high electron mobility transistor HEMT1 will be described below taking the dual channel HEMT of fig. 6 as an example. As shown in fig. 7, in some possible implementations, a HEMT may include a plurality of transistor cells (e.g., C1, C2, C3) arranged in parallel and in parallel in sequence, and two adjacent transistor cells are symmetrically arranged. Specifically, the plurality of transistor units include a first transistor unit C1, a second transistor unit C2, and a third transistor unit C3, which are sequentially and adjacently disposed. The first transistor unit C1 and the second transistor unit C2 share the same source S, that is, the first transistor unit C1 and the second transistor unit C2 adopt the same source pattern; and the first transistor cell C1 and the second transistor cell C2 are symmetrically disposed along the source. The second transistor unit C2 and the third transistor unit C3 share the first drain D1, that is, the second transistor unit C2 and the third transistor unit C3 share the first drain pattern, and the second transistor unit C2 and the third transistor unit C3 are symmetrically disposed along the first drain D1. In addition, in each transistor unit (e.g., C1, C2, C3), the second drain D2 is located in a region between the source S and the first drain D1, and the gate G is located in a region between the source S and the second drain D2.

Of course, in the first HEMT1, the sources S of all the transistor cells are connected to the same conductive pattern as the source of the transistor, all the first drains D1 are connected to the same conductive pattern as one output pin of the transistor through the leads, and all the second drains D2 are connected to the same conductive pattern as the other output pin of the transistor through the leads to be connected to the subsequent circuit through the two output pins. The lead wire connected with the first drain electrode D1 and the lead wire connected with the second drain electrode D2 can be isolated by a dielectric bridge or an air bridge, so as to ensure the normal operation of the two output pins.

It is to be understood that the first transistor unit C1, the second transistor unit C2, and the third transistor unit C3 are not particularly limited to the fixed three transistor units in the first HEMT1, but may be any three transistor units disposed adjacently in order among a plurality of transistor units.

In addition, for the layout design of the plurality of transistor cells in the single-channel second high electron mobility transistor HEMT2, the layout of the second drain D2 may be omitted in the transistor cells of the aforementioned first high electron mobility transistor HEMT 1.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

The Doherty power amplifier is characterized by comprising a main power amplifier circuit, a first auxiliary power amplifier circuit and a second auxiliary power amplifier circuit;

The main power amplifier circuit comprises a first amplifying tube, wherein the first amplifying tube is used for amplifying signals input to the main power amplifier circuit;

The first auxiliary power amplifier circuit comprises a second amplifying tube, and the second amplifying tube is used for amplifying signals input to the first auxiliary power amplifier circuit;

The second auxiliary power amplifier circuit comprises a third amplifying tube, and the third amplifying tube is used for amplifying signals input to the second auxiliary power amplifier circuit;

The Doherty power amplifier comprises a high electron mobility transistor; the high electron mobility transistor comprises a source electrode, a grid electrode, a first channel layer, a second channel layer, a first drain electrode and a second drain electrode; the first drain electrode is electrically connected with the first channel layer, and the second drain electrode is electrically connected with the second channel layer;

The source electrode of the first amplifying tube is the same as the source electrode of the third amplifying tube, and the source electrodes of the high electron mobility transistors are multiplexed;

The grid electrode of the first amplifying tube is the same as the grid electrode of the third amplifying tube, and the grid electrode of the high electron mobility transistor is multiplexed;

A first drain of the high electron mobility transistor serves as a drain of the first amplifying tube;

The second drain of the high electron mobility transistor serves as the drain of the third amplifier tube.
The Doherty power amplifier of claim 1, wherein,

The starting voltage of the second amplifying tube is larger than that of the third amplifying tube.
The Doherty power amplifier of claim 1 or 2, wherein,

The source electrode of the high electron mobility transistor is connected with the grounding end;

And after the input signals of the grid electrodes of the high electron mobility transistors are amplified by the first amplifying tube and the third amplifying tube, the input signals are output through the first drain electrode and the second drain electrode respectively.
A Doherty power amplifier as claimed in any one of claims 1-3, wherein,

The Doherty power amplifier further comprises: the first microstrip line, the second microstrip line, the third microstrip line, the fourth microstrip line, the fifth microstrip line and the power divider; the power divider comprises a first output end and a second output end;

The first output terminal is connected to the grid electrode of the high electron mobility transistor through the first microstrip line;

the second output end is connected with the grid electrode of the second amplifying tube;

The first drain electrode is connected to a combining point through the second microstrip line;

the drain electrode of the second amplifying tube is connected to the combining point through the third microstrip line and the fourth microstrip line in sequence;

The second drain electrode is connected between the third microstrip line and the fourth microstrip line;

The combining point is connected to the output end of the Doherty power amplifier through the fifth microstrip line.
The Doherty power amplifier of any one of claims 1-4, wherein,

The high electron mobility transistor includes:

A substrate;

The first channel layer and the first barrier layer are stacked on the substrate, and the first barrier layer is positioned on one side of the first channel layer away from the substrate;

the second channel layer and the second barrier layer are stacked on the first barrier layer, and the second barrier layer is positioned on one side of the second channel layer away from the substrate;

A cap layer disposed on a side of the second barrier layer remote from the substrate;

A first drain electrode disposed on the first channel layer and electrically connected to the first channel layer;

the source electrode, the grid electrode and the second drain electrode are arranged on the cap layer, the second drain electrode is electrically connected with the second channel layer, and the source electrode is electrically connected with the first channel layer and the second channel layer.
The Doherty power amplifier of claim 5, wherein,

The first drain electrode is in ohmic contact with the first channel layer;

the second drain electrode is in ohmic contact with the second channel layer;

The source electrode is in ohmic contact with the first channel layer and the second channel layer.
The Doherty power amplifier of claim 5 or 6, wherein,

A first insertion layer is arranged between the first channel layer and the first barrier layer;

a second insertion layer is disposed between the second channel layer and the second barrier layer.
The Doherty power amplifier of any one of claims 5-7, wherein,

A nucleation layer and a buffer layer are arranged between the substrate and the first channel layer;

the nucleation layer is proximate to the substrate relative to the buffer layer.
The Doherty power amplifier of any one of claims 5-8, wherein,

The high electron mobility transistor comprises a plurality of transistor units which are arranged in parallel in sequence;

The plurality of transistor units comprise a first transistor unit, a second transistor unit and a third transistor unit which are sequentially and adjacently arranged;

The first transistor unit and the second transistor unit share a source and are symmetrically arranged along the source;

The second transistor unit and the third transistor unit share a first drain and are symmetrical along the first drain;

In each of the transistor cells, a second drain is located in a region between the source and the first drain, and the gate is located in a region between the source and the second drain.
The Doherty power amplifier of any one of claims 1-9, wherein the high electron mobility transistor is GaNHEMT.
An electronic device comprising a transmitter; a Doherty power amplifier as claimed in any one of claims 1-10 for use in said transmitter.