CN118132324B - Chip memory repair method and device - Google Patents
Chip memory repair method and device Download PDFInfo
- Publication number
- CN118132324B CN118132324B CN202410544668.6A CN202410544668A CN118132324B CN 118132324 B CN118132324 B CN 118132324B CN 202410544668 A CN202410544668 A CN 202410544668A CN 118132324 B CN118132324 B CN 118132324B
- Authority
- CN
- China
- Prior art keywords
- sub
- memory
- column
- characteristic value
- row
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0793—Remedial or corrective actions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F18/00—Pattern recognition
- G06F18/20—Analysing
- G06F18/22—Matching criteria, e.g. proximity measures
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Data Mining & Analysis (AREA)
- Quality & Reliability (AREA)
- Artificial Intelligence (AREA)
- Evolutionary Computation (AREA)
- Evolutionary Biology (AREA)
- Computer Vision & Pattern Recognition (AREA)
- Bioinformatics & Computational Biology (AREA)
- Bioinformatics & Cheminformatics (AREA)
- Life Sciences & Earth Sciences (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The application provides a method and a device for repairing a chip memory, wherein the method comprises the following steps: acquiring a characteristic value, wherein the characteristic value is formed by splicing a plurality of sub-characteristic values; each of the plurality of sub-feature values is a row feature value or a column feature value; the line characteristic value is used for indicating the position of a damaged line in the chip memory; the column characteristic value is used for indicating the position of a damaged column in the chip memory; acquiring accessed memory information, wherein the memory information comprises a memory address; determining a repair register corresponding to a first sub-feature value under the condition that the memory address is matched with the first sub-feature value in the feature values; the first sub-feature value is one of a plurality of sub-feature values; and repairing the memory location indicated by the memory address according to the repair register corresponding to the first sub-characteristic value. By adopting the method, the row characteristic value and the column characteristic value can be obtained at one time to repair the two modes, namely the row mode and the column mode, so that the memory repair capability is improved.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a method and an apparatus for repairing a chip memory.
Background
The memory test of a System On Chip (SOC) is an important component in the mass production test of chips, and the memory test of the chips is generally performed by an automatic test equipment (Automatic Test Equipment, ATE), and after the test, the chips with damaged or defective memory in the Chip production and manufacturing process can be screened out and repaired.
The traditional memory repair mode mainly comprises two types of column mode repair and row mode repair, however, as the chip production process is continuously developed to low nanometer size, the probability of occurrence of memory manufacturing defects is continuously increased, and the traditional memory repair schemes of the column mode and the row mode are limited by the size of a memory and cannot effectively perform memory repair.
Therefore, how to improve the memory repair capability of SOC chips is a major concern.
Disclosure of Invention
The application provides a method and a device for repairing a chip memory, which are used for improving the repairing capability of the chip memory.
In a first aspect, the present application provides a method for repairing a chip memory, the method comprising:
acquiring a characteristic value, wherein the characteristic value is formed by splicing a plurality of sub-characteristic values; each sub-feature value in the plurality of sub-feature values is a row feature value or a column feature value; the line characteristic value is used for indicating the position of a damaged line in the chip memory; the column characteristic value is used for indicating the position of a damaged column in the chip memory;
Acquiring accessed memory information, wherein the memory information comprises a memory address;
Determining a repair register corresponding to a first sub-feature value in the memory address and the first sub-feature value in the feature values under the condition that the memory address is matched with the first sub-feature value; the first sub-feature value is one of the plurality of sub-feature values;
and repairing the memory location indicated by the memory address according to the repair register corresponding to the first sub-characteristic value.
According to the chip memory repair method provided by the application, the acquired characteristic value is formed by splicing a plurality of sub-characteristic values, the sub-characteristic values can be row characteristic values or column characteristic values, that is, the characteristic values can be composed of two types of characteristic values, namely the row characteristic values and the column characteristic values, but not composed of a single type of characteristic values, when an accessed memory address is matched with a first sub-characteristic value in the characteristic values, a repair register corresponding to the first sub-characteristic value is determined according to the first sub-characteristic value, and the memory address is repaired according to the repair register corresponding to the first sub-characteristic value.
In one possible design, the memory information further includes a type of the memory address; and determining a repair register corresponding to a first sub-feature value in the memory address and the feature value under the condition that the first sub-feature value is matched, wherein the repair register comprises: determining a repair register corresponding to a first sub-feature value under the condition that the memory address is matched with the first sub-feature value in the feature values and the type of the memory address is matched with the type of the first sub-feature value; the matching of the type of the memory address with the type of the first sub-characteristic value comprises that the type of the memory address is a row address, and the type of the first sub-characteristic value is a row characteristic value; or the type of the memory address is a column address, and the type of the first sub-characteristic value is a column characteristic value.
In one possible design, the repair register corresponding to the first sub-feature value is one of K repair registers; the K repair registers are determined according to I redundant rows and J redundant columns of the chip memory; i and J are positive integers, K is the sum of I and J, and K is an integer greater than or equal to 2; and each repair register is used for repairing the damaged point in the chip memory based on the redundant row or the redundant column.
In one possible design, the repair register corresponding to the first sub-feature value corresponds to a first redundant row; repairing the memory location indicated by the memory address according to a repair register corresponding to the first sub-feature value, including: and repairing the damaged point in the line indicated by the memory address according to the first redundant line.
If the accessed memory address is matched with the first sub-characteristic value and the first sub-characteristic value belongs to the line characteristic value, the fact that a damage point exists in a line indicated by the currently accessed memory address or the line is damaged by the line indicated by the currently accessed memory address is indicated, and the damage point in the line indicated by the currently accessed memory address is repaired according to a first redundant line corresponding to a repair register corresponding to the first sub-characteristic value; or replacing the currently accessed row indicated by the memory address with the first redundant row corresponding to the repair register corresponding to the first sub-characteristic value so as to achieve the effect of memory row repair.
In one possible design, the repair register corresponding to the first sub-feature value corresponds to a first redundant column; repairing the memory location indicated by the memory address according to a repair register corresponding to the first sub-feature value, including: and repairing the damaged point in the column indicated by the memory address according to the first redundant column.
If the accessed memory address is matched with the first sub-characteristic value and the first sub-characteristic value belongs to the column characteristic value, the fact that a damage point exists in a column indicated by the currently accessed memory address or the column indicated by the currently accessed memory address is a damage column is indicated, and the damage point in the column indicated by the currently accessed memory address is repaired according to a first redundant column corresponding to a repair register corresponding to the first sub-characteristic value; or replacing the column indicated by the currently accessed memory address with a first redundant column corresponding to the repair register corresponding to the first sub-characteristic value so as to achieve the effect of memory column repair.
In one possible design, the obtaining the feature value includes:
and executing a memory self-built automatic test (BIST) on the chip memory by adopting Automatic Test Equipment (ATE) to acquire the characteristic value.
In a second aspect, the present application further provides a device for repairing a chip memory, where the device includes: a transceiver unit and a processing unit;
The receiving and transmitting unit is used for acquiring a characteristic value, and the characteristic value is formed by splicing a plurality of sub-characteristic values; each sub-feature value in the plurality of sub-feature values is a row feature value or a column feature value; the line characteristic value is used for indicating the position of a damaged line in the chip memory; the column characteristic value is used for indicating the position of a damaged column in the chip memory; acquiring accessed memory information, wherein the memory information comprises a memory address;
The processing unit is used for determining a repair register corresponding to a first sub-characteristic value in the memory address and the first sub-characteristic value in the characteristic values under the condition that the memory address is matched with the first sub-characteristic value; the first sub-feature value is one of the plurality of sub-feature values; and repairing the memory location indicated by the memory address according to the repair register corresponding to the first sub-characteristic value.
In one possible design, the memory information further includes a type of the memory address; in the case that the memory address matches a first sub-feature value of the feature values, the processing unit is configured to, when determining a repair register corresponding to the first sub-feature value: determining a repair register corresponding to a first sub-feature value under the condition that the memory address is matched with the first sub-feature value in the feature values and the type of the memory address is matched with the type of the first sub-feature value; the matching of the type of the memory address with the type of the first sub-characteristic value comprises that the type of the memory address is a row address, and the type of the first sub-characteristic value is a row characteristic value; or the type of the memory address is a column address, and the type of the first sub-characteristic value is a column characteristic value.
In one possible design, the repair register corresponding to the first sub-feature value is one of K repair registers; the K repair registers are determined according to I redundant rows and J redundant columns of the chip memory; i and J are positive integers, K is the sum of I and J, and K is an integer greater than or equal to 2; and each repair register is used for repairing the damaged point in the chip memory based on the redundant row or the redundant column.
In one possible design, the repair register corresponding to the first sub-feature value corresponds to a first redundant row; the processing unit is configured to, when repairing the memory location indicated by the memory address according to the repair register corresponding to the first sub-feature value: and repairing the damaged point in the line indicated by the memory address according to the first redundant line.
In one possible design, the repair register corresponding to the first sub-feature value corresponds to a first redundant column; the processing unit is configured to, when repairing the memory location indicated by the memory address according to the repair register corresponding to the first sub-feature value: and repairing the damaged point in the column indicated by the memory address according to the first redundant column.
In one possible design, the transceiver unit is configured to, when acquiring the feature value: and executing a memory self-built automatic test (BIST) on the chip memory by adopting Automatic Test Equipment (ATE) to acquire the characteristic value.
In a third aspect, the present application further provides a device for repairing a chip memory, including: one or more processors and one or more memories, wherein the one or more memories store one or more programs that, when executed by the one or more processors, cause the apparatus to perform the method of any of the above first aspects.
In a fourth aspect, the present application also provides a computer readable storage medium comprising a program which, when executed on an apparatus, causes the apparatus to perform the method of any of the first aspects above.
In a fifth aspect, the application also provides a computer program product comprising a computer program which, when executed by a processor, implements the method of any of the first aspects described above.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a chip memory according to an embodiment of the present application;
FIG. 2 is a schematic flow chart of a method for repairing a chip memory according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a repair register setting logic according to an embodiment of the present application;
FIG. 4 is a schematic diagram illustrating a connection between repair registers according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a chip memory repair device according to an embodiment of the present application;
fig. 6 is a schematic diagram of a second embodiment of a chip memory repair device.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail below with reference to the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The application scenario described in the embodiment of the present application is for more clearly describing the technical solution of the embodiment of the present application, and does not constitute a limitation on the technical solution provided by the embodiment of the present application, and as a person of ordinary skill in the art can know that the technical solution provided by the embodiment of the present application is applicable to similar technical problems as the new application scenario appears. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.
Conventional SOC memory repair generally only supports row mode repair or column mode repair, and has very limited repair capability, for example, taking the chip memory shown in fig. 1 as an example, the memory shown in fig. 1 has 13 rows and 13 columns, and the black small square in fig. 1 is a damage point, which may also be called a defect (defect) point or a fault point, and if a certain row or a certain column has a damage point, it indicates that the row or the column is a damaged column, and the row or the column cannot be accessed normally.
The 2 nd, 3 rd, 6 th and 9 th rows of the chip memory shown in fig. 1 have damage points, that is, the 4 th rows cannot be accessed normally and need to be repaired; similarly, in fig. 1, there are damage points in columns 3, 5, 6 and 7, that is, the 4 columns cannot be accessed normally and also need to be repaired.
In the design stage of the chip memory, a redundancy column or redundancy row is generally preset to enable the memory to have a certain fault tolerance, for example, the 10 th to 13 th rows in fig. 1 are preset redundancy columns, and the 10 th to 13 th rows are preset redundancy rows. If the memory shown in fig. 1 is repaired according to a single line mode repair, since one redundant line can repair only one damaged line, the 4 redundant lines 10 to 13 are required to repair the 4 damaged lines 2,3, 6 and 9 in fig. 1, respectively, that is, the single line mode repair requires 4 redundant lines in total to completely repair the 4 damaged lines in fig. 1.
If the memory shown in fig. 1 is repaired according to a single column pattern repair, only one damaged column can be repaired by one redundant column, and therefore, the 4 damaged columns of the 3 rd column, the 5 th column, the 6 th column and the 7 th column in fig. 1 need to be repaired by using the 4 redundant columns of the 10 th to 13 th columns, that is, the 4 damaged columns in fig. 1 can be completely repaired by using the single column pattern repair.
From the above, if the preset redundant rows have only 2 rows or the preset redundant columns have only 2 columns, only 2 rows of the 4 damaged rows in fig. 1 can be repaired; or repairing 2 of the 4 damaged columns in fig. 1, namely, all the damaged rows and all the damaged columns shown in fig. 1 cannot be repaired, and the repairing capability is limited; if enough redundant columns and redundant rows are preset, larger memory space is occupied, and the design cost is higher.
In order to solve the above problem of limited repair capability of performing single row mode repair and single column mode repair, the present application proposes a method for repairing a chip memory as shown in fig. 2, where the method adopts repair registers to repair a memory, each repair register may also be called repair node (repair node), and each repair register has a corresponding comparison module, where the comparison module may be in communication with the repair register and is used to perform matching between an accessed memory address and a feature value, i.e. execute step 202, where an execution body of the method may be the repair register or the comparison module corresponding to the repair register, which is not limited in this application.
The chip memory repair method provided by the application is developed by taking a comparison module corresponding to a repair register as an execution main body, and the method specifically comprises the following steps:
step 200: the comparison module obtains the characteristic value.
For example, the ATE is used to perform a memory self-building automatic test (Built-IN SELF TEST, BIST) on the chip memory to be tested, so that the feature value of the chip to be tested can be obtained, where the feature value is formed by splicing multiple sub-feature values, each of the multiple sub-feature values is a row feature value or a column feature value, where the row feature value is used to indicate a location of a damaged row in the chip memory to be tested, and the column feature value is used to indicate a location of a damaged column in the chip memory to be tested.
In addition, the comparison module may further obtain the number of the row feature values in the plurality of sub-feature values, the number of the bit of the row feature values, the number of the column feature values in the plurality of sub-feature values, the number of the column feature values, and the order of the plurality of sub-feature values. Illustratively, the order of the plurality of sub-feature values may be a row feature value followed by a column feature value, or a column feature value followed by a row feature value, etc., as the application is not limited in this regard.
Illustratively, the line feature value is a binary number, the number of bits of the line feature value is associated with the number of memory lines, and assuming that the number of memory lines is denoted as a, the calculation formula of the number of bits of the line feature value is as follows:
For example, the number of rows in the chip memory shown in fig. 1 is 13, then the number of bits of the row feature value is 4, the row feature value 0010 is used to indicate the 2 nd row of the damaged row in fig. 1, the row feature value 0011 is used to indicate the 3 rd row of the damaged row in fig. 1, the row feature value 0110 is used to indicate the 6 th row of the damaged row in fig. 1, and the row feature value 1111 is used to indicate the 9 th row of the damaged row in fig. 1.
Illustratively, the column feature value is a binary number, the number of bits of the column feature value is associated with the number of memory columns, and assuming that the number of memory columns is B, the calculation formula of the number of bits of the column feature value is as follows:
for example, the number of columns in the chip shown in fig. 1 is 13, and then the number of bits of the column feature value is also 4, the column feature value 0011 is used to indicate that the 3 rd column in fig. 1 is a damaged column, the column feature value 0101 is used to indicate that the 5 th column in fig. 1 is a damaged column, the column feature value 0110 is used to indicate that the 6 th column in fig. 1 is a damaged column, and the column feature value 0111 is used to indicate that the 7 th column in fig. 1 is a damaged column.
Further exemplary, if there are M damage points in the chip memory, where M is a positive integer, the M damage points at most correspond to M row feature values and M column feature values, that is, any two damage points in the M damage points are located in different rows or any two damage points are located in different columns. If there are at least two damage points located in the same row, the at least two damage points correspond to the same row feature value, for example, taking two damage points in the 2 nd row in fig. 1 as an example, the two damage points are located in the 2 nd row, that is, the corresponding row feature values are the same. If there are at least two damage points located in the same column, the at least two damage points correspond to the same column feature value, for example, taking two damage points in column 3 in fig. 1 as an example, the two damage points are located in column 3, that is, the corresponding column feature values are the same.
Based on the relationship between the damage points and the feature values, for the chip memory shown in fig. 1, after the BIST test is executed, the feature values obtained by the disposable programming component (fuse box) in the chip are formed by splicing 2 row feature values and 1 column feature value, and the 2 row feature values are row feature values ①: 0010 (indicating row 2 in fig. 1) and row feature values ②: 0110 (for indicating the 6 th row of behavior damage in fig. 1), 1 column eigenvalue is column eigenvalue ①: 0101 (for indicating that column 5 in fig. 1 is a damaged column), assuming that the splicing order is that the row eigenvalue is before, the obtained eigenvalue is 2 row eigenvalues and then 1 column eigenvalue is spliced again, that is, row eigenvalue ① is spliced with row eigenvalue ② and then column eigenvalue ① is 001001100101.
In an exemplary embodiment, the logic of setting a repair register in a chip memory in the chip design stage is shown in fig. 3, and it is first determined whether there is a redundant row in the chip memory, if there is a redundant row, a repair register is set in the chip memory, and only one repair register can be set in the chip memory at a time; if the redundant row does not exist in the chip memory, judging whether a redundant column exists in the chip memory, and if the redundant column exists, setting a repair register in the chip memory; the order of determining whether the redundant rows and the redundant columns exist in fig. 3 may be exchanged, and the present application is not limited thereto.
Illustratively, K repair registers in the chip memory are determined from I redundant rows and J redundant columns in the chip memory, I and J being positive integers, K being the sum of I and J, K being an integer greater than or equal to 2; each repair register in the K repair registers is used for repairing a damaged point in the chip memory based on the redundant row; or for repairing a defective spot in the chip memory based on the redundant columns.
For example, assuming that 1 row of redundant columns and 1 column of redundant columns exist in a certain chip memory, a repair register is set in the memory according to the 1 row of redundant columns and a repair register is set in the memory according to the 1 column of redundant columns, that is, there are 2 repair registers in total in the memory; assuming that 2 rows of redundant columns and 1 column of redundant columns exist in a certain chip memory, 2 repair registers are sequentially arranged in the memory according to the 2 rows of redundant columns, and one repair register is arranged in the memory according to the 1 column of redundant columns, namely 3 repair registers are arranged in the memory in total.
It should be noted that, the correspondence between each repair register and the redundant row or the redundant column may be set by itself. If one repair register corresponds to the redundant row, the repair register can repair the damaged row indicated by any row characteristic value; if one repair register corresponds to a redundant column, the repair register can repair a damaged column indicated by any column characteristic value, which is not limited in the application.
For example, in fig. 1, there are 4 rows and 4 columns of redundant columns, and then 8 repair registers are in the memory shown in fig. 1, and are denoted as repair registers 1-8; assuming that the repair register 1 corresponds to the 10 th row redundancy row of fig. 1, the repair register 2 corresponds to the 11 th row redundancy row of fig. 1, the repair register 3 corresponds to the 12 th row of fig. 1, the repair register 4 corresponds to the 13 th row of fig. 1, the repair register 5 corresponds to the 10 th column redundancy column of fig. 1, the repair register 6 corresponds to the 11 th column redundancy column of fig. 1, the repair register 7 corresponds to the 12 th column redundancy column of fig. 1, and the repair register 8 corresponds to the 13 th column redundancy column of fig. 1, the repair registers 1 to 4 can repair the location of the damaged row indicated by the row characteristic value, and the repair registers 5 to 8 can repair the location of the damaged column indicated by the column characteristic value.
Illustratively, the fuse box is connected with the repair registers in the chip memory through a joint test working group (Joint Test Action Group, JTAG) chain, the fuse box transmits the acquired characteristic value to the repair registers through the JTAG chain, the repair registers are also connected through the JTAG chain, and the repair registers can communicate with each other to transmit the characteristic value.
For example, as shown in fig. 4, the fuse box is connected with the repair register 1 through a JTAG chain, the repair registers 1 and 2 are connected with each other through a JTAG chain, the repair registers 2 and 3 are connected with each other through a JTAG chain, and the connection between the repair registers 3 to 8 is similar to the connection between the repair registers 1 to 3, and will not be repeated here. The fuse box transfers the acquired characteristic value 001001100101 to the repair register 1, the repair register 1 transfers the characteristic value to the repair register 2, and the repair register 2 transfers the characteristic value to the repair register 3.
Illustratively, as described above, each repair register has a corresponding comparison module, each repair register is communicable with the corresponding comparison module, and the repair registers transmit the obtained characteristic values to the corresponding comparison modules for subsequent matching with the accessed memory addresses. The corresponding relation between the repair register and the comparison module is as follows:
First kind: different repair registers correspond to different comparison modules, for example, repair register 1 has a corresponding comparison module 1, and repair register 1 transmits the characteristic value to comparison module 1; the repair register 2 is provided with a corresponding comparison module 2, and the repair register 2 transmits the characteristic value to the comparison module 2; the repair register 3 has a corresponding comparison module 3, and the repair register 3 transmits the characteristic value to the comparison module 3.
Second kind: the plurality of repair registers correspond to the same comparison module, for example, repair registers 1-8 correspond to the same comparison module, and any one of repair registers 1-8 transmits the characteristic value to the comparison module.
Through the step, the method and the device are based on the same logic area and complexity of the chip memory as that of single row mode repair or single column mode repair, the repair register can acquire the characteristic value formed by splicing the row characteristic value and the column characteristic value at one time, and the repair register transmits the acquired characteristic value to the corresponding comparison module for matching with the accessed memory address in the subsequent step 202.
Step 201: the comparison module obtains the accessed memory information, wherein the memory information comprises a memory address.
The memory address may be a binary number, including a row address or a column address, for example; if the memory address is a row address, the row address may indicate a row in the memory; if the memory address is a column address, the column address may indicate a column in the memory; the row address and the row characteristic value are expressed in the same manner, and the column address and the column characteristic value are expressed in the same manner, which is not described herein. The accessed memory information further includes a type of memory address, where the type of memory address is used to indicate that the memory address is a row address or a column address, for example, the type of memory address may be used to identify the row address with 0 and identify the column address with 1, and after the memory address is spliced, other identification manners may also be used, and the row address and the column address may be distinguished. The comparison module can obtain the accessed memory information from the reading module in the chip memory.
For example, assuming that the 6 th row of the memory shown in fig. 1 is accessed, the accessed memory information obtained by the comparison module from the reading module is 01100, where 0110 indicates the 6 th row of the row indicating the accessed memory address, and 0 of the last bit is the type of the memory address and is used to identify the accessed memory address as a row address; assuming that column 3 of the memory shown in fig. 1 is accessed, the accessed memory information obtained by the comparison module from the reading module is 00111, where 0011 indicates that the column indicated by the accessed memory address is column 2, and the last 1 is the type of the memory address and is used to identify that the accessed memory address is a column address.
Step 202: in the case that the memory address matches a first sub-feature value of the feature values, the comparison module determines a repair register corresponding to the first sub-feature value.
The comparison module may obtain the feature value through the step 200, the comparison module may obtain the accessed memory address through the step 201, after the comparison module obtains the feature value, the obtained feature value is split into a plurality of sub-feature values according to the number of the row feature values, the number of the column feature values and the number of the column feature values (the splitting operation may also be performed in a repair register, the repair register may transmit the split plurality of sub-feature values to the comparison module, the application is not limited thereto), if the comparison module determines that the accessed memory address is not matched with the plurality of sub-feature values, it indicates that the accessed memory address is not damaged, repair is not required, and normal access may be performed; if the memory address matches a first sub-feature value in the feature values, indicating that the memory location indicated by the accessed memory address is damaged, determining a repair register corresponding to the first sub-feature value, wherein the first sub-feature value is one of a plurality of sub-feature values.
Further, in addition to the matching of the memory address with the first sub-feature value in the feature values, it is also required to determine whether the type of the memory address matches the type of the first sub-feature value. The type of the memory address is matched with the type of the first sub-characteristic value, wherein the type of the memory address is a row address, and the type of the first sub-characteristic value is a row characteristic value; or the type of the memory address is a column address, and the type of the first sub-feature value is a column feature value.
And determining a repair register corresponding to the first sub-characteristic value under the condition that the first sub-characteristic value in the memory address and the characteristic value is matched and the type of the memory address is matched with the type of the first sub-characteristic value.
Assuming that the corresponding relation between the repair register and the comparison module is the first one, the repair register 1-8 corresponds to the comparison module 1-8, the feature value obtained by the comparison module 1-8 is 001001100101, and the comparison module obtains that the number of the row feature values included in the feature value is 2, the number of the row feature values is 4, the number of the column feature values is 1, and the number of the column feature values is 4. The comparison modules 1-8 divide the obtained characteristic values 001001100101 into a plurality of sub-characteristic values ① according to the number of the row characteristic values being 2, the number of the bit numbers of the row characteristic values being 4, the number of the column characteristic values being 1 and the number of the bit numbers of the column characteristic values being 4: 0010. sub-feature value ②: 0110 and sub-feature value ③: 0101.
In example 1, assuming that the accessed memory information obtained by the comparison module 1 is 10000, where the first 4 bits in the memory information are memory addresses, the last bit is the type of the memory address, and the currently accessed memory address can be determined to be a row address according to the last bit being 0, the comparison module 1 determines that the currently accessed memory address 1000 and the sub-feature value ①~③ are not matched, which indicates that the row indicated by the accessed memory address 1000 is not damaged, and normal access can be performed without repair.
Example 2, assuming that the accessed memory information obtained by the comparison module 1 is 00100, where the first 4 bits in the memory information are memory addresses, the last bit is the type of the memory address, and according to the last bit being 0, it can be determined that the currently accessed memory address is a row address, and the comparison module 1 determines the memory address 0010 and the sub-feature value ①: 0010, namely, the sub-feature value ① is a first sub-feature value, which indicates that the line indicated by the accessed memory address 0010 is damaged and needs to be repaired, the type of the memory address is a row address, the type of the first sub-feature value is a row feature value, that is, the memory address is matched with the first sub-feature value, and the type of the memory address is matched with the type of the first sub-feature value, and the comparison module 1 determines that the repair register corresponding to the first sub-feature value is the repair register 1 corresponding to the comparison module 1.
Example 3, assuming that the accessed memory information obtained by the comparison module 2 is 01100, wherein the first 4 bits in the memory information are memory addresses, the last bit is the type of the memory address, the currently accessed memory address can be determined to be a row address according to the last bit being 0, and the comparison module 2 determines the memory address 0010 and the sub-feature value ②: the match of 0110, that is, the sub-feature value ② is a first sub-feature value, which indicates that there is a damage to the line indicated by the accessed memory address 0110, and the type of the memory address is a row address, and the type of the first sub-feature value is a row feature value, that is, the memory address is matched with the first sub-feature value, and the type of the memory address is matched with the type of the first sub-feature value, and the comparison module 2 determines that the repair register corresponding to the first sub-feature value is the repair register 2 corresponding to the comparison module 2.
Example 4, assume that the accessed memory information obtained by the comparison module 5 is 01011, where the first 4 bits in the memory information are memory addresses, the last bit is the type of the memory address, and according to the last bit being 1, it can be determined that the currently accessed memory address is a column address, and the comparison module 5 determines the memory address 0101 and the sub-feature value ③: 0101, namely, the sub-feature value ③ is a first sub-feature value, which indicates that the column indicated by the accessed memory address 0101 is damaged and needs to be repaired, the type of the memory address is the column address, the type of the first sub-feature value is the column feature value, that is, the memory address is matched with the first sub-feature value, and the type of the memory address is matched with the type of the first sub-feature value, and the comparison module 5 determines that the repair register corresponding to the first sub-feature value is the repair register 5 corresponding to the comparison module 5.
In addition, if the correspondence between the repair registers and the comparison modules is the second type, that is, the repair registers 1 to 8 correspond to the same comparison module, the feature values obtained by the comparison module are 001001100101, and the comparison module obtains that the number of the row feature values included in the feature values is 2, the number of the bit numbers of the row feature values is 4, the number of the column feature values is 1, and the number of the bit numbers of the column feature values is 4. The comparison module divides the acquired characteristic values 001001100101 into a plurality of sub-characteristic values ① according to the number of the row characteristic values being 2, the number of the bit numbers of the row characteristic values being 4, the number of the column characteristic values being 1 and the number of the bit numbers of the column characteristic values being 4: 0010. sub-feature value ②: 0110 and sub-feature value ③: 0101.
Assuming that the accessed memory information obtained by the comparison module is 00100, where the first 4 bits in the memory information are memory addresses, the last bit is the type of the memory address, and the currently accessed memory address can be determined to be a row address according to the last bit being 0, and the comparison module determines the accessed memory address 0010 and the sub-feature value ①: 0010, namely, the sub-feature value ① is a first sub-feature value, which indicates that there is a damage to the line indicated by the accessed memory address 0010, and the type of the memory address is a row address, the type of the first sub-feature value is a row feature value, that is, the memory address is matched with the first sub-feature value, and the type of the memory address is matched with the type of the first sub-feature value, and the repair register corresponding to the determination of the first sub-feature value by the comparison module may be any one of the repair registers 1 to 4.
Assuming that the accessed memory information obtained by the comparison module is 01011, wherein the first 4 bits in the memory information are memory addresses, the last bit is the type of the memory address, the currently accessed memory address can be determined to be a column address according to the last bit being 1, and the comparison module determines the accessed memory address 0101 and the sub-feature value ②: 0110, i.e. the sub-feature value ② is a first sub-feature value, which indicates that there is a defect in the column indicated by the accessed memory address 0101, and the type of the memory address is a column address, the type of the first sub-feature value is a column feature value, that is, the memory address is matched with the first sub-feature value, and the type of the memory address is matched with the type of the first sub-feature value, and the comparison module determines that the repair register corresponding to the first sub-feature value may be any one of the repair registers 5 to 8.
In the step, if the type of the memory address is a row address and the type of the first sub-feature value is a row feature value under the condition that the accessed memory address is matched with the first sub-feature value and the type of the memory address is matched with the type of the first sub-feature value, the fact that the row is damaged by the action indicated by the currently accessed memory address is indicated, and a repair register can be used for performing row mode repair on the memory row address; if the type of the memory address is a column address and the type of the first sub-characteristic value is a column characteristic value, the column indicated by the currently accessed memory address is indicated as a damaged column, and the column mode repair can be performed on the memory column address by using the repair register.
Step 203: and repairing the memory location indicated by the memory address according to the repair register corresponding to the first sub-characteristic value.
In an exemplary embodiment, when the accessed memory address matches the first sub-feature value and the type of the memory address matches the type of the first sub-feature value, if the type of the memory address is a row address, the type of the first sub-feature value is a row feature value, and the repair register corresponding to the first sub-feature value corresponds to a redundant row.
In an exemplary embodiment, when the accessed memory address matches the first sub-feature value and the type of the memory address matches the type of the first sub-feature value, if the type of the memory address is a column address, the type of the first sub-feature value is a column feature value, and the repair register corresponding to the first sub-feature value corresponds to a redundant column, and the redundant column is described below as a first redundant column, the repair of the memory location indicated by the memory address according to the repair register corresponding to the first sub-feature value, that is, the repair of the defective point in the column indicated by the memory address according to the first redundant column is performed.
For example, taking example 2 in step 202 as an example, the first sub-feature value 0010 is a line feature value, the repair register corresponding to the first sub-feature value is repair register 1, and assuming that the first redundancy line corresponding to the repair register 1 is the 10 th line in fig. 1, the line indicated by the memory address 0010 is repaired according to the 10 th line, that is, the 2 nd line in fig. 1; taking example 3 in step 202 as an example, the first sub-feature value 0110 is a line feature value, the repair register corresponding to the first sub-feature value is the repair register 2, and assuming that the first redundancy line corresponding to the repair register 2 is the 11 th line in fig. 1, the line indicated by the memory address 0110 is repaired according to the 11 th line, that is, the 6 th line in fig. 1; taking example 4 in step 202 as an example, the first sub-feature value 0101 is a column feature value, the repair register corresponding to the first sub-feature value is the repair register 5, the first redundancy column corresponding to the repair register 5 is the 10 th column in fig. 1, and the column indicated by the memory address 0101, that is, the 5 th column in fig. 1, is repaired by using the 10 th column.
In this step, the damaged row and the damaged column in fig. 1 can be completely repaired by using the repair register 1, the repair register 2 and the repair register 5, namely, the memory shown in fig. 1 can be completely repaired by using 2 rows of redundant rows and 1 column of redundant columns, and the memory shown in fig. 1 can be completely repaired by using 4 rows of redundant rows in the single row mode, and the memory shown in fig. 1 can be completely repaired by using 4 columns of redundant columns in the single column mode.
Fig. 5 and fig. 6 are schematic structural diagrams of a possible chip memory repair device according to an embodiment of the application. The chip memory repair devices can be used for realizing the functions of the host in the method embodiment, so that the beneficial effects of the method embodiment can be realized.
As shown in fig. 5, the chip memory repair device 500 includes a transceiver unit 510 and a processing unit 520. The chip memory repair device 500 is used to implement the function of the comparison module in the method embodiment shown in fig. 2.
The transceiver unit 510 is configured to obtain a feature value, where the feature value is formed by splicing multiple sub-feature values; each sub-feature value in the plurality of sub-feature values is a row feature value or a column feature value; the line characteristic value is used for indicating the position of a damaged line in the chip memory; the column characteristic value is used for indicating the position of a damaged column in the chip memory; acquiring accessed memory information, wherein the memory information comprises a memory address;
The processing unit 520 is configured to determine a repair register corresponding to a first sub-feature value in the memory address and the first sub-feature value in the feature values if the memory address matches the first sub-feature value; the first sub-feature value is one of the plurality of sub-feature values; and repairing the memory location indicated by the memory address according to the repair register corresponding to the first sub-characteristic value.
In one possible design, the memory information further includes a type of the memory address; in the case that the memory address matches a first sub-feature value of the feature values, the processing unit 520 is configured to, when determining a repair register corresponding to the first sub-feature value: determining a repair register corresponding to a first sub-feature value under the condition that the memory address is matched with the first sub-feature value in the feature values and the type of the memory address is matched with the type of the first sub-feature value; the matching of the type of the memory address with the type of the first sub-characteristic value comprises that the type of the memory address is a row address, and the type of the first sub-characteristic value is a row characteristic value; or the type of the memory address is a column address, and the type of the first sub-characteristic value is a column characteristic value.
In one possible design, the repair register corresponding to the first sub-feature value is one of K repair registers; the K repair registers are determined according to I redundant rows and J redundant columns of the chip memory; i and J are positive integers, K is the sum of I and J, and K is an integer greater than or equal to 2; and each repair register is used for repairing the damaged point in the chip memory based on the redundant row or the redundant column.
In one possible design, the repair register corresponding to the first sub-feature value corresponds to a first redundant row; the processing unit 520 is configured to, when repairing the memory location indicated by the memory address according to the repair register corresponding to the first sub-feature value: and repairing the damaged point in the line indicated by the memory address according to the first redundant line.
In one possible design, the repair register corresponding to the first sub-feature value corresponds to a first redundant column; the processing unit 520 is configured to, when repairing the memory location indicated by the memory address according to the repair register corresponding to the first sub-feature value: and repairing the damaged point in the column indicated by the memory address according to the first redundant column.
In one possible design, the transceiver unit 510 is configured to, when acquiring the feature value: and executing a memory self-built automatic test (BIST) on the chip memory by adopting Automatic Test Equipment (ATE) to acquire the characteristic value.
The above-mentioned more detailed descriptions of the transceiver unit 510 and the processing unit 520 may be directly obtained by referring to the related descriptions in the method embodiment shown in fig. 2, which are not repeated herein.
As shown in fig. 6, the chip memory repair device 600 includes a processor 610 and an interface circuit 620. The processor 610 and the interface circuit 620 are coupled to each other. It is understood that the interface circuit 620 may be a transceiver or an input-output interface. Optionally, the chip memory repair device 600 may further include a memory 630 for storing instructions executed by the processor 610 or for storing input data required by the processor 610 to execute the instructions or for storing data generated after the processor 610 executes the instructions.
When the chip memory repair device 600 is used to implement the method shown in fig. 2, the processor 610 is used to implement the functions of the processing unit 520, and the interface circuit 620 is used to implement the functions of the transceiver unit 510.
The division of the units in the embodiments of the present application is schematically shown, which is merely a logic function division, and may have another division manner when actually implemented, and in addition, each functional unit in each embodiment of the present application may be integrated in one processor, or may exist separately and physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (9)
1. The method for repairing the chip memory is characterized by comprising the following steps:
Acquiring a characteristic value, wherein the characteristic value is formed by splicing a plurality of sub-characteristic values; each sub-feature value in the plurality of sub-feature values is a row feature value or a column feature value; the line characteristic value is used for indicating the position of a damaged line in the chip memory, the line characteristic value is a binary number, and the number of bits of the line characteristic value is associated with the number of lines of the chip memory: if the number of lines of the chip memory is A, the number of bits of the line characteristic value is A is a positive integer; the column characteristic value is used for indicating the position of a damaged column in the chip memory, the column characteristic value is a binary number, and the number of bits of the column characteristic value is associated with the number of columns of the chip memory: if the column number of the chip memory is B, the number of bits of the line characteristic value isB is a positive integer; if M damage points exist in the chip memory, the M damage points correspond to M row characteristic values and M column characteristic values at most, and any two damage points in the M damage points are located in different rows or any two damage points are located in different columns; if at least two damage points located in the same row exist in the M damage points, the at least two damage points located in the same row correspond to the same row characteristic value; if at least two damage points located in the same column exist in the M damage points, the at least two damage points located in the same column correspond to the same column characteristic value; m is a positive integer;
Acquiring accessed memory information, wherein the memory information comprises a memory address; the memory address is a binary number and comprises a row address or a column address, and if the memory address is a row address, the row address indicates a row in the chip memory; if the memory address is a column address, the column address indicates a column in the chip memory;
Determining a repair register corresponding to a first sub-feature value in the memory address and the first sub-feature value in the feature values under the condition that the memory address is matched with the first sub-feature value; the first sub-feature value is one of the plurality of sub-feature values; the memory information further includes a type of the memory address, and determining a repair register corresponding to a first sub-feature value in the case that the memory address matches the first sub-feature value, where the determining includes: determining a repair register corresponding to a first sub-feature value under the condition that the memory address is matched with the first sub-feature value in the feature values and the type of the memory address is matched with the type of the first sub-feature value; the matching of the type of the memory address with the type of the first sub-characteristic value comprises that the type of the memory address is a row address, and the type of the first sub-characteristic value is a row characteristic value; or the type of the memory address is a column address, and the type of the first sub-characteristic value is a column characteristic value;
and repairing the memory location indicated by the memory address according to the repair register corresponding to the first sub-characteristic value.
2. The method of claim 1, wherein the repair register corresponding to the first sub-feature value is one of K repair registers;
the K repair registers are determined according to I redundant rows and J redundant columns of the chip memory; i and J are positive integers, K is the sum of I and J, and K is an integer greater than or equal to 2;
And each repair register is used for repairing the damaged point in the chip memory based on the redundant row or the redundant column.
3. The method of claim 2, wherein the repair register corresponding to the first sub-feature value corresponds to a first redundant row;
repairing the memory location indicated by the memory address according to a repair register corresponding to the first sub-feature value, including:
And repairing the damaged point in the line indicated by the memory address according to the first redundant line.
4. The method of claim 2, wherein the repair register corresponding to the first sub-feature value corresponds to a first redundant column;
repairing the memory location indicated by the memory address according to a repair register corresponding to the first sub-feature value, including:
and repairing the damaged point in the column indicated by the memory address according to the first redundant column.
5. The method of claim 1, wherein obtaining the feature value comprises:
and executing a memory self-built automatic test (BIST) on the chip memory by adopting Automatic Test Equipment (ATE) to acquire the characteristic value.
6. The device is characterized by comprising a receiving and transmitting unit and a processing unit;
the receiving and transmitting unit is used for acquiring a characteristic value, and the characteristic value is formed by splicing a plurality of sub-characteristic values; each sub-feature value in the plurality of sub-feature values is a row feature value or a column feature value; the line characteristic value is used for indicating the position of a damaged line in the chip memory, the line characteristic value is a binary number, and the number of bits of the line characteristic value is associated with the number of lines of the chip memory: if the number of lines of the chip memory is A, the number of bits of the line characteristic value is A is a positive integer; the column characteristic value is used for indicating the position of a damaged column in the chip memory, the column characteristic value is a binary number, and the number of bits of the column characteristic value is associated with the number of columns of the chip memory: if the column number of the chip memory is B, the number of bits of the line characteristic value isB is a positive integer; if M damage points exist in the chip memory, the M damage points correspond to M row characteristic values and M column characteristic values at most, and any two damage points in the M damage points are located in different rows or any two damage points are located in different columns; if at least two damage points located in the same row exist in the M damage points, the at least two damage points located in the same row correspond to the same row characteristic value; if at least two damage points located in the same column exist in the M damage points, the at least two damage points located in the same column correspond to the same column characteristic value; m is a positive integer; acquiring accessed memory information, wherein the memory information comprises a memory address; the memory address is a binary number and comprises a row address or a column address, and if the memory address is a row address, the row address indicates a row in the chip memory; if the memory address is a column address, the column address indicates a column in the chip memory;
The processing unit is used for determining a repair register corresponding to a first sub-characteristic value in the memory address and the first sub-characteristic value in the characteristic values under the condition that the memory address is matched with the first sub-characteristic value; the first sub-feature value is one of the plurality of sub-feature values; the memory information further includes a type of the memory address, and the processing unit is configured to, when the memory address matches a first sub-feature value of the feature values, determine a repair register corresponding to the first sub-feature value: determining a repair register corresponding to a first sub-feature value under the condition that the memory address is matched with the first sub-feature value in the feature values and the type of the memory address is matched with the type of the first sub-feature value; the matching of the type of the memory address with the type of the first sub-characteristic value comprises that the type of the memory address is a row address, and the type of the first sub-characteristic value is a row characteristic value; or the type of the memory address is a column address, and the type of the first sub-characteristic value is a column characteristic value; and repairing the memory location indicated by the memory address according to the repair register corresponding to the first sub-characteristic value.
7. A chip memory repair device, comprising: one or more processors and one or more memories; wherein the one or more memories store one or more programs that, when executed by the one or more processors, cause the apparatus to perform the method of any of claims 1-5.
8. A computer readable storage medium having stored therein computer executable instructions which when executed by a processor are adapted to carry out the method of any one of claims 1-5.
9. A computer program product comprising a computer program which, when executed by a processor, implements the method of any of claims 1-5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410544668.6A CN118132324B (en) | 2024-05-06 | 2024-05-06 | Chip memory repair method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410544668.6A CN118132324B (en) | 2024-05-06 | 2024-05-06 | Chip memory repair method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN118132324A CN118132324A (en) | 2024-06-04 |
| CN118132324B true CN118132324B (en) | 2024-08-02 |
Family
ID=91238138
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410544668.6A Active CN118132324B (en) | 2024-05-06 | 2024-05-06 | Chip memory repair method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118132324B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112612637A (en) * | 2020-12-10 | 2021-04-06 | 海光信息技术股份有限公司 | Memory data storage method, memory controller, processor chip and electronic equipment |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8381052B2 (en) * | 2009-11-10 | 2013-02-19 | International Business Machines Corporation | Circuit and method for efficient memory repair |
| KR20160138617A (en) * | 2015-05-26 | 2016-12-06 | 에스케이하이닉스 주식회사 | Smart Self Repair Device and Method |
| US11455221B2 (en) * | 2019-10-31 | 2022-09-27 | Qualcomm Incorporated | Memory with concurrent fault detection and redundancy |
| CN115705262A (en) * | 2021-08-17 | 2023-02-17 | 华为技术有限公司 | A memory failure recovery method, system and memory |
| US12174698B2 (en) * | 2022-03-24 | 2024-12-24 | Cypress Semiconductor Corporation | Apparatus for on demand access and cache encoding of repair data |
| CN116414312A (en) * | 2023-03-10 | 2023-07-11 | 上海御渡半导体科技有限公司 | Method for storing large data volume failure address of chip |
-
2024
- 2024-05-06 CN CN202410544668.6A patent/CN118132324B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112612637A (en) * | 2020-12-10 | 2021-04-06 | 海光信息技术股份有限公司 | Memory data storage method, memory controller, processor chip and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN118132324A (en) | 2024-06-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100536984B1 (en) | Hierarchical built-in self-test for system-on-chip design | |
| US5337318A (en) | Memory IC testing apparatus with redundancy circuit | |
| US7127647B1 (en) | Apparatus, method, and system to allocate redundant components | |
| US6550023B1 (en) | On-the-fly memory testing and automatic generation of bitmaps | |
| CN114639439B (en) | Chip internal SRAM test method and device, storage medium and SSD device | |
| CN113486625A (en) | Chip verification method and verification system | |
| CN103137212A (en) | Synchronous dynamic random access memory (SDRAM) testing method | |
| US4912710A (en) | Self-checking random access memory | |
| CN100446129C (en) | Method and system for memory fault testing | |
| US6934205B1 (en) | Bist for parallel testing of on chip memory | |
| CN101727980A (en) | Multi-chip module | |
| US5195096A (en) | Method of functionally testing cache tag RAMs in limited-access processor systems | |
| CN112799887B (en) | Chip FT test system and test method | |
| CN118711649A (en) | Method and system for accelerating memory chip testing, and electronic device | |
| CN118132324B (en) | Chip memory repair method and device | |
| US8694838B2 (en) | Cache memory, processor, and production methods for cache memory and processor | |
| CN115691632B (en) | Test control system and method | |
| US11631474B2 (en) | Redundancy analysis method and redundancy analysis apparatus | |
| CN117290165A (en) | Method, system, device and storage medium for chip test | |
| CN116189748A (en) | Method and device for determining repair route of DDR chip | |
| CN113254290A (en) | Memory particle multidimensional test method, device and system and readable storage medium | |
| JP7592889B2 (en) | Repairing logical memory using shared physical memory | |
| CN119418750B (en) | DRAM chip, test system and test method for preventing row hammer attack | |
| US20060156090A1 (en) | Memory array manufacturing defect detection system and method | |
| CN112666443B (en) | FPGA-based test unit and test system and test method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |