CN117746963A - Self-aging method, device, equipment and storage medium - Google Patents
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Abstract
The invention discloses a self-aging method, a device, equipment and a storage medium. The method comprises the following steps: connecting a storage control chip which needs to be subjected to aging test; selecting one of the memory control chips as a master device and the rest memory control chips as slave devices; initializing all storage control chips, wherein the storage control chip serving as a master device is responsible for initializing all storage control chips serving as slave devices, and one storage control chip serving as a slave device is responsible for initializing the storage control chip serving as the master device; and the paired memory control chips are paired in pairs, and the paired memory control chips execute the burn-in test in an alternate read-write operation mode. According to the method, the host and the flash memory particles are omitted, aging can be realized only by means of communication interaction between the storage control chip and the storage control chip, and the host is prevented from being damaged in an extreme environment for a long time. Omitting the host and flash memory particles can also reduce the burn-in cost.
Description
Technical Field
The present invention relates to the field of chip burn-in technologies, and in particular, to a self-burn-in method, device, apparatus, and storage medium.
Background
Currently, for the mainstream electronic storage devices (such as USB flash disk, SD card, solid state disk, etc.), the electronic storage device mainly comprises a memory control chip, flash particles, and PCB components. The memory control chip is used as a core unit for managing the flash memory particles, and is used for executing operations such as writing, reading, erasing and the like of data of the flash memory particles, and the stability of the memory control chip is related to the durability of the electronic memory device, so that before the memory control chip is formally produced in mass production, the memory control chip can be subjected to an aging test, and the purpose of the aging test is to test whether the memory control chip can execute the operations of uninterrupted reading and writing for a long time under an extreme environment.
In the related art, the burn-in test requires that the host, the memory control chip and the flash memory particles are simultaneously placed in a high-temperature environment, and the host cannot withstand the high-temperature environment for a long time, so that serious damage is easily caused to the host. In addition, since the host and the flash memory particles are needed to participate, the cost of the burn-in test is correspondingly increased.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a self-aging method, device, equipment and storage medium, which can avoid serious damage to a host and reduce the aging test cost.
A first aspect of the present application provides a self-aging method comprising:
connecting a storage control chip which needs to be subjected to aging test;
selecting one of the memory control chips as a master device and the rest memory control chips as slave devices;
initializing all the storage control chips, wherein the storage control chip serving as a master device is responsible for initializing all the storage control chips serving as slave devices, and one storage control chip serving as a slave device is responsible for initializing the storage control chip serving as the master device;
and pairing the storage control chips in pairs according to the initialization sequence, and executing the aging test on the paired storage control chips in an alternate read-write operation mode.
In one embodiment, the paired memory control chips perform burn-in testing in an alternating read and write operation, including:
one of the memory control chips generates a random number, sends a writing command to the other memory control chip, and writes the random number into the other memory control chip;
the storage control chip generating the random number sends a reading command to another storage control chip, reads the written random number and checks the read random number;
and the matched storage control chips are alternately executed in pairs in turn until the random number verification fails.
In one embodiment, the initialization of the memory control chip is performed as follows:
sending a reset command to the storage control chip, and resetting the storage control chip to an idle state;
sending a read voltage command to the storage control chip to acquire the voltage range of the storage control chip;
sending a readiness command to the storage control chip, and adjusting the storage control chip to a readiness state;
sending an ID reading command to the storage control chip to acquire the ID of the storage control chip;
and sending a device address reading command to the storage control chip, and acquiring the device address of the storage control chip.
In one embodiment, the connection of the memory control chip which needs to be subjected to burn-in test includes:
the memory control chips that need to be burn-in tested are connected in a manner that shares a set of buses.
A second aspect of the present application provides a self-aging device comprising:
the connection module is used for connecting the storage control chip which needs to be subjected to the aging test;
the master-slave marking module is used for selecting one of the storage control chips as master equipment and the rest storage control chips as slave equipment;
the initialization module is used for initializing all the storage control chips, wherein the storage control chip serving as a master device is responsible for initializing all the storage control chips serving as slave devices, and one of the storage control chips serving as slave devices is responsible for initializing the storage control chip serving as the master device;
and the aging module is used for pairwise pairing the storage control chips, and the paired storage control chips execute aging test in an alternate read-write operation mode.
In one embodiment, the burn-in module is configured to perform a burn-in test on the paired memory control chips in an alternating read-write operation, and includes: one of the memory control chips generates a random number, sends a writing command to the other memory control chip, and writes the random number into the other memory control chip;
the storage control chip generating the random number sends a reading command to another storage control chip, reads the written random number and checks the read random number;
and the matched storage control chips are alternately executed in pairs in turn until the random number verification fails.
In one embodiment, the initialization module performs initialization of the memory control chip as follows:
sending a reset command to the storage control chip, and resetting the storage control chip to an idle state;
sending a read voltage command to the storage control chip to acquire the voltage range of the storage control chip;
sending a readiness command to the storage control chip, and adjusting the storage control chip to a readiness state;
sending an ID reading command to the storage control chip to acquire the ID of the storage control chip;
and sending a device address reading command to the storage control chip, and acquiring the device address of the storage control chip.
In one embodiment, the connection module is configured to connect a memory control chip that needs to be subjected to burn-in test, and includes:
the memory control chips that need to be burn-in tested are connected in a manner that shares a set of buses.
A third aspect of the present application provides an electronic device, comprising:
processor and method for controlling the same
And a memory storing executable code that, when executed by the processor, causes the processor to perform the self-aging method as described above.
A fourth aspect of the present application provides a computer readable storage medium, characterized in that executable code is stored, which when executed by a processor of an electronic device, causes the processor to perform a self-aging method as described above.
The technical scheme of this application includes: connecting a storage control chip which needs to be subjected to aging test; selecting one of the memory control chips as a master device and the rest memory control chips as slave devices; initializing all storage control chips, wherein the storage control chip serving as a master device is responsible for initializing all storage control chips serving as slave devices, and one storage control chip serving as a slave device is responsible for initializing the storage control chip serving as the master device; and the paired memory control chips are paired in pairs, and the paired memory control chips execute the burn-in test in an alternate read-write operation mode. According to the method, the host and the flash memory particles are omitted, ageing can be realized only by means of communication interaction between the storage control chip and the storage control chip, and damage to the host caused by the fact that the host is in an extreme environment for a long time can be well avoided. In addition, the burn-in test cost can be reduced by omitting a host and flash memory particles.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a self-aging method according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a self-aging device according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of an electronic device according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a burn-in system according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a burn-in system according to another embodiment of the present application.
Detailed Description
In order that the invention may be understood more fully, the invention will be described with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "fixed to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only and are not meant to be the only embodiment.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
In the related art, the burn-in test requires that the host, the memory control chip and the flash memory particles are simultaneously placed in a high-temperature environment, and the host cannot withstand the high-temperature environment for a long time, so that serious damage is easily caused to the host. In addition, since the host and the flash memory particles are needed to participate, the cost of the burn-in test is correspondingly increased.
Therefore, the application discloses a self-aging method to solve the problems that a host is damaged in an extreme environment and the aging test cost is high.
The following describes the technical scheme of the present application in detail with reference to the accompanying drawings.
FIG. 1 is a flow chart of a self-aging method according to an embodiment of the present application.
Referring to fig. 1, a self-aging method is provided, which includes:
step S110, connecting the memory control chip which needs to be subjected to the burn-in test.
The self-aging is realized by the communication interaction between the memory control chip and the memory control chip, namely, the self-aging is realized by the communication interaction between the same type of objects.
Referring to fig. 4, the burn-in test system of the present application is built by taking 2 memory control chips as an example, where the 2 memory control chips have the same pins including Clock pins Clock, command pins CMD, data pins Dat0 to Dat3, and sync pins Syn. The Clock pin Clock is used for outputting a Clock signal, so that the memory control chip can realize corresponding operation according to the rising edge or the falling edge of the Clock signal. The command pin CMD is used for outputting a command signal for controlling the memory control chip. The total number of data pins Dat0 to Dat3 is 4 for outputting data. The synchronous pin Syn is used for generating a mutual exclusion signal, so that only 1 memory control chip is operated when each time of initialization or aging is guaranteed, and 2 memory control chips are prevented from being operated mutually. The above 7 pins are bi-directional, but the signal flow is unidirectional.
It should be noted that, the burn-in test system shown in fig. 4 is built by using 2 storage control chips, and the burn-in test system of the present application may also be optimized and improved, and is built by using 2n (n is a positive integer greater than or equal to 2) storage control chips, as shown in fig. 5, and is a burn-in test system built by using 4 storage control chips, where all storage control chips are connected in a manner of sharing a set of buses. The mode of sharing a set of buses can reduce the overall complexity of the aging test system to the greatest extent. More mainly, the ageing test system built by 2n storage control chips can carry out ageing test on a plurality of storage control chips in batches within the same time period, and the more the storage control chips are subjected to ageing test, the higher the accuracy of an ageing test result is, so that the influence on the accuracy and stability of the ageing test result due to the fact that the number of ageing tests is too small is well avoided.
And step S120, selecting one of the storage control chips from the plurality of storage control chips as a master device, and using the rest of the storage control chips as slave devices.
Taking the burn-in test system shown in fig. 5 as an example, 4 memory control chips, namely, memory control chips A, B, C and D, are shown in fig. 5, a memory control chip a is selected as a master device, the remaining memory control chips B, C and D are initialized later by the memory control chip a as the master device, and 1 memory control chip a is selected from the memory control chips B, C and D to perform subsequent initialization operation on the memory control chip a later by the memory control chip a as the master device.
Step S130, initializing all the storage control chips, wherein the storage control chip serving as the master device is responsible for initializing all the storage control chips serving as the slaves, and one of the storage control chips serving as the slaves is responsible for initializing the storage control chip serving as the master device.
The initialization is generally understood to be similar to the power-on and power-on process, and for the storage control chip, whether the initialization is applied to the storage control chip of the USB disk or the storage control chip of the SD card, the initialization operation is required according to the USB standard protocol and the SD card standard protocol, if the initialization is not performed, the storage control chip cannot work normally, namely the initialization operation is not performed, the two-to-two storage control chips cannot communicate data normally, and the commands cannot be mutually sent or received, so that the initialization is a necessary flow for the storage control chip.
After confirming which memory control chip is the master and which memory control chip is the slave, all memory control chips can be initialized by using the priority relationship between the master and the slave. In the above example, the memory control chip a sequentially initializes the memory control chips B, C and D, and after successful initialization, the memory control chip C initializes the memory control chip a to complete the initialization of the entire burn-in test system.
It should be noted that, for the memory control chip applied to the SD card, the initialization process is performed as follows: sending a reset command CMD0 to the memory control chip to reset the memory control chip to an idle state; sending a read voltage command CMD8 to a memory control chip to acquire a voltage range of the memory control chip; sending a ready command ACMD41 to the storage control chip to adjust the storage control chip to a ready state; sending a read ID command CMD2 to a storage control chip to acquire the ID of the storage control chip; and sending a read device address command CMD3 to the memory control chip to acquire the device address of the memory control chip. Through the above process, the initialization of the memory control chip can be completed.
Step S140, the paired memory control chips are paired in pairs, and the paired memory control chips execute the burn-in test in an alternate read-write operation mode.
The paired memory control chips are mutually operated by each other to finish the burn-in test. In the above example, the memory control chips a and B were paired, and the memory control chips C and D were paired. It should be noted that, since the memory control chips A, B, C and D are connected in a manner of sharing a set of buses, in the initialization stage, when the memory control chip a sequentially initializes B, C and D, the memory control chip a transmits the read device address commands CMD3 to B, C and D, so that the device addresses of B, C and D can be obtained, and then the memory control chip a transmits all the obtained device addresses to B, C and D through the buses, so that the memory control chips B, C and D can know the device addresses of all the other memory control chips except "themselves". When the storage control chip C initializes the storage control chip A, the storage control chip C sends the device address reading commands CMD3 to A, obtains the device address of A, and sends all the obtained device addresses to C and D through a bus, and at the moment, all the storage control chips in the aging test system read all the device addresses. Similarly, when all the memory control chips in the burn-in test system need to read the IDs of all the chips, the method principle is consistent with the above, and will not be repeated.
The paired memory control chips execute the burn-in test in an alternating read and write operation, as follows: one of the memory control chips generates a random number, sends a writing command to the other memory control chip, and writes the random number into the other memory control chip; the storage control chip for generating the random number sends a reading command to another storage control chip, reads the written random number and performs verification; the paired memory control chips are sequentially and alternately executed until the random number verification fails.
After the memory control chips a and B are paired, the memory control chip a generates a random number, sends a write command to the memory control chip B, and writes the generated random number to the memory control chip B. And then the storage control chip A sends a reading command to the storage control chip B, reads the written random number, compares the read random number with the random number before writing, checks whether the random number is consistent, and if so, represents that the current aging test of the storage control chip B is passed. Then, the burn-in test of the memory control chip a is performed by the memory control chip B, and the principle process is the same except that the memory control chip a is operated by the memory control chip B. The above-mentioned processes are alternatively executed until the condition that the random number verification fails to pass occurs, and the aging is stopped.
In addition, considering that only one pair of paired memory control chips can be used at a time when a set of buses is shared, the burn-in test system is not suitable to be built with too many memory control chips, and the number of the memory control chips is preferably 4 or 6, otherwise, the burn-in test efficiency of the burn-in test system is greatly reduced because the memory control chips a and B are in a stagnant state when the memory control chip C performs the burn-in test on the memory control chip D. Therefore, when the aging test system is built by adopting a plurality of storage control chips, the storage control chips can be connected in a mode of not sharing one set of bus, the storage control chips can be grouped in advance, the storage control chips in the same group are connected with each other, so that the aging test can be executed by the 2 storage control chips in different groups in the same time, and the aging test efficiency can be improved.
According to the method, the host and flash memory particles are omitted, aging can be realized only by means of communication interaction between the storage control chip and the storage control chip, and damage to the host caused by the fact that the host is in an extreme environment for a long time can be well avoided. In addition, the burn-in test cost can be reduced by omitting a host and flash memory particles.
Corresponding to the foregoing method embodiments, the present application provides a self-aging device.
Fig. 2 is a schematic structural diagram of a self-aging device according to an embodiment of the present application.
Referring to fig. 2, a self-aging device 200 includes a connection module 210, a master-slave marking module 220, an initialization module 230, and an aging module 240. Wherein:
the connection module 210 is used for connecting the memory control chip that needs to be subjected to the burn-in test.
The master-slave marking module 220 is configured to select one of the plurality of memory control chips as a master device, and the remaining memory control chips as slave devices.
The initialization module 230 is configured to initialize all the storage control chips, where the storage control chip serving as a master device is responsible for initializing all the storage control chips serving as slave devices, and one of the storage control chips serving as slave devices is responsible for initializing the storage control chip serving as the master device.
The burn-in module 240 is configured to pair the memory control chips in pairs, and the paired memory control chips perform burn-in test in an alternating read/write operation.
Further, when the burn-in module is configured to perform a burn-in test on the paired memory control chips in an alternating read/write operation, the burn-in module includes: one of the memory control chips generates a random number, sends a writing command to the other memory control chip, and writes the random number into the other memory control chip; the storage control chip for generating the random number sends a reading command to another storage control chip, reads the written random number and performs verification; the paired memory control chips are sequentially and alternately executed until the random number verification fails.
Further, the initialization module performs initialization of the memory control chip as follows: sending a reset command CMD0 to the memory control chip to reset the memory control chip to an idle state; sending a read voltage command CMD8 to a memory control chip to acquire a voltage range of the memory control chip; sending a ready command ACMD41 to the storage control chip to adjust the storage control chip to a ready state; sending a read ID command CMD2 to a storage control chip to acquire the ID of the storage control chip; and sending a read device address command CMD3 to the memory control chip to acquire the device address of the memory control chip.
Further, the connection module is used for connecting the memory control chip which needs to be subjected to the burn-in test, and comprises: the memory control chips that need to be burn-in tested are connected in a manner that shares a set of buses.
It should be noted that, the method of implementing the zero-loss monitoring device by using the zero-loss monitoring device disclosed in this embodiment is similar to the above embodiment, so that detailed description thereof will not be given here. Alternatively, each module in the present embodiment and the other operations or functions described above are respectively for realizing the method in the foregoing embodiment.
Referring to fig. 3, another embodiment of the present application shows a computing electronic device 300 including a memory 310 and a processor 320.
The processor 320 may be a central processing unit (Central Processing Unit, CPU), but may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), field programmable gate arrays (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like.
A general purpose processor may be a microprocessor or the processor may be any conventional processor memory 320 that may include various types of storage elements, such as system memory, read Only Memory (ROM), and persistent storage.
Where the ROM may store static data or instructions that are required by the processor 320 or other modules of the computer. The persistent storage may be a readable and writable storage. The persistent storage may be a non-volatile memory device that does not lose stored instructions and data even after the computer is powered down. In some embodiments, the persistent storage device employs a mass storage device (e.g., magnetic or optical disk, flash memory) as the persistent storage device.
In other embodiments, the persistent storage may be a removable storage device (e.g., diskette, optical drive). The system memory may be a read-write memory device or a volatile read-write memory device, such as dynamic random access memory. The system memory may store instructions and data that are required by some or all of the processors at runtime.
Furthermore, memory 310 may include any combination of computer-readable storage media including various types of semiconductor memory chips (e.g., DRAM, SRAM, SDRAM, flash memory, programmable read-only memory), magnetic disks, and/or optical disks may also be employed.
In some implementations, memory 310 may include a readable and/or writable removable storage device such as a Compact Disc (CD), a digital versatile disc read only (e.g., DVD-ROM, dual layer DVD-ROM), a blu-ray read only disc, an ultra-dense disc, a flash memory card (e.g., SD card, min SD card, micro-SD card, etc.), a magnetic floppy disk, and the like. The computer readable storage medium does not contain a carrier wave or an instantaneous electronic signal transmitted by wireless or wired transmission. The memory 310 has stored thereon executable code that, when processed by the processor 320, can cause the processor 320 to perform some or all of the methods described above.
Furthermore, the method according to the present application may also be implemented as a computer program or computer program product comprising computer program code instructions for performing part or all of the steps of the above-described method of the present application.
Alternatively, the present application may also be embodied as a computer-readable storage medium (or non-transitory machine-readable storage medium or machine-readable storage medium) having stored thereon executable code (or a computer program or computer instruction code) which, when executed by a processor of an electronic device (or a server, etc.), causes the processor to perform part or all of the steps of the above-described methods according to the present application.
The embodiments of the present application have been described above, the foregoing description is exemplary, not exhaustive, and not limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (10)
1. A method of self-aging comprising:
connecting a storage control chip which needs to be subjected to aging test;
selecting one of the memory control chips as a master device and the rest memory control chips as slave devices;
initializing all the storage control chips, wherein the storage control chip serving as a master device is responsible for initializing all the storage control chips serving as slave devices, and one storage control chip serving as a slave device is responsible for initializing the storage control chip serving as the master device;
and pairing the memory control chips in pairs, and executing aging test on the paired memory control chips in an alternating read-write operation mode.
2. The self-aging method of claim 1, wherein the paired memory control chips perform aging tests in alternating read and write operations, comprising:
one of the memory control chips generates a random number, sends a writing command to the other memory control chip, and writes the random number into the other memory control chip;
the storage control chip generating the random number sends a reading command to another storage control chip, reads the written random number and checks the read random number;
and the matched storage control chips are alternately executed in pairs in turn until the random number verification fails.
3. The self-aging method according to claim 1, wherein the initializing of the memory control chip is performed as follows:
sending a reset command to the storage control chip, and resetting the storage control chip to an idle state;
sending a read voltage command to the storage control chip to acquire the voltage range of the storage control chip;
sending a readiness command to the storage control chip, and adjusting the storage control chip to a readiness state;
sending an ID reading command to the storage control chip to acquire the ID of the storage control chip;
and sending a device address reading command to the storage control chip, and acquiring the device address of the storage control chip.
4. The self-aging method according to claim 1, wherein said connecting the memory control chip requiring the aging test comprises:
the memory control chips that need to be burn-in tested are connected in a manner that shares a set of buses.
5. A self-aging device, comprising:
the connection module is used for connecting the storage control chip which needs to be subjected to the aging test;
the master-slave marking module is used for selecting one of the storage control chips as master equipment and the rest storage control chips as slave equipment;
the initialization module is used for initializing all the storage control chips, wherein the storage control chip serving as a master device is responsible for initializing all the storage control chips serving as slave devices, and one of the storage control chips serving as slave devices is responsible for initializing the storage control chip serving as the master device;
and the aging module is used for pairwise pairing the storage control chips, and the paired storage control chips execute aging test in an alternate read-write operation mode.
6. The self-aging device of claim 5, wherein the aging module is configured to perform an aging test on the paired memory control chips in an alternating read and write operation, comprising: one of the memory control chips generates a random number, sends a writing command to the other memory control chip, and writes the random number into the other memory control chip;
the storage control chip generating the random number sends a reading command to another storage control chip, reads the written random number and checks the read random number;
and the matched storage control chips are alternately executed in pairs in turn until the random number verification fails.
7. The self-aging device of claim 5, wherein the initialization module performs the initialization of the memory control chip as follows:
sending a reset command to the storage control chip, and resetting the storage control chip to an idle state;
sending a read voltage command to the storage control chip to acquire the voltage range of the storage control chip;
sending a readiness command to the storage control chip, and adjusting the storage control chip to a readiness state;
sending an ID reading command to the storage control chip to acquire the ID of the storage control chip;
and sending a device address reading command to the storage control chip, and acquiring the device address of the storage control chip.
8. The self-aging device of claim 5, wherein the connection module is configured to connect a memory control chip that needs to be subjected to an aging test, and comprises:
the memory control chips that need to be burn-in tested are connected in a manner that shares a set of buses.
9. An electronic device, comprising:
processor and method for controlling the same
A memory storing executable code that, when executed by the processor, causes the processor to perform the self-aging method of any one of claims 1-4.
10. A computer readable storage medium, characterized in that executable code is stored, which when executed by a processor of an electronic device causes the processor to perform the self-aging method according to any of claims 1-4.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20190049513A1 (en) * | 2018-06-25 | 2019-02-14 | Intel Corporation | Scalable infield scan coverage for multi-chip module for fuctional safety mission application |
| CN110716126A (en) * | 2019-10-14 | 2020-01-21 | 珠海亿智电子科技有限公司 | Chip aging test system, method and device |
| CN115512757A (en) * | 2022-11-02 | 2022-12-23 | 深圳三地一芯电子有限责任公司 | Error recurrence repairing method, device, equipment and storage medium |
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2023
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| US6473346B1 (en) * | 1995-12-26 | 2002-10-29 | Hyundai Electronics Industries Co., Ltd. | Self burn-in circuit for semiconductor memory |
| US20080054260A1 (en) * | 2004-09-02 | 2008-03-06 | Takashi Ishitobi | Semiconductor Integrated Circuit Device, Method For Testing The Semiconductor Integrated Circuit Device, Semiconductor Wafer And Burn-In Test Apparatus |
| US20190049513A1 (en) * | 2018-06-25 | 2019-02-14 | Intel Corporation | Scalable infield scan coverage for multi-chip module for fuctional safety mission application |
| CN110716126A (en) * | 2019-10-14 | 2020-01-21 | 珠海亿智电子科技有限公司 | Chip aging test system, method and device |
| CN115512757A (en) * | 2022-11-02 | 2022-12-23 | 深圳三地一芯电子有限责任公司 | Error recurrence repairing method, device, equipment and storage medium |
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