CN117725863A - Chip signal analysis hardware module, system, processor chip and electronic equipment - Google Patents

Abstract

This application provides a chip signal analysis hardware module, system, processor chip and electronic equipment, which carries or calls software resources for chip signal analysis through the software resource module, and reads the software resources and obtains the target through the chip data acquisition module. The circuit data on the wiring is then transmitted to the bus protocol conversion module using the data transmission protocol of the server chip. The bus protocol conversion module completes the timing synchronization and protocol conversion process, and encapsulates the circuit data into packages according to the preset target protocol. The data is transmitted to the debugging module using the target protocol for chip signal analysis. This improves the universality of the application scenario, improves the efficiency of software interaction, reduces the occupation of software resources during the chip signal analysis process, and solves the problem of POWER architecture. In the post-silicon chip verification process of the processor chip signal analysis system, the software interaction efficiency is low and the software resources are occupied.

Description

Chip signal analysis hardware modules, systems, processor chips and electronic equipment

Technical field

This application relates to electronic design technology, and in particular to a chip signal analysis hardware module, system, processor chip and electronic equipment.

Background technique

In the field of server chip design, such as POWER architecture server chips, post-silicon chip verification methods are usually implemented using hardware modules with debugging and traceability functions. After the chip returns from the manufacturer, this hardware module can provide chip designers with a large number of continuous, Microscopic integrated circuit electronic signals are a key means of chip hardware positioning. Chip designers can set trigger conditions at the location of a fault. With the help of corresponding on-chip hardware resources, the circuit changes over a period of time can be provided. If a fault event occurs, the signals and circuit conditions before and after the fault can be captured.

However, currently only some chips have the aforementioned hardware modules. For most chip manufacturers, some interfaces will be retained on the chip. Through some matrix strobes internally and external logic analyzers, some timing changes can be observed to achieve functions such as chip hardware positioning, signal analysis, and troubleshooting. . The current post-silicon chip verification method is implemented through the software resource module and the chip data acquisition module used for data tracing on the chip wiring. That is, in the original POWER architecture, it is used to store software resource information or call third-party software resource information. The software resource module and the chip data acquisition module corresponding to data tracing constitute the entire technical solution. The software can configure the working mode of the chip data acquisition module through the bus. After a chip failure occurs, the chip controls the start and stop of the data tracing module. Collect data; the software needs to poll and wait during this process. When the chip data acquisition module completes the collection of circuit data on the target wiring, the software reads the data in the storage medium sequentially through the summary interface.

Therefore, for the resources of the software part, due to limited chip resources, the application scenarios are limited, and during the chip signal analysis process such as post-silicon chip verification, the efficiency of software and chip data interaction is not high, and software resources are occupied. In summary, the processor chip signal analysis system under the POWER architecture has problems such as low software interaction efficiency and large software resource usage during the post-silicon chip verification process.

Contents of the invention

This application provides a chip signal analysis hardware module, system, processor chip and electronic equipment to solve the problem of low software interaction efficiency and software resource occupation during the post-silicon chip verification process of the processor chip signal analysis system under the POWER architecture. Big question.

In a first aspect, this application provides a chip signal analysis hardware module. The chip signal analysis hardware module is applied to a target chip under the POWER architecture. The chip signal analysis hardware module is used to obtain the preset target path in the target chip. The circuit data on the line is encapsulated with the target protocol, the encapsulated data is obtained and transmitted to the preset storage unit or debugging unit;

Wherein, the target protocol includes an advanced tracking bus protocol ATB, and the encapsulation data is used to analyze the signal response of the target wiring and obtain the working status information or fault information of the target wiring.

In a second aspect, this application provides a chip signal analysis system, which includes:

Software resource module, chip data acquisition module, debugging module and the chip signal analysis hardware module described in the first aspect, the chip signal analysis hardware module includes a bus protocol conversion module;

Wherein, the software resource module is used to carry or call external software resources for chip signal analysis;

The chip data acquisition module includes a storage medium. The chip data acquisition module is used to obtain circuit data on the preset target wiring line through the software resources. The storage medium is used to access said circuit data;

The debugging module is used to obtain the packaging data and perform signal analysis on the target wiring according to the packaging data;

Wherein, the software resource module and the chip data analysis module realize data interaction through memory access;

The chip data analysis module is connected to the bus protocol conversion module, and the bus protocol conversion module is connected to the debugging module.

As an optional implementation, the bus protocol conversion module includes a read-write control unit;

Wherein, the read-write control unit is connected to the storage medium in the chip data acquisition module;

And, the read-write control unit is used to control the operating parameters of reading and writing the circuit data, and read and write the circuit data according to the operating parameters.

As an optional implementation, the read-write control unit includes a trigger sending control subunit;

The trigger sending control subunit is used to control the chip data acquisition module to generate a target information packet after completing the collection of circuit data on the target wiring, and drive the target information packet to be transmitted to the debugging module.

As an optional implementation, the read-write control unit includes a dynamic sending control subunit;

The dynamic transmission control subunit is used to control the bus protocol conversion module to transmit encapsulated data to the debugging module while acquiring circuit data on the target wiring.

As an optional implementation, the read-write control unit includes a mode control subunit;

The mode control subunit is used to control the data sending mode of the bus protocol conversion module.

As an optional implementation, the read-write control unit includes a data emptying control subunit;

The data emptying control subunit is used to control the data emptying in the storage medium according to the clock domain of the circuit structure corresponding to each target wiring, and send it to the bus protocol conversion module.

As an optional implementation, the bus protocol conversion module also includes a priority processing unit;

Wherein, the priority processing unit is connected to the read-write control unit and connected to the storage medium in the chip data acquisition module;

And, the priority processing unit is used to process the data read and write requests of the read and write control unit, and control the priority of data reading and writing;

And, the bus protocol conversion module also includes a protocol conversion unit;

Wherein, the protocol conversion unit is connected to the read-write control unit and connected to the debugging module through a bus based on the target protocol;

And, the protocol conversion unit is configured to receive a data write request from the debugging module through the bus, and send the encapsulated data to the debugging module according to the data write request.

In a third aspect, the present application provides a processor chip, which includes the chip signal analysis system described in the second aspect.

In a fourth aspect, the present application provides an electronic device, which includes the processor chip as described in the third aspect.

The chip signal analysis hardware modules, systems, processor chips and electronic equipment provided by this application are equipped with or called software resources for chip signal analysis through the software resource module, and are equipped with or called software resources used for chip signal analysis through the software resource module. , and through the chip data acquisition module, read the software resources, obtain the circuit data on the target wiring, and then transmit the circuit data to the bus protocol conversion module using the data transmission protocol of the server chip. The bus protocol conversion module completes timing synchronization and protocol The conversion process encapsulates the circuit data into encapsulated data according to the preset target protocol, and transmits it to the debugging module for chip signal analysis using the target protocol. This improves the universality of the application scenario, improves the efficiency of software interaction, and reduces It eliminates the occupation of software resources during the chip signal analysis process and solves the problems of low software interaction efficiency and large software resource occupation during the post-silicon chip verification process of the processor chip signal analysis system under the POWER architecture.

Description of the drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

Figure 1 is a schematic structural diagram of a chip signal analysis system disclosed in an embodiment of the present invention;

Figure 2 is a schematic structural diagram of another chip signal analysis system disclosed in an embodiment of the present invention;

Figure 3 is a schematic structural diagram of another chip signal analysis system disclosed in an embodiment of the present invention;

Figure 4 is a schematic flowchart of the operation logic of a chip signal analysis system disclosed in an embodiment of the present invention;

Figure 5 is a schematic flowchart of the operation logic of another chip signal analysis system disclosed in the embodiment of the present invention;

Reference signs:

11. Software resource module;

12. Chip data acquisition module;

13. Bus protocol conversion module;

14. Debugging module;

Read/write Control, read and write control unit;

Trigger Send Control, trigger send control subunit;

Active Send Control, dynamic send control subunit;

Work Mode Control, mode control subunit;

Flush Control, data emptying control subunit;

SP, priority processing unit;

ATB Master, protocol conversion unit;

Through the above-mentioned drawings, clear embodiments of the present application have been shown, which will be described in more detail below. These drawings and text descriptions are not intended to limit the scope of the present application's concepts in any way, but are intended to illustrate the application's concepts for those skilled in the art with reference to specific embodiments.

Detailed ways

Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with this application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the appended claims.

In server chip architectures such as IBM POWER, data tracing and data debugging are an important method for post-silicon chip verification. After the chip returns from the manufacturer, it can provide chip designers with a large number of continuous and microscopic integrated circuit electronic signals. A key means of chip hardware positioning. Chip designers can set trigger conditions at the location of a fault. With the help of on-chip hardware resources for data tracing and data debugging, circuit changes over a period of time can be provided, and the conditions before and after the fault can be accurately captured.

At present, in VLSI, only some manufacturers have similar on-chip chip verification capabilities. Most chip manufacturers in the industry do not set up corresponding hardware resources on the chip. They usually reserve some interfaces on the input and output interfaces of the chip, and internally Through some matrix gating and external connection to some logic analyzers, some timing changes can be observed.

Please refer to Figure 1. Figure 1 is a schematic structural diagram of a chip signal analysis system disclosed in an embodiment of the present invention. As shown in Figure 1, as an exemplary implementation, in the POWER architecture, it is used to store software resource information. Or the software resource module that calls third-party software resource information, and the chip data acquisition module corresponding to data tracing form the entire technical solution. The software can configure the working mode of the chip data acquisition module through the bus. After a chip failure occurs, the chip Control the data tracing module to start and stop collecting data; the software needs to poll and wait during this process. When the chip data acquisition module completes the collection of circuit data on the target wiring, the software sequentially reads the data in the storage medium through the summary interface. data.

The current chip signal analysis system has the following problems in the post-silicon chip verification process applied to POWER architecture server chips:

First, due to chip resources, the storage capacity is limited, and each target path only contains a limited number of interfaces. Even with data compression algorithms, the stored information is relatively limited. In addition, with the addition of timestamps, compressed time differences and other information, the effective data is further reduced. Increasing the storage capacity on silicon will only provide a small improvement, but will increase the cost by a huge amount.

Second, in the IBM POWER architecture, the software can obtain the data stored on the chip through bus access, but the efficiency is low.

Third, the software consumes a lot of money. During the chip signal analysis process, the software needs to continuously poll and obtain on-chip data.

Based on this, this application provides a chip signal analysis hardware module. The chip signal analysis hardware module is applied to the target chip under the POWER architecture. The chip signal analysis hardware module is used to obtain circuit data on the preset target wiring in the target chip. Encapsulate with the target protocol, obtain the encapsulated data and transmit it to the preset storage unit or debugging unit;

Among them, the target protocol includes the advanced tracking bus protocol ATB, and the encapsulated data is used to analyze the signal response of the target wiring and obtain the working status information or fault information of the target wiring.

As a result, the chip signal analysis hardware module completes the timing synchronization and protocol conversion process, and encapsulates the circuit data into encapsulated data according to the preset target protocol, realizing data interaction and conversion, and improving the application of the chip signal analysis hardware module. It has universal applicability in scenarios, improves the efficiency of software interaction, reduces the occupation of software resources during the chip signal analysis process, and solves the problem of software interaction during the post-silicon chip verification process of the processor chip signal analysis system under the POWER architecture. Problems of low efficiency and large software resource usage.

The technical concept of this application is to complete the packaging and interaction of data through the bus protocol conversion module for protocol conversion. The system structure provided by this application is mainly divided into software (software resource module), POWER Trace (chip data acquisition module), Trace to atb transfer (bus protocol conversion module), DDR/Debugger (debugging module) and other four parts. The software can be software running on the chip driver core, or third-party software. Third-party software requires the use of chip peripherals. POWER Trace is the original hardware structure in the IBM POWER architecture. It supports compression algorithms and can compress signals that change infrequently within a period of time. It supports non-compression algorithms. When the storage medium is limited, the observed signal range is smaller; Triggers can be set based on the observation signal to control the collection of several data on the target path. The bus protocol conversion module is the core of this technical solution and is used to solve current technical problems. DDR is a large-capacity hardware storage device, and Debugger is a third-party software and hardware debugging box. According to the actual application scenarios of the hardware system, the corresponding implementation method is selected to realize the software debugging function.

Specifically, this application carries or calls software resources for chip signal analysis through the software resource module, loads or calls software resources for chip signal analysis through the software resource module, and reads the software resources through the chip data acquisition module to obtain The circuit data on the target wiring is then transmitted to the bus protocol conversion module using the data transmission protocol of the server chip. The bus protocol conversion module completes the timing synchronization and protocol conversion process, and encapsulates the circuit data according to the preset target protocol. The data is encapsulated and transmitted to the debugging module using the target protocol for chip signal analysis. This improves the universality of the application scenario, improves the efficiency of software interaction, reduces the occupation of software resources during the chip signal analysis process, and solves the problem of POWER In the post-silicon chip verification process of the processor chip signal analysis system under the architecture, the software interaction efficiency is low and the software resources are occupied.

Please refer to Figure 2. Figure 2 is a schematic structural diagram of another chip signal analysis system disclosed in an embodiment of the present invention. The system includes a chip signal analysis hardware module. The chip signal analysis hardware module is applied to the target chip under the POWER architecture. Specifically, As shown in Figure 2, the system includes:

The software resource module 11 , the chip data acquisition module 12 , the debugging module 14 and the chip signal analysis hardware module as in the aforementioned embodiments. The chip signal analysis hardware module includes a bus protocol conversion module 13 .

Software resource module 11, used to carry or call software resources for chip signal analysis;

The software resource module is used to carry all software resources that may be involved in the chip signal analysis process. In a specific implementation, it can be understood as a back-end database for storing software resources, which is called according to the corresponding instructions initiated by the front-end. For the debugging module mentioned later, one implementation may be that software resources used for debugging are also obtained through the software resource module.

In addition, it should be noted that the software resource module can also be used to indicate the interface for obtaining external software resources. That is, the software resource module can not only be used to carry software resources, but can also be used as software and hardware for data interaction with third-party software data. Interface to implement software resource acquisition function.

Chip data acquisition module 12. The chip data acquisition module 12 includes a storage medium. The chip data acquisition module 12 is used to obtain circuit data on the target wiring through software resources. The storage medium is used to access circuit data;

This part of the structure is used to implement the Trace process in the traditional server chip architecture, that is, the process of tracking electronic devices on the target wiring and obtaining the corresponding electrical parameters.

The bus protocol conversion module 13 is used to encapsulate the circuit data on the target wiring according to the target protocol to obtain the encapsulated data and transmit it;

In this application, compared with the traditional server chip signal analysis system architecture, the added bus protocol conversion module is mainly used for data encapsulation and protocol conversion. Specifically, the bus protocol conversion module executes the processing of hardware devices in different clock domains. The protocol conversion process of timing synchronization and encapsulated data encapsulates the circuit data into encapsulated data according to the preset target protocol, and transmits it to the debugging module using the target protocol for chip signal analysis.

Among them, the bus protocol conversion module 13 is a specific implementation method of the chip signal analysis hardware module provided by the present application. The chip signal analysis hardware module is applied to the target chip under the POWER architecture. The chip signal analysis hardware module includes the bus protocol conversion module 13 ;

Among them, the bus protocol conversion module 13 is used to obtain the circuit data on the preset target wiring in the target chip, package it with the target protocol, obtain the packaged data and transmit it to the preset storage unit or debugging unit;

Among them, the target protocol includes the advanced tracking bus protocol ATB, and the encapsulated data is used to analyze the signal response of the target wiring and obtain the working status information or fault information of the target wiring.

The debugging module 14 is used to obtain packaging data and perform signal analysis on the target wiring according to the packaging data;

Among them, the software resource module 11 and the chip data analysis module realize data interaction through memory access;

The chip data analysis module is connected to the bus protocol conversion module 13 , and the bus protocol conversion module 13 is connected to the debugging module 14 .

The debugging module 14 serves as a software and hardware analysis module for post-silicon chip verification. The hardware part can be implemented as a large-capacity storage device, and the software part is loaded on the storage device, or obtained from the software resource module as before.

The software resource module is used to load or call software resources for chip signal analysis, and through the chip data acquisition module, the software resources are read and the circuit data on the target wiring is obtained, and then the circuit data is transmitted using the data transmission protocol of the server chip. To the bus protocol conversion module, the bus protocol conversion module completes the timing synchronization and protocol conversion process, encapsulates the circuit data into encapsulated data according to the preset target protocol, and transmits it to the debugging module for chip signal analysis using the target protocol. This improves the application The universality of the scenario improves the efficiency of software interaction, reduces the occupation of software resources during the chip signal analysis process, and solves the problem of software interaction efficiency in the post-silicon chip verification process of the processor chip signal analysis system under the POWER architecture. The problem is that it is low and takes up a lot of software resources.

Please refer to Figure 3. Figure 3 is a schematic structural diagram of another chip signal analysis system disclosed in an embodiment of the present invention. As shown in Figure 3, the bus protocol conversion module 13 includes a read and write control unit;

It should be noted that in the description of Figure 3, the following concepts are consistent and should be commonly understood in the specific description:

Read/write Control, read and write control unit; Trigger Send Control, trigger send control subunit; Active Send Control, dynamic send control subunit; Work Mode Control, mode control subunit; Flush Control, data emptying control subunit; SP, priority processing unit; ATB Master, protocol conversion unit;

And, in Figure 3, the software resource module is the box with the word "software" in the upper left corner. It realizes data interaction with the chip data acquisition module through memory access. The chip data acquisition module is the box with the word "POWER8 Trace" in the upper right corner. Through the storage medium and priority The processing unit interacts with the bus protocol conversion module for data. The bus protocol conversion module is the box marked Trace to atb in the lower right corner. It interacts with the debugging module marked DDR or Debugger in the lower left corner through the ATB bus.

Among them, the read-write control unit is connected to the storage medium in the chip data acquisition module 12;

And, the reading and writing control unit is used to control the working parameters of reading and writing circuit data, and to read and write the circuit data according to the working parameters.

Through the read-write control unit, the working parameters of data interaction between the chip data acquisition module and the bus protocol conversion module 13 can be determined, information such as the data interaction mode can be determined, and the process of reading and writing circuit data according to the determined working parameters can be executed. This improves the universality of application scenarios, improves the efficiency of software interaction, and reduces the occupation of software resources during chip signal analysis.

In a feasible architecture, the software resource module 11 and the chip data acquisition module 12 form the entire technical solution. The software can configure the working mode of the chip data acquisition module 12 through the bus. After a chip failure occurs, the chip controls the target path. Start and stop data collection; the software needs to poll and wait during this process. When the target path data collection is completed, the software reads the data in the storage medium sequentially through the summary interface.

In contrast, the implementation provided by this application also adds a Trace to ATB hardware module, which can encapsulate the data in the storage medium into a data packet in the ARM ATB protocol format, and then send the data to the DDR through the corresponding hardware structure. , or you can send it directly to a dedicated Debugger.

As an optional implementation manner, the reading and writing control unit includes a trigger sending control subunit;

The trigger sending control subunit is used to control the chip data acquisition module 12 to generate a target information packet after completing the collection of circuit data on the target wiring, and drive the target information packet to be transmitted to the debugging module 14 .

Specifically, for the Trigger Send Control logic of the trigger send control sub-unit, after the Trace data collection is completed, the data is actively pushed to the outside. After the data push is completed, the Debugger can be actively notified through interrupts and special packets to save software overhead and thereby There is no need for software to keep polling and waiting.

The control subunit is sent through a trigger, which can actively push data to the outside after the circuit data collection is completed, and inform the debugging module of the current data status through the preset target information packet, eliminating the need for repeated polling and waiting by the software, thereby improving read and write performance. It controls the efficiency of data interaction between units, improves the universality of application scenarios, improves the efficiency of software interaction, and reduces the occupation of software resources during the chip signal analysis process.

As an optional implementation manner, the reading and writing control unit includes a dynamic sending control subunit;

The dynamic transmission control subunit is used to control the bus protocol conversion module 13 to transmit encapsulated data to the debugging module 14 while acquiring the circuit data on the target wiring.

For the Active Send Control logic of the dynamic send control subunit, data can be sent out while data is being collected. When the data rate does not change much, longer observations can be achieved through the compression algorithm. Ideally, , the information of the entire chip operation cycle can be observed.

Through the dynamic sending control sub-unit, the read-write control unit can realize the function of sending data out while collecting data. The compression algorithm can achieve longer period of data observation, which improves the universality of application scenarios and improves the The efficiency of software interaction reduces the occupation of software resources during chip signal analysis.

As an optional implementation manner, the reading and writing control unit includes a mode control subunit;

The mode control subunit is used to control the data sending mode of the bus protocol conversion module 13.

For the mode control sub-unit Work Mode Control, it not only maintains the operation of the work, but is also responsible for coordinating the switching of various different working modes.

The mode control sub-unit maintains the normal operation of the read-write control unit and coordinates the data transmission mode of the bus protocol conversion module, which improves the efficiency of data interaction, improves the universality of application scenarios, and reduces the software cost in the chip signal analysis process. Resource occupation.

As an optional implementation manner, the read/write control unit includes a data emptying control subunit;

The data emptying control subunit is used to control the data emptying in the storage medium according to the clock domain of the circuit structure corresponding to each target wiring, and sends it to the bus protocol conversion module 13 .

For the logic related to the data flushing control subunit Flush Control, it mainly completes the flushing of data in the storage medium to ensure that all hardware modules working in different clock domains can flush data effectively and accurately to ensure that the software gets enough data.

Through the data emptying control subunit, data emptying in the storage medium can be completed, ensuring that hardware modules working in different clock domains can effectively empty data, so that the software side can obtain sufficient data, improving the efficiency of data interaction and improving It improves the universality of application scenarios and reduces the occupation of software resources during chip signal analysis.

As an optional implementation manner, the bus protocol conversion module 13 also includes a priority processing unit;

Among them, the priority processing unit is connected to the read-write control unit and connected to the storage medium in the chip data acquisition module 12;

And, the priority processing unit is used to process the data reading and writing requests of the reading and writing control unit, and control the priority of data reading and writing.

The priority processing unit can be used to process data read and write requests from the read and write control unit, and control the priority of data read and write, which improves the efficiency of data interaction, improves the universality of application scenarios, and reduces the chip signal analysis process. usage of software resources.

As an optional implementation manner, the target protocol includes Advanced Trace Bus Protocol ATB;

The bus protocol conversion module 13 also includes a protocol conversion unit;

Among them, the protocol conversion unit is connected to the read-write control unit and connected to the debugging module 14 through a bus based on the target protocol;

And, the protocol conversion unit is configured to receive the data write request from the debugging module 14 through the bus, and send the encapsulated data to the debugging module 14 according to the data write request.

Regarding the relevant logic of the protocol conversion unit ATB Master, this unit is the unit that finally completes the protocol conversion. It can send data downward, receive downstream Flush requests, and complete related data emptying.

According to the preset ATB bus protocol, protocol conversion and data emptying are completed through the protocol conversion unit, which improves the efficiency of data interaction, improves the universality of application scenarios, and reduces the occupation of software resources during chip signal analysis.

For the remaining logical parts in the figure, such as the third-party read and write control interface, it is used to initiate corresponding read requests and receive read data according to the working mode; SP is the aforementioned priority processing unit, used to control the timing of data reading and writing, usually It is necessary to ensure that the writing priority is the highest; the data packaging logic part mainly inserts status and tag information; the AFIFO part is responsible for completing asynchronous conversion of different clock domains.

In summary, this application realizes data encapsulation, protocol conversion and data interaction through the design of the bus protocol conversion module 13, thereby improving the universality of application scenarios, improving the efficiency of software interaction, and reducing the cost of chip signal analysis. The occupation of software resources during the process solves the problem of low software interaction efficiency and large software resource occupation during the post-silicon chip verification process of the processor chip signal analysis system under the POWER architecture. The previous implementation methods can be combined and implemented. In a specific application scenario, the system structure of the entire technical solution is mainly divided into four parts: software, Power Trace, Trace to ATB transfer, and DDR/Debugger. The software can be software running on the Power Core, or it can be third-party software. Third-party software needs to use the peripherals of the chip. Generally speaking, software resources can be carried or externalized in the form of software resource modules. Interaction. Power Trace is the original hardware structure in the IBM Power architecture. It supports compression algorithms and can compress signals that change infrequently within a period of time. It supports non-compression algorithms. When the storage medium is limited, the observed signal range is smaller; The trigger conditions and trigger signals can be set according to the observation signal, and the chip data acquisition module 12 is controlled to collect several data on the target wiring. The design of the bus protocol conversion module 13 is implemented with the hardware structure of Trace to ATB as shown in the figure, which realizes data encapsulation, protocol conversion and data interaction, thus improving the universality of application scenarios, improving the efficiency of software interaction and reducing It eliminates the occupation of software resources during the chip signal analysis process and solves the problems of low software interaction efficiency and large software resource occupation during the post-silicon chip verification process of the processor chip signal analysis system under the POWER architecture. In addition, DDR is a large-capacity hardware storage device, and Debugger is a third-party software and hardware debugging box, which is the specific software and hardware implementation of the debugging module 14. For details, please refer to the relevant descriptions mentioned above.

Specifically, the Trace to atb hardware module includes the following logical units. As mentioned above, the consistency of the hardware module name description remains unchanged. You can still refer to the corresponding description of Figure 3.

The software resource module 11 is equipped with or obtains third-party software resources in real time through the interface, and realizes data communication connection through the storage memory channel and the built-in data tracking chip under the POWER architecture, that is, the aforementioned chip data acquisition module 12, which directly Used to obtain data on the target trace to achieve subsequent post-silicon chip verification functions. Among them, the Power8 Trace module realizes data interaction with the Trace to ATB hardware module provided by this application through the storage medium, realizes data interaction with the software resource module through the serial register access interface, and realizes software timing control through the data read and write control unit. , as well as data operations such as data storage, data capture mode setting, data compression, etc., and integrates packaged data, and initiates data read and write requests to the bus protocol conversion module 13.

The main units of the bus protocol conversion module 13 include the relevant structures of the read-write control unit and the protocol conversion unit. For the Trace to ATB hardware module shown in the figure, the data in the storage medium of the data acquisition module 12 can be encapsulated into the ARM ATB protocol format. The data is encapsulated, and then the data protocol conversion and timing matching are completed through the protocol conversion unit. The data is sent to the DDR through the ATB bus, or directly to a dedicated Debugger to implement the debugging function.

The read-write control unit can include the four sub-logic units mentioned above. These four sub-units can be implemented together, designed in the read-write control unit, and connected to a third-party read-write control interface to further connect to external priority Functional units such as level processing, data marking, and protocol conversion control the working mode or data interaction mode of the corresponding unit in the post-silicon chip verification process.

Specifically, the Trigger Send Control logic unit can automatically transmit and push data after the data acquisition module completes the electronic data collection on the target wiring. After the data push is completed, it can be designed under specific application scenarios with interrupts. The encapsulated data of the function is actively notified to the Debugger, saving software overhead. This eliminates the need for the software to poll and wait all the time, reducing the consumption of software resources. The Active Send Control logic unit, while controlling the data acquisition module 12 to collect data, can send data to external structures such as the bus protocol conversion module 13 to achieve parallel execution of data reading and writing. When the data rate changes little, through The compressed algorithm can achieve longer-term observations. Ideally, information on the entire chip operation cycle can be observed, which increases the amount of data observed during post-silicon chip verification, thereby improving the efficiency of data observation. The Work Mode Control unit not only maintains the operation of the work, but is also responsible for coordinating the switching of various working modes. It is mainly used to obtain data from the target wiring and control the data interaction process between modules to ensure the efficiency and effectiveness of data interaction. . The logic unit related to Flush Control mainly completes the emptying of data in the storage medium, ensuring that all hardware modules working in different clock domains can effectively and accurately empty data, and ensuring that sufficient data can be obtained in the debugging module 14. for data debugging. The read-write control module improves the efficiency of software interaction and reduces the occupation of software resources by controlling the working mode and data interaction method.

Another important unit, the protocol conversion unit and its surrounding structures, can be used to improve the universality of application scenarios. The related logical unit of the ATB Master is the unit that ultimately completes the protocol conversion and can send data downwards and receive downstream Flush requests. , complete related data emptying.

For the remaining logical units of the bus protocol conversion module 13, the third-party read-write control interface initiates a read-write request to the upstream chip data acquisition module 12 and obtains data according to the working mode and data interaction mode determined by the read-write control unit; SP It is an absolute priority processing module. In specific application scenarios, it is usually necessary to ensure that the writing priority is the highest; in the Package part, status and mark information such as Flag and status are mainly inserted to enrich the amount of information in the packaged data and facilitate other modules based on the packaged data. Obtain the relevant data status; the AFIFO part is used to complete asynchronous conversion of different clock domains. For its conversion logic, please refer to the relevant descriptions in Figure 4 and Figure 5 below.

Please refer to Figure 4. Figure 4 is a schematic flow chart of the operation logic of a chip signal analysis system disclosed in an embodiment of the present invention. As shown in Figure 4, when the data emptying control subunit faces hardware modules in different clock domains, its electrical For the flat transformation method and execution process, please refer to the transformation direction and text description shown in the figure.

Specifically, the running logic shown in the diagram is used to instruct the process of interaction and conversion of the clock domain of the processor chip core and the clock domain under the ATB protocol through software to the signals of the hardware structure to ultimately realize the protocol conversion.

Among them, the left side of the timing diagram is used to indicate the core clock domain of the processor chip core itself, the right side is used to indicate the target clock domain atb clock domain under the ATB protocol, and the flush request indicates the request used to control the data flow in the software. Information, process the data in the buffer to achieve the effect of obtaining or controlling the data flow on demand, that is, emptying the data in the illustration. flush_req and flush_ack are indication signals initiated during the timing conversion process. According to the conversion methods and conditions of these two signals, the logic for realizing the conversion of the protocol can be formed.

The atb clock domain receives the flush request and initiates a high-level flush_req to the core clock domain, that is, the flush_req signal in the direction of atb2core is raised. The core clock domain detects the request of the atb clockdomain and begins to read the data of the Trace array until all After all the flush data is read, when the data in the package is also emptied, an ACK signal is pulled up, that is, the core2atb_flush_ack signal is pulled high. The atb clock domain receives the ACK signal from the core clock domain and begins to wait for all data in AFIFO and ATB master. The data is drained in the downstream direction of the arrow. After the emptying is completed, flush_req is pulled low, that is, the flush_req signal in the atb2core direction is pulled low. The core clockdomain detects that the flush_req of the atb clock domain is pulled low, and enters the IDLE state. At the same time, the ACK signal is pulled low, that is, the flush_req signal is pulled low. core2atb direction flush_ack signal, finally, atb clock domain detects the ACK signal and pulls it low, and also enters the IDLE state.

In addition, please refer to Figure 5. Figure 5 is a schematic flowchart of the operation logic of another chip signal analysis system disclosed in an embodiment of the present invention. As shown in Figure 5, during the operation of the data emptying control subunit, its level changes For conditions and corresponding program commands, please refer to the relevant descriptions shown in the figure.

Similarly, the left side of the timing diagram is used to indicate the clock domain of the processor chip core itself, and the right side is used to indicate the target clock domain under the ATB protocol. In one implementation, the core clock domain is included in the process shown in the timing diagram. There are four flush-related data states, namely Flush_IDLE, Flush_ARR, FLUSH_PKT and ATB_FLUSH, and the atb clockdomain also includes four flush-related data states, namely IDLE, Trace_FLUSH, ATB_FLUSH and FLUSH_END. The process from IDLE to Trace_FLUSH is used to instruct the atb clock domain to receive a flush request and when the coresight_aflush_req||software_trig&trig_mode||trace_run_stop_trig&trig_mode command is met, a high-level flush_req is initiated to the core clock domain, that is, the atb2core_flush_req_d3 command, triggering the core clock domain to start from IDLE The state is converted to a state where flush is declared, and the packaging and encapsulation of flush-related data is triggered through the arr_has_rd_out command. When the pkt_flush_finish state appears, it is determined that the encapsulation is completed, and a signal is sent to the atb clock domain side, that is, the aforementioned core clock domain detects the request of the atb clock domain. , start reading the data of the Trace array until all the flush data is read. When the data in the package is also emptied, pull up an ACK signal and pull up the core2atb_flush_ack signal, that is, the core2atb_flush_ack_d3 command. The atb clock domain receives the core clock Domain's ACK signal starts waiting for all data in AFIFO and ATB master to be emptied in the downstream direction of the arrow. After the emptying is completed, the atb_domain_empty command is initiated to trigger the action of pulling down the flush_req signal in the atb2core direction. The core clock domain detects the atb clock domain The flush_req is pulled low, that is! After the atb2core_flush_req_d3 command, it enters the IDLE state and pulls down the ACK signal at the same time, that is, pulls down the flush_ack signal in the core2atb direction. Finally, the atb clock domain detects that the ACK signal is pulled down, that is! After the core2atb_flush_ack_d3 command, it also enters the IDLE state.

Among them, regarding the naming method, data commands and declaration statements related to the flush request, you can refer to the specific development language for settings, and its logical functions can be understood in conjunction with Figure 4.

In summary, the implementation provided by this application can save software overhead. After the data is pushed, the Debugger can be notified, so that the software no longer needs to poll and wait all the time, and improves work efficiency. It actively pushes data through the dedicated ATB bus, and the working frequency Higher, larger bus bandwidth, and in scenarios where the storage medium remains unchanged and the data changes slowly, data can be collected over a longer period of time. Ideally, data within the entire chip operating cycle can be observed.

The software resource module is used to load or call software resources for chip signal analysis, and through the chip data acquisition module, the software resources are read and the circuit data on the target wiring is obtained, and then the circuit data is transmitted using the data transmission protocol of the server chip. To the bus protocol conversion module, the bus protocol conversion module completes the timing synchronization and protocol conversion process, encapsulates the circuit data into encapsulated data according to the preset target protocol, and transmits it to the debugging module for chip signal analysis using the target protocol. This improves the application The universality of the scenario improves the efficiency of software interaction, reduces the occupation of software resources during the chip signal analysis process, and solves the problem of software interaction efficiency in the post-silicon chip verification process of the processor chip signal analysis system under the POWER architecture. The problem is that it is low and takes up a lot of software resources.

In addition, the present application provides a processor chip, which includes the chip signal analysis system as in any embodiment.

And, the present application provides an electronic device, which includes the processor chip as in any embodiment.

The device embodiments described above are only illustrative. The modules described as separate components may or may not be physically separated. The components shown as modules may or may not be physical modules, that is, they may be located in one place. , or it can be distributed to multiple network modules.

Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Persons of ordinary skill in the art can understand and implement the method without any creative effort.

Other embodiments of the present application will be readily apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary technical means in the technical field that are not disclosed in this application. . It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It is to be understood that the present application is not limited to the precise structures described above and illustrated in the accompanying drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (10)

1. A chip signal analysis hardware module. The chip signal analysis hardware module is applied to the target chip under the POWER architecture. It is characterized in that the chip signal analysis hardware module is used to obtain the preset target wiring in the target chip. The circuit data on the device is encapsulated with the target protocol, the encapsulated data is obtained and transmitted to the preset storage unit or debugging unit; Wherein, the target protocol includes an advanced tracking bus protocol ATB, and the encapsulation data is used to analyze the signal response of the target wiring and obtain the working status information or fault information of the target wiring. 2. A chip signal analysis system, characterized in that the system includes: Software resource module, chip data acquisition module, debugging module and chip signal analysis hardware module as claimed in claim 1, the chip signal analysis hardware module includes a bus protocol conversion module; Wherein, the software resource module is used to carry or call external software resources for chip signal analysis; The chip data acquisition module includes a storage medium. The chip data acquisition module is used to obtain circuit data on the preset target wiring line through the software resources. The storage medium is used to access said circuit data; The debugging module is used to obtain the packaging data and perform signal analysis on the target wiring according to the packaging data; Wherein, the software resource module and the chip data analysis module realize data interaction through memory access; The chip data analysis module is connected to the bus protocol conversion module, and the bus protocol conversion module is connected to the debugging module. 3. The system according to claim 2, characterized in that the bus protocol conversion module includes a read-write control unit; Wherein, the read-write control unit is connected to the storage medium in the chip data acquisition module; And, the read-write control unit is used to control the operating parameters of reading and writing the circuit data, and read and write the circuit data according to the operating parameters. 4. The system according to claim 3, characterized in that the read and write control unit includes a trigger sending control subunit; The trigger sending control subunit is used to control the chip data acquisition module to generate a target information packet after completing the collection of circuit data on the target wiring, and drive the target information packet to be transmitted to the debugging module. 5. The system according to claim 4, characterized in that the read and write control unit includes a dynamic transmission control subunit; The dynamic transmission control subunit is used to control the bus protocol conversion module to transmit encapsulated data to the debugging module while acquiring circuit data on the target wiring. 6. The system according to claim 5, characterized in that the read and write control unit includes a mode control subunit; The mode control subunit is used to control the data sending mode of the bus protocol conversion module. 7. The system according to claim 6, characterized in that the read and write control unit includes a data emptying control subunit; The data emptying control subunit is used to control the data emptying in the storage medium according to the clock domain of the circuit structure corresponding to each target wiring, and send it to the bus protocol conversion module. 8. The system according to any one of claims 3-7, characterized in that the bus protocol conversion module further includes a priority processing unit; Wherein, the priority processing unit is connected to the read-write control unit and connected to the storage medium in the chip data acquisition module; And, the priority processing unit is used to process the data read and write requests of the read and write control unit, and control the priority of data reading and writing; And, the bus protocol conversion module also includes a protocol conversion unit; Wherein, the protocol conversion unit is connected to the read-write control unit and connected to the debugging module through a bus based on the target protocol; And, the protocol conversion unit is configured to receive a data writing request from the debugging module through the bus, and send the encapsulated data to the debugging module according to the data writing request. 9. A processor chip, characterized in that the processor chip includes the chip signal analysis system according to any one of claims 2-8. 10. An electronic device, characterized in that the electronic device includes the processor chip according to claim 9.