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CN117673033B - Semiconductor structure and method for forming semiconductor structure - Google Patents

Semiconductor structure and method for forming semiconductor structure Download PDF

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Publication number
CN117673033B
CN117673033B CN202211067996.9A CN202211067996A CN117673033B CN 117673033 B CN117673033 B CN 117673033B CN 202211067996 A CN202211067996 A CN 202211067996A CN 117673033 B CN117673033 B CN 117673033B
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buffer
buffer structure
forming
recess
recessed portion
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CN117673033A (en
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张永会
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202211067996.9A priority Critical patent/CN117673033B/en
Priority to PCT/CN2022/132025 priority patent/WO2024045349A1/en
Publication of CN117673033A publication Critical patent/CN117673033A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

一种半导体结构及其制造方法，该半导体结构包括：衬底、第一缓冲结构、第二缓冲结构和导电结构，衬底包括相背的第一面和第二面；第一缓冲结构位于所述衬底中，且沿第一方向延伸，所述第一方向为由所述第一面指向所述第二面的方向；第二缓冲结构位于所述第一缓冲结构的部分侧壁上，且沿第二方向延伸，所述第二方向与所述第一方向相交；导电结构位于所述第一缓冲结构中，且沿所述第一方向延伸。本公开提供的半导体结构提高了应力释放能力，改善了半导体结构中应力集中的问题。

A semiconductor structure and a manufacturing method thereof, the semiconductor structure comprising: a substrate, a first buffer structure, a second buffer structure and a conductive structure, the substrate comprising a first surface and a second surface opposite to each other; the first buffer structure is located in the substrate and extends along a first direction, the first direction being a direction from the first surface to the second surface; the second buffer structure is located on a part of the sidewall of the first buffer structure and extends along a second direction, the second direction intersecting with the first direction; the conductive structure is located in the first buffer structure and extends along the first direction. The semiconductor structure provided by the present disclosure improves the stress release capability and improves the problem of stress concentration in the semiconductor structure.

Description

Semiconductor structure and forming method thereof
Technical Field
The disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for forming the semiconductor structure.
Background
With the development of semiconductors, moore's law is moving toward a limit, and 2.5D and 3D integration technologies are becoming effective means for continuing moore's law, improving performance and functional density of electronic systems, and TSV (Through Silicon Via, through silicon vias) conductive vias are being used in large numbers in 2.5D and 3D integration technologies. The TSV technology can realize direct three-dimensional interconnection between wafers (chips) or between chips and a substrate by forming metal upright posts in the wafers and matching with metal convex points, so that the limitation of two-dimensional wiring of the traditional semiconductor chips can be overcome. Compared with the traditional stacking technology such as bonding technology, the interconnection mode has the advantages of high stacking density in the three-dimensional direction, small outline dimension after packaging and the like, so that the speed of chips is greatly improved, and the power consumption is reduced. Therefore, TSV technology has been widely considered as a fourth generation packaging technology following bonding, tape bonding, and flip chip, and will gradually become a mainstream technology in the field of high-density packaging.
However, the conventional process for interconnecting the front end of the TSV has the disadvantage that in the current isotropic dry etching process of the TSV, a protruding portion occurs at the edge of the TSV hole, and when the insulating layer, the seed layer and the metal filling are fabricated, a "stress concentration" region of a multi-layer structure is formed, so that delamination or cracks are easily generated between the insulating layer and the substrate, thereby seriously affecting the quality and reliability of the TSV, and the current process and structure cannot eliminate the influence of the stress concentration region.
It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The present disclosure is directed to a semiconductor structure and a method of forming the semiconductor structure that improves stress relief capability and improves stress concentration in the semiconductor structure.
Other features and advantages of the present disclosure will be apparent from the following detailed description, or may be learned in part by the practice of the disclosure.
According to an aspect of an embodiment of the present disclosure, there is provided a semiconductor structure including:
a substrate comprising a first side and a second side opposite to each other;
A first buffer structure located in the substrate and extending along a first direction, wherein the first direction is a direction from the first face to the second face;
a second buffer structure located on a part of the side wall of the first buffer structure and extending along a second direction intersecting the first direction, and
And the conductive structure is positioned in the first buffer structure and extends along the first direction.
In one exemplary embodiment of the present disclosure, the second buffer structure is located at an end of the first buffer structure near the first face.
In an exemplary embodiment of the present disclosure, the second buffer structure is annular convex in a circumferential direction of the first buffer structure.
In one exemplary embodiment of the present disclosure, the semiconductor structure includes a plurality of second buffer structures uniformly distributed in the first direction.
In an exemplary embodiment of the present disclosure, the width of the second buffer structure in the first direction increases gradually and then decreases gradually along the second direction.
In one exemplary embodiment of the present disclosure, the first buffer structure and the second buffer structure are a unitary structure.
In one exemplary embodiment of the present disclosure, the first buffer structure is of a different material than the second buffer structure.
In one exemplary embodiment of the present disclosure, the first buffer structure has a protrusion on a sidewall thereof, the protrusion having a first surface and a second surface, the first surface and the second surface intersecting, the second buffer structure extending on the first surface in the second direction.
In an exemplary embodiment of the present disclosure, the semiconductor structure further includes:
and a blocking structure located on the first surface of the boss.
In one exemplary embodiment of the present disclosure, the blocking structure is located at both sides of the second buffer structure.
In one exemplary embodiment of the present disclosure, the blocking structure is annular in a circumferential direction of the first buffer structure.
In an exemplary embodiment of the present disclosure, both ends of the conductive structure are exposed from the first face and the second face, respectively.
According to another aspect of an embodiment of the present disclosure, there is provided a method of forming a semiconductor structure, the method including:
Providing a substrate comprising a first side and a second side opposite to each other;
Forming a first recess on the first face of the substrate along a first direction, the first direction being a direction from the first face to the second face;
Forming a second recess along a second direction on a side wall of the first recess, the second direction intersecting the first direction;
Forming a second buffer structure in the second concave part and forming a first buffer structure in the first concave part;
A conductive structure is formed in the first buffer structure, the conductive structure extending in the first direction.
In one exemplary embodiment of the present disclosure, forming a second recess on a sidewall of the first recess along a second direction includes:
Forming a blocking structure on a part of the side wall of the first concave part;
and etching part of the side wall of the first concave part by taking the blocking structure as a mask to form a second concave part.
In one exemplary embodiment of the present disclosure, forming a blocking structure on a portion of a sidewall of the first recess includes:
and carrying out ion doping on part of the side wall of the first concave part, wherein the ion doped region forms a blocking structure.
In one exemplary embodiment of the present disclosure, a plurality of blocking structures are formed on a portion of sidewalls of the first recess, and sidewalls of the first recess between two adjacent blocking structures are laterally etched in the second direction to form the second recess.
In one exemplary embodiment of the present disclosure, the second buffer structure is formed by filling a second buffer material in the second recess, and the first buffer structure is formed by filling a first buffer material in the first recess.
In one exemplary embodiment of the present disclosure, the first buffer structure is etched in the first direction to form a first buffer structure having a first trench in which the conductive structure is formed.
In an exemplary embodiment of the present disclosure, after forming the first buffer structure, before forming the conductive structure, the forming method further includes:
Filling a blocking material in the first groove to form a blocking initial layer;
and etching the blocking initial layer along the first direction to form a blocking layer with a second groove, and forming the conductive structure in the second groove.
In one exemplary embodiment of the present disclosure, the first buffer structure and the second buffer structure are made of the same material, and the first buffer structure is formed in the first recess and the second buffer structure is formed in the second recess through the same filling process.
In one exemplary embodiment of the present disclosure, a conductive structure is formed in the first buffer structure;
forming a conductive initial structure in the first buffer structure;
and carrying out chemical mechanical polishing from the second surface to form a conductive structure with two ends respectively exposed from the first surface and the second surface.
According to the semiconductor structure, the first buffer structure in the contact structure covers the side wall of the conductive structure and can serve as the stress buffer layer to release the stress concentration area of the TSV, and the second buffer structure is located on the outer side of the first buffer structure and can further release the stress of the TSV and alleviate the problem of stress concentration in the TSV in the semiconductor structure.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort. In the drawings:
FIG. 1 is a schematic diagram of a semiconductor structure provided in one embodiment of the present disclosure;
Fig. 2 is a flow chart of a method of forming a semiconductor structure according to an embodiment of the present disclosure;
fig. 3-14 are process diagrams illustrating the formation of a semiconductor structure according to one embodiment of the present disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein, but rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the disclosed aspects may be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the disclosure.
Furthermore, the drawings are merely schematic illustrations of the present invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus a repetitive description thereof will be omitted. The terms "a," "an," "the," and "said" are used to indicate the presence of one or more elements/components/etc., the terms "comprising" and "having" are intended to mean that there may be additional components, etc., in addition to the listed components, and the terms "first," "second," etc., are used merely as labels, and do not limit the number of its objects.
After the TSV is manufactured, in the process of thinning the wafer back, the bottom stress of the TSV is the largest, and a stress concentration area is formed, so that delamination or cracks are easily generated at the bottom of the TSV, and the quality and reliability of the TSV are seriously affected.
In view of the above technical problems, an embodiment of the present disclosure first provides a semiconductor structure, as shown in fig. 1, including a substrate 100, a first buffer structure 210, a second buffer structure 220, and a conductive structure 400, where the first buffer structure 210, the second buffer structure 220, and the conductive structure 400 form a contact structure.
The substrate 100 includes a first surface 101 and a second surface 102 opposite to each other, a first recess 110 extending along a first direction Y is disposed on the first surface 101, a first buffer structure 210 is located in the substrate 100 and extends along the first direction Y, the first direction Y is a direction from the first surface 101 to the second surface 102, a second buffer structure 220 is located on a portion of a sidewall of the first buffer structure 210 and extends along a second direction X, the second direction X intersects the first direction Y, and a conductive structure 400 is located in the first buffer structure 210 and extends along the first direction Y.
In the semiconductor structure provided by the disclosure, the first buffer structure 210 in the contact structure covers the side wall of the conductive structure 400 and can be used as a stress buffer layer to release the stress concentration region of the TSV, and the second buffer structure 220 is positioned on the outer side of the first buffer structure 210 and can be used for further releasing the stress of the TSV and relieving the problem of stress concentration in the TSV in the semiconductor structure.
Specifically, as shown in fig. 4 to 8, the first surface 101 of the substrate 100 is provided with a first recess 110, a sidewall of the first recess 110 is provided with a second recess 140 extending along the second direction X, and the second recess 140 is located at an end of the first recess 110 near the first surface 101. The second buffer structure 220 is located in the second recess 140 and is connected to the second buffer structure 220, as shown in fig. 8, a third recess 210 is disposed on a side of the first buffer structure 210 facing away from the inner wall, and as shown in fig. 12, the conductive structure 400 is located in the third recess 210. The second direction X is a direction pointing to the periphery of the sidewall in the circumferential direction of the first buffer structure 210, and the plane included angle between the second direction X and the first direction Y may be a right angle or an acute angle.
By way of example, the substrate 100 may be a wafer having opposite first and second sides 101, 102. The wafer may be, for example, si, ge, siGe, siC, siGeC, inAs, gaAs, inP or a combination thereof, a multilayer structure of these semiconductor materials, or may be silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeO), or the like, and may further include an epitaxial layer for forming a drift region of a split gate trench power device, for example, an N-type MOSFET device, and the doping types of the wafer and epitaxial layer are N-type.
In addition, the material of the substrate 100 may be formed of other inorganic materials or organic materials. The inorganic material may be, for example, a glass material such as soda lime glass, quartz glass, or sapphire glass, or a metal material such as stainless steel, aluminum, nickel, or various metals or alloys thereof. The organic material may be, for example, polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyethersulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or a combination thereof. The material of the substrate 100 may also be a flexible material. Such as Polyimide (PI).
In one embodiment of the present disclosure, as shown in fig. 1, the first recess 110 does not penetrate the wafer in the thickness direction of the wafer.
Wherein a first recess 110 extending towards the second side 102 may be formed on the first side 101 of the wafer by a Bosch process. The Bosch process realizes etching and side wall passivation by alternately converting etching gas and passivation gas, wherein the etching gas is SF 6, the passivation gas is C 4F8,C4F8, a fluorocarbon polymer can be formed in plasma, the fluorocarbon polymer can be deposited on the surface of silicon to prevent the reaction of fluorine ions and silicon, the etching and passivation process converts each period of 5 s-10 s, the surface of the silicon which is just etched is passivated after short-time isotropic etching, and passivation films can be reserved in the depth direction due to physical sputtering bombardment of ions, so that the etching in the next period can not generate lateral etching, and the etching is only performed along the depth direction through the periodic etching-passivation-etching, thereby meeting the requirement of deeper TSVs.
In the Bosch process, each etching is isotropic due to the mutual conversion of etching and passivation, so that the Bosch process causes a moire effect (scalloping) of etching the sidewall surface as shown in fig. 3, i.e., the sidewalls of the first recess 110 form a plurality of convex structures 120 spaced apart in the depth direction. Wherein the cross section of the bump structure 120 is formed to have a fan-shaped structure (scalep).
In one embodiment of the present disclosure, as shown in fig. 8, since the sidewall of the formed first recess 110 may form a plurality of protrusion structures 120 spaced apart in the depth direction, after the first buffer structure 210 is formed in the first recess 110, the sidewall of the first buffer structure 210 may have a protrusion 2110 thereon, the protrusion 2110 may have a first surface 2111 and a second surface 2112, the first surface 2111 and the second surface 2112 may intersect, and the second buffer structure 220 may extend on the first surface 2111 along the second direction X.
The shape of the protruding portion 2110 matches the shape of the recess formed by the rows of the plurality of protruding structures 120 on the sidewall of the first recess 110, the cross section of the protruding portion 2110 in the first direction Y is triangular or in a shape of a circular segment, or in other irregular shapes, etc., and the shape and the size of the plurality of protruding portions 2110 may be the same or different, which is not limited in the present disclosure.
In one embodiment of the present disclosure, the semiconductor structure further includes a blocking structure 130. As shown in fig. 1, the blocking structure 130 is located on the second surface 2112 of the protrusion 2110, covering a portion of the sidewall of the first buffer layer 210, and the blocking structure 130 is disposed adjacent to the second buffer structure 220.
Specifically, as shown in fig. 4, after the first recess 110 is formed on the substrate 100, ion doping may be added to dope the raised structure 120 at the opening end of the first recess 110, so that the etching attribute of the portion of the raised structure 120 facing the upper layer of the first surface 101 can be changed, so that the modified surface layer portion of the raised structure 120 forms the barrier structure 130, that is, the formed barrier structure 130 is the ion implantation region of the raised structure 120.
The selective etching ratio of the barrier structure 130 formed by the particle doping is different from that of the substrate 100, and due to the different selective etching ratio of the barrier structure 130 to the substrate 100, a portion of the sidewall of the first recess 110 may be etched with the barrier structure 130 as a mask, as shown in fig. 5, to form a second recess 140 recessed into the sidewall of the first recess 110 along the second direction X.
Of course, a mask layer may be directly formed on the surface of the bump structure 120 by a deposition process or the like, and the mask layer may serve as the barrier structure 130. A portion of the sidewall of the first recess is etched through the mask layer to form a second recess 140 recessed into the sidewall of the first recess 110 along the second direction X.
In one embodiment of the present disclosure, after the second recess 140 is formed at the sidewall of the first recess 100, the second buffer structure 220 may be disposed in the second recess 140 through a filling process. By filling the second buffer structure 220 in the second recess 140, the second buffer structure 220 completely fills the second recess 140, so that a gap between the second buffer structure 220 and the substrate 100 is avoided, the effect of releasing stress by the buffer structure is further provided, and the product yield of the semiconductor structure is improved.
As shown in fig. 1, the width of the second buffer structure 220 in the first direction Y gradually increases and then gradually decreases along the second direction X. The second buffer structure 220 is, for example, elliptical in cross section in the plane of the first direction Y and the second direction X, but of course, may also be in a circular segment shape or an irregular shape, which is not limited in this disclosure.
For example, as shown in fig. 1, a plurality of second buffer structures 220 are provided. For example, two, three or more second buffer structures 220 are provided, and of course, only one second buffer structure 220 may be provided, which is not limited in this disclosure. By arranging a plurality of second buffer structures 220, the release of stress by the buffer structures can be further improved, and the stress concentration of the contact structures can be further avoided, but arranging a plurality of second buffer structures 220 can increase the process difficulty, improve the manufacturing cost of the semiconductor structure and reduce the manufacturing efficiency.
When the first recess 110 is formed on the substrate 100 by TVS, the formed protrusion structure 120 is annular on the sidewall of the first recess 110, and then the barrier structure 130 formed by ion doping is also annular. In the first direction Y, the blocking structure 130 is located at two sides of the second buffer structure 220, and the second recess 140 formed by taking the blocking structure 130 as a mask is also annular, so that the second buffer structure 220 filled in the second recess 140 is also annular. The second buffer structure 220 is made to be annular, and stress can be released through the second buffer structure 220 in the circumferential direction of the contact structure, so that the stress release is more uniform, and the problem of stress concentration of the contact structure is further relieved.
In one embodiment of the present disclosure, as shown in fig. 1, the plurality of second buffer structures 220 are uniformly distributed in the first direction Y, i.e., the gaps between the connected second buffer structures 220 are the same in size. By uniformly distributing the plurality of second buffer structures 220 in the first direction Y, uniformity of stress release in the first direction Y can be improved, thereby further improving the effect of stress release on the contact structure. Of course, the plurality of second buffer structures 220 may be distributed uniformly in the first direction Y, or may be distributed non-uniformly in the first direction Y, which is not limited by the disclosure.
In one embodiment of the present disclosure, the plurality of second buffer structures 220 are symmetrically distributed. By symmetrically distributing the plurality of second buffer structures 220, uniformity of stress relief can be improved, thereby further improving the effect of stress relief on the contact structure. Of course, the plurality of second buffer structures 220 may be partially and asymmetrically distributed, or the plurality of second buffer structures 220 may be asymmetrically distributed, which is not limited in this disclosure.
Specifically, as shown in fig. 1, the plurality of second buffer structures 220 are located at an end of the sidewall of the first buffer structure 210 near the first surface 101 in the first direction Y. The plurality of second buffer structures 220 are located at one end of the side wall of the first buffer structure 210 in the first direction Y, so that stress concentration of the contact structure at the end can be relieved to a greater extent, and the effect of releasing the stress of the contact structure at the end is ensured.
Of course, the plurality of second buffer structures 220 are located at one end of the sidewall of the first buffer structure 210 near the second surface 102 in the first direction Y, or the plurality of second buffer structures 220 are uniformly located on the sidewall of the first buffer structure 210 in the first direction Y, or any of the plurality of second buffer structures 220 is distributed on the sidewall of the first buffer structure 210 in the first direction Y, which is not limited in the present disclosure, and by locating the second buffer structures 220 outside the first buffer structure 210, the stress of the TSV can be further released, so that the problem of stress concentration in the TSV in the semiconductor structure is alleviated.
The material of the first buffer structure 210 is an oxide, such as silicon oxide, silicon oxynitride, or silicon nitride, and the material of the second buffer structure 220 is an oxide, such as silicon oxide, silicon oxynitride, or silicon nitride.
The materials of the first buffer structure 210 and the second buffer structure 220 may be the same or different, and the same material of the first buffer structure 210 and the second buffer structure 220 can reduce the manufacturing cost of the semiconductor structure, and the first buffer structure 210 and the second buffer structure 220 may be an integral structure, thereby improving the structural stability of the first buffer structure 210 and the second buffer structure 220.
Specifically, as shown in fig. 1, the contact structure further includes a barrier layer 310. The barrier layer 310 is located between the conductive structure 400 and the first buffer structure 210. The material of the barrier layer 310 may be, for example, tantalum (Ta), titanium (Ti), platinum (Pt), ruthenium (Ru), gold (Au), silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), neodymium (Nd), or a combination of the above materials and compounds thereof.
The material of the conductive structure 400 may be, for example, a metal, a conductive metal oxide, a conductive polymer, a conductive composite material, or a combination thereof. The metal may be platinum, gold, silver, aluminum, chromium, nickel, copper, molybdenum, titanium, magnesium, calcium, barium, sodium, palladium, iron, manganese or a combination thereof, the conductive metal oxide may be InO 2、SnO2, indium Tin Oxide (ITO), fluorine doped tin oxide (FTO), aluminum doped zinc oxide (AZO), gallium doped zinc oxide (GZO) or a combination thereof, the conductive polymer may be polyaniline, polypyrrole, polythiophene, polyacetylene, poly (3, 4-ethylenedioxythiophene)/polystyrene sulfonic acid (PEDOT/PSS) or a combination thereof, the conductive composite material may be a conductive composite material dispersed with carbon black, graphite powder, metal microparticles or the like, and the like.
The semiconductor structure may include a plurality of contact structures, the plurality of contact structures may be distributed on the substrate in an array, and the plurality of contact structures may be identical or partially identical and partially different. The number of the plurality of contact structures and the specific distribution manner on the substrate may be set as desired, which is not limited by the present disclosure.
In one embodiment of the present disclosure, as shown in fig. 14, the first recess 110 penetrates the substrate 100 in the first direction Y. As shown in fig. 13, the semiconductor structure may be thinned from the second side 102 of the substrate, for example, by mechanical chemical polishing (CMP) to achieve BVR (Backside VIA REVEAL, backside hole exposure), as needed, to form a first recess 110 through the substrate 100 so that both ends of the conductive structure 400 are exposed from the first side 101 and the second side 102, respectively. In the process of thinning, the first surface 101 is located at the bottom, and since the second buffer structure 220 is located at the end of the first recess 110 near the first surface 101, the stress of the end of the TSV near the first surface 101 can be further released, so that the problem of stress concentration of the end of the TSV near the first surface 101 in the semiconductor structure in the process of thinning is solved.
The embodiment of the disclosure also provides a method for forming a semiconductor structure, as shown in fig. 2, the method comprises:
step S100, providing a substrate, wherein the substrate comprises a first surface and a second surface which are opposite;
Step 200, forming a first concave part extending along a first direction on a first surface of a substrate, wherein the first direction is from the first surface to a second surface;
step S300, forming a second concave part on the side wall of the first concave part along a second direction, wherein the second direction intersects with the first direction;
Step S400, forming a second buffer structure in the second concave part and forming a first buffer structure in the first concave part;
Step S500, forming a conductive structure in the first buffer structure, wherein the conductive structure extends in a first direction.
The method for forming the semiconductor structure comprises the steps of forming a first concave part extending towards a second surface on a first surface of a substrate, forming a second concave part formed along a second direction on part of the side wall of the first concave part, forming a first buffer structure in the first concave part, forming a second buffer structure in the second concave part, and finally forming a conductive structure in the first buffer structure.
Next, each step in the method for forming a semiconductor structure provided by the present disclosure will be described in detail.
In step S100, a substrate is provided, the substrate including first and second opposing faces.
Specifically, as shown in FIG. 3, a substrate 100 is provided, the substrate 100 may be, for example, a wafer comprising a first side 101 and a second side 102 opposite to each other, the material of the wafer may be Si, ge, siGe, siC, siGeC, inAs, gaAs, inP or a combination thereof, the wafer may also be a multi-layer structure formed of these semiconductor materials, or the like, or be silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), germanium-on-insulator (GeO), or the like. The wafer may also include an epitaxial layer for forming a drift region for the split gate trench power device, for example an N-type MOSFET device, the doping types of the wafer and the epitaxial layer being N-type.
In addition, the material of the substrate may be formed of other inorganic materials or organic materials. The inorganic material may be, for example, a glass material such as soda lime glass, quartz glass, or sapphire glass, or a metal material such as stainless steel, aluminum, nickel, or various metals or alloys thereof. The organic material may be, for example, polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyethersulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or a combination thereof. The material of the substrate 100 may also be a flexible material. Such as Polyimide (PI).
In step S200, a first recess extending in a first direction from a first face to a second face of a substrate is formed on the first face.
In one embodiment of the present disclosure, as shown in fig. 3, the first recess 110 does not penetrate the substrate 100 in the thickness direction of the substrate 100.
Wherein a first recess 110 extending towards the second side 102 may be formed on the first side 101 of the wafer by a Bosch process. The Bosch process realizes etching and side wall passivation by alternately converting etching gas and passivation gas, wherein the etching gas is SF 6, the passivation gas is C 4F8,C4F8, a fluorocarbon polymer can be formed in plasma, the fluorocarbon polymer can be deposited on the surface of silicon to prevent the reaction of fluorine ions and silicon, the etching and passivation process converts each period of 5 s-10 s, the surface of the silicon which is just etched is passivated after short-time isotropic etching, and passivation films can be reserved in the depth direction due to physical sputtering bombardment of ions, so that the etching in the next period can not generate lateral etching, and the etching is only performed along the depth direction through the periodic etching-passivation-etching, thereby meeting the requirement of deeper TSVs.
In the Bosch process, each etching is isotropic due to the mutual conversion of etching and passivation, so that the Bosch process causes a moire effect (scalloping) of etching the sidewall surface as shown in fig. 3, i.e., the sidewalls of the first recess 110 form a plurality of convex structures 120 spaced apart in the depth direction. Wherein the cross section of the bump structure 120 is formed to have a fan-shaped structure (scalep).
For example, a mask structure may be formed on the first surface 101 of the substrate, an opening is formed on the mask structure, a first etching is performed on the substrate through the opening, for example, using etching gas SF 6 to form a groove, then a passivation layer is formed in the formed groove by using passivation gas C 4F8 to protect a sidewall of the groove, then a second etching and passivation process is performed on a bottom of the groove through the opening, after the groove is formed by the second etching process, a bump structure 120 is formed at a connection portion with the groove formed by the first etching process, and the above steps are repeated to realize the alternate process of protecting and etching a sidewall of the groove until a first recess portion penetrating through the wafer is formed, and a number of bump structures 120 corresponding to the number of etching processes are formed on the sidewall of the first recess portion.
The plurality of first recesses 110 may be formed on the semiconductor structure, and the plurality of first recesses 110 may be distributed on the substrate 100 in an array. The number of the plurality of first recesses 110 and the specific distribution pattern on the substrate 100 may be set as desired, which is not limited in this disclosure.
In step S300, a second recess is formed on a sidewall of the first recess along a second direction, the second direction intersecting the first direction.
Specifically, as shown in fig. 3, the first recess upper bump structure 120 formed by the TSV has a fan-shaped structure in a cross section. As shown in fig. 4, after the first recess 110 is formed on the substrate 100, an ion doping may be added to dope the protruding structure 120 at an opening end of the first recess 110, so that etching properties of the protruding structure 120 toward an upper layer of the first surface 101 can be changed, so that the modified surface layer portion of the protruding structure 120 forms the barrier structure 130, and a selective etching ratio of the barrier structure 130 formed by the ion doping and the substrate 100 is different.
The properties of the upper layer on the surface of the protruding structure 120 may be changed by changing the energy and angle of ion implantation, and ion doping of the protruding structure 120 in the target area in the first recess may be implemented, that is, the formed blocking structure 130 is the ion implantation area of the protruding structure 120.
Of course, a mask layer may be directly formed on the surface of the bump structure 120 through a deposition process, etc., where the mask layer is used as the barrier structure 130, and the selective etching ratio of the mask layer and the substrate 100 may meet the etching requirement.
Specifically, as shown in fig. 5, after the first recess 110 is formed on the substrate 100 through the TSV, since the selective etching ratio of the blocking structure 130 formed by the particle doping is different from that of the substrate 100, a portion of the sidewall of the first recess 110 is etched with the blocking structure 130 as a mask, thereby forming the second recess 140. The second recess 140 extends along a second direction X, and the second direction X intersects the first direction Y.
In one embodiment of the present disclosure, as shown in fig. 5, when the first recess 110 does not penetrate the substrate 100 in the thickness direction of the substrate 100, the second recess 140 is located at one end near the opening of the first recess 110.
The barrier structures 130 include a plurality of barrier structures 130, and the sidewalls of the first recess 110 between two adjacent barrier structures 130 are laterally etched. Wherein, the plurality of second buffer structures 220 are formed at one end of the sidewall of the first buffer structure 210 near the first surface 101 in the first direction Y. In the first direction Y, the depth of the area of the first recess 110 where the second recess 140 is formed is not greater than one third of the depth of the first recess 110, and it should be clear to those skilled in the art that providing a larger number of second recesses 140 increases the process difficulty, increases the manufacturing cost of the semiconductor structure and reduces the manufacturing efficiency, and the present disclosure sets the depth of the area of the first recess 110 where the second recess 140 is formed to be not greater than one third of the depth of the first recess 110, which can avoid increasing the manufacturing cost of the semiconductor structure and reducing the manufacturing efficiency on the premise of ensuring a sufficient stress release effect, and of course, the depth of the area of the first recess 110 where the second recess 140 is formed may also be greater than one third of the depth of the first recess 110, which is not limited in the present disclosure.
Of course, the formed plurality of second buffer structures 220 are located at one end of the sidewall of the first buffer structure 210 near the second surface 102 in the first direction Y, or the plurality of second buffer structures 220 are uniformly located on the sidewall of the first buffer structure 210 in the first direction Y, or any of the plurality of second buffer structures 220 is distributed on the sidewall of the first buffer structure 210 in the first direction Y, which is not limited in the present disclosure, and by locating the second buffer structures 220 outside the first buffer structure 210, the stress of the TSV can be further released, thereby reducing the problem of stress concentration in the TSV in the semiconductor structure.
Wherein, the protruding structure 120 formed in the first recess 110 by the Bosch process is ring-shaped, the blocking structure 130 is also ring-shaped formed on the protruding structure 120, and the second recess 140 formed by adjacent two blocking structures 130 is also ring-shaped. Of course, the blocking structures 130 may also have an arc shape of a non-closed structure, and the second recess 140 formed by two adjacent blocking structures 130 also matches the corresponding arc shape of the non-closed structure, which is not limited by the specific shape of the blocking structures in the present disclosure.
In step S400, a second buffer structure is formed in the second recess and a first buffer structure is formed in the first recess.
In one embodiment of the present disclosure, the first buffer structure 210 is of a different material than the second buffer structure 220. When the material of the first buffer structure 210 is different from that of the second buffer structure 220, a second buffer structure is formed in the first recess 110 by filling, then a mask structure having an opening is formed on the first face 101 of the substrate 100, the second buffer structure in the first recess 110 is etched through the mask structure to remove the second buffer structure located outside the second recess 140, thereby forming the second buffer structure 220 in the second recess 140, then the first buffer structure 210 is formed in the first recess 110 by filling, then a mask structure having an opening is formed on the first face 101 of the substrate 100, and the first buffer structure 210 in the first recess 110 is etched through the mask structure in the first direction Y, thereby forming the first buffer structure 210 having the third recess 230 on the side facing away from the inner wall thereof in the second recess 140.
In another embodiment of the present disclosure, the first buffer structure 210 is the same material as the second buffer structure 220. As shown in fig. 6, when the first buffer structure 210 and the second buffer structure 220 are made of the same material, the buffer material is simultaneously filled into the first recess 110 and the second recess 140 through the same filling process to form the buffer initial structure 200, and the buffer initial structure 200 located in the second recess 140 forms the second buffer structure 220. Next, as shown in fig. 7, a mask structure 510 having an opening is formed on the first face 101 of the substrate 100, and as shown in fig. 8, the buffer initiation structure 200 in the first recess 110 is etched in the first direction Y through the mask structure 510, thereby forming a first buffer structure 210 having a third recess 230 on a side facing away from the inner wall thereof in the second recess 140.
By adopting the first buffer structure 210 and the second buffer structure 220 of the same material, one deposition and mask etching processes can be reduced, and thus the manufacturing cost of the semiconductor structure can be reduced. In addition, the first buffer structure 210 and the second buffer structure 220 made of the same material may be formed into an integrated structure, so that the structural stability of the first buffer structure 210 and the second buffer structure 220 is further improved, and further the stress release effect of the first buffer structure 210 and the second buffer structure 220 is improved.
The material of the first buffer structure 210 is an oxide, such as at least one of silicon oxide, silicon oxynitride, and silicon nitride, and the material of the second buffer structure 220 is an oxide, such as at least one of silicon oxide, silicon oxynitride, and silicon nitride.
In one embodiment of the present disclosure, as shown in fig. 3, since the formed sidewall of the first recess 110 may form a plurality of protruding structures 120 spaced apart in the depth direction, as shown in fig. 8, after the first buffer structure 210 is formed in the first recess 110, the first buffer structure 210 may have protruding portions 2110 on the sidewall, the protruding portions 2110 may have a first surface 2111 and a second surface 2112, the first surface 2111 and the second surface 2112 may intersect, and the second buffer structure 220 may extend on the first surface 2111 along the second direction X.
The shape of the protruding portion 2110 matches the shape of the recess formed by the rows of the plurality of protruding structures 120 on the sidewall of the first recess 110, the cross section of the protruding portion 2110 in the first direction Y is triangular or in a shape of a circular segment, or in other irregular shapes, etc., and the shape and the size of the plurality of protruding portions 2110 may be the same or different, which is not limited in the present disclosure.
In step S500, a conductive structure is formed in the first buffer structure, the conductive structure extending in a first direction.
Specifically, as shown in fig. 9, the third recess 230 is filled with a conductive material to form a conductive structure 400. The first buffer structure 210 is disposed between the conductive structure 400 and the sidewalls of the first recess 110 and between the conductive structure and the second buffer structure 220.
In one embodiment of the present disclosure, after forming the first buffer structure 210 and before forming the conductive structure 400, the forming method further includes filling a barrier material in the third recess 230 to form a barrier initiation layer 300, forming a mask structure 520 having a second opening over the barrier initiation layer 300, as shown in fig. 10, etching the barrier initiation layer 300 through the second opening in the first direction Y to form a barrier layer 310 having a fourth recess 320, as shown in fig. 11, and filling a conductive material in the fourth recess 320 to form the conductive initiation structure, as shown in fig. 12.
Specifically, after the semiconductor structure is formed, when the first recess 110 does not penetrate through the substrate 100, as shown in fig. 13, the first surface 101 of the substrate 100 may be disposed on the base 600, and the semiconductor structure may be thinned from the second surface 102 of the substrate 100 as needed, for example, by performing a thinning process using a mechanical chemical polishing (CMP) to achieve BVR (Backside VIA REVEAL, backside hole exposure), as shown in fig. 14, a first recess penetrating through the substrate 100 is formed so that both ends of the conductive initial structure are exposed from the first surface 101 and the second surface 102, respectively, to form the conductive structure 400.
According to the method for forming the semiconductor structure, the blocking structure 1301 is formed on part of the side wall of the first concave part 110 on the substrate 100, the blocking structure 130 is used as a mask to etch part of the side wall of the first concave part 110 to form the second concave part 140, the first buffer structure 210 is formed in the first concave part 110, the second buffer structure 220 is formed in the second concave part 140, finally the conductive structure 400 is formed in the first buffer structure 210, the first buffer structure 210 and the second buffer structure 220 after the conductive structure 400 is formed can serve as a stress buffer layer, so that stress can be released through the second buffer structure 220 when the semiconductor structure is thinned from the second face 102 of the substrate 100, the influence of stress concentration is eliminated, the problem of stress concentration in the semiconductor structure is relieved, and the product yield is improved.
It should be noted that the flow diagrams depicted in the figures are merely exemplary and do not necessarily include all of the elements and operations/steps, nor are they necessarily performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the order of actual execution may be changed according to actual situations.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It is to be understood that the present disclosure is not limited to the precise arrangements and instrumentalities shown in the drawings, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims (18)

1.一种半导体结构，其特征在于，1. A semiconductor structure, characterized in that: 包括：include: 衬底，包括相背的第一面和第二面；A substrate including a first surface and a second surface opposite to each other; 第一缓冲结构，位于所述衬底中，且沿第一方向延伸，所述第一方向为由所述第一面指向所述第二面的方向；第二缓冲结构，位于所述第一缓冲结构的部分侧壁上，且沿第二方向延伸，所述第二方向与所述第一方向相交；A first buffer structure is located in the substrate and extends along a first direction, wherein the first direction is a direction from the first surface to the second surface; a second buffer structure is located on a portion of a sidewall of the first buffer structure and extends along a second direction, wherein the second direction intersects the first direction; 以及as well as 导电结构，位于所述第一缓冲结构中，且沿所述第一方向延伸；A conductive structure, located in the first buffer structure and extending along the first direction; 所述第一缓冲结构的侧壁上具有凸起部，所述凸起部具有第一表面和第二表面，所述第一表面和所述第二表面相交，所述第二缓冲结构在所述第一表面上沿所述第二方向延伸；以及A convex portion is provided on a side wall of the first buffer structure, the convex portion has a first surface and a second surface, the first surface and the second surface intersect, and the second buffer structure extends along the second direction on the first surface; and 阻挡结构，位于所述凸起部的所述第一表面上。A blocking structure is located on the first surface of the protrusion. 2.根据权利要求1所述的半导体结构，其特征在于，2. The semiconductor structure according to claim 1, characterized in that 所述第二缓冲结构位于所述第一缓冲结构上靠近所述第一面的一端。The second buffer structure is located on an end of the first buffer structure close to the first surface. 3.根据权利要求1所述的半导体结构，其特征在于，3. The semiconductor structure according to claim 1, characterized in that: 所述第二缓冲结构在所述第一缓冲结构的周向上呈环形凸起。The second buffer structure is an annular protrusion in the circumferential direction of the first buffer structure. 4.根据权利要求1所述的半导体结构，其特征在于，4. The semiconductor structure according to claim 1, characterized in that: 所述半导体结构包括多个第二缓冲结构，所述多个第二缓冲结构在所述第一方向上均匀分布。The semiconductor structure includes a plurality of second buffer structures, and the plurality of second buffer structures are uniformly distributed in the first direction. 5.根据权利要求1所述的半导体结构，其特征在于，5. The semiconductor structure according to claim 1, characterized in that: 所述第二缓冲结构在所述第一方向上的宽度，沿所述第二方向先逐渐增大，后逐渐减小。The width of the second buffer structure in the first direction first gradually increases and then gradually decreases along the second direction. 6.根据权利要求1所述的半导体结构，其特征在于，6. The semiconductor structure according to claim 1, characterized in that 所述第一缓冲结构与所述第二缓冲结构为一体式结构。The first buffer structure and the second buffer structure are an integrated structure. 7.根据权利要求1所述的半导体结构，其特征在于，7. The semiconductor structure according to claim 1, characterized in that: 所述第一缓冲结构与所述第二缓冲结构的材料不同。The first buffer structure and the second buffer structure are made of different materials. 8.根据权利要求1所述的半导体结构，其特征在于，8. The semiconductor structure according to claim 1, characterized in that: 所述阻挡结构位于所述第二缓冲结构的两侧。The blocking structure is located at two sides of the second buffer structure. 9.根据权利要求1所述的半导体结构，其特征在于，9. The semiconductor structure according to claim 1, characterized in that: 所述阻挡结构在所述第一缓冲结构的周向上呈环状。The blocking structure is annular in a circumferential direction of the first buffer structure. 10.根据权利要求1所述的半导体结构，其特征在于，10. The semiconductor structure according to claim 1, characterized in that: 所述导电结构两端分别从所述第一面和所述第二面露出。Two ends of the conductive structure are exposed from the first surface and the second surface respectively. 11.一种半导体结构的形成方法，其特征在于，11. A method for forming a semiconductor structure, characterized in that: 包括：include: 提供衬底，所述衬底包括相背的第一面和第二面；Providing a substrate, the substrate comprising a first side and a second side opposite to each other; 在所述衬底的所述第一面上沿第一方向形成第一凹陷部，所述第一方向为由所述第一面指向所述第二面的方向；forming a first recessed portion on the first surface of the substrate along a first direction, wherein the first direction is a direction from the first surface to the second surface; 在所述第一凹陷部的部分侧壁上形成阻挡结构；forming a blocking structure on a portion of the sidewall of the first recessed portion; 以所述阻挡结构为掩膜对所述第一凹陷部的部分侧壁进行刻蚀，在所述第一凹陷部的侧壁上沿第二方向形成第二凹陷部，所述第二方向与所述第一方向相交；Using the blocking structure as a mask, etching a portion of the sidewall of the first recessed portion to form a second recessed portion on the sidewall of the first recessed portion along a second direction, wherein the second direction intersects the first direction; 在所述第二凹陷部中形成第二缓冲结构，在所述第一凹陷部中形成第一缓冲结构；forming a second buffer structure in the second recessed portion, and forming a first buffer structure in the first recessed portion; 在所述第一缓冲结构中形成导电结构，所述导电结构在所述第一方向上延伸。A conductive structure is formed in the first buffer structure, and the conductive structure extends in the first direction. 12.根据权利要求11所述的形成方法，其特征在于，12. The forming method according to claim 11, characterized in that: 在所述第一凹陷部的部分侧壁上形成阻挡结构，包括：Forming a blocking structure on a portion of the sidewall of the first recessed portion, comprising: 在所述第一凹陷部的部分侧壁进行离子掺杂，所述离子掺杂区域形成阻挡结构。Ion doping is performed on a portion of the sidewalls of the first recessed portion, and the ion doped region forms a blocking structure. 13.根据权利要求11所述的形成方法，其特征在于，13. The forming method according to claim 11, characterized in that: 在所述第一凹陷部的部分侧壁上形成多个阻挡结构，对相邻两个所述阻挡结构之间的所述第一凹陷部侧壁沿所述第二方向进行侧向刻蚀，形成所述第二凹陷部。A plurality of blocking structures are formed on a portion of the sidewalls of the first recessed portion, and the sidewalls of the first recessed portion between two adjacent blocking structures are laterally etched along the second direction to form the second recessed portion. 14.根据权利要求11所述的形成方法，其特征在于，14. The forming method according to claim 11, characterized in that: 在所述第二凹陷部中填充第二缓冲材料形成第二缓冲结构；在所述第一凹陷部中填充第一缓冲材料形成所述第一缓冲结构。The second recessed portion is filled with a second buffer material to form a second buffer structure; and the first recessed portion is filled with a first buffer material to form the first buffer structure. 15.根据权利要求14所述的形成方法，其特征在于，15. The forming method according to claim 14, characterized in that: 对所述第一缓冲结构沿所述第一方向进行刻蚀，形成具有第一沟槽的第一缓冲结构，在所述第一沟槽中形成所述导电结构。The first buffer structure is etched along the first direction to form a first buffer structure having a first trench, and the conductive structure is formed in the first trench. 16.根据权利要求15所述的形成方法，其特征在于，16. The forming method according to claim 15, characterized in that: 在形成所述第一缓冲结构之后，形成所述导电结构之前，所述形成方法还包括：After forming the first buffer structure and before forming the conductive structure, the forming method further includes: 在所述第一沟槽中填充阻挡材料形成阻挡初始层；Filling a barrier material in the first trench to form a barrier initial layer; 对所述阻挡初始层沿所述第一方向进行刻蚀，形成具有第二沟槽的阻挡层；在所述第二沟槽中形成所述导电结构。The blocking initial layer is etched along the first direction to form a blocking layer having a second groove; and the conductive structure is formed in the second groove. 17.根据权利要求11所述的方法，其特征在于，17. The method according to claim 11, characterized in that 所述第一缓冲结构与所述第二缓冲结构的材料相同；通过同一次填充工艺，在所述第一凹陷部中形成第一缓冲结构，在所述第二凹陷部中形成第二缓冲结构。The first buffer structure and the second buffer structure are made of the same material; the first buffer structure is formed in the first recessed portion, and the second buffer structure is formed in the second recessed portion through a same filling process. 18.根据权利要求11所述的方法，其特征在于，18. The method according to claim 11, characterized in that 在所述第一缓冲结构中形成导电结构；forming a conductive structure in the first buffer structure; 在所述第一缓冲结构中形成导电初始结构；forming a conductive initial structure in the first buffer structure; 从所述第二面进行化学机械抛光，形成两端分别从所述第一面和所述第二面露出的导电结构。Chemical mechanical polishing is performed on the second surface to form a conductive structure with two ends exposed from the first surface and the second surface respectively.
CN202211067996.9A 2022-09-01 2022-09-01 Semiconductor structure and method for forming semiconductor structure Active CN117673033B (en)

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