CN117637831B - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Abstract

The invention discloses a semiconductor device and a method for manufacturing the semiconductor device, the semiconductor device includes: a base; a drift layer of the first conductivity type; a well layer of the second conductivity type; a base layer of the second conductivity type, the base layer and the well layer being arranged in a second direction, the well layer having a depth greater than a depth of the base layer; the first groove is arranged in the transition region, the depth of the first groove extends from the first main surface towards the first direction, the first groove is positioned between the well layer and the base layer in the second direction, and two sides of the first groove in the second direction are respectively contacted with the well layer and the base layer. Therefore, the first groove is arranged between the well layer and the base layer, so that the first groove can prevent the second conductive type dopant of the well layer from diffusing towards the base layer, a curved surface is prevented from being formed in the transition region, the electric field distribution of the transition region can be optimized, the electric field concentration is avoided, the reliability of the semiconductor device can be improved, and the safe working region of the semiconductor device can be increased.

Description

Semiconductor device and method for manufacturing semiconductor device

Technical Field

The present invention relates to the technical field of semiconductor devices, and in particular to a semiconductor device and a method for manufacturing the semiconductor device.

Background Art

Insulated gate bipolar transistor (IGBT) is a high-voltage power device. In practical applications, it often works under relatively harsh conditions such as high voltage, high current, and high frequency, which increases the requirements for the reliability and safe operating area of IGBT devices.

In the related art, the insulated gate bipolar transistor includes an active region, a terminal region and a transition region. To ensure the normal operation and voltage resistance of the transition region, the transition region includes a well layer and a base layer. The depth and concentration of the dopant in the well layer are greater than the depth and concentration of the dopant in the base layer. In this way, the dopant in the well layer will diffuse into the base layer, resulting in the formation of a curved surface between the well layer and the base layer. When the device is in reverse voltage resistance, electric field concentration is prone to occur at this position, and the electric field strength is large, which may cause the safe operating area to become smaller and the reliability of the device to be reduced.

Summary of the invention

The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a semiconductor device with more uniform electric field distribution and higher reliability.

The present invention further provides a method for manufacturing a semiconductor device.

According to an embodiment of the present invention, a semiconductor device comprises: a substrate, the substrate having a first main surface and a second main surface, the first main surface and the second main surface being spaced apart from each other in a first direction; a drift layer of a first conductivity type, the drift layer being arranged on the substrate and located between the first main surface and the second main surface; a well layer of a second conductivity type, the well layer being arranged on a side of the drift layer facing the first main surface corresponding to a portion of a transition region of the semiconductor device, a side of the well layer adjacent to the first main surface constituting a portion of the first main surface, the length of the well layer extending in the second direction and the depth extending in the first direction; a base layer of a second conductivity type, the base layer being arranged on a side of the drift layer facing the first main surface, the length of the base layer extending in the second direction The first main surface of the semiconductor device is provided with a first groove, the first groove is provided with a first groove, the first groove is provided with a second ...

Therefore, by setting the first groove so that the first groove is located between the well layer and the base layer, the first groove can block the second conductive type dopant of the well layer from diffusing toward the base layer, thereby avoiding the formation of a curved surface in the transition zone, optimizing the electric field distribution in the transition zone, and avoiding electric field concentration, thereby improving the reliability of the semiconductor device and increasing the safe operating area of the semiconductor device.

In some examples of the present invention, the depth of the first trench is D1, the depth of the base layer is D2, and D1 and D2 satisfy the relationship: D1 ≥ D2.

In some examples of the present invention, the depth of the well layer is D3, and D1 and D3 satisfy the relationship: D1≤D3.

In some examples of the present invention, the semiconductor device further includes: a carrier storage layer of a first conductivity type, the carrier storage layer being disposed on a side of the drift layer facing the first main surface, the carrier storage layer being located between the drift layer and the base layer, the length of the carrier storage layer extending in a second direction and extending from an active area of the semiconductor device to a transition area of the semiconductor device, the carrier storage layer being located on a side of the first trench in a second direction facing the base layer, the depth of the carrier storage layer extending in the first direction, the depth of the carrier storage layer being D4, and D4, D2 and D1 satisfying the relationship: D4+D2≤D1.

In some examples of the present invention, the semiconductor device also includes a second trench, the depth of the second trench extending from the first main surface toward the first direction to the drift layer, the length of the second trench extending in the second direction and extending from the active area of the semiconductor device to the transition area of the semiconductor device, there are multiple second trenches, and the multiple second trenches are spaced apart in the third direction, and the depth of the second trench is the same as that of the first trench.

A method for manufacturing a semiconductor device according to an embodiment of the present invention is used to manufacture the semiconductor device described above, and the method for manufacturing the semiconductor device comprises: injecting a second conductive type dopant of a first doping concentration into a portion of the drift layer corresponding to the transition zone on a side of the drift layer facing the first main surface to form the well layer of a first depth; injecting a second conductive type dopant of a second doping concentration into a side of the drift layer facing the first main surface to form a base layer of a second depth arranged in a second direction with the well layer, wherein the second doping concentration is less than the first doping concentration, and the second depth is less than the first depth; and etching the first groove extending from the first main surface toward the first direction between the well layer and the base layer.

In some examples of the present invention, the step of etching the first groove extending from the first main surface toward the first direction between the well layer and the base layer includes: spacing the first groove and the ion implantation region of the well layer toward the side boundary of the base layer in the second direction.

In some examples of the present invention, a spacing distance between the first trench and a boundary of the ion implantation region of the well layer facing the base layer on one side in the second direction is D5, and D5 satisfies the relationship: 0.5um≤D5≤2.0um.

In some examples of the present invention, after the step of injecting a second conductive type dopant with a first doping concentration into a portion of the transition zone corresponding to a side of the drift layer facing the first main surface to form the well layer of a first depth, and before the step of injecting a second conductive type dopant with a second doping concentration into a side of the drift layer facing the first main surface to form a base layer of a second depth arranged in a second direction with the well layer, wherein the second doping concentration is less than the first doping concentration and the second depth is less than the first depth, it also includes: injecting a first conductive type dopant into a side of the drift layer facing the first main surface to form a carrier storage layer.

In some examples of the present invention, after the step of injecting a first conductive type dopant on a side of the drift layer facing the first main surface to form a carrier storage layer, the step further includes: using a high temperature gas at a first preset temperature to push the well at high temperature for a first preset time.

In some examples of the present invention, after the step of injecting a second conductive type dopant of a first doping concentration into a portion of the drift layer corresponding to the transition zone on a side of the drift layer facing the first main surface to form the well layer of the first depth, the step further includes: using a high-temperature gas at a second preset temperature to push the well at high temperature for a second preset time.

In some examples of the present invention, after the step of injecting a second conductive type dopant of a second doping concentration on a side of the drift layer facing the first main surface to form a base layer of a second depth arranged in a second direction with the well layer, it also includes: using a high-temperature gas at a third preset temperature to push the well at high temperature for a third preset time.

In some examples of the present invention, after the step of etching the first groove extending from the first main surface toward the first direction between the well layer and the base layer, the semiconductor device further includes: growing an oxide insulating layer on the surface of the well layer, the first trench and the base layer; depositing polysilicon on the surface of the oxide insulating layer and etching the polysilicon; and depositing a dielectric layer on the surface of the polysilicon, the well layer and the base layer.

In some examples of the present invention, while the step of etching the first trench extending from the first main surface toward the first direction between the well layer and the base layer, the semiconductor device also includes: etching a second trench extending from the first main surface toward the first direction to the drift layer, wherein the second trench extends in the second direction and extends from the active area of the semiconductor device to the transition area of the semiconductor device, there are a plurality of second trenches, the plurality of second trenches are spaced apart in the third direction, and the depth of the second trench is the same as that of the first trench.

Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and/or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

FIG. 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention;

FIG2 is a schematic diagram of a layout design of a transition zone according to an embodiment of the present invention;

Fig. 3 is a cross-sectional view of a transition zone along the A-A direction according to an embodiment of the present invention;

Fig. 4 is a cross-sectional view of a transition zone along the B-B direction according to an embodiment of the present invention;

5 is a cross-sectional view of a transition zone along the C-C direction according to an embodiment of the present invention;

6 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

7 is a flow chart of a method for manufacturing a semiconductor device according to another embodiment of the present invention;

FIG8 is a cross-sectional view of a structure 1 according to an embodiment of the present invention;

FIG9 is a cross-sectional view of a structure 2 according to an embodiment of the present invention;

FIG10 is a cross-sectional view of a structure 3 according to an embodiment of the present invention;

FIG11 is a cross-sectional view of a structure 4 according to an embodiment of the present invention;

FIG12 is a cross-sectional view of a structure 5 according to an embodiment of the present invention;

FIG13 is a cross-sectional view of a structure 6 according to an embodiment of the present invention;

FIG. 14 is a cross-sectional view of a structure 7 according to an embodiment of the present invention.

Reference numerals:

100, semiconductor device; 101, active region; 102, transition region; 103, terminal region; 104, gate pad;

10. drift layer; 11. well layer; 12. base layer; 13. carrier storage layer; 14. dielectric layer;

20. first groove; 30. second groove;

40. Oxidation insulating layer; 50. Trench gate polysilicon; 60. Planar gate polysilicon;

70. substrate; 71. first main surface; 72. second main surface.

DETAILED DESCRIPTION

Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

The semiconductor device 100 according to an embodiment of the present invention is described below with reference to FIGS. 1 to 14 . The semiconductor device 100 may adopt a method for manufacturing the semiconductor device 100 . The semiconductor device 100 may be an insulated gate bipolar transistor. In the following description, N and P represent the conductivity type of the semiconductor. In the present invention, the first conductivity type is set to N type and the second conductivity type is set to P type for description.

As shown in FIGS. 1 to 5 , the semiconductor device 100 according to the present invention may mainly include: a substrate 70 , a drift layer 10 of a first conductivity type, a well layer 11 of a second conductivity type, and a base layer 12 of a second conductivity type.

Specifically, the substrate 70 has a first main surface 71 and a second main surface 72, the first main surface 71 and the second main surface 72 are spaced apart from each other in the first direction, the drift layer 10 is disposed in the substrate 70 so that the drift layer 10 is located between the first main surface 71 and the second main surface 72, and a well layer 11 is disposed on a portion of the drift layer 10 facing the first main surface 71 corresponding to the transition region 102 of the semiconductor device 100, a side of the well layer 11 adjacent to the first main surface 71 constitutes a portion of the first main surface 71, a length of the well layer 11 extends in the second direction, a depth of the well layer 11 extends in the first direction, and a portion of the drift layer 10 facing the first main surface 71 is formed on the side of the drift layer 10 facing the first main surface 71. A base layer 12 is also provided on a portion of the transition zone 102 of the semiconductor device 100 on a side facing the first main surface 71. A side of the base layer 12 adjacent to the first main surface 71 constitutes a portion of the first main surface 71. The length of the base layer 12 extends in the second direction and extends from the active area 101 of the semiconductor device 100 to the transition zone 102 of the semiconductor device 100. The depth of the base layer 12 extends in the first direction, so that the base layer 12 and the well layer 11 are arranged in the second direction. In this way, the basic structure of the transition zone 102 of the semiconductor device 100 can be formed to ensure the normal operation of the semiconductor device 100.

Among them, considering that the transition zone 102 of the semiconductor device 100 is located between the terminal area 103 and the active area 101, the structure of the transition zone 102 is relatively complex, and it is easier for voltage breakdown to occur there. By setting the well layer 11, the depth of the well layer 11 is set to be greater than the depth of the base layer 12, and the doping concentration of the second conductive type dopant in the well layer 11 is greater than the doping concentration of the second conductive type dopant in the base layer 12, the electric field distribution in the transition zone 102 can be optimized and the voltage resistance of the transition zone 102 can be improved.

As shown in Figures 2 and 3, the semiconductor device 100 may also include: a first trench 20, the first trench 20 is arranged in the transition zone 102, the depth of the first trench 20 extends from the first main surface 71 toward the first direction, the length of the first trench 20 extends in the third direction, the first trench 20 is located between the well layer 11 and the base layer 12 in the second direction, and the two sides of the first trench 20 in the second direction are respectively in contact with the well layer 11 and the base layer 12, wherein the first direction, the second direction and the third direction are perpendicular to each other.

Specifically, considering that the base layer 12 is spaced apart from the well layer 11 in the second direction, and there is a difference in the doping concentration of the second conductive type dopant in the base layer 12 and the well layer 11, the second conductive type dopant in the well layer 11 will diffuse toward the base layer 12 in the second direction, and due to the difference in depth between the base layer 12 and the well layer 11, a curved surface will be formed at the junction of the base layer 12 and the well layer 11. When the semiconductor device 100 is reversely withstand voltage, electric field concentration will occur at this position with a high electric field intensity, which may cause the safe operating area to become smaller and the reliability of the semiconductor device 100 to be reduced.

A direction perpendicular to both the first direction and the second direction is defined as a third direction. By setting a second trench 30, an oxide insulating layer 40 and polysilicon can be grown in the second trench 30, and the first trench 20 is located between the well layer 11 and the base layer 12 in the second direction. The first trench 20 has two side walls spaced apart in the second direction. The two side walls of the first trench 20 extend in the first direction. By making the two side walls of the first trench 20 in the second direction contact the well layer 11 and the base layer 12 respectively, the first trench 20 can be blocked between the well layer 11 and the base layer 12 in the second direction, thereby blocking the second conductive type dopant in the well layer 11 from diffusing toward the base layer 12, thereby avoiding the formation of a curved surface in the transition region 102. When the semiconductor device 100 withstands reverse voltage, the electric field concentration in the transition region 102 can be avoided, thereby improving the reliability of the semiconductor device 100 and increasing the safe working area of the semiconductor device 100.

Therefore, by setting the first trench 20 so that the first trench 20 is located between the well layer 11 and the base layer 12, the first trench 20 can block the second conductive type dopant of the well layer 11 from diffusing toward the base layer 12, thereby avoiding the formation of a curved surface in the transition zone 102, optimizing the electric field distribution in the transition zone 102, and avoiding electric field concentration, thereby improving the reliability of the semiconductor device 100 and increasing the safe operating area of the semiconductor device 100.

As shown in FIG3 , the depth of the first trench 20 is D1, the depth of the base layer 12 is D2, and D1 and D2 satisfy the relationship: D1 ≥ D2. Specifically, by setting the depth of the first trench 20 to be not less than the depth of the base layer 12, it can be ensured that the first trench 20 completely blocks the base layer 12 in the first direction, thereby more reliably blocking the second conductive type dopant in the well layer 11 from diffusing into the base layer 12, avoiding the generation of a curved surface at the junction of the well layer 11 and the base layer 12, and further improving the reliability of the semiconductor device 100 and increasing the safe operating area of the semiconductor device 100.

Further, in combination with FIG3 , the depth of the well layer 11 is D3, and D1 and D3 satisfy the relationship: D1≤D3. Specifically, the first groove 20 is also provided with a bottom wall, and the bottom wall connects the ends of the two side walls toward the second main surface 72. The curvature of the bottom wall is small, and electric field concentration is prone to occur. By setting the depth of the first groove 20 to be no greater than the depth of the well layer 11, it can be ensured that the well layer 11 wraps at least part of the bottom wall of the first groove 20, so that the electric field near the bottom wall can be optimized to avoid electric field concentration, thereby ensuring the voltage resistance of the semiconductor device 100 and the reliability of the semiconductor device 100.

In combination with Figures 2-5, the semiconductor device 100 may further include: a carrier storage layer 13 of a first conductivity type, the carrier storage layer 13 is arranged on the side of the drift layer 10 facing the first main surface 71, the carrier storage layer 13 is located between the drift layer 10 and the base layer 12, the length of the carrier storage layer 13 extends in the second direction and extends from the active area 101 of the semiconductor device 100 to the transition area 102 of the semiconductor device 100, the carrier storage layer 13 is located on the side of the first trench 20 facing the base layer 12 in the second direction, the depth of the carrier storage layer 13 extends in the first direction, the depth of the carrier storage layer 13 is D4, D4, D2 and D1 satisfy the relationship: D4+D2≤D1.

Specifically, by setting a first conductive type carrier storage layer 13, the carrier storage layer 13 is set on the side of the drift layer 10 facing the first main surface 71, and the length of the carrier storage layer 13 extends in the second direction and extends from the active area 101 of the semiconductor device 100 to the transition area 102 of the semiconductor device 100, so that the carrier storage layer 13 is at least partially located between the drift layer 10 and the base layer 12, and the depth of the carrier storage layer 13 extends in the first direction. In this way, the carrier storage layer 13 plays a role in blocking holes, which can promote the injection of electrons into the drift layer 10, thereby enhancing the conductivity modulation effect, reducing the forward conduction voltage drop of the semiconductor device 100, and improving the normal operation of the semiconductor device 100.

Furthermore, the carrier storage layer 13 is located on the side of the first groove 20 facing the base layer 12 in the second direction. By setting the sum of the depth of the carrier storage layer 13 and the depth of the base layer 12 to be smaller than the depth of the first groove 20, the first groove 20 can completely block the carrier storage layer 13 in the first direction, thereby blocking the first conductive type dopant in the carrier storage layer 13 from diffusing toward the well layer 11, avoiding the carrier storage layer 13 and the well layer 11 from generating a PN junction with a small curvature in the second direction, optimizing the electric field distribution in the transition zone 102, avoiding electric field concentration, and further improving the reliability of the semiconductor device 100 and increasing the safe operating area of the semiconductor device 100.

As shown in Figures 2 and 5, the semiconductor device 100 may further include a second trench 30, the depth of the second trench 30 extends from the first main surface 71 toward the first direction to the drift layer 10, the length of the second trench 30 extends in the second direction, and the second trench 30 extends from the active area 101 of the semiconductor device 100 to the transition area 102 of the semiconductor device 100 in the second direction, and there are multiple second trenches 30, and the multiple second trenches 30 are arranged at intervals in the third direction.

Specifically, by setting the second trench 30, the second trench 30 extends from the first main surface 71 toward the first direction to the drift layer 10, and the second trench 30 is extended in the second direction, by growing the oxide insulating layer 40 in the second trench 30, and depositing polysilicon, and setting the first conductive type emitter layer on both sides of the second trench 30, the second trench 30 can have a conductive channel and have current passing capability.

Furthermore, the second groove 30 can be set to be multiple, and the multiple second grooves 30 are arranged at intervals in the third direction, and when the second groove 30 extends in the second direction, it can extend from the active area 101 to the transition area 102, so that the multiple second grooves 30 can be connected to the gate pad 104 through the planar gate polysilicon 60 of the transition area 102, so that the current can be drawn out to ensure the normal operation of the semiconductor device 100.

Further, the second trench 30 has the same depth as the first trench 20. Specifically, the depth of the first trench 20 can be set to be the same as the depth of the first trench 20, so that the first trench 20 and the second trench 30 can be etched synchronously, thereby simplifying the process flow of the semiconductor device 100.

The method for manufacturing the semiconductor device 100 according to the present invention can be used to manufacture the semiconductor device 100 described above.

In some embodiments of the present invention, in combination with Figure 6, the manufacturing method of the semiconductor device 100 may mainly include the following steps: injecting a second conductive type dopant of a first doping concentration into a portion of the transition zone 102 corresponding to a side of the drift layer 10 facing the first main surface 71 to form a well layer 11 of a first depth; injecting a second conductive type dopant of a second doping concentration into a side of the drift layer 10 facing the first main surface 71 to form a base layer 12 of a second depth arranged in a second direction with the well layer 11, wherein the second doping concentration is less than the first doping concentration, and the second depth is less than the first depth; and etching a first trench 20 extending from the first main surface 71 toward the first direction between the well layer 11 and the base layer 12.

Specifically, when manufacturing the semiconductor device 100, a substrate material may be provided as the drift layer 10 first, and a second conductive type dopant of a first doping concentration may be implanted into a portion of the drift layer 10 corresponding to the transition region 102 on a side facing the first main surface 71 to form a well layer 11 of a first depth, which may improve the withstand voltage capability of the transition region 102, and then a second conductive type dopant of a second doping concentration may be implanted into a side of the drift layer 10 facing the first main surface 71 to form a base layer 12 of a second depth. The second doping concentration is less than the first doping concentration, and the second depth is less than the first depth, that is, the doping concentration of the second conductive type dopant in the well layer 11 is greater than the doping concentration of the second conductive type dopant in the base layer 12, and the depth of the well layer 11 in the first direction is greater than the depth of the base layer 12 in the first direction, so that, under the premise of ensuring the withstand voltage capability of the transition region 102, there will be a depth difference and a concentration difference between the well layer 11 and the base layer 12.

Afterwards, a first trench 20 extending from the first main surface 71 toward the first direction is etched between the well layer 11 and the base layer 12, so that the first trench 20 can block between the well layer 11 and the base layer 12, thereby blocking the second conductive type dopant of the well layer 11 from diffusing toward the base layer 12, thereby improving the reliability of the semiconductor device 100. The first conductive type dopant can be phosphorus ions, and the second conductive type dopant can be boron ions, which are not specifically limited here.

2 , the step of etching a first groove 20 extending from the first main surface 71 toward the first direction between the well layer 11 and the base layer 12 may include: spacing the first groove 20 and the ion implantation region of the well layer 11 toward the side boundary of the base layer 12 in the second direction.

Specifically, after the second conductive type dopant is injected into the portion of the transition zone 102 corresponding to the side of the drift layer 10 facing the first main surface 71, the second conductive type dopant will diffuse in the second direction, that is, the well layer 11 finally formed will exceed the ion implantation region of the well layer 11 in the second direction. By etching the first trench 20 extending from the first main surface 71 toward the first direction between the well layer 11 and the base layer 12, the first trench 20 and the boundary of the ion implantation region of the well layer 11 facing the side of the base layer 12 are spaced apart from each other in the second direction. In this way, a distance can be reserved for the diffusion of the second conductive type dopant in the well layer 11 in the second direction, ensuring that the first trench 20 can be located between the well layer 11 and the subsequent base layer 12, avoiding electric field concentration, and thereby increasing the safe operating area of the semiconductor device 100.

Further, the spacing distance between the first trench 20 and the boundary of the ion implantation region of the well layer 11 facing the side of the base layer 12 in the second direction is D4, and D5 satisfies the relationship: 0.5um≤D5≤2.0um. Specifically, by setting the spacing distance between the first trench 20 and the boundary of the ion implantation region of the well layer 11 facing the side of the base layer 12 in the second direction within a reasonable range, it can not only ensure that the first trench 20 is located between the well layer 11 and the subsequently formed base layer 12, avoiding the formation of a curved surface between the well layer 11 and the base layer 12, but also ensure that the base layer 12 formed after the second conductive type dopant diffuses in the second direction at least partially wraps the bottom wall of the first trench 20, avoiding the electric field concentration in the first trench 20, so that the electric field distribution in the transition region 102 can be optimized, the safe working area of the semiconductor device 100 can be increased, and the reliability of the semiconductor device 100 can be improved.

In some embodiments of the present invention, in combination with Figure 7, after the step of injecting a second conductive type dopant of a first doping concentration into a portion of the transition zone 102 corresponding to a side of the drift layer 10 facing the first main surface 71 to form a well layer 11 of a first depth, and before the step of injecting a second conductive type dopant of a second doping concentration into a side of the drift layer 10 facing the first main surface 71 to form a base layer 12 of a second depth arranged in a second direction with the well layer 11, wherein the second doping concentration is less than the first doping concentration and the second depth is less than the first depth, the manufacturing method of the semiconductor device 100 may further include: injecting a first conductive type dopant into a side of the drift layer 10 facing the first main surface 71 to form a carrier storage layer 13.

Specifically, during the manufacturing process of the semiconductor device 100, after forming the well layer 11 and before forming the base layer 12, a first conductive type dopant can also be injected into the side of the drift layer 10 facing the first main surface 71, so that a carrier storage layer 13 can be formed in the semiconductor device 100, thereby improving the operating performance of the semiconductor device 100.

Furthermore, the carrier storage layer 13 is at least partially located between the drift layer 10 and the base layer 12, and the carrier storage layer 13 and the well layer 11 are spaced apart in the second direction, so that the well layer 11 and the carrier storage layer 13 can also be separated by the first groove 20. The first groove 20 can block the first conductive type dopant in the carrier storage layer 13 from diffusing into the well layer 11, thereby preventing the formation of a PN junction with a small curvature and optimizing the electric field distribution.

Further, in conjunction with FIG. 7 , after the step of implanting the first conductive type dopant on the side of the drift layer 10 facing the first main surface 71 to form the carrier storage layer 13, the method for manufacturing the semiconductor device 100 may further include: using a high temperature gas at a first preset temperature to push the trap at a high temperature for a first preset time, so that the rate and uniformity of the distribution and diffusion of the first conductive type dopant in the substrate can be improved, thereby optimizing the working performance of the carrier storage layer 13 and even the semiconductor device 100, and improving the reliability of the semiconductor device 100. The high temperature gas may be N ₂ , the first preset temperature may be 1150° C., and the first preset time may be 120 min, which are not specifically limited here.

As shown in FIG6 and FIG7, after the step of implanting the second conductive type dopant into the portion of the drift layer 10 corresponding to the transition region 102 on the side facing the first main surface 71 to form the well layer 11, the manufacturing method of the semiconductor device 100 may further include: using a high temperature gas at a second preset temperature to push the well at a high temperature for a second preset time, so that the rate and uniformity of the distribution and diffusion of the second conductive type dopant in the substrate can be improved, thereby optimizing the working performance of the well layer 11 and even the semiconductor device 100, and improving the reliability of the semiconductor device 100. The high temperature gas may be _N2 , the second preset temperature may be 1150°C, and the second preset time may be 80 minutes, which are not specifically limited here.

As shown in FIG6 and FIG7, after the step of injecting a second conductive type dopant with a second doping concentration into the side of the drift layer 10 facing the first main surface 71 to form a base layer 12 of a second depth arranged with the well layer 11 in the second direction, the manufacturing method of the semiconductor device 100 may further include: using a high temperature gas at a third preset temperature to push the well at a high temperature for a third preset time, so that the rate and uniformity of the distribution and diffusion of the second conductive type dopant in the substrate can be improved, thereby optimizing the working performance of the base layer 12 and even the semiconductor device 100, and improving the reliability of the semiconductor device 100. The high temperature gas may be _N2 , the third preset temperature may be 1150°C, and the third preset time may be 80 minutes, which are not specifically limited here.

As shown in Figures 6 and 7, after the step of etching the first groove 20 extending from the first main surface 71 toward the first direction between the well layer 11 and the carrier storage layer 13, the manufacturing method of the semiconductor device 100 may also include: growing an oxide insulating layer 40 on the surface of the well layer 11, the first groove 20 and the base layer 12; depositing polycrystalline silicon on the surface of the oxide insulating layer 40, and etching the polycrystalline silicon; depositing a dielectric layer 14 on the surface of the polycrystalline silicon, the well layer 11 and the base layer 12.

Specifically, after etching the first groove 20 extending from the first main surface 71 toward the first direction between the well layer 11 and the base layer 12, an oxide insulating layer 40 can be further grown on the surface of the well layer 11, the first groove 20 and the carrier storage layer 13, and then polysilicon is deposited on the surface of the oxide insulating layer 40, so that the polysilicon can be located on the surface of the well layer 11, in the first groove 20 and on the surface of the base layer 12, and then the polysilicon is etched to retain the polysilicon located in the first groove 20 to form a trench gate polysilicon 50, and retain part of the polysilicon on the surface of the well layer 11 to form a planar gate polysilicon 60, and then a dielectric layer 14 is deposited on the surface of the polysilicon, the well layer 11 and the base layer 12, so that the dielectric layer 14 can protect the surfaces of the polysilicon, the well layer 11 and the base layer 12, thereby improving the structural reliability of the semiconductor device 100.

As shown in Figures 6 and 7, while etching the first groove 20 extending from the first main surface 71 toward the first direction between the well layer 11 and the base layer, the semiconductor device 100 may also include: etching the second groove 30 extending from the first main surface 71 toward the first direction to the drift layer 10, wherein the second groove 30 extends in the second direction, there are multiple second grooves 30, and the multiple second grooves 30 are arranged at intervals in the third direction, and the second groove 30 and the first groove 20 have the same depth, so that the first groove 20 and the second groove 30 can be formed synchronously, and in subsequent steps, an oxide insulating layer 40 can be grown in the second groove 30 and polysilicon can be deposited, so that the second groove 30 is connected to the gate, thereby simplifying the manufacturing method of the semiconductor device 100 and ensuring the normal operation of the semiconductor device 100.

The following describes the manufacturing method of the semiconductor device 100 by way of example in conjunction with FIG. 3 and FIG. 8 to FIG. 13 :

As shown in FIG8 , a substrate material is provided, wherein the substrate material may be a phosphorus-doped silicon substrate with a resistivity of 25 ohm.cm to form a structure 1 .

As shown in FIG9 , based on structure 1, impurity boron ions are implanted with an energy of 60kev and a dose of 5E13cm ^-2 , and high temperature well driving is performed, wherein the high temperature well driving uses high temperature 1150°C gas N ₂ for 80 minutes to form a well layer 11. Structure 2 is formed.

As shown in FIG10 , based on structure 2, impurity phosphorus ions are implanted with an energy of 200kev and a dose of 5E12cm ^-2 , and high temperature well driving is performed, wherein the high temperature well driving uses high temperature 1150°C gas N ₂ for 120 minutes to form a carrier storage layer 13. Structure 3 is formed.

As shown in FIG11 , on the basis of structure 3 , a first trench 20 is etched to form structure 4 .

As shown in FIG12 , on the basis of structure 4 , gas O ₂ at 1100° C. is injected to generate 0.12 μm thick silicon dioxide as an insulating oxide insulating layer 40 , thereby forming structure 5 .

As shown in FIG13 , based on structure 5 , 0.8 um thick polysilicon is deposited in the first trench 20 and on the flat surface, and the excess polysilicon is etched away to form structure 6 .

As shown in FIG14 , based on structure 6, impurity boron ions are implanted with an energy of 100kev and a dosage of 2E13cm ^-2 , and high temperature well driving is performed, wherein the high temperature well driving uses high temperature 1150°C gas N ₂ for 80 minutes to form a base layer 12 . Structure 7 is formed.

As shown in FIG3 , on the basis of structure 7, 1 μm thick silicon dioxide is deposited as a dielectric layer 14 to form a semiconductor device 100. It should be noted that the semiconductor device 100 provided with a carrier storage layer 13 is taken as an example here, and the specific manufacturing process of the semiconductor device 100 not provided with a carrier storage layer 13 can be obtained in the same way, which will not be described here.

Other structures and operations of the semiconductor device 100 according to the embodiment of the present invention are known to those skilled in the art and will not be described in detail here.

In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims (13)

1. A semiconductor device, comprising: A substrate (70), the substrate (70) having a first main surface (71) and a second main surface (72), the first main surface (71) and the second main surface (72) being spaced apart from each other in a first direction; A drift layer (10) of a first conductivity type, the drift layer (10) being arranged on the substrate (70) and located between the first main surface (71) and the second main surface (72); a well layer (11) of a second conductivity type, the well layer (11) being arranged on a side of the drift layer (10) facing the first main surface (71) corresponding to a portion of a transition region (102) of the semiconductor device (100), a side of the well layer (11) adjacent to the first main surface (71) constituting a portion of the first main surface (71), the length of the well layer (11) extending in the second direction and the depth extending in the first direction; a base layer (12) of a second conductivity type, the base layer (12) being arranged on a side of the drift layer (10) facing the first main surface (71), the length of the base layer (12) extending in a second direction and extending from an active region (101) of the semiconductor device (100) to a transition region (102) of the semiconductor device (100), a side of the base layer (12) adjacent to the first main surface (71) constituting a portion of the first main surface (71), the depth of the base layer (12) extending in the first direction, the base layer (12) and the well layer (11) being arranged in the second direction, the depth of the well layer (11) being greater than the depth of the base layer (12); a first groove (20), the first groove (20) being arranged in the transition region (102), the depth of the first groove (20) extending from the first main surface (71) toward the first direction, the length of the first groove (20) extending in the third direction, the first groove (20) being located between the well layer (11) and the base layer (12) in the second direction, and the two sides of the first groove (20) in the second direction being in contact with the well layer (11) and the base layer (12) respectively, wherein the first direction, the second direction and the third direction are perpendicular to each other; A second trench (30), the depth of the second trench (30) extending from the first main surface (71) toward the first direction to the drift layer (10), the length of the second trench (30) extending in the second direction and extending from the active area (101) of the semiconductor device (100) to the transition area (102) of the semiconductor device (100), the second trench (30) being multiple, the multiple second trenches (30) being arranged at intervals in the third direction, and the second trench (30) and the first trench (20) having the same depth. 2. The semiconductor device according to claim 1, characterized in that the depth of the first trench (20) is D1, the depth of the base layer (12) is D2, and D1 and D2 satisfy the relationship: D1 ≥ D2. 3. The semiconductor device according to claim 2, characterized in that the depth of the well layer (11) is D3, and D1 and D3 satisfy the relationship: D1≤D3. 4. The semiconductor device according to claim 2, characterized in that it further comprises: a carrier storage layer (13) of a first conductivity type, the carrier storage layer (13) being arranged on a side of the drift layer (10) facing the first main surface (71), the carrier storage layer (13) being located between the drift layer (10) and the base layer (12), the length of the carrier storage layer (13) extending in a second direction and extending from an active area (101) of the semiconductor device (100) to a transition area (102) of the semiconductor device (100), the carrier storage layer (13) being located on a side of the first trench (20) facing the base layer (12) in the second direction, the depth of the carrier storage layer (13) extending in the first direction, the depth of the carrier storage layer (13) being D4, and D4, D2 and D1 satisfying the relationship: D4+D2≤D1. 5. A method for manufacturing a semiconductor device, for manufacturing the semiconductor device according to any one of claims 1 to 4, characterized in that it comprises: Implanting a second conductive type dopant with a first doping concentration into a portion of the drift layer (10) corresponding to the transition zone (102) on a side of the drift layer (10) facing the first main surface (71), so as to form the well layer (11) of a first depth; Injecting a second conductive type dopant of a second doping concentration into a side of the drift layer (10) facing the first main surface (71) to form a base layer (12) of a second depth arranged in a second direction with the well layer (11), wherein the second doping concentration is less than the first doping concentration and the second depth is less than the first depth; The first groove (20) extending from the first main surface (71) toward a first direction is etched between the well layer (11) and the base layer (12). 6. The method for manufacturing a semiconductor device according to claim 5, characterized in that the step of etching the first trench (20) extending from the first main surface (71) toward the first direction between the well layer (11) and the base layer (12) comprises: The first trench (20) and the ion implantation region of the well layer (11) are spaced apart from each other in the second direction toward a side boundary of the base layer (12). 7. The method for manufacturing a semiconductor device according to claim 6, characterized in that the spacing distance between the first trench (20) and the boundary of the ion implantation region of the well layer (11) facing the base layer (12) in the second direction is D5, and D5 satisfies the relationship: 0.5um≤D5≤2.0um. 8. The method for manufacturing a semiconductor device according to claim 5, characterized in that after the step of implanting a second conductive type dopant with a first doping concentration into a portion of the drift layer (10) corresponding to the transition region (102) on a side facing the first main surface (71) to form the well layer (11) of a first depth, and before the step of implanting a second conductive type dopant with a second doping concentration into a side facing the first main surface (71) to form a base layer (12) of a second depth arranged with the well layer (11) in a second direction, wherein the second doping concentration is less than the first doping concentration and the second depth is less than the first depth, the method further comprises: A first conductive type dopant is injected into a side of the drift layer (10) facing the first main surface (71) to form a carrier storage layer (13). 9. The method for manufacturing a semiconductor device according to claim 8, characterized in that after the step of injecting a first conductive type dopant on a side of the drift layer (10) facing the first main surface (71) to form a carrier storage layer (13), the method further comprises: A high temperature gas at a first preset temperature is used to push the high temperature trap for a first preset time. 10. The method for manufacturing a semiconductor device according to claim 5, characterized in that after the step of implanting a second conductivity type dopant with a first doping concentration into a portion of the drift layer (10) corresponding to the transition region (102) on a side of the drift layer (10) facing the first main surface (71) to form the well layer (11) of the first depth, the method further comprises: A high temperature gas at a second preset temperature is used to push the high temperature trap for a second preset time. 11. The method for manufacturing a semiconductor device according to claim 5, characterized in that after the step of implanting a second conductive type dopant with a second doping concentration on a side of the drift layer (10) facing the first main surface (71) to form a base layer (12) of a second depth arranged in a second direction with the well layer (11), the method further comprises: A high temperature gas at a third preset temperature is used to push the high temperature trap for a third preset time. 12. The method for manufacturing a semiconductor device according to claim 5, characterized in that after the step of etching the first trench (20) extending from the first main surface (71) toward the first direction between the well layer (11) and the base layer (12), the method further comprises: Growing an oxidized insulating layer (40) on the surfaces of the well layer (11), the first trench (20) and the base layer (12); Depositing polysilicon on the surface of the oxidized insulating layer (40), and etching the polysilicon; A dielectric layer (14) is deposited on the surfaces of the polysilicon, the well layer (11) and the base layer (12). 13. The method for manufacturing a semiconductor device according to claim 5, characterized in that, while the step of etching the first trench (20) extending from the first main surface (71) toward the first direction between the well layer (11) and the base layer (12), it also comprises: Etching a second trench (30) extending from the first main surface (71) toward the first direction to the drift layer (10), wherein the second trench (30) extends in the second direction and extends from the active area (101) of the semiconductor device (100) to the transition area (102) of the semiconductor device (100), there are a plurality of second trenches (30), the plurality of second trenches (30) are spaced apart in the third direction, and the second trench (30) and the first trench (20) have the same depth.