CN117594653A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

Embodiments of the present invention provide a semiconductor device with high channel mobility and a manufacturing method of the semiconductor device. The semiconductor device includes: a first impurity region formed of silicon carbide of the first conductivity type; a drift layer formed of silicon carbide of the first conductivity type; a plurality of body regions formed of silicon carbide of the second conductivity type; a plurality of third Two impurity regions are respectively formed of silicon carbide of the first conductivity type; a plurality of body contact regions are respectively formed of silicon carbide of the second conductivity type; a plurality of gate electrodes are respectively formed inside a plurality of trenches; a plurality of third an electrode layer on each of the plurality of body regions to contact the second impurity region; a second electrode layer formed in the first impurity region; and a plurality of nitride crystal insulating layers formed in the plurality of trenches The interior of each trench and between the gate electrode contains aluminum and nitrogen.

Description

Semiconductor device and manufacturing method thereof

Technical field

The present invention relates to a semiconductor device and a manufacturing method of the semiconductor device.

Background technique

Patent Document 1 discloses a semiconductor device. According to this semiconductor device, the connectivity between the impurity layer and the electrode layer can be suppressed from being reduced.

existing technical documents

patent documents

Patent Document 1: Japanese Patent Application Publication No. 2022-102450

Contents of the invention

However, in the semiconductor device described in Patent Document 1, in the structure of the conventional gate insulating film and the conventional gate insulating film formation method, the base layer (or body region) is insulated from the gate. The interface of the film acts as a defect to introduce a high density of interface energy levels. Therefore, the inherently high channel mobility of silicon carbide is suppressed. As a result, the channel resistance cannot be sufficiently reduced.

The present invention has been completed in order to solve the above-mentioned problems. An object of the present invention is to provide a semiconductor device with high channel mobility and a manufacturing method of the semiconductor device.

The semiconductor device related to the present invention includes: a first impurity region formed of silicon carbide of a first conductivity type; a drift layer disposed on a first surface of the first impurity region, the drift layer being formed of a first conductivity type silicon carbide. formed of silicon carbide; a plurality of body regions provided in the drift layer, the plurality of body regions being respectively formed of silicon carbide of the second conductivity type; a plurality of second impurity regions provided in the plurality of body regions In each body region, the plurality of second impurity regions are respectively formed of silicon carbide of the first conductivity type with an impurity concentration higher than the drift layer; a plurality of body contact regions, in each of the plurality of body regions One body region is surrounded by a second impurity region, and the plurality of body contact regions are respectively formed of silicon carbide of a second conductivity type with an impurity concentration higher than that of the body region; a plurality of gate electrodes, the plurality of gate electrodes are formed Inside a plurality of trenches, the trenches penetrate the body region and the second impurity region between adjacent body regions and reach the drift layer; a plurality of first electrode layers are disposed on the plurality of on each body region and in contact with the second impurity region respectively; a second electrode layer formed on the second surface of the first impurity region; and a plurality of nitride crystal insulating layers formed on the Between the inner surfaces of the plurality of trenches and the gate electrode, the plurality of nitride crystal insulating layers include aluminum and nitrogen.

As one aspect of the present invention, the plurality of nitride crystal insulating layers are respectively formed on the bottom surfaces and side surfaces of the plurality of trenches.

As one aspect of the present invention, the plurality of nitride crystal insulating layers are formed of aluminum and nitrogen.

As one aspect of the present invention, the plurality of nitride crystal insulating layers contain boron.

As one aspect of the present invention, the plurality of nitride crystal insulating layers include at least one of gallium, indium, and scandium.

As one aspect of the present invention, the semiconductor device further includes a plurality of oxide layers disposed inside each of the plurality of trenches and formed between the nitride crystal insulating layer and the gate. between electrodes.

As one aspect of the present invention, the plurality of oxide layers are silicon dioxide layers.

As one aspect of the present invention, the plurality of oxide layers are aluminum oxide layers.

As one aspect of the present invention, the plurality of nitride crystal insulating layers are thicker than the plurality of oxide layers.

As one aspect of the present invention, side surfaces of the plurality of trenches are non-polar surfaces.

The manufacturing method of a semiconductor device according to the present invention includes: a drift layer forming process, forming a drift layer from silicon carbide of the first conductivity type on the first surface of the first impurity region, and the first impurity region is made of silicon carbide of the first conductivity type. The formation of silicon carbide; the body region forming process, forming a plurality of body regions from silicon carbide of the second conductivity type in the drift layer; the second impurity region forming process, in each of the plurality of body regions A plurality of second impurity regions are respectively formed from silicon carbide of the first conductivity type with an impurity concentration higher than that of the drift layer; in the body contact region forming process, each body region of the plurality of body regions is surrounded by a second impurity region. In a surrounding manner, multiple body contact regions are respectively formed by silicon carbide of the second conductivity type with an impurity concentration higher than that of the body region; a trench forming process is between adjacent body regions to penetrate the body region and the second impurity region. To reach the drift layer, a plurality of trenches are formed; a gate electrode forming process includes forming a plurality of gate electrodes inside each of the plurality of trenches; a first electrode layer forming process includes A plurality of first electrode layers are formed on each of the plurality of body regions, and the plurality of first electrode layers are respectively in contact with the second impurity regions; in the second electrode layer forming process, in the first impurity region forming a second electrode layer on the second surface; and a nitride crystal insulating layer forming process, after the trench forming process and before the gate electrode forming process, corresponding to each trench of the plurality of trenches A plurality of nitride crystal insulating layers containing aluminum and nitrogen are respectively formed on the inner surface.

As one aspect of the present invention, the nitride crystal insulating layer forming step includes a step of heteroepitaxially growing the plurality of nitride crystal insulating layers.

As one aspect of the present invention, the method of manufacturing a semiconductor device further includes an annealing step of smoothing the connections between the bottom surfaces and side surfaces of the plurality of trenches after the trench forming step.

As one aspect of the present invention, the nitride crystal insulating layer forming step includes a step of supplying hydrogen as a carrier gas.

As one aspect of the present invention, the nitride crystal insulating layer forming step includes forming the plurality of nitride crystal insulating layers by a MOCVD method or an ALD method.

As one aspect of the present invention, the method of manufacturing a semiconductor device further includes: an oxide layer forming step of forming, respectively, on the plurality of nitride crystal insulating layers inside each of the plurality of trenches. A plurality of oxide layers are formed, and the gate electrode forming step includes a step of forming the plurality of gate electrodes on the plurality of oxide layers inside each of the plurality of trenches.

As one aspect of the present invention, the trench forming step includes forming the plurality of trenches so that side surfaces of the plurality of trenches are non-polar surfaces.

According to the present invention, it is possible to provide a semiconductor device with high channel mobility and a method for manufacturing the semiconductor device.

Description of drawings

FIG. 1 is a longitudinal cross-sectional view of a main part of the semiconductor device in Embodiment 1.

FIG. 2 is a diagram used to explain a method of selecting a nitride crystal insulating layer of the semiconductor device in Embodiment 1. FIG.

FIG. 3 is a flowchart for explaining the method of manufacturing the semiconductor device in Embodiment 1. FIG.

Explanation of reference signs

1: Semiconductor device; 2: Drain layer (first impurity region); 3: Drift layer (epitaxial layer); 4: Body region; 5: Source layer (second impurity region); 6: Body contact region; 7 : Oxide layer; 8: Gate electrode; 9: Interlayer insulating layer; 10: Source electrode layer (first electrode layer); 11: Wiring electrode layer; 12: Drain electrode layer (second electrode layer); 13: Nitride crystal insulating layer.

Detailed ways

The embodiment will be described based on the drawings. In addition, in each figure, the same or equivalent part is attached|subjected with the same symbol. Simplify or omit repeated instructions in this section as appropriate.

Embodiment 1.

FIG. 1 is a longitudinal cross-sectional view of a main part of the semiconductor device in Embodiment 1.

In FIG. 1 , the semiconductor device 1 is a silicon carbide MISFET (Metal Insulator Semiconductor Field Effect Transistor). The semiconductor device 1 is of trench type. The semiconductor device 1 includes a drain layer 2, a drift layer 3 (also called an epitaxial layer), a plurality of body regions 4, a plurality of source layers 5, a plurality of body contact regions 6, a plurality of oxide layers 7, and a plurality of Gate electrode 8 , a plurality of interlayer insulating layers 9 , a plurality of source electrode layers 10 , a wiring electrode layer 11 , a drain electrode layer 12 and a plurality of nitride crystal insulating layers 13 .

It should be noted that in FIG. 1 , only one of the plurality of oxide layers 7 , the plurality of gate electrodes 8 , the plurality of interlayer insulating layers 9 and the plurality of nitride crystal insulating layers 13 is illustrated.

The drain layer 2 serves as a first impurity region and is formed of silicon carbide of the first conductivity type. For example, the drain layer 2 is formed of n ⁺ -type 4H-SiC. For example, the drain layer 2 is formed using nitrogen as an impurity. The drift layer 3 is formed on the first surface (the upper surface in FIG. 1 ) of the drain layer 2 . The drift layer 3 is formed of silicon carbide of the first conductivity type which has a lower impurity concentration than the drain layer 2 . For example, the drift layer 3 is an n ^- type layer. For example, the drift layer 3 is formed on the drain layer 2 by epitaxial growth.

A plurality of body regions 4 are formed in the drift layer 3 . The plurality of body regions 4 are formed of silicon carbide of the second conductivity type. For example, the plurality of body regions 4 are p ^- type layers. For example, the plurality of body regions 4 are formed by ion implantation using aluminum as an impurity. A plurality of source layers 5 are formed in each of the plurality of body regions 4 as second impurity regions. The plurality of source layers 5 are formed of silicon carbide of the first conductivity type that has a higher impurity concentration than the drift layer 3 . For example, the plurality of source layers 5 are n ⁺ -type layers. For example, the plurality of source layers 5 are formed by an ion implantation method using nitrogen as an impurity. A plurality of body contact areas 6 are formed on each of the plurality of body areas 4 . In each of the plurality of body regions 4 , the body contact region 6 is surrounded by the source layer 5 . The plurality of body contact regions 6 are formed of silicon carbide of the second conductivity type with a higher impurity concentration than the plurality of body regions 4 . For example, the plurality of body contact regions 6 are p ⁺ -type layers. For example, the plurality of body contact regions 6 are formed by ion implantation using aluminum as an impurity.

A plurality of oxide layers 7 are formed inside a plurality of trenches T respectively. Each trench T penetrates the body region 4 and the source layer 5 between adjacent body regions 4 to the drift layer 3. For example, the plurality of oxide layers 7 are silicon dioxide layers. For example, the plurality of oxide layers 7 are aluminum oxide layers. For example, the plurality of oxide layers 7 are formed by thermal oxidation. For example, the plurality of oxide layers 7 are formed by a CVD (Chemical Vapor Deposition) method or an ALD (Atomic layer deposition) method. The plurality of gate electrodes 8 are respectively formed on the plurality of oxide layers 7 inside each of the plurality of trenches T. For example, the plurality of gate layers 8 are formed of polysilicon by a CVD method.

The plurality of interlayer insulating layers 9 are formed to cover the plurality of gate electrodes 8 respectively, that is, the plurality of interlayer insulating layers 9 are arranged in one-to-one correspondence with the plurality of gate electrodes 8 . For example, the plurality of interlayer insulating layers 9 are formed by the CVD method. The plurality of source electrode layers 10 are formed corresponding to each of the plurality of body regions 4 . The source electrode layer 10 is formed as a first electrode layer in contact with the source layer 5 . The source electrode layer 10 may also be formed across the body contact 6 . For example, the plurality of source electrode layers 10 are formed by depositing Ni (nickel) or the like by a sputtering method and subjecting the film to heat treatment. For example, the plurality of source electrode layers 10 are formed by depositing Ti (titanium) or the like by a sputtering method. The wiring electrode layer 11 is formed to cover the plurality of source electrode layers 10 . For example, the wiring electrode layer 11 is formed of an aluminum alloy by a sputtering method.

The drain electrode layer 12 is formed on the second surface (lower surface in FIG. 1 ) of the drain electrode layer 2 as a second electrode layer. For example, the drain electrode layer 12 is formed by depositing Ni or the like into a film by a sputtering method and subjecting it to heat treatment.

In this embodiment, a plurality of nitride crystal insulating layers 13 are added. A plurality of nitride crystal insulating layers 13 are formed between the inner surface of each of the plurality of trenches T and the oxide layer 7 . Specifically, a plurality of nitride crystal insulating layers 13 are formed on the bottom surfaces and side surfaces of the trenches T respectively. The total thickness of the plurality of nitride crystal insulating layers 13 ranges from 2 nm to 200 nm. The total thickness of the plurality of oxide layers 7 ranges from 2 nm to 200 nm. The thicknesses of the plurality of nitride crystal insulating layers 13 and the plurality of oxides 7 may be arbitrarily combined within the above range. For example, the plurality of nitride crystal insulating layers 13 are thicker than the plurality of oxide layers 7 . Specifically, for example, the total thickness of the plurality of nitride crystal insulating layers 13 is 80 nm, and the total thickness of the plurality of oxide layers 7 is 3 nm. Alternatively, the total thickness of the plurality of nitride crystal insulating layers 13 is 40 nm, and the total thickness of the plurality of oxide layers 7 is 20 nm. For example, the plurality of nitride crystal insulating layers 13 are thinner than the plurality of oxide layers 7 .

The plurality of nitride crystal insulating layers 13 contain aluminum and nitrogen. For example, the plurality of nitride crystal insulating layers 13 are formed of aluminum and nitrogen only. For example, the plurality of nitride crystal insulating layers 13 contain boron. For example, the plurality of nitride crystal insulating layers 13 contain gallium. For example, the plurality of nitride crystal insulating layers 13 contain indium or scandium.

It should be noted that the bottom surface of the trench T is a polar surface. Specifically, the bottom surface of the trench T is the (0001) Si surface or the (000-1) C surface. The side surfaces of the trench T are non-polar surfaces. Specifically, the side surface of the trench T is the (11-20) A surface, the (1-100) M surface, or the (03-38) surface.

For example, the nitride crystal insulating layer 13 is formed by heteroepitaxial growth using the bottom surface (crystal plane) and side surfaces (crystal plane) of the trench T as growth surfaces, in an environment lower than the homoepitaxial growth temperature of silicon carbide. For example, the nitride crystal insulating layer 13 is formed by a MOCVD (Metal-organic Chemical Vapor Deposition) method or an ALD method using the bottom and side surfaces of the trench T as growth surfaces. For example, the nitride crystal insulating layer 13 is formed in an environment in which hydrogen is supplied as a carrier gas.

Next, a method of selecting the nitride crystal insulating layer 13 will be described using FIG. 2 .

FIG. 2 is a diagram used to explain a method of selecting a nitride crystal insulating layer of the semiconductor device in Embodiment 1. FIG.

In FIG. 2 , regarding the silicon carbide (4H-SiC) and the nitride crystal insulating layer 13 , the band gap, electron affinity, lattice constant a, lattice constant c, number of molecular layers in the c-axis direction, and single molecules are shown. Layer length.

The composition of the nitride crystal insulating layer 13 considers the band gap, electron affinity, lattice constant a, monolayer length, its own band gap, electron affinity, lattice constant a, and monolayer length of silicon carbide (4H-SiC) And selected.

In the case of the trench type semiconductor device 1 , for the bottom surface of the trench T, it is preferable that the difference between the lattice constant a of the nitride crystal insulating layer 13 and the lattice constant a of silicon carbide (4H-SiC) is small, for example, nitride The difference percentage between the lattice constant a of the crystal insulating layer 13 and the lattice constant a of silicon carbide (4H-SiC) is -5% to +5%. In this embodiment, the percentage difference between the two lattice constants a refers to the ratio of the difference between the two lattice constants a to the lattice constant a of silicon carbide, that is, the percentage difference between the two lattice constants a = (Nitride The lattice constant a of the crystal insulating layer 13 - the lattice constant a) of silicon carbide/the lattice constant a of silicon carbide. On the other hand, for the side surface of the trench T, it is preferable that the difference between the monolayer length of the nitride crystal insulating layer 13 and the monolayer length of silicon carbide (4H-SiC) is small, for example, the length of the monomolecule of the nitride crystal insulating layer 13 The percentage difference between the layer length and the monolayer length of silicon carbide (4H-SiC) ranges from -5% to +5%. In this embodiment, the percentage difference in the length of the two monolayers is the ratio of the difference in the length of the two monolayers to the length of the monolayer of silicon carbide, that is, the percentage difference in the length of the two monolayers = (Nitride crystal insulation The monolayer length of layer 13 - the monolayer length of silicon carbide) / the monolayer length of silicon carbide.

As shown in FIG. 2 , the difference between the lattice constant a of aluminum nitride (AlN) and the lattice constant a of silicon carbide (4H-SiC) is small. As shown in Figure 2, the difference percentage between the lattice constant a of aluminum nitride and the lattice constant a of silicon carbide is (0.311-0.307)/0.307=1.3%. The difference between the monolayer length of aluminum nitride (AlN) and that of silicon carbide (4H-SiC) is small. As shown in Figure 2, the difference percentage between the length of the monomolecular layer of aluminum nitride and the length of the monomolecular layer of silicon carbide is (0.249-0.251)/0.251=-0.79%. Therefore, in the first example, aluminum nitride (AlN) is selected as the nitride crystal insulating layer 13 .

The nitride crystal insulating layer 13 may also be selected in such a way that the lattice constant a and the monolayer length of the nitride crystal insulating layer 13 are closer to those of silicon carbide (4H-SiC), respectively. composition. By changing the composition of the nitride crystal insulating layer 13, the band gap, electron affinity, lattice constant a and monomolecular layer length change, sometimes in a manner close to the lattice constant a and monomolecular layer length of silicon carbide (4H-SiC). The composition of the nitride crystal insulating layer 13 is selected in this manner.

For example, a composition in which several percent of boron (B) is added to the nitride crystal insulating layer 13 of the first example is selected as the nitride crystal insulating layer 13 of the second example. In the second example, the doping concentration of boron is, for example, 0.1% to 50%. For example, a composition in which several percent of gallium (Ga) is added to the nitride crystal insulating layer 13 of the first example or the nitride crystal insulating layer 13 of the second example is selected as the nitride crystal insulating layer 13 of the third example. In the third example, the doping concentration of gallium is, for example, 0.1% to 50%. For example, a composition in which several percent of indium (In) is added to any one of the nitride crystal insulating layer 13 of the first example to the nitride crystal insulating layer 13 of the third example is selected as the nitride crystal of the fourth example. Insulating layer 13. In the fourth example, the doping concentration of indium is, for example, 0.1% to 50%. For example, a composition in which several percent of scandium (Sc) is added to any one of the nitride crystal insulating layer 13 of the first to fourth examples is selected as the nitride crystal of the fifth example. Insulating layer 13. In the fifth example, the doping concentration of scandium is, for example, 0.1% to 50%. That is, the nitride crystal insulating layer 13 may only be composed of undoped AlN, or any one or more of B, Ga, In, and Sc may be selected as the dopant to be doped into aluminum nitride (AlN) to form nitrogen. compound crystal insulating layer 13.

The nitride crystal insulating layer 13 may be a combination of multiple material sub-layers, that is, the nitride crystal insulating layer is a stack composed of multiple sub-layers, and the materials of adjacent sub-layers may be the same or different. For example, when aluminum nitride of the first example is used as the nitride crystal insulating layer 13, the nitride crystal insulating layer 13 may be a stacked layer composed of multiple sub-layers whose material is undoped AlN. For example, when the doped aluminum nitride doped with a dopant in any one of the second to fifth examples is used as the nitride crystal insulating layer 13, the nitride crystal insulating layer 13 may be made of multiple materials and be doped AlN. A stack composed of sub-layers, wherein the dopant in the AlN-doped sub-layer is one or more of B, Ga, In and Sc. The materials of the sub-layers in which adjacent materials are doped AlN may be the same or different. For example, the nitride crystal insulating layer 13 may also be formed by combining sub-layers of any one of the materials in the first example and the second to fifth examples, that is, the multiple sub-layers may include multiple sub-layers whose material is undoped AlN. and the plurality of materials are AlN-doped sub-layers, wherein the dopant in the AlN-doped sub-layer is one or more of B, Ga, In and Sc. For example, multiple sublayers can form a superlattice structure.

For example, the thin nitride crystal insulating layer 13 of the first example and the thin nitride crystal insulating layer of another composition may be combined to form a superlattice structure layer as the nitride crystal insulating layer 13 of the sixth example. In the sixth example, the thickness of a single layer in the layer of the superlattice structure is, for example, 1 nm to 10 nm.

For example, the plurality of sub-layers may include a plurality of sub-layers whose material is undoped AlN and a plurality of sub-layers whose material is boron nitride. For example, the thin nitride crystal insulating layer 13 of the first example and a thin layer of boron nitride (BN) may be combined to form a superlattice structure layer as the nitride crystal insulating layer 13 of the seventh example. In the seventh example, the thickness of a single layer in the layer of the superlattice structure is, for example, 1 nm to 10 nm.

Next, a method of manufacturing the semiconductor device 1 will be described using FIG. 3 .

FIG. 3 is a flowchart for explaining the method of manufacturing the semiconductor device in Embodiment 1. FIG.

As shown in FIG. 3 , the semiconductor device 1 undergoes a first impurity region forming process, a drift layer forming process, a body region forming process, a second impurity region forming process, a body contact region forming process, a high-temperature annealing process, a trench forming process, and annealing. manufacturing process, a nitride crystal insulating layer forming process, an oxide layer forming process, a gate electrode forming process, an interlayer insulating layer forming process, a first electrode layer forming process, a wiring electrode layer forming process, and a second electrode layer forming process. .

In step S1, a first impurity region forming step is performed. In the first impurity region forming step, the substrate is formed as the drain layer 2 . Thereafter, in step S2, a drift layer forming process is performed. In the drift layer forming step, an epitaxial layer is formed as the drift layer 3 .

Thereafter, in step S3, a body region forming process is performed. In the body region forming step, a plurality of body regions 4 are formed by ion implantation. Thereafter, in step S4, a second impurity region forming step is performed. In the second impurity region forming process, a plurality of source electrode layers 5 are formed as second impurity regions by an ion implantation method. Thereafter, in step S5, a body contact area forming process is performed. In the body contact region forming process, a plurality of body contact regions 6 are formed by ion implantation. Thereafter, in step S6, a high-temperature annealing process is performed. In the high-temperature annealing process, annealing treatment is performed in a high-temperature environment in order to activate the ion-implanted impurity elements (dopants).

Thereafter, in step S7, a trench forming process is performed. In the trench forming process, a plurality of trenches T are formed by etching. At this time, the non-polar surfaces of the side surfaces are exposed by etching, thereby forming a plurality of trenches T. Thereafter, in step S8, an annealing process is performed. In the annealing process, in the plurality of trenches T, the flatness of the bottom surface and the side surfaces is improved, and the connection between the bottom surface and the side surfaces is smoothed. For example, the annealing process is performed in a silicon gas environment.

Thereafter, in step S9, a nitride crystal insulating layer forming process is performed. In the nitride crystal insulating layer forming process, as an example, a plurality of nitride crystal insulating layers 13 are formed by heteroepitaxial growth using the MOCVD method, for example, a stack of multiple sub-layers is formed. Alternatively, a plurality of crystalline nitride crystal insulating layers 13 are formed by the ALD method. Thereafter, in step S10, an oxide layer forming process is performed. In the oxide layer forming step, a plurality of oxide layers 7 are formed by the CVD method. Thereafter, in step S11, a gate electrode forming process is performed. In the gate electrode forming step, a plurality of gate electrodes 8 are formed.

Thereafter, in step S12, an interlayer insulating layer forming process is performed. In the interlayer insulating layer forming step, the interlayer insulating layer 9 is formed. Thereafter, in step S13, a first electrode layer forming process is performed. In the first electrode layer forming process, a plurality of source electrode layers 10 are formed as the first electrode layers. Thereafter, in step S14, a wiring electrode layer forming process is performed. In the wiring electrode layer forming step, the wiring electrode layer 11 is formed.

Thereafter, in step S15, a second electrode layer forming process is performed. In the second electrode layer forming process, the drain electrode layer 12 is formed as the second electrode layer.

According to Embodiment 1 described above, inside each of the plurality of trenches T, the nitride crystal insulating layer 13 is formed between the inner surface of the trench T and the gate electrode 8 . Nitride crystal insulating layer 13 contains aluminum and nitrogen. Therefore, the interface defect density between the inner surface of the trench T and the nitride crystal insulating layer 13 can be reduced. As a result, channel mobility can be improved.

In addition, a nitride crystal insulating layer 13 is formed on the bottom and side surfaces of the trench T. Therefore, the channel mobility can be improved more reliably.

In addition, the nitride crystal insulating layer 13 is formed of aluminum and nitrogen. Therefore, the nitride crystal insulating layer 13 can be easily formed.

In addition, the nitride crystal insulating layer 13 contains boron. Therefore, the channel mobility can be improved more reliably.

In addition, the nitride crystal insulating layer 13 contains at least one of gallium, indium, and scandium. Therefore, the channel mobility can be improved more reliably.

In addition, inside each of the plurality of trenches T, the oxide layer 7 is formed between the nitride crystal insulating layer 13 and the gate electrode 8 . Therefore, gate leakage current can be suppressed.

In addition, the oxide layer 7 is silicon dioxide. Therefore, the oxide layer 7 can be easily formed.

In addition, the oxide layer 7 is aluminum oxide. Therefore, the oxide layer 7 can be easily formed.

In addition, the nitride crystal insulating layer 13 is thicker than the oxide layer 7 . Therefore, the reliability of the semiconductor device 1 can be improved.

It should be noted that when misfit dislocations are introduced in the nitride crystal insulating layer 13 due to lattice mismatch, the nitride crystal insulating layer 13 may be thinned to a thickness that does not introduce misfit dislocations, and additionally deposit oxide Object level 7 is enough. In this case, the gate leakage current can be suppressed more reliably. As a result, the reliability of the semiconductor device 1 can be improved.

In addition, the side surfaces of the trench T are non-polar surfaces. In this case, in the nitride crystal insulating layer 13 grown heteroepitaxially on the side surface of the trench T, the generation of the piezoelectric field can be suppressed. Therefore, unevenness caused by the piezoelectric field can be suppressed. A high-quality semiconductor device 1 with suppressed performance variation can be obtained.

In addition, the nitride crystal insulating layer 13 is formed by heteroepitaxial growth. The heteroepitaxial growth temperature of nitride is lower than that of silicon carbide (4H-SiC). Furthermore, in the heteroepitaxial growth furnace, oxygen is eliminated. Therefore, it is possible to form a high-quality nitride crystal insulating layer 13 while suppressing oxidation of silicon carbide.

In addition, through the annealing process, the flatness of the bottom surface and the side surfaces of the trench T is improved, and the connection between the bottom surface and the side surfaces of the trench T is smoothed. In this case, the area where the electric field becomes locally high at the boundary between the bottom surface and the side surface of the trench T can be reduced. Therefore, the electric field distribution at the boundary between the bottom surface and the side surface of the trench T can be improved. Can inhibit the occurrence of insulation damage.

In addition, the nitride crystal insulating layer 13 is formed in an atmosphere in which hydrogen is supplied as a carrier gas. Therefore, a high-quality nitride crystal insulating layer 13 can be formed.

In addition, the nitride crystal insulating layer 13 is formed by the MOCVD method or the ALD method. Therefore, a high-quality nitride crystal insulating layer 13 can be formed.

It should be noted that the gate insulating layer may be formed of only the nitride crystal insulating layer 13 without forming the oxide layer 7 . In this case, the process of step S10 in FIG. 3 may be unnecessary.

In addition, the first conductivity type may be p-type and the second conductivity type may be n-type. In this case, the channel mobility can also be improved.

In addition, the semiconductor device 1 may be an IGBT (Insulated Gate Bipolar Transistor). In this case, the drain layer 2 serving as the first impurity region may be a P ⁺ -type collector layer. The source layer 5 serving as the second impurity region may be used as the emitter layer. The source electrode layer 10 as the first electrode layer may be used as the emitter electrode layer. The drain electrode layer 12 as the second electrode layer may be used as the collector layer.

Although some aspects of at least one embodiment have been described, it should be understood that various changes, modifications and improvements will readily occur to those skilled in the art. Such changes, modifications, and improvements are intended to be part of this invention, and are intended to be within the scope of this invention.

It is to be understood that the embodiments of the methods and apparatus described herein are not limited in application to the details of construction and the arrangement of components described in the above description or illustrated in the drawings. The methods and apparatus are capable of other implementations and of being carried out or performed in various ways.

Specific implementation examples are given for purposes of illustration only and are not intended to be limiting.

The expressions and terminology used in the present invention are for the purpose of description and should not be regarded as limiting. The use of "including," "having," "having," "including" and variations thereof herein is meant to include the items listed below and their equivalents and additional items.

References to "or (or)" may be interpreted such that use of any term stated "or (or)" indicates one, more than one and all of the stated terms.

The terms front and back, left and right, top and bottom, up and down, horizontal and vertical, and inside and outside are all for convenience of explanation. This reference is not intended to limit the location or spatial orientation of any of the components of the invention. Therefore, the above description and drawings are exemplary only.

Claims (28)

1. A semiconductor device, comprising:

a first impurity region formed of silicon carbide of a first conductivity type;

a drift layer provided on a first surface of the first impurity region, the drift layer being formed of silicon carbide of a first conductivity type;

a plurality of body regions disposed in the drift layer, the plurality of body regions being formed of silicon carbide of a second conductivity type, respectively;

a plurality of second impurity regions provided in each of the plurality of body regions, the plurality of second impurity regions being formed of silicon carbide of the first conductivity type having an impurity concentration higher than that of the drift layer, respectively;

a plurality of body contact regions surrounded by the second impurity region in each of the plurality of body regions, the plurality of body contact regions being formed of silicon carbide of the second conductivity type having a higher impurity concentration than the body regions, respectively;

a plurality of gate electrodes formed inside a plurality of trenches penetrating the body region and the second impurity region between adjacent body regions to the drift layer;

a plurality of first electrode layers disposed on each of the plurality of body regions and respectively contacting the second impurity regions;

a second electrode layer formed on a second surface of the first impurity region; and

a plurality of nitride crystal insulating layers formed between the inner surfaces of the plurality of trenches and the gate electrode, the plurality of nitride crystal insulating layers including aluminum and nitrogen.

2. The semiconductor device according to claim 1, wherein,

the plurality of nitride crystal insulating layers are respectively formed on bottom surfaces and side surfaces of the plurality of grooves.

3. The semiconductor device according to claim 1, wherein,

the plurality of nitride crystal insulating layers are formed of aluminum and nitrogen.

4. The semiconductor device according to claim 1, wherein,

the plurality of nitride crystal insulating layers include boron.

5. The semiconductor device according to claim 1, wherein,

the plurality of nitride crystal insulating layers contain at least one of gallium, indium, and scandium.

6. The semiconductor device according to any one of claims 1 to 5, wherein,

further comprises: and a plurality of oxide layers disposed inside each of the plurality of trenches and formed between the nitride crystal insulating layer and the gate electrode.

7. The semiconductor device according to claim 6, wherein,

the plurality of oxide layers are silicon dioxide layers.

8. The semiconductor device according to claim 6, wherein,

the plurality of oxide layers are aluminum oxide layers.

9. The semiconductor device according to claim 6, wherein,

the plurality of nitride crystal insulating layers are thicker than the plurality of oxide layers.

10. The semiconductor device according to any one of claims 1 to 4, wherein,

the sides of the plurality of grooves are nonpolar surfaces.

11. A method for manufacturing a semiconductor device, comprising:

a drift layer forming step of forming a drift layer from silicon carbide of the first conductivity type on the first surface of the first impurity region; the first impurity region is formed of silicon carbide of a first conductivity type;

a body region forming step of forming a plurality of body regions from silicon carbide of the second conductivity type in the drift layer;

a second impurity region forming step of forming a plurality of second impurity regions from silicon carbide of the first conductivity type having an impurity concentration higher than that of the drift layer in each of the plurality of body regions;

a body contact region forming step of forming a plurality of body contact regions from silicon carbide of the second conductivity type having an impurity concentration higher than that of the body regions, respectively, in such a manner that each of the plurality of body regions is surrounded by the second impurity region;

a trench forming step of forming a plurality of trenches between adjacent body regions so as to penetrate the body region and the second impurity region and reach the drift layer;

a gate electrode forming step of forming a plurality of gate electrodes in each of the plurality of trenches;

a first electrode layer forming step of forming a plurality of first electrode layers on each of the plurality of body regions, the plurality of first electrode layers being in contact with the second impurity regions, respectively;

a second electrode layer forming step of forming a second electrode layer on a second surface of the first impurity region; and

and a nitride crystal insulating layer forming step of forming a plurality of nitride crystal insulating layers containing aluminum and nitrogen on the inner surface of each of the plurality of trenches, respectively, after the trench forming step and before the gate electrode forming step.

12. The method for manufacturing a semiconductor device according to claim 11, wherein,

the nitride crystal insulating layer forming process includes a process of growing the plurality of nitride crystal insulating layers using a process of heteroepitaxial growth.

13. The method for manufacturing a semiconductor device according to claim 11, wherein,

further comprises: and an annealing step of smoothing the junction between the bottom surfaces and the side surfaces of the plurality of trenches after the trench forming step.

14. The method for manufacturing a semiconductor device according to claim 11, wherein,

the nitride crystal insulating layer forming step includes a step of supplying hydrogen as a carrier gas.

15. The method for manufacturing a semiconductor device according to claim 11, wherein,

the nitride crystal insulating layer forming step includes a step of forming the plurality of nitride crystal insulating layers by an MOCVD method or an ALD method.

16. The method for manufacturing a semiconductor device according to claim 11, wherein,

further comprises: an oxide layer forming step of forming a plurality of oxide layers on the plurality of nitride crystal insulating layers, respectively, in the interior of each of the plurality of trenches;

the gate electrode forming step includes a step of forming the plurality of gate electrodes on the plurality of oxide layers, respectively, inside each of the plurality of trenches.

17. The method for manufacturing a semiconductor device according to any one of claims 11 to 16, wherein,

the groove forming step includes a step of forming the plurality of grooves such that side surfaces of the plurality of grooves are nonpolar surfaces.

18. A semiconductor device, comprising:

a first impurity region which is silicon carbide of a first conductivity type;

a drift layer provided on the first surface of the first impurity region, the drift layer being silicon carbide of a first conductivity type;

a plurality of body regions disposed in the drift layer, the plurality of body regions being silicon carbide of a second conductivity type,

and a second impurity region and a body contact region provided in the body region;

a trench disposed between adjacent body regions and having a bottom surface extending to the drift layer, wherein a gate electrode and a nitride crystal insulating layer are disposed in the trench, the gate electrode is disposed in the trench, the nitride crystal insulating layer is disposed on the bottom surface and the side surface of the trench, the gate electrode is insulated from the body regions and the drift layer, and the nitride crystal insulating layer contains elements Al and N;

a first electrode layer disposed on the surface of the body region and in contact with the second impurity region;

and a second electrode layer provided on a second surface of the first impurity region, the first surface being opposite to the second surface.

19. The semiconductor device according to claim 18, wherein the nitride crystal insulating layer is a stack of a plurality of sublayers of material undoped AlN.

20. The semiconductor device of claim 18, wherein the nitride crystal insulating layer is a stack of a plurality of sub-layers of material doped AlN, wherein dopants In the sub-layers doped AlN are one or more of B, ga, in, and Sc.

21. The semiconductor device of claim 18, wherein the plurality of nitride crystal insulating layers are stacks of a plurality of sub-layers including a plurality of sub-layers of undoped AlN and a plurality of sub-layers of doped AlN, wherein dopants In the sub-layers of doped AlN are one or more of B, ga, in, and Sc.

22. The semiconductor device according to claim 18, wherein the plurality of nitride crystal insulating layers are stacked layers composed of a plurality of sub-layers of undoped AlN and a plurality of sub-layers of BN.

23. The semiconductor device according to claim 18, wherein the plurality of nitride crystal insulating layers are stacked layers composed of a plurality of sub-layers of a material doped with AlN and a plurality of sub-layers of a material doped with BN, wherein a dopant In the sub-layers doped with AlN is one or more of B, ga, in, and Sc.

24. The semiconductor device according to any one of claims 20 to 23, wherein the nitride crystal insulating layer is a superlattice structure.

25. The semiconductor device according to claim 18, wherein an oxide layer is further provided in the trench, the oxide layer being provided between the nitride crystal insulating layer and the gate electrode.

26. The semiconductor device according to claim 25, wherein a material of the oxide layer is silicon oxide or aluminum oxide.

27. The semiconductor device according to claim 18, wherein a side surface of the trench is a nonpolar surface.

28. The semiconductor device according to claim 18, wherein,

the plurality of nitride crystal insulating layers contain at least one of gallium, indium, and scandium.