CN117573453B - A system and method for verifying modular FLASH function - Google Patents
A system and method for verifying modular FLASH function Download PDFInfo
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- CN117573453B CN117573453B CN202311605098.9A CN202311605098A CN117573453B CN 117573453 B CN117573453 B CN 117573453B CN 202311605098 A CN202311605098 A CN 202311605098A CN 117573453 B CN117573453 B CN 117573453B
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Abstract
本申请实施例提供一种用于验证模块化FLASH功能的系统及方法，所述系统包括：待验证模块化FLASH，被配置为执行第一类任务和第二类任务；驱动输入接口模块，被配置为定义多个接口信号并定义对所述多个接口信号进行操作的任务；读写任务配置模块，包括读写任务接口，且被配置为定义对待验证模块化FLASH进行读写操作的读数据任务和写数据任务；信号监控接口模块，被配置定义多个监控信号；测试用例模块，包含多个与待验证模块化FLASH的功能点相对应的测试用例，每个测试用例均包括定向配置参数和随机配置参数。采用本申请实施例每个测试用例都包含有定向配置和随机配置的参数，保证功能的完备性。
The embodiment of the present application provides a system and method for verifying the function of modular FLASH, the system comprising: a modular FLASH to be verified, configured to perform a first type of task and a second type of task; a drive input interface module, configured to define multiple interface signals and define tasks for operating the multiple interface signals; a read-write task configuration module, including a read-write task interface, and configured to define a read data task and a write data task for performing read and write operations on the modular FLASH to be verified; a signal monitoring interface module, configured to define multiple monitoring signals; a test case module, comprising multiple test cases corresponding to the functional points of the modular FLASH to be verified, each test case comprising directional configuration parameters and random configuration parameters. Using the embodiment of the present application, each test case comprises parameters for directional configuration and random configuration to ensure the completeness of the function.
Description
Technical Field
The application relates to the field of digital chip verification, in particular to a system and a method for verifying a modularized FLASH function.
Background
FLASH is a non-volatile memory that is commonly used in embedded systems to store systems, applications, data, and the like. The modern SOC chip uses the embedded FLASH, but as the functional complexity of the SOC chip is higher, the requirements on the FLASH are higher, the traditional embedded FLASH has relatively single function and only has the function of reading, writing and erasing, and the requirements of the complex SOC can not be met, so that the modularized FLASH is generated, and the modularized FLASH integrates the FLASH IP and other special functional modules into a whole, so that the function of reading, writing and erasing is supported, and other customized special functions are also supported.
The traditional embedded FLASH verification is realized by writing different testbench with Verilog HDL language to verify each function of FLASH or writing test cases with assembly language at the SOC system level to verify each function of FLASH, so that the verification of FLASH with relatively fewer traditional functions can be satisfied. However, the inventor of the present application found in research that the conventional FLASH verification method cannot meet the verification requirement of the modularized FLASH.
Disclosure of Invention
The embodiment of the application aims to provide a system and a method for verifying a modularized FLASH function, which are used for organizing each test case in a unified configuration mode, wherein each test case comprises parameters of directional configuration and random configuration, so that the completeness of the function is ensured, and meanwhile, the automatic comparison of general FLASH read-write data and the automatic comparison of special function identification signals are added in each test case, so that the reliability of verification is ensured.
In a first aspect, the embodiment of the application provides a system for verifying functions of a modularized FLASH, the system comprises a modularized FLASH to be verified, a test case base class module and a driving input interface module, wherein the modularized FLASH to be verified is configured to execute a first type task and a second type task, the first type task comprises a data reading task and a data writing task, the second type task comprises tasks except the first type task, the modularized FLASH to be verified comprises a test case base class module configured to create a test case base class, the driving input interface module is configured to define a plurality of interface signals and define a task for operating the plurality of interface signals, the plurality of interface signals are signals corresponding to interfaces connected with input ports, the input ports are data input ports except the data reading and writing function ports of the modularized FLASH to be verified, the read and write task configuration module comprises a data reading task and a data writing task which are configured to define data reading tasks and data writing tasks which are performed on the modularized to be verified, the test case base class module is configured to define a plurality of monitoring signals, the monitoring signals are used for at least comparing function identification signals, the testing signals are configured to be used for obtaining parameters of the test case base class of the test case, and the test case base class of the test case is configured to be random to be tested by the modularized FLASH.
In some embodiments, the read-write task interface is used to define interface signals related to reading data and writing data.
In some embodiments, the test case base class module further comprises a system parameter integration module, a clock generation module, a parameter configuration module and a function operation module, wherein the system parameter integration module comprises clock frequency configuration parameters, modularized FLASH register configuration parameters and function operation parameters and is configured to configure registers of the modularized FLASH to be verified according to the modularized FLASH register configuration parameters, the clock generation module comprises a clock interface and is configured to generate corresponding system clocks according to the clock frequency configuration parameters, the clock interface is used for defining interface signals related to all clocks in the modularized FLASH to be verified, the parameter configuration module is configured to configure orientation parameters and random parameters, and the function operation module is configured to perform corresponding function operation on the modularized FLASH to be verified according to the function operation parameters and automatically compare data with corresponding function identification signals.
In some embodiments, the test case base class module is configured to create objects of the system parameter integration module and the clock generation module, randomize the system parameter integration module at the parameter configuration module, access handles of interfaces corresponding to the drive input interface module, the read-write task configuration module and the signal monitoring interface module for the test case module to use, and define empty virtual tasks corresponding to the functional operation module so that the test case module can add corresponding operations as required.
In some embodiments, the to-be-verified modularized FLASH realizes a function of configuring a relevant register in the to-be-verified modularized FLASH by calling a register configuration task through the system parameter integration module, the to-be-verified modularized FLASH realizes a function of storing and taking out data of the to-be-verified modularized FLASH by calling a data writing task and a data reading task defined by the read-write task configuration module in the function operation module, the to-be-verified modularized FLASH realizes a function relevant to an input port of the to-be-verified modularized FLASH by calling a task defined by the driving input interface module in the function operation module, and the to-be-verified modularized FLASH introduces a relevant function identification signal of the to-be-verified modularized FLASH module into the function operation module through the signal monitoring interface module for comparison.
In some embodiments, each test case adopts a combination of orientation and random on parameter configuration, where the combination of orientation and random includes configuring parameters of the system parameter integration module by the parameter configuration module to generate random clock configuration parameters, and the random clock configuration parameters are used by the clock generation module to generate a random system clock.
In some embodiments, the combining of the orientation and the randomization includes configuring parameters of the system parameter integration module by the parameter configuration module, resulting in orientation and randomization function configuration parameters that may be provided to the system parameter integration module or used by the function operation module to operate the corresponding functions.
In some embodiments, each test case adopts a comprehensive configuration mode in terms of functional operation, wherein the comprehensive configuration mode is that a read data task or a write data task defined by the read-write task configuration module is called by the functional operation module to perform a first type of functional verification operation for the modularized FLASH to be verified, the first type of functional verification operation is read-write data operation, or a port operation task defined by the driving input interface module is called to perform a second type of functional verification operation for the modularized FLASH to be verified, and the second type of functional verification operation comprises encryption and decryption operations.
In some embodiments, the data comparison and the function identification signal comparison are combined on result verification, wherein the combination of the data comparison and the function identification signal comparison comprises the steps of simultaneously calling a data reading task or a data writing task defined by the read-write task configuration module in the function operation module, comparing the data written in and read out, and referring to the function identification signal defined by the signal monitoring interface module to perform target function comparison, wherein the target function comparison is a comparison result corresponding to the second type of function verification operation.
According to a second aspect, some embodiments of the present application provide a method for verifying a modularized FLASH, the method being operated in a system according to the first aspect, the method including that each test case directionally configures a part of parameters of a system parameter integration module in a parameter configuration module according to a function point to be tested, the rest of parameters except the part of parameters are randomly configured, a random system clock is generated through a clock generation module according to the configured parameters and connected to a clock port of the modularized FLASH to be verified, a register of the modularized FLASH to be verified is configured through the system parameter integration module, a port operation task defined by an input interface module is called through a function operation module, a function signal value corresponding to a second type of function verification operation is transmitted to an input port of the modularized FLASH to be verified, the second type of function verification operation is a function except the first type of function verification operation, the first type of function verification operation includes a read data function verification operation and a write data function verification operation, the write data task defined by calling the read data task configuration module writes data to a storage area of the modularized FLASH to be verified, the read data is read by the read data task configuration module and the read data task is compared with the read data of the modularized FLASH to the function to be verified by the modularized FLASH, and the function to be verified by the module is compared with the function interface to the function to be verified by the modularized FLASH.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and should not be considered as limiting the scope, and other related drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is one of the block diagrams of a system for verifying modular FLASH functionality provided by an embodiment of the present application;
FIG. 2 is a block diagram of a test case base class module according to an embodiment of the present application;
Fig. 3 is a system for verifying a modular FLASH in accordance with an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application.
It should be noted that like reference numerals and letters refer to like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
The inventor of the application finds that the test cases written aiming at the traditional embedded FLASH are relatively scattered and lack of systematicness in research, the test cases are relatively obvious direct cases and cannot cover some unexpected application scenes, the test cases lack of completeness in terms of functional coverage, and meanwhile, the test cases lack of reliability in terms of verification results by simultaneously comparing the basic functions of reading, writing and erasing with the results of other special functions. Therefore, conventional FLASH verification cannot meet the verification requirements of the modular FLASH.
Different from the related art, the technical problem to be solved by the embodiment of the application is to provide a modularized FLASH verification system based on UVM, each test case is organized in a unified configuration mode, each test case comprises parameters of directional configuration and random configuration, the completeness of the function is ensured, and meanwhile, the automatic comparison of general FLASH read-write data and the automatic comparison of special function identification signals are added in each test case, so that the reliability of verification is ensured.
For example, a system for verifying a modular FLASH function in some embodiments of the present application includes a test case module, a test case base class module, a drive input interface module, a read-write task configuration module, a signal monitoring interface module, and a modular FLASH to be verified.
Referring to fig. 1, fig. 1 shows a system for verifying a modular FLASH function according to an embodiment of the present application, where the system includes a test case module 100, a test case base class module 110, a driving input interface module 120, a read-write task configuration module 130, a signal monitoring interface module 140, and a modular FLASH 150 to be verified.
The modularized FLASH to be verified is configured to execute a first type of task and a second type of task, wherein the first type of task comprises a data reading task and a data writing task, and the second type of task comprises tasks which are possessed by the modularized FLASH and are other than the first type of task.
And the test case base class module is configured to create a test case base class.
The driving input interface module is configured to define a plurality of interface signals and define tasks for operating the plurality of interface signals, wherein the plurality of interface signals are signals corresponding to interfaces connected by input ports, and the input ports are data input ports of the modularized FLASH to be verified except for read-write data function ports.
That is, the driving input interface module flash_interface of some embodiments of the present application defines some interface signals connected to other input ports of the design to be tested, except for reading and writing data, and task tasks for operating these interface signals, and the input ports associated with the present module can be operated by calling the task of the present module in other places.
And the read-write task configuration module comprises a read-write task interface and is configured to define a read-data task and a write-data task for performing read-write operation on the modularized FLASH to be verified.
That is, the read-write task configuration module ahb _package of some embodiments of the present application includes an interface ahb _interface, and defines a read data task ahb _read () and a write data task ahb _write () that perform read-write operations on the design under test. Interface ahb _interface defines interface signals related to read data and write data, and the read-write data operation can be performed on the interface signals related to the module by calling the read-write data task of the module at other places.
And the signal monitoring interface module is configured to define a plurality of monitoring signals, wherein the monitoring signals are used for at least comparing the function identification signals.
That is, the signal monitoring interface module debug_interface of some embodiments of the present application defines some monitoring signals, and referencing these monitoring signals elsewhere can facilitate the verification system to debug and compare certain function identification signals.
The test case module comprises a plurality of test cases corresponding to the function points of the modularized FLASH to be verified, each test case is obtained based on the test case base of the test case base module, and each test case comprises a directional configuration parameter and a random configuration parameter.
That is, in some embodiments of the present application, the test case module includes a series of test cases corresponding to the design function points to be tested, each of which extends from the test case base class test_base and includes all parts of the test case base class test_base.
The above-described correlation module and verification process are exemplarily described below.
It should be noted that, in some embodiments of the present application, the read-write task interface is used to define interface signals related to reading data and writing data.
In some embodiments of the present application, the test case base class module is configured to create an object of a system parameter integration module and a clock generation module, randomize the system parameter integration module at the parameter configuration module, access a handle of an interface corresponding to the driving input interface module, the read-write task configuration module and the signal monitoring interface module for the test case module to use, define a virtual empty task corresponding to the functional operation module so that the test case module adds corresponding operations as required, wherein the system parameter integration module comprises a clock frequency configuration parameter, a modularized FLASH register configuration parameter and a functional operation parameter, and is configured to configure a register of the modularized FLASH to be verified according to the modularized FLASH register configuration parameter, and the clock generation module comprises a clock interface and is configured to generate a corresponding system clock according to the clock frequency configuration parameter, wherein the clock interface is used for defining interface signals related to all clocks in the modularized to be verified.
In some embodiments of the present application, the test case base class module further includes a parameter configuration module configured to configure the orientation parameter and the random parameter, and a function operation module configured to perform corresponding function operation on the to-be-verified modular FLASH according to the function operation parameter, and automatically compare data (the data is data read from or written to the modular FLASH) with corresponding function identification signals.
That is, as shown in fig. 2, the test case base class module test_base of some embodiments of the present application includes a system parameter integration module 111, a clock generation module 112, a parameter configuration module 113, and a functional operation module 114, where the system parameter integration module flash_cfg includes a clock frequency configuration parameter, a design register configuration parameter, and a functional operation parameter, and configures a register to be designed, the clock generation module clk_generator includes an interface clock_interface, and generates a corresponding system clock according to the clock frequency configuration parameter, interface signals related to all clocks to be designed are defined in the interface clock_interface, the parameter configuration module flash_para_gen configures an orientation parameter and a random parameter, and the functional operation module flash_operation module performs a corresponding functional operation on the design to be designed according to the functional operation parameter, and performs an automatic comparison on data and a corresponding functional identification signal.
The following illustrates the interaction process of the modular FLASH to be verified with the remaining modules.
In some embodiments of the present application, the to-be-verified modular FLASH invokes a register configuration task through the system parameter integration module to implement a function of configuring a relevant register in the to-be-verified modular FLASH, the to-be-verified modular FLASH invokes a data writing task and a data reading task defined by the read-write task configuration module in the functional operation module to implement a function of storing and taking out data of the to-be-verified modular FLASH, the to-be-verified modular FLASH invokes a task defined by the driving input interface module in the functional operation module to implement a function related to an input port of the to-be-verified modular FLASH, and the to-be-verified modular FLASH introduces a relevant function identification signal of the to-be-verified modular FLASH module into the functional operation module through the signal monitoring interface module to perform comparison.
The following describes a system for verifying the functionality of a modular FLASH according to some embodiments of the present application in three stages, respectively.
In some embodiments of the present application, each test case adopts a combination of orientation and random on parameter configuration, where the combination of orientation and random includes configuring parameters of the system parameter integration module by the parameter configuration module to generate random clock configuration parameters, and the random clock configuration parameters are used by the clock generation module to generate a random system clock.
In some embodiments of the present application, the combination of orientation and randomization includes configuring parameters of the system parameter integration module by the parameter configuration module to generate orientation and randomization function configuration parameters that may be provided to the system parameter integration module or used by the function operation module to operate the corresponding functions.
That is, in some embodiments of the present application, each test case adopts a combination of orientation and randomness in parameter configuration, and configures parameters of the system parameter integration module flash_cfg in the parameter configuration module flash_para_gen, for example, generates random clock configuration parameters, sends the random clock configuration parameters to the clock generation module to generate a random system clock, generates orientation and random function configuration parameters, and sends the orientation and random function configuration parameters to the system parameter integration module flash_cfg and the function operation module flash_operation to operate corresponding functions.
In some embodiments of the present application, each test case adopts a comprehensive configuration mode in terms of functional operation, where the comprehensive configuration mode is that a first type of functional verification operation for the modularized FLASH to be verified is performed by calling a read data task or a write data task defined by the read data task configuration module through the functional operation module, where the first type of functional verification operation is a read data operation, or a second type of functional verification operation for the modularized FLASH to be verified is performed by calling a port operation task defined by the driving input interface module, where the second type of functional verification operation includes encryption and decryption operations.
That is, in some embodiments of the present application, each test case adopts a configuration mode that is generally combined with a special function in terms of functional operation, and the read-write data task defined in the read-write task configuration module ahb _package is called by the function operation module flash_operation to perform a general functional operation (i.e., a first type of functional verification operation) of the modularized FLASH, that is, a read-write data operation. And calling a port operation task defined in a drive input interface module flash_interface to perform some special function operations (namely, a second type of function verification operation) of the modularized FLASH, such as encryption and decryption operations.
In some embodiments of the present application, each test case adopts a method of combining data comparison and function identification signal comparison on result verification, where the combination of data comparison and function identification signal comparison includes that a read data task or a write data task defined by the read-write task configuration module is called simultaneously in the function operation module, data written in and read out are compared, and a function identification signal defined by the signal monitoring interface module is referenced to perform target function comparison, where the target function comparison is a comparison result corresponding to the second type of function verification operation.
That is, in some embodiments of the present application, each test case uses a method of combining data comparison and function identification signal comparison in result verification, and invokes the read-write data task defined by the read-write task configuration module ahb _package module in the function operation module flash_operation module at the same time, so as to compare the data written in and read out, and refers to some function identification signals defined by the signal monitoring interface module debug_interface to perform special function comparison.
It is not easy to understand that according to the system for verifying the modularized FLASH provided by the embodiment of the application, the system effectively organizes all the test cases, all application scenes of the design to be tested are covered as much as possible, and all the test cases are automatically compared to obtain more reliable results. Moreover, the debug efficiency is automatically higher than that of the conventional waveform-looking debug mode.
The system for verifying a modular FLASH according to the embodiment of the present application is exemplarily described below with a UVM-based modular FLASH verification system.
For example, as shown in FIG. 3, the system for verifying a modularized FLASH according to an embodiment of the present application includes a test case (as an example of the test case module of FIG. 1), a test case base class module test_base (as an example of the test case base class module of FIG. 1), a drive input interface module flash_interface (as an example of the drive input interface module of FIG. 1), a read/write task configuration module ahb _package (as an example of the read/write task configuration module of FIG. 1), a signal monitor interface module debug_interface (as an example of the signal monitor interface module of FIG. 1), and a design to be tested FLASH due module (as an example of the modularized FLASH to be verified), wherein the test case base class module test_base includes a UVM-based system parameter integration module flash_cfg (as an example of the system parameter integration module of FIG. 2), a clock generation module clk_generator (as an example of the clock generation module of FIG. 2), and a parameter configuration module flash_interface (as an example of the parameter configuration module of FIG. 2).
The system parameter integration module flash_cfg comprises clock frequency configuration parameters, design register configuration parameters to be tested and functional operation parameters, defines a parameter calculation function, is used for calculating individual parameters according to specific requirements, defines a register configuration task, and is used for writing the last configured register configuration parameters into registers of the design module to be tested.
The clock generation module clk_generator comprises an interface clock_interface and a parameter integration module flash_cfg, all clock signals related to the design to be tested are defined in the interface clock_interface, and the interface signals are assigned to clock input port signals corresponding to the design to be tested through continuous assignment statement. And generating a corresponding system clock according to clock frequency configuration parameters in the system parameter integration module flash_cfg, and then sending the corresponding system clock to the design module to be tested through an interface clock_interface.
The parameter configuration module flash_para_gen randomizes the system parameter integration module flash_cfg, adjusts the values of some parameters in the system parameter integration module flash_cfg to target values, and finally calls the parameter calculation function of the system parameter integration module flash_cfg to process the parameters to be calculated.
And the function operation module flash_operation calls corresponding tasks in the driving input interface module flash_interface according to the function operation parameters of the system parameter integration module flash_cfg to configure values for certain input ports of the design to be tested. And calling a read-write data task in a read-write task configuration module ahb _package to write data into a storage area to be designed, read the data, and automatically comparing the read-write data. And (3) carrying out special function point automatic comparison on some function points of the design to be tested by referring to some function identification signals of the signal monitoring interface module debug_interface.
The driving input interface module flash_interface defines some interface signals connected with other input ports of the design to be tested except read-write data and tasks for operating the interface signals, the interface signals are assigned to corresponding input port signals of the design to be tested through continuous assignment statement, and then the corresponding tasks of the module are called to carry out numerical configuration on relevant input ports of the design to be tested according to specific configuration in the function operation module flash_operation.
The read-write task configuration module ahb _package declares an interface ahb _interface and defines a read data task ahb _read () for reading data from the memory area of the design under test. A write data task ahb _write () is defined for writing data to the memory area of the design under test. Interface ahb _interface defines interface signals related to read data and write data, and assigns the interface signals to read-write input port signals corresponding to the design to be tested through continuous assignment statement, and then the read-write data operation can be carried out on the read-write related input port of the design to be tested according to the read-write data task of the module, which is specifically configured in the function operation module flash_operation.
The signal monitoring interface module debug_interface module defines a plurality of monitoring signals, corresponding signals in the design to be tested are assigned to the monitoring signals through continuous assignment statement, and then the monitoring signals are referenced in the function operation module flash_operation, so that the system can be conveniently verified to debug and compare certain function identification signals.
The test case base class module test_base gathers the system parameter integration module flash_cfg, the clock generation module clk_generator, the parameter configuration module flash_para_gen and the function operation module flash_operation together for unified scheduling, firstly creates the entity of the system parameter integration module flash_cfg and the clock generation module clk_generator, then calls the parameter configuration module flash_para_gen in the UVM self-built function building_phase (), calls the register configuration task of the system parameter integration module flash_cfg in the UVM self-built task configuration_phase (), and finally calls the function operation module flash_operation in the UVM self-built task main_phase ().
The test case base class module is configured to create objects of the system parameter integration module flash_cfg and the clock generation module clk_generator. And randomizing a system parameter integration module flash cfg in a parameter configuration module flash_para_gen, and then fine-tuning individual parameters. The handle of the interface corresponding to the drive input interface module flash_interface, the read-write task configuration module ahb _package and the signal monitoring interface module debug_interface is accessed for the test case module to use. And defining a virtual task of a blank corresponding to the flash_operation of the functional operation module so as to facilitate the test case module to add operation details according to specific requirements.
The test case module comprises a series of test cases corresponding to the function points of the design to be tested, each test case is expanded from a test case base module test_base and comprises all parts of the test case base module test_base, each test case carries out directional configuration on individual parameters of a system parameter integration module flash_cfg in a parameter configuration module flash_para_gen module according to the function points to be tested, and other parameters are randomly configured. Then a random system clock is generated through a clock generation module and connected to a clock port of a design to be tested, a register of the design to be tested is configured through a system parameter integration module flash_cfg, a port operation task defined in a function operation module flash_operation call drive input interface module flash_interface is used for transmitting a special function signal value to a corresponding input port of a modularized FLASH, a data writing task defined in a read-write task configuration module ahb _package is called for writing data into a storage area of the modularized FLASH, a data reading task defined in a read-write task configuration module ahb _package is called for reading the data from the storage area of the modularized FLASH to the function operation module flash_operation, the data is compared with the written data (namely, the data which is randomly generated in each test case and accords with a FLASH storage area format is written into the FLASH memory area firstly, and then read out), the specific expression is that the written data is assigned to one variable, the read-out data is assigned to the other variable, the values of the two variables are compared, the written-in the memory area and the data are not required to be read out, and the data is not required to be read out in the theoretical process is the same as the problem of the design to be tested, and the problem is not required to be read out if the data is not read out in the specific process. And transmitting some function identification signals of the design to be tested to a function operation module flash_operation for special function comparison by referring to interface signals defined by a signal monitoring interface module debug_interface.
The design module to be tested flash dut mainly comprises functions of storing and taking out data, functions related to an input port, such as encryption and decryption functions and the like, and functions configured by a register, such as instruction cache, data cache and the like. The register configuration task defined in the system parameter integration module flash_cfg is called to realize the register configuration function related to the design module flash dut to be tested, the data storage and extraction function of the design module flash dut to be tested is realized by calling the data writing task defined by the read-write task configuration module ahb _package and the data reading task in the function operation module flash_operation, and the special function related to the input port of the design module flash dut to be tested is realized by calling the task defined by the drive input interface module flash_interface. And introducing certain function identification signals of the flash dut of the design module to be tested into the flash operation of the function operation module for comparison through the signal monitoring interface module debug_interface.
The specific verification flow based on the verification system of fig. 3 is:
The method comprises the steps of creating a FLASH-like cfg, adding system clock parameters such as clock frequency clk_freq into the FLASH-like cfg, adding register parameters of a design to be tested such as a write enable register, an erase data register, a prefetch instruction enable register and the like, and adding input port configuration parameters such as dividing different encryption area parameters for a FLASH sector. A function set_cfg () is defined in the class flash_cfg, and the partial parameters can be calculated in the function according to the need. Defining a task init_cfg (), after the parameters are completely set, calling a data writing task ahb _write () defined in a read-write task configuration module ahb _package in the task to set the set parameters into a register of a design to be tested.
And secondly, creating an interface clock_interface, and defining all clock signals required by the modularized FLASH in the interface clock_interface.
Creating an interface flash_interface, defining interface signals connected with other input ports of the design to be tested except read-write data and tasks for operating the interface signals in the interface flash_interface, assigning the interface signals to corresponding input port signals of the design to be tested through continuous assignment statement, and then calling the tasks of the module at other places to operate related input ports of the design to be tested.
And step four, an interface ahb _interface is created, the interface ahb _interface defines interface signals related to read data and write data, and the interface signals are assigned to read-write input port signals corresponding to the design to be tested through continuous assignment statement.
Step five, an interface debug_interface is created, and monitoring signals such as interrupt signals are defined in the interface debug_interface. The corresponding signals in the design to be tested are assigned to the monitoring signals through continuous assignment statement, and then the monitoring signals are referenced in other places, so that the verification system can be conveniently debugged and compared with certain function identification signals.
Step six, creating a class clk_generator, declaring a virtual interface clock_interface and a class flash_cfg in the class clk_generator, generating a corresponding clock according to the clock parameters in the class flash_cfg, and then sending a clock signal to a clock port of the design to be tested through the interface clock_interface.
Step seven, creating a package ahb _package, declaring a virtual interface ahb _interface in the package ahb _package, and defining a read data task ahb _read () and a write data task ahb _write () for performing read/write operation on the design to be tested. The data reading and writing task of the module can be called at other places to perform data reading and writing operation on the to-be-tested design. Specifically, the interface signals related to the read-write data in the interface AHB _interface are defined according to the port format of the AHB protocol of AMBA 2.0, and the read-write data task is defined according to the read-write operation timing requirement specified by the AHB protocol of AMBA 2.0.
Creating a top module dut_top, declaring an interface clock_interface, an interface flash_interface, an interface debug_interface and an interface ahb _interface in the top module dut_top, importing a packet ahb _packet, connecting an imaginary interface ahb _interface in the packet ahb _packet with an interface ahb _interface of the top module dut_top, and transmitting the rest interfaces to a class test_base through a config_db mechanism of UVM methodology. And instantiating a flash dut of the design to be tested, and finally, calling a task of an interface flash_interface in an initial block to initialize an input port of the design to be tested.
Step nine, creating a class test_base, declaring class flash_cfg and class clk_generator in the class test_base, and then creating function flash_para_gen (), function flash_para_adj () and task flash_operation (). And receiving the interface sent in the step eight in UVM built-in function build_phase through a config_db mechanism of UVM methodology, creating objects for the class flash_cfg and the class clk_generator, and then calling a function flash_para_gen (). The method comprises the steps of randomizing a class flash_cfg in a function flash_para_gen (), calling the function flash_para_adj (), and finally calling a function set_cfg () in the class flash_cfg to calculate certain parameters. And (3) invoking a task init_cfg () similar to the flash_cfg in the UVM built-in task config_phase, and configuring a register to be designed. And calling task flash_operation () in UVM built-in task main_phase. Specifically, the function flash_para_adj () is a null virtual function and the task flash_operation () is a null virtual task, and an entity needs to be added in the test case to implement a specific function.
Step ten, a test case is created, the test case is expanded from the class test_base and comprises all parts of the class test_base, random part system parameters are adjusted in a function flash_para_adj () of the test case, and the random part system parameters are configured into desired parameter values, such as specific clock frequency, a value of a certain register is designated, and the like. And calling a data writing task defined in a packet ahb _package in task flash_operation () to write data into a storage area of the modularized FLASH, calling a data reading task defined in a packet ahb _package to read the data from the storage area of the modularized FLASH, and comparing the read data with the written data. And calling port operation tasks defined in the interface flash_interface to carry out input port configuration values related to some special functions of the modularized FLASH. Special function comparison is performed by referring to some function identification signals defined by the interface debug_interface.
The verification of the traditional modularized FLASH is based on a test platform testbench built by verilog language at a module level, a corresponding test platform testbench is built for each functional point, each test platform testbench is relatively independent, functions or tasks for verification are written by adopting the idea of hardware logic, parameters cannot be randomly configured, only can be directionally configured, and thus some unexpected scenes cannot be covered, each test platform testbench needs to write some common configurations again and lacks reusability, each test platform testbench lacks structure and has an unclear hierarchy when processing different data, such as clock configuration, register reading and writing, input port signal configuration of design to be tested, and data processing and comparison are all placed in one test platform testbench. The calls of each function and task by each test platform testbench are manually arranged, and because the functions and tasks for multiple data processing are contained in the same test platform testbench, the improper arrangement of the calls of the functions and tasks often occurs, which results in errors of the verification platform and influences the verification efficiency. The verification system based on the UVM modularized FLASH adopts an object-oriented programming idea to create different types of components, then adds corresponding functions and tasks in each component to realize the processing of different types of data, such as the created system parameter component which is used for managing system parameters, the created clock generation component which is used for generating a system clock, each created interface component which is used for transmitting data between a verification platform and a design to be tested, and the created test case component uniformly schedules the components, so that the orientation and the random configuration of the parameters are realized, the structure with better reusability and distinct layers is realized, and due to the characteristic of the automatic execution of the UVM methodology, the different types of processing only need to be correspondingly placed in the different functions and tasks of the self-construction of the UVM methodology, thereby greatly reducing the error rate of the verification platform.
In the conventional UVM-based verification system, because the design to be tested needs to process input data and then output the input data, the output data mostly includes a data generating component UVM _sequence, a data transmitting component UVM _ sequencer, a data driving component UVM _driver, an input data collecting component UVM _monitor, a reference model component UVM _reference, an output data collecting component UVM _monitor and a data comparing component UVM _ scoreboard. The data package required by the design to be tested is generated through the data generating component uvm _sequence, then the data package is transmitted to the data driving component uvm _driver through the data transmitting component uvm _ sequencer, the data driving component uvm _driver drives the received data package to the design to be tested, the input data collecting component uvm _monitor sends data collected from the input end of the design to be tested to the reference model component uvm _reference for processing and then to the data comparing component uvm _ scoreboard, the output data collecting component uvm _monitor sends data collected from the output end of the design to be tested to the data comparing component uvm _ scoreboard, and the data comparing component uvm _ scoreboard compares the two groups of received data. The modularized FLASH core is used for storing and reading data, and is added with some auxiliary functions, and the processing of the data is not involved, so that the modularized FLASH verification system based on UVM does not comprise the common components, but builds a proper verification system according to the characteristics of the modularized FLASH, and the system comprises a system parameter configuration component flash_cfg, a clock generation component clk_generator, various interface components and a base component test_base. The system parameter configuration component flash_cfg generates the configuration of various auxiliary functions of the modularized FLASH, the clock generation component clk_generator generates a system clock, the interface components transmit data, the base component test_base uniformly schedules the system parameter configuration component flash_cfg, the clock generation component clk_generator and the interface components, configures directional and random parameters, compares the stored and read data, and checks the identification signals of the auxiliary functions. Compared with the prior verification system based on UVM, the modularized FLASH verification system based on UVM is generally more simplified and has no loss of completeness.
Compared with the traditional FLASH verification system, the modularized FLASH verification system based on the UVM has the advantages that the hierarchy is clear, the systematicness and the reliability are better considered, and compared with the traditional verification system based on the UVM, the modularized FLASH verification system based on the UVM is more simplified and has no loss of completeness. In addition, the verification system has good expansibility and reusability, and can meet the requirements of relevant verification system upgrading brought by future modularized FLASH upgrading.
The method comprises the steps of carrying out directional configuration on partial parameters of a system parameter integration module according to function points to be tested in a parameter configuration module, carrying out random configuration on the rest parameters except the partial parameters, generating a random system clock according to the configured parameters through a clock generation module, connecting the random system clock to a clock port of a modularized FLASH to be verified, configuring a register of the modularized FLASH to be verified through the system parameter integration module, calling a port operation task defined by an input interface module through a function operation module, transmitting a function signal value corresponding to a second type of function verification operation to an input port of the modularized FLASH to be verified, wherein the second type of function verification operation is a function except the first type of function verification operation of the modularized FLASH, the first type of function verification operation comprises a read data function verification operation and a write data function verification operation, calling a write data task defined by a read data configuration module to write data to a storage area of the modularized FLASH to be verified, calling the write data task defined by the read data task to the modularized FLASH to be verified, and comparing the read data of the read data with the read data of the modularized FLASH to be verified by the function, and comparing the read data of the read data with the function of the modularized FLASH to be verified by the function module.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The apparatus embodiments described above are merely illustrative, for example, of the flowcharts and block diagrams in the figures that illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules in the embodiments of the present application may be integrated together to form a single part, or each module may exist alone, or two or more modules may be integrated to form a single part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. The storage medium includes a U disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, an optical disk, or other various media capable of storing program codes.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and variations will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application. It should be noted that like reference numerals and letters refer to like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
Claims (9)
1. A system for verifying modular FLASH functionality, the system comprising:
The modularized FLASH to be verified is configured to execute a first type of task and a second type of task, wherein the first type of task comprises a data reading task and a data writing task, and the second type of task comprises tasks which are possessed by the modularized FLASH and are other than the first type of task;
the test case base class module is configured to create a test case base class;
The driving input interface module is configured to define a plurality of interface signals and define tasks for operating the plurality of interface signals, wherein the plurality of interface signals are signals corresponding to interfaces connected by input ports, and the input ports are data input ports of the modularized FLASH to be verified except for read-write data function ports;
The read-write task configuration module comprises a read-write task interface and is configured to define a read-data task and a write-data task for performing read-write operation on the modularized FLASH to be verified, wherein the read-write task interface is used for defining interface signals related to read data and write data;
The signal monitoring interface module is configured to define a plurality of monitoring signals, wherein the monitoring signals are used for at least comparing the functional identification signals;
The test case module comprises a plurality of test cases corresponding to the function points of the modularized FLASH to be verified, each test case is obtained based on the test case base of the test case base module, and each test case comprises a directional configuration parameter and a random configuration parameter.
2. The system of claim 1, wherein,
The test case base class module further includes:
The system parameter integration module comprises a clock frequency configuration parameter, a modularized FLASH register configuration parameter and a functional operation parameter and is configured to configure the register of the modularized FLASH to be verified according to the modularized FLASH register configuration parameter;
the clock generation module comprises a clock interface and is configured to generate a corresponding system clock according to the clock frequency configuration parameters, wherein the clock interface is used for defining interface signals related to all clocks in the modularized FLASH to be verified;
A parameter configuration module configured to configure the orientation parameters and the random parameters, and
And the function operation module is configured to perform corresponding function operation on the modularized FLASH to be verified according to the function operation parameters, and automatically compare the data with corresponding function identification signals.
3. The system of claim 2, wherein the test case base class module is configured to:
Creating objects of the system parameter integration module and the clock generation module;
Randomizing the system parameter integration module at the parameter configuration module;
the handle of the interface corresponding to the driving input interface module, the read-write task configuration module and the signal monitoring interface module is connected and led in for the test case module to use;
And defining the empty virtual task corresponding to the functional operation module so that the test case module adds corresponding operation according to the requirement.
4. The system of claim 3, wherein the system comprises,
The to-be-verified modularized FLASH realizes the function of configuring the related registers in the to-be-verified modularized FLASH by calling the register configuration task through the system parameter integration module;
The modularized FLASH to be verified realizes the functions of data storage and extraction of the modularized FLASH to be verified by calling the data writing task and the data reading task defined by the read-write task configuration module in the function operation module;
the modularized FLASH to be verified realizes the functions related to the input ports of the modularized FLASH to be verified by calling the tasks defined by the driving input interface module in the function operation module;
And the modularized FLASH to be verified introduces the relevant function identification signals of the modularized FLASH module to be verified into the function operation module for comparison through the signal monitoring interface module.
5. The system of claim 3, wherein each test case is oriented and randomly combined in a parameter configuration, wherein,
The method for combining orientation and randomization comprises the steps of configuring parameters of the system parameter integration module through the parameter configuration module to generate random clock configuration parameters, wherein the random clock configuration parameters are used for generating a random system clock by the clock generation module.
6. The system of claim 5, wherein the means for combining orientation and randomization comprises configuring parameters of the system parameter integration module by the parameter configuration module to generate orientation and randomization function configuration parameters that can be provided to the system parameter integration module or used by the function operation module to operate the corresponding functions.
7. The system of claim 3, wherein each test case adopts a comprehensive configuration mode in terms of functional operation, the comprehensive configuration mode is that a read data task or a write data task defined by the read-write task configuration module is called by the functional operation module to perform a first type of functional verification operation for the modularized FLASH to be verified, the first type of functional verification operation is read-write data operation, or a port operation task defined by the driving input interface module is called to perform a second type of functional verification operation for the modularized FLASH to be verified, and the second type of functional verification operation comprises encryption and decryption operations.
8. The system of claim 7, wherein each test case is combined with function identification signal comparison in result verification, and the combination of data comparison and function identification signal comparison comprises simultaneously calling a data reading task or a data writing task defined by the read-write task configuration module in the function operation module, comparing the data written in and read out, and referring to the function identification signal defined by the signal monitoring interface module to perform target function comparison, wherein the target function comparison is a comparison result corresponding to the second type of function verification operation.
9. A method for verifying a modular FLASH, operating in a system according to any one of claims 1-8, the method comprising:
Each test case performs directional configuration on partial parameters of the system parameter integration module in the parameter configuration module according to the functional points to be tested, and performs random configuration on other parameters except the partial parameters;
generating a random system clock through a clock generation module according to the configured parameters, and connecting the random system clock to a clock port of the modularized FLASH to be verified;
Configuring a register of the modularized FLASH to be verified through a system parameter integration module, and transferring a function signal value corresponding to a second type of function verification operation to an input port of the modularized FLASH to be verified through a port operation task defined by a function operation module call driving input interface module, wherein the second type of function verification operation is a function of the modularized FLASH except a first type of function verification operation, and the first type of function verification operation comprises a read data function verification operation and a write data function verification operation;
Invoking a data writing task defined by a read-write task configuration module to write data into a storage area of the modularized FLASH to be verified;
Calling a data reading task defined by a data reading task configuration module to read data to be read from a storage area of the modularized FLASH to be verified to a functional operation module, and comparing the data with the written data;
And transmitting part of functional identification signals of the modularized FLASH to be verified to a functional operation module through interface signals defined by the reference signal monitoring interface module to perform corresponding functional comparison to be tested.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111221693B (en) * | 2019-12-31 | 2020-10-27 | 深圳市芯天下技术有限公司 | Verification method, system, device and storage medium for NOR flash configuration module |
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