CN117527636A

CN117527636A - A data processing method, device and storage medium

Info

Publication number: CN117527636A
Application number: CN202311578912.2A
Authority: CN
Inventors: 韩迪; 孙旭; 李永浩; 鄢贵海
Original assignee: Yusur Technology Co ltd
Current assignee: Yusur Technology Co ltd
Priority date: 2023-11-23
Filing date: 2023-11-23
Publication date: 2024-02-06
Anticipated expiration: 2043-11-23
Also published as: CN117527636B

Abstract

The application discloses a data processing method, a device and a storage medium, wherein the method is applied to a DPU device, and comprises the following steps: confirming that the received message is a Bidirectional Forwarding Detection (BFD) message through a hardware analyzer and carrying out bit identification on the BFD message; identifying the BFD message according to the bit identification and sending the BFD message to an Open Virtual Switch (OVS); and receiving BFD session information sent by the OVS according to the BFD message and receiving a BFD control message sent by a network processor NP according to a preset interval. By the method, processing time delay can be reduced, and timeliness and accuracy of fault detection are improved.

Description

Data processing method, device and storage medium

Technical Field

The present invention relates to the field of data processing, and in particular, to a method, an apparatus, and a storage medium for data processing.

Background

In the DPU design, the quick detection of communication faults is accomplished by ECHO BFD of the OVS between different node neighbors. However, due to the fast response nature of ECHO BFD messages, such messages may not be handled in time, resulting in BFD failure. Because if these messages cannot be handled in time, the sender may not be able to accurately determine the status of the connection, and thus cannot repair the failure correctly.

Disclosure of Invention

The embodiment of the application provides a data processing method, which reduces processing time delay and improves timeliness and accuracy of fault detection.

In a first aspect, a method for data processing is provided, which is applied to a DPU device, the method comprising the steps of:

confirming that the received message is a Bidirectional Forwarding Detection (BFD) message through a hardware analyzer and carrying out bit identification on the BFD message;

identifying the BFD message according to the bit identification and sending the BFD message to an Open Virtual Switch (OVS);

and receiving BFD session information sent by the OVS according to the BFD message and receiving a BFD control message sent by a network processor NP according to a preset interval. .

Through the steps, the problems that the analysis and the identification of the BFD message are not timely enough in the current DPU-based implementation and the processing time delay caused by the processing of the ECHO BFD message by software is large can be solved. The DPU can rapidly process BFD messages and establish control messages of BFD session in a hardware marking mode, processing time delay is reduced, and timeliness and accuracy of fault detection are improved. Meanwhile, through cooperation optimization with the OVS, the flexibility and reliability of network connection can be further enhanced.

With reference to the first aspect, in certain implementations of the first aspect, the method further includes: and the hardware analyzer analyzes through a layered protocol, and performs bit identification on the BFD message.

With reference to the first aspect, in certain implementations of the first aspect, the method further includes:

each stage of processing module of the hardware analyzer is added with 2 32bits of flags register, analyzes the layering protocol based on the message content, and carries out 1 setting operation on the corresponding bits.

With reference to the first aspect, in certain implementations of the first aspect, the method includes:

and determining whether the message is a BFD message or not through the mark of the flags register.

With reference to the first aspect, in certain implementations of the first aspect, the method further includes: and storing an initialization session from the OVS in a hash table manner in a data unloading engine DOE, and setting an initialization state as down.

and when the NP receives the BFD echo message responded by the opposite terminal, setting the state as up, and if no message is received within the configuration time interval, setting the state as down.

In a second aspect, the present application provides a data processing apparatus comprising a memory and a processor; the memory is coupled to the processor; the memory is used for storing computer program codes, and the computer program codes comprise computer instructions; wherein the computer instructions, when executed by the processor, cause the data processing apparatus to perform the data processing method as in the first aspect.

The apparatus in the second aspect may be a chip, the processor may be implemented by hardware or may be implemented by software, and when implemented by hardware, the processor may be a logic circuit, an integrated circuit, or the like; when implemented in software, the processor may be a general-purpose processor, implemented by reading software code stored in a memory, which may be integrated in the processor, or may reside outside the processor, and exist separately.

In a third aspect, the present application provides a processor comprising: input circuit, output circuit and processing circuit. The processing circuit is configured to receive a signal via the input circuit and transmit a signal via the output circuit, such that the processor performs the method of the first aspect.

In a fourth aspect, the present application provides a computer program product comprising: a computer program (which may also be referred to as code, or instructions) which, when executed, causes a computer to perform the method of the first aspect.

In a fifth aspect, the present application provides a computer readable storage medium storing a computer program (which may also be referred to as code, or instructions) which, when run on data processing apparatus, causes the data processing apparatus to perform the method of the first aspect described above.

Drawings

FIG. 1 is a schematic flow chart of a data processing method provided in an embodiment of the present application;

FIG. 2 is a diagram of a network architecture according to an embodiment of the present application;

FIG. 3 is a flowchart of a method for sending bfd control messages to detect link status and update bfd session according to an embodiment of the present application;

fig. 4 is a schematic diagram of session information provided in an embodiment of the present application;

fig. 5 is a schematic block diagram of a data processing apparatus according to the embodiment of the present application.

Detailed Description

For the purpose of making apparent the objects, technical solutions and advantages of the present invention, the present invention will be further described in detail with reference to the following examples and the accompanying drawings, wherein the exemplary embodiments of the present invention and the descriptions thereof are for illustrating the present invention only and are not to be construed as limiting the present invention. Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise. "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b, and c may represent: a, or b, or c, or a and b, or a and c, or b and c, or a, b and c. Wherein a, b and c can be single or multiple respectively. The relevant description relating to network element a sending a message, information or data to network element B and network element B receiving a message, information or data from network element a is intended to illustrate to which network element the message, information or data is intended for, and not to limit whether it is sent directly between them or indirectly via other network elements. The descriptions of "when … …", "in the case of … …", "if" and "if" etc. all refer to the corresponding processing that the device will perform under some objective condition, are not limited in time, nor do they require that the device must have a judging action in its implementation, nor are they meant to imply other limitations.

In addition, the architecture and the service scenario described in the embodiments of the present application are for more clearly describing the technical solution of the embodiments of the present application, and do not constitute a limitation on the technical solution provided in the embodiments of the present application, and those skilled in the art can know that, with the evolution of the architecture and the appearance of a new service scenario, the technical solution provided in the embodiments of the present application is equally applicable to similar technical problems.

The following are abbreviations for some terms in this application and full Chinese and English designations: DPU (Data Processing Unit ), OVS (Open vSwitch, open virtual switch), BFD (Bidirectional Forwarding Detection, bi-directional forwarding detection), DOE (Data Offload Engine ), ETH (Ethernet, ethernet), VLAN (Virtual Local Area Network ), IPV4 (Internet Protocol Version 4, internet protocol version 4), IPV6 (Internet Protocol Version, internet protocol version 6), UDP (User Datagram Protocol ), session, parser (parser).

In DPU designs, the different nodes need to communicate in some way to ensure that the data is properly transferred throughout the system. To achieve this, it is necessary to use a software called OVS (Open vSwitch), which is an open source virtual switch that can provide management and monitoring of network connections.

BFD is a network protocol that is directed to providing a fast connection state detection and notification mechanism. By bidirectional detection, BFD is able to independently discover changes in network connections, such as link failures or node downtime, in real time. The basic principle involves sending control messages periodically, which contain critical information about the connection status, such as sequence numbers and peer IP addresses. The key feature of BFD is its extremely short messaging interval, typically on the order of milliseconds, to ensure that faults are detected quickly and timely action is taken. BFD describes changes in connection state, including initialization, start and stop states, by a defined state machine. The flexible protocol can be widely applied to a plurality of fields such as a data center network, a wide area network, a mobile network and the like so as to improve the stability and the reliability of the network, and is particularly suitable for scenes requiring low delay and rapid fault detection. BFD is a lightweight, fast-response protocol that provides an efficient failure detection and notification mechanism for the network, ensuring the stability of the network connection.

In the DPU design, the BFD ECHO of the OVS is used for completing the rapid detection of communication faults among different node neighbors. ECHO BFD is a special message used to confirm whether the connection between the sender and the receiver is still valid. If the sender does not receive a response to such a message within a certain time, it will consider the connection to have been broken and then take appropriate action to fix the problem.

However, due to the fast response nature of ECHO BFD messages, such messages may not be handled in time, resulting in BFD failure. Because if these messages cannot be handled in time, the sender may not be able to accurately determine the status of the connection, and thus cannot repair the failure correctly.

Fig. 1 is a schematic flow chart of a method 100 of data processing provided herein. The method 100 includes at least some of the following:

s201, confirming that the received message is a Bidirectional Forwarding Detection (BFD) message through a hardware analyzer and carrying out bit identification on the BFD message;

in one embodiment, the hardware parser in the DPU is able to identify BFD messages because these messages are encapsulated with a specific identification at the time of transmission. In the BFD protocol, the message has a special field that identifies the type of message. The hardware parser will first check the value of this field after receiving the message. If the value of this field indicates that the message is a BFD message, then the hardware burst will perform special processing on this message, for example, set a specific bit to mark this message as a BFD message.

In other possible implementations, the hardware parser performs deep parsing on the network traffic through a deep packet inspection technology, so that messages of various protocols, including BFD messages, can be identified. The technology can analyze the network flow packet by packet, identify the feature codes and field information of various protocols, and judge the type of the message.

After the message enters the DPU, the BFD message is rapidly identified by a bit identification mode of the hardware parser. Hardware parser is a hardware component specifically designed to parse network messages, and can use specific bit identifiers to quickly identify BFD messages. The identification may be a predetermined flag or field for indicating that the message is a BFD message. In this way, the DPU can quickly identify and process BFD messages without relying on software parsing and identification.

The following is a way of identifying BFD messages by the hardware parser:

each stage of processing module of the programmable Parser pipeline is added with 2 32bits of flags (registers) to carry out logic of arbitrary bit 1; the processing module can analyze the layered protocol and mark the layered protocol to a certain extent, and the bit mark of each layered protocol is not limited to 2bits because the processing module can be combined and linked, so that more marks can be provided through combination.

Each processing module can be 1 for any bit, namely, the same bit or operation of a plurality of layered protocols can be realized.

The message is marked by adding marking logic on the Parser pipeline of the DPU. Therefore, BFD messages and other layered protocols can be identified and analyzed more quickly, and the speed and efficiency of data processing are improved.

Fig. 2 is a diagram of a network structure, in which, in the network structure shown in fig. 2, BFD packets are parsed layer by layer from an ETH node, and the parsing paths thereof will advance in the feasible direction of the arrow in fig. 2, and corresponding parsing actions will be executed every time a node passes. The bit marking capability of the programmable Parser provides the marking capability of each node on FIG. 2. Such as parsing a BFD message with VLAN encapsulation, ETH- > VLAN1- > IPV4- > UDP- > BFD.

S102, identifying the BFD message according to the bit identifier and sending the BFD message to an Open Virtual Switch (OVS);

the DPU sends the identified BFD message to the OVS for processing. OVS is a virtual switch responsible for managing and handling network packets and may also be used to configure and manage BFD sessions. The OVS issues BFD Session to the DPU according to rules and configuration information of the BFD state machine. The BFD state machine is used to manage state transitions of the BFD session, including establishment, maintenance, and termination. The BFD Session contains parameters and configuration related to the Session to enable subsequent link state detection.

In an alternative embodiment, the method further comprises:

s103: and receiving BFD session information sent by the OVS according to the BFD message and receiving BFD control messages sent by the NP according to a preset interval.

BFD session is issued to the DPU by the OVS, and then a control message is sent BFD by the NP timing according to the configured time interval to detect the link state and update the BFD session.

In one embodiment, the OVS issues initialization echo BFD session DOE according to BFD configuration information, the information content including the following fields:

Bfd configure:

bfd:enable

Bfd:fowrding_if_rx

Bfd:min_rx

Bfd:min_tx

Bfd:status

Bfd:bfd_src_ip

Bfd:bfd_dst_ip

wherein BFD _src_ip can be generated by configuration for a random IP address, BFD _dst_ip is an opposite terminal IP, initialized BFD: status is DOWN, the home terminal sends a BFD echo message, when the NP receives the BFD echo message responded by the opposite terminal, the state is set to UP, and if no message is received in a configuration time interval, the state is set to DOWN, which indicates that a problem occurs in a link.

Fig. 3 is a flowchart of a method for optionally sending bfd control messages to detect link status and update bfd session, where the method is implemented:

the echo bfd initialization session is uniformly issued to DOE (Data offload engine) by the OVS configuration and stored in a hash table mode, the content of session information is shown in fig. 4, and the initialization status is down.

And judging by the NP according to the BFD enabling bit, if BFD session in BFD polling DOE (Data offload engine) is enabled, returning the session content, putting the session content into a local buffer, and triggering BFD echo message transmission.

The NP allocates timer resources according to the min_tx and then constructs an echo BFD message to be sent to the designated exit.

4. When receiving an echo BFD message returned by the opposite terminal, updating the state of the corresponding session to be UP, then sending a BFD echo message at regular time intervals, if the echo BFD of the opposite terminal is not received within the specified detection time, considering that the link is problematic, and then updating the state of the session to be Down.

And 5, when the NP updates the status of the session in DOE (Data offload engine), if the status changes, the NP needs to notify software such as OVS in an interrupt mode to link corresponding software protocol processing so as to achieve the purpose of quick response.

Fig. 5 is a schematic structural diagram of a data processing apparatus according to an exemplary embodiment of the present application. As shown in fig. 5, the data processing apparatus 500 includes at least one processor 501 and a memory 502 coupled to the processor 501, where the processor 501 may perform the respective steps of the above-described methods disclosed in the embodiments of the present disclosure.

The processor 501 may also be referred to as a central processing unit (central processing unit, CPU), which may be an integrated circuit chip with signal processing capabilities. The steps of the above-described methods disclosed in the embodiments of the present disclosure may be accomplished by instructions in the form of integrated logic circuits or software of hardware in the processor 501. The processor 501 may be a general purpose processor, a digital signal processor (digital signal processing, DSP), an ASIC, an off-the-shelf programmable gate array (field-programmable gate array, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the embodiments of the present disclosure may be embodied directly in hardware, in a decoded processor, or in a combination of hardware and software modules in a decoded processor. The software modules may be located in memory 502, such as random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, and other well-known storage media. The processor 501 reads the information in the memory 502 and in combination with its hardware performs the steps of the method described above. The data processing device may further comprise a transceiver 503 coupled to the processor 501 for receiving and transmitting information or data.

The disclosed embodiments also provide a computer-readable storage medium, wherein instructions in the computer-readable storage medium, when executed by a processor of an electronic device, enable the electronic device to perform the above-described method disclosed by the disclosed embodiments.

A computer readable storage medium in embodiments of the present disclosure may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable storage medium described above can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specifically, the computer-readable storage medium described above may include one or more wire-based electrical connections, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

The computer readable medium may be contained in the data processing apparatus; or may exist alone without being incorporated into the data processing apparatus.

The disclosed embodiments also provide a computer program product comprising a computer program, wherein the computer program, when executed by a processor, implements the above-described methods of the disclosed embodiments.

In an embodiment of the present disclosure, computer program code for performing the operations of the present disclosure may be written in one or more programming languages, including but not limited to an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server.

In this specification, adjectives such as first and second may be used solely to distinguish one element or action from another element or action without necessarily requiring or implying any actual such relationship or order. Where the environment permits, reference to an element or component or step (etc.) should not be construed as limited to only one of the element, component, or step, but may be one or more of the element, component, or step, etc.

In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for a hardware+program class embodiment, the description is relatively simple, as it is substantially similar to the method embodiment, as relevant see the partial description of the method embodiment.

The foregoing describes specific embodiments of the present disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

Although the present application provides method operational steps as described in the examples or flowcharts, more or fewer operational steps may be included based on conventional or non-inventive labor. The order of steps recited in the embodiments is merely one way of performing the order of steps and does not represent a unique order of execution. When implemented by an actual device or client product, the instructions may be executed sequentially or in parallel (e.g., in a parallel processor or multi-threaded processing environment) as shown in the embodiments or figures.

The system, apparatus, module or unit set forth in the above embodiments may be implemented in particular by a computer chip or entity, or by a product having a certain function.

Although the present description provides method operational steps as described in the examples or flowcharts, more or fewer operational steps may be included based on conventional or non-inventive means. The order of steps recited in the embodiments is merely one way of performing the order of steps and does not represent a unique order of execution. When implemented in an actual device or end product, the instructions may be executed sequentially or in parallel (e.g., in a parallel processor or multi-threaded processing environment, or even in a distributed data processing environment) as illustrated by the embodiments or by the figures. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, it is not excluded that additional identical or equivalent elements may be present in a process, method, article, or apparatus that comprises a described element.

For convenience of description, the above devices are described as being functionally divided into various modules, respectively. Of course, when implementing the embodiments of the present disclosure, the functions of each module may be implemented in the same or multiple pieces of software and/or hardware, or a module that implements the same function may be implemented by multiple sub-modules or a combination of sub-units, or the like. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

Those skilled in the art will also appreciate that, in addition to implementing the controller in a pure computer readable program code, it is well possible to implement the same functionality by logically programming the method steps such that the controller is in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc. Such a controller can be regarded as a hardware component, and means for implementing various functions included therein can also be regarded as a structure within the hardware component. Or even means for achieving the various functions may be regarded as either software modules implementing the methods or structures within hardware components.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

In one typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.

The memory may include volatile memory in a computer-readable medium, random Access Memory (RAM) and/or nonvolatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of computer-readable media.

Computer readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device. Computer-readable media, as defined herein, does not include transitory computer-readable media (transmission media), such as modulated data signals and carrier waves.

It will be appreciated by those skilled in the art that embodiments of the present description may be provided as a method, system, or computer program product. Accordingly, the present specification embodiments may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present description embodiments may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

The present embodiments may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The embodiments of the specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.

In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, as relevant to see a section of the description of method embodiments. In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present specification. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.

The foregoing is merely an example of an embodiment of the present disclosure and is not intended to limit the embodiment of the present disclosure. Various modifications and variations of the illustrative embodiments will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, or the like, which is within the spirit and principles of the embodiments of the present specification, should be included in the scope of the claims of the embodiments of the present specification.

Claims

1. A data processing method, characterized in that it is applied to the data processing unit DPU, and the method includes:

Through the hardware parser, confirm that the received message is a bidirectional forwarding detection BFD message and perform bit identification on the BFD message;

Identify the BFD message according to the bit identifier and send it to the open virtual switch OVS;

Receive BFD session information sent by the OVS according to the BFD message, and receive BFD control messages sent by the network processor NP at preset intervals.

2. The method according to claim 1, characterized in that the hardware parser performs bit identification on the BFD message through layered protocol parsing.

3. The method according to claim 2, characterized in that the method includes:

Each level of the processing module of the hardware parser is added with two 32-bit flags registers, which performs layered protocol parsing based on the message content and sets the corresponding bit to 1.

4. The method according to claim 1, characterized in that,

Determine whether the packet is a BFD packet through the flag in the flags register.

5. The method according to claim 1, wherein the receiving the BFD session information sent by the OVS according to the BFD message includes:

The initialization session from the OVS is stored in a hash table in the data offload engine DOE, and the initialization state is set to down.

6. The method according to claim 4, characterized in that the method includes:

When the NP receives the BFD echo message from the peer, it sets the status to up. If no message is received within the configured time interval, the NP sets the status to down.

7. A data processing device, characterized in that:

Comprising a memory and a processor; the memory is coupled to the processor; the memory is used to store computer program code, the computer program code includes computer instructions; wherein, when the processor executes the computer instructions, such that The data processing device executes the data processing method according to any one of claims 1-6.

8. A computer-readable storage medium, characterized in that:

The computer-readable storage medium stores computer instructions; wherein, when the computer instructions are run on a data processing device, the data processing device is caused to execute the data processing method according to any one of claims 1-7. .