CN117391035A - Chip with self-defined pin function and implementation method - Google Patents
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Abstract
The invention provides a chip with a self-defined pin function and an implementation method thereof, wherein the chip comprises a first signal pin, a first power pin, a chip core, a switch matrix and a logic control module; the chip core is provided with a second signal pin and a second power pin; the first signal pin is connected with the second signal pin through the switch matrix; the first power supply pin is connected with the second power supply pin; the logic control module is connected with the control end of the switch matrix and is used for controlling the switch matrix to carry out different gating, so that different pin functions of the chip are realized. The invention can dynamically map the functions of the second signal pins of the chip core and the first signal pins of the final chip through the switch matrix and the logic control module, thereby realizing the self-defined pin functions of the chip and enabling the chip to have flexibility and expandability; in addition, the invention can be applied to manufacturing symmetrical equipment, simplify the manufacturing process of the symmetrical equipment and improve the production efficiency.
Description
Technical Field
The invention relates to the technical field of chip design, in particular to a chip with a self-defined pin function and an implementation method.
Background
The problem of pin definition in chip design is one of the challenges that prevail in the chip design process. In conventional chip designs, each pin is typically predefined as a specific function or signal input/output. However, as the complexity and diversity of chip designs increases, a single pin definition often cannot meet the requirements of different application scenarios.
Currently, there have been some solutions that attempt to address the flexibility and scalability issues of pin definition in chip design. One common approach is to use multiple versions of the chip design, each optimized for a different application scenario. However, this approach has some limitations: first, separate designs and verifications need to be made for each version, which increases development cycle and cost; second, when application requirements change, new chip versions need to be redesigned and produced, resulting in wasted resources and time delays.
Therefore, there is an urgent need to propose a new solution to achieve flexibility and scalability of pin definition in chip design. The solution should be capable of achieving flexible switching of different pin functions through simple configuration or adjustment in a design stage or a production stage, thereby meeting the requirements of different application scenes. By adopting the solution, the chip design flow is greatly simplified, the development efficiency is improved, and the development cost is reduced.
Disclosure of Invention
The invention aims to provide a chip with a self-defined pin function and an implementation method thereof, so as to solve the problem that the pin definition of the chip in the traditional chip design lacks flexibility and expandability.
The invention provides a chip with a self-defined pin function, which comprises a first signal pin, a first power pin, a chip core, a switch matrix and a logic control module, wherein the first power pin is connected with the first signal pin; the chip core is provided with a second signal pin and a second power pin;
the first signal pins are connected with the second signal pins through the switch matrix;
the first power supply pin is connected with the second power supply pin;
the logic control module is connected with the control end of the switch matrix and is used for controlling the switch matrix to carry out different gating so as to realize different pin functions of the chip.
Further, the first signal pin and the second signal pin are provided with N signal pins; correspondingly, the switch matrix comprises N selection switches;
the N signal pins of the first signal pin are connected with the N signal pins of the second signal pin in a one-to-one correspondence manner after passing through the N selection switches.
Further, the selection switch is provided with an input end and M output ends, wherein M is less than or equal to N;
the input ends of the N selection switches are respectively connected with N signal pins of the second signal pins in a one-to-one correspondence manner; m output ends of each selection switch are connected with M signal pins in the first signal pins.
In one application, the logic control modules are multiple, and each logic control module is realized by a different logic control circuit;
different logic control circuits are used for carrying out different gating through controlling the switch matrix so as to realize different pin functions of the chip;
according to the pin function of the chip to be realized, only one corresponding logic control module is connected with the control end of the switch matrix.
In another application, the logic control module is operated with logic control software;
the logic control software is used for controlling the switch matrix to carry out different gating, so that different pin functions of the chip are realized.
In one application, the implementation method of the chip with the custom pin function comprises the following steps:
according to the signal pin number N of the first signal pin and the second signal pin and the fixed M pin functions of the chip, the selection switch number N of the switch matrix and the output end number M of the selection switch are configured, wherein M is less than or equal to N;
according to M pin functions, M different logic control circuits are designed, and each logic control circuit forms a logic control module;
connecting the first signal pin with the second signal pin through the switch matrix, and connecting the first power pin with the second power pin; then, according to the pin function of the chip to be realized, selecting a corresponding logic control module to be connected with the control end of the switch matrix;
packaging and powering up the chip for testing; the logic control module in the chip inputs control signals to the N selection switches and controls the N selection switches to carry out corresponding gating, so that the N signal pins of the first signal pin are correspondingly connected with the N signal pins of the second signal pin after passing through the N selection switches, and corresponding pin functions of the chip are realized.
In another application, the implementation method of the chip with the custom pin function comprises the following steps:
according to the number N of signal pins of the first signal pin and the second signal pin and the pin function of the chip to be realized, configuring the number N of the selection switches of the switch matrix and the number M of the output ends of the selection switches, wherein M=N;
connecting the first signal pin with the second signal pin through the switch matrix, and connecting the first power pin with the second power pin; then, connecting the logic control module with a control end of the switch matrix;
packaging and powering up the chip for testing; according to the pin functions of the chip to be realized, logic control software running on the logic control module controls the switch matrix to carry out corresponding gating, so that N signal pins of the first signal pin are correspondingly connected with N signal pins of the second signal pin after passing through N selection switches, and the corresponding pin functions of the chip are realized.
In summary, due to the adoption of the technical scheme, the beneficial effects of the invention are as follows:
1. in the traditional chip design, the pin function of the chip is fixed and cannot be adjusted according to different requirements. The invention can dynamically map the functions of the second signal pins of the chip core and the first signal pins of the final chip through the switch matrix and the logic control module, thereby realizing the self-defined pin functions of the chip and enabling the chip to have flexibility and expandability.
2. In the conventional chip design, the manufacturing of the symmetrical device requires complicated wiring and adjustment, which is time-consuming and labor-consuming. The invention can also be applied to manufacturing symmetrical equipment, and the manufacturing process of the symmetrical equipment can be simplified and the production efficiency can be improved through the switch matrix and the logic control module.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following description will briefly describe the drawings in the embodiments, it being understood that the following drawings only illustrate some embodiments of the present invention and should not be considered as limiting the scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a chip with a custom pin function according to the present invention.
Fig. 2 is a flowchart of an implementation method of a chip with a custom pin function according to an exemplary embodiment of the present invention.
Fig. 3a is a schematic diagram illustrating pin functions of a chip of a left device in a symmetrical device according to an exemplary embodiment of the present invention.
Fig. 3b is a schematic diagram illustrating pin functions of a chip of a right device in a symmetrical device according to an exemplary embodiment of the present invention.
Fig. 4 is a flowchart of an implementation method of a chip with a custom pin function according to a second embodiment of the present invention.
Fig. 5a is a schematic diagram illustrating a default chip pin function according to example two of the present invention.
Fig. 5b is a schematic diagram of a pin function of a chip after the sequence of signal pins is modified in the first requirement of the second example of the present invention.
Fig. 5c is a schematic diagram of a pin function of a chip after the sequence of signal pins is modified in the second requirement of the second embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Examples
As shown in fig. 1, the present embodiment provides a chip with a function of a custom pin, including a first signal pin, a first power pin, a chip core, a switch matrix, and a logic control module; the chip core is provided with a second signal pin and a second power pin; wherein chip cores (also commonly referred to as Die, die being the core component of the chip, which is formed by fabricating functional circuitry of various functional modules on a semiconductor material), each chip core typically has one or more functions, such as a central processor, a graphics processor, a memory controller, and/or a communication interface, etc.;
the first signal pins are connected with the second signal pins through the switch matrix;
the first power supply pin is connected with the second power supply pin;
the logic control module is connected with the control end of the switch matrix and is used for controlling the switch matrix to carry out different gating so as to realize different pin functions of the chip.
Further, the first signal pin and the second signal pin are provided with N signal pins; correspondingly, the switch matrix comprises N selection switches; the N signal pins of the first signal pin are connected with the N signal pins of the second signal pin in a one-to-one correspondence manner after passing through the N selection switches.
Further, the selection switch is provided with an input end and M output ends, wherein M is less than or equal to N; the input ends of the N selection switches are respectively connected with N signal pins of the second signal pins in a one-to-one correspondence manner; m output ends of each selection switch are connected with M signal pins in the first signal pins. Typically, the selector switch may be implemented as a single pole, multi-throw switch or a rotary transfer switch.
In some application scenarios, the chip has a fixed M pin function, and at this time, a plurality of logic control modules can be configured, and each logic control module is realized by a different logic control circuit; different logic control circuits are used for carrying out different gating through controlling the switch matrix so as to realize different pin functions of the chip; according to the pin function of the chip to be realized, only one corresponding logic control module is connected with the control end of the switch matrix.
Under some application scenes, the chip can customize various pin functions, and can be realized through software control at the moment, and the logic control module is configured to run logic control software; the logic control software is used for controlling the switch matrix to carry out different gating, so that different pin functions of the chip are realized.
The invention is described in detail below by way of examples of application scenarios:
example one, a chip has a fixed M pin functionality:
in some special application scenarios, it is desirable to manufacture symmetrical devices, such as left and right symmetrical headphones. Such symmetric devices typically require that both chips have the same functionality and layout, but due to the existence of the symmetric structure, the pin definitions on the chips must have corresponding exchange relationships.
The chip with the custom pin function can be suitable for the application scene. By using the switch matrix and the logic control module, the mirror image chip can be conveniently produced, and the symmetrical equipment can work normally.
A requirement that can be determined from symmetrical devices is that the chip has 2 pin functions fixed. As shown in fig. 2, the corresponding method for implementing the chip with the custom pin function includes the following steps:
s101, configuring the number of selection switches n=6 of the switch matrix according to the number of signal pins n=6 of the first signal pin and the second signal pin; and, according to the chip has fixed 2 kinds of pin functions, dispose the output end quantity M=2 of the selector switch;
s102, designing 2 different logic control circuits according to 2 pin functions, wherein each logic control circuit forms a logic control module; in this embodiment, the logic control module includes:
the first logic control module is used for controlling the gating of the switch matrix through input analog voltage to realize the pin function of the chip of the left device;
and the second logic control module is used for inputting analog voltage to control the gating of the switch matrix and realizing the pin function of the chip of the right equipment.
It should be noted that, the logic control circuit may be configured according to a control function to be implemented, for example, an analog circuit is used to control the switch matrix through an analog voltage input, or a digital circuit is used to control the switch matrix through a digital signal, so that detailed description of a specific circuit structure is omitted.
S103, connecting the first signal pin with the second signal pin through a switch matrix, and connecting the first power pin with the second power pin; then, according to the pin function of the chip to be realized, selecting a corresponding logic control module to be connected with the control end of the switch matrix;
fig. 3a is a schematic diagram of the pin function of the chip of the left device in a symmetrical device, and fig. 3b is a schematic diagram of the pin function of the chip of the right device in a symmetrical device. The first signal pin of the chip comprises 6 signal pins which are a signal pin A1, a signal pin B1, a signal pin C1, a signal pin D1, a signal pin E1 and a signal pin F1 respectively; the second signal pins of the chip core include 6 signal pins including a signal pin A2, a signal pin B2, a signal pin C2, a signal pin D2, a signal pin E2 and a signal pin F2, respectively.
The 6 selection switches of the switch matrix are all single-pole double-throw switches; wherein:
the input end of the selection switch SW11 is connected with the signal pin A2; two output ends of the selection switch SW11 are connected with the signal pin A1 and the other signal pin F1;
the input end of the selection switch SW12 is connected with the signal pin B2; two output ends of the selection switch SW12 are connected with the signal pin B1 and the other signal pin E1;
the input end of the selection switch SW13 is connected with the signal pin C2; two output ends of the selection switch SW13 are connected with the signal pin C1 and the other signal pin D1;
the input end of the selection switch SW14 is connected with the signal pin D2; two output ends of the selection switch SW14 are connected with the signal pin D1 and the other signal pin C1;
the input end of the selection switch SW15 is connected with the signal pin E2; two output ends of the selection switch SW15 are connected with the signal pin E1 and the signal pin B1;
the input end of the selection switch SW16 is connected with the signal pin F2; two output ends of the selection switch SW16 are connected with the signal pin F1 and the other signal pin A1;
for the pin function of the chip of the left device to be implemented, the first logic control module is selected to be connected to the control terminal of the switch matrix, as shown in fig. 3 a.
For the pin function of the chip of the right device to be implemented, a second logic control module is selected to be connected to the control terminal of the switch matrix, as shown in fig. 3 b.
S104, packaging and powering up the chip for testing; the logic control module in the chip inputs control signals to the 6 selection switches, and controls the 6 selection switches to perform corresponding gating, so that the 6 signal pins of the first signal pin are correspondingly connected with the 6 signal pins of the second signal pin after passing through the 6 selection switches, and corresponding pin functions of the chip are realized.
As shown in fig. 3a, for the pin function of the chip of the left device to be implemented, the first logic control module inputs control signals to the 6 selection switches to control the 6 selection switches to perform corresponding gating:
the selection switch SW11 communicates the signal pin A2 with the signal pin A1;
the selection switch SW12 communicates the signal pin B2 with the signal pin B1;
the selection switch SW13 communicates the signal pin C2 with the signal pin C1;
the selection switch SW14 communicates the signal pin D2 with the signal pin D1;
the selection switch SW15 communicates the signal pin E2 with the signal pin E1;
the selection switch SW16 communicates the signal pin F2 with the signal pin F1.
As shown in fig. 3b, for the pin function of the chip of the right device to be implemented, the second logic control module inputs control signals to the 6 selection switches to control the 6 selection switches to perform corresponding gating:
the selection switch SW11 communicates the signal pin A2 with the signal pin F1;
the selection switch SW12 communicates the signal pin B2 with the signal pin E1;
the selection switch SW13 communicates the signal pin C2 with the signal pin D1;
the selection switch SW14 communicates the signal pin D2 with the signal pin C1;
the selection switch SW15 communicates the signal pin E2 with the signal pin B1;
the selection switch SW16 communicates the signal pin F2 with the signal pin A1.
Through the above process, the pin functions of the chip of the left device are exactly symmetrical with the pin functions of the chip of the device, so that a pair of symmetrical devices is formed. According to the invention, the production of the symmetrical chips can be effectively realized only by replacing the logic control module according to the pin function of the chip to be realized, and the production efficiency and the consistency of equipment are improved. If the invention is not adopted, the symmetrical chip can be produced only by re-wiring.
Example two, the chip may customize multiple pin functions:
in conventional chip designs, the pin functions of the chip are well defined during the chip design stage, and if the pin functions of the chip need to be changed, the chip needs to be redesigned or external wiring needs to be changed. By applying the invention, the function of each signal pin in the custom chip can be realized through software control. Specifically, the logic control module is configured to run logic control software; the logic control software is used for controlling the switch matrix to carry out different gating, so that different pin functions of the chip are realized.
The chip of the example provides the order of 4 signal pins to the outside, which is input pin, clock pin, reset pin and output pin in turn. The first requirement is that the order of the 4 signal pins, in turn, output pin, reset pin, input pin and clock pin, can be custom modified. The second requirement is that the order of the 4 signal pins, in turn, output pin, input pin, clock pin and reset pin, can be custom modified. As shown in fig. 4, the corresponding implementation method of the chip with the custom pin function includes the following steps:
s201, configuring the number of selection switches n=4 of the switch matrix and the number of output ends m=4 of the selection switches according to the number of signal pins n=4 of the first signal pin and the second signal pin;
s202, connecting a first signal pin with a second signal pin through a switch matrix, and connecting a first power pin with a second power pin; then, connecting the logic control module with a control end of the switch matrix;
fig. 5a is a schematic diagram of the pin function of the default chip. Fig. 5b is a schematic diagram showing the pin functions of the chip after the sequence of the signal pins in the first requirement is modified. FIG. 5c is a schematic diagram showing the pin functions of the chip after the sequence of the signal pins is modified in the second requirement. The first signal pin of the chip comprises 4 signal pins which are respectively a signal pin AA1, a signal pin BB1, a signal pin CC1 and a signal pin DD1; the second signal pins of the chip core include 4 signal pins AA2, BB2, CC2 and DD2, respectively.
The 4 selection switches of the switch matrix are all single-pole four-throw switches; wherein:
the input end of the selection switch SW21 is connected with the signal pin AA2; four output ends of the selection switch SW21 are respectively connected with the signal pin AA1, the signal pin BB1, the signal pin CC1 and the signal pin DD1;
the input end of the selection switch SW22 is connected with the signal pin BB2; four output ends of the selection switch SW22 are respectively connected with the signal pin AA1, the signal pin BB1, the signal pin CC1 and the signal pin DD1;
the input end of the selection switch SW23 is connected with the signal pin CC2; four output ends of the selection switch SW23 are respectively connected with the signal pin AA1, the signal pin BB1, the signal pin CC1 and the signal pin DD1;
the input end of the selection switch SW24 is connected with the signal pin DD2; four output ends of the selection switch SW24 are respectively connected with the signal pin AA1, the signal pin BB1, the signal pin CC1 and the signal pin DD1;
s203, packaging and powering up the chip for testing; according to the pin functions of the chip to be realized, logic control software running on the logic control module controls the switch matrix to carry out corresponding gating, so that 4 signal pins of the first signal pin are correspondingly connected with 4 signal pins of the second signal pin after passing through 4 selection switches, and the corresponding pin functions of the chip are realized.
It should be noted that, the logic control software may be developed according to the control function to be implemented, and a general implementation manner of the logic control module and the logic control software may be that a computer program is run on a microprocessor, and specific programming of the logic control software is not described herein.
As shown in fig. 5a, when the pin function of the default chip is implemented, the order of outputting the 4 signal pins of the first signal pin is sequentially an input pin, a clock pin, a reset pin and an output pin. Logic control software running on the logic control module controls the 4 selection switches to carry out corresponding gating:
the selection switch SW21 communicates the signal pin AA2 with the signal pin AA 1;
the selection switch SW22 communicates the signal pin BB2 with the signal pin BB 1;
the selection switch SW23 communicates the signal pin CC2 with the signal pin CC 1;
the selection switch SW24 communicates the signal pin DD2 with the signal pin DD 1.
As shown in fig. 5b, when the pin function of the first-requirement chip is implemented, the order of the output of the 4 signal pins of the first signal pin is sequentially an output pin, a reset pin, an input pin and a clock pin. Logic control software running on the logic control module controls the 4 selection switches to carry out corresponding gating:
the selection switch SW21 communicates the signal pin AA2 with the signal pin CC 1;
the selection switch SW22 communicates the signal pin BB2 with the signal pin DD1;
the selection switch SW23 communicates the signal pin CC2 with the signal pin BB 1;
the selection switch SW24 communicates the signal pin DD2 with the signal pin AA 1.
As shown in fig. 5c, when the pin function of the chip of the second requirement is implemented, the order of outputting the 4 signal pins of the first signal pin is sequentially an output pin, an input pin, a clock pin and a reset pin. Logic control software running on the logic control module controls the 4 selection switches to carry out corresponding gating:
the selection switch SW21 communicates the signal pin AA2 with the signal pin BB 1;
the selection switch SW22 communicates the signal pin BB2 with the signal pin CC 1;
the selection switch SW23 communicates the signal pin CC2 with the signal pin DD1;
the selection switch SW24 communicates the signal pin DD2 with the signal pin AA 1.
Through the process, the pin functions of the chip can be customized according to different requirements. On the one hand, the chip design flow is simplified, and the time and cost for redesigning the chip and changing the external wiring are saved. On the other hand, development efficiency is improved, and customized chip products can be more quickly pushed out. Most importantly, the method meets the changing application requirements, so that the chip has flexibility and expandability.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. The chip with the self-defined pin function is characterized by comprising a first signal pin, a first power pin, a chip core, a switch matrix and a logic control module; the chip core is provided with a second signal pin and a second power pin;
the first signal pins are connected with the second signal pins through the switch matrix;
the first power supply pin is connected with the second power supply pin;
the logic control module is connected with the control end of the switch matrix and is used for controlling the switch matrix to carry out different gating so as to realize different pin functions of the chip.
2. The chip with the custom pin function according to claim 1, wherein the first signal pin and the second signal pin each have N signal pins; correspondingly, the switch matrix comprises N selection switches;
the N signal pins of the first signal pin are connected with the N signal pins of the second signal pin in a one-to-one correspondence manner after passing through the N selection switches.
3. The chip with the custom pin function according to claim 2, wherein the selector switch has one input end and M output ends, M is less than or equal to N;
the input ends of the N selection switches are respectively connected with N signal pins of the second signal pins in a one-to-one correspondence manner; m output ends of each selection switch are connected with M signal pins in the first signal pins.
4. A chip with a custom pin function according to any of claims 1-3, wherein there are a plurality of logic control modules, each logic control module being implemented by a different logic control circuit;
different logic control circuits are used for carrying out different gating through controlling the switch matrix so as to realize different pin functions of the chip;
according to the pin function of the chip to be realized, only one corresponding logic control module is connected with the control end of the switch matrix.
5. A chip with a custom pin function according to any of claims 1-3, wherein the logic control module runs logic control software;
the logic control software is used for controlling the switch matrix to carry out different gating, so that different pin functions of the chip are realized.
6. The method for implementing the chip with the custom pin function according to claim 4, comprising the following steps:
according to the signal pin number N of the first signal pin and the second signal pin and the fixed M pin functions of the chip, the selection switch number N of the switch matrix and the output end number M of the selection switch are configured, wherein M is less than or equal to N;
according to M pin functions, M different logic control circuits are designed, and each logic control circuit forms a logic control module;
connecting the first signal pin with the second signal pin through the switch matrix, and connecting the first power pin with the second power pin; then, according to the pin function of the chip to be realized, selecting a corresponding logic control module to be connected with the control end of the switch matrix;
packaging and powering up the chip for testing; the logic control module in the chip inputs control signals to the N selection switches and controls the N selection switches to carry out corresponding gating, so that the N signal pins of the first signal pin are correspondingly connected with the N signal pins of the second signal pin after passing through the N selection switches, and corresponding pin functions of the chip are realized.
7. The method for implementing the chip with the custom pin function according to claim 5, comprising the following steps:
according to the number N of signal pins of the first signal pin and the second signal pin and the pin function of the chip to be realized, configuring the number N of the selection switches of the switch matrix and the number M of the output ends of the selection switches, wherein M=N;
connecting the first signal pin with the second signal pin through the switch matrix, and connecting the first power pin with the second power pin; then, connecting the logic control module with a control end of the switch matrix;
packaging and powering up the chip for testing; according to the pin functions of the chip to be realized, logic control software running on the logic control module controls the switch matrix to carry out corresponding gating, so that N signal pins of the first signal pin are correspondingly connected with N signal pins of the second signal pin after passing through N selection switches, and the corresponding pin functions of the chip are realized.
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| CN114296808A (en) * | 2021-12-23 | 2022-04-08 | 科东(广州)软件科技有限公司 | Pin configuration method and device, electronic equipment and storage medium |
| CN219225516U (en) * | 2023-01-09 | 2023-06-20 | 合肥市卓怡恒通信息安全有限公司 | Time-sharing multiplexing circuit for multiplexing pins |
| CN117031255A (en) * | 2023-08-30 | 2023-11-10 | 北京中科格励微科技有限公司 | Chip test system sharing chip function pins |
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| CN114296808A (en) * | 2021-12-23 | 2022-04-08 | 科东(广州)软件科技有限公司 | Pin configuration method and device, electronic equipment and storage medium |
| CN219225516U (en) * | 2023-01-09 | 2023-06-20 | 合肥市卓怡恒通信息安全有限公司 | Time-sharing multiplexing circuit for multiplexing pins |
| CN117031255A (en) * | 2023-08-30 | 2023-11-10 | 北京中科格励微科技有限公司 | Chip test system sharing chip function pins |
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Application publication date: 20240112 |