CN117371171A - Evaluation method for reliability of sealing ring - Google Patents
Evaluation method for reliability of sealing ring Download PDFInfo
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- CN117371171A CN117371171A CN202311125674.XA CN202311125674A CN117371171A CN 117371171 A CN117371171 A CN 117371171A CN 202311125674 A CN202311125674 A CN 202311125674A CN 117371171 A CN117371171 A CN 117371171A
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Abstract
The embodiment of the application provides a method for evaluating the reliability of a sealing ring, which comprises the following steps: constructing a simulation model of the sealing ring according to the actual structure of the sealing ring; the simulation model at least comprises a plurality of metal layers which extend along a first direction and are stacked along a second direction, and metal vias positioned on two adjacent metal layers; defining test stress and test temperature of a simulation model; applying test stress in different directions to a stress surface of the simulation model at a certain test temperature to determine deformation performance of a metal layer in the sealing ring; the stress surface of the simulation model is parallel to a plane formed by the first direction and the second direction; and under the condition that the deformation performance meets the preset condition, confirming that the reliability of the sealing ring meets the requirement.
Description
Technical Field
The application relates to the technical field of semiconductor simulation modeling, and relates to a method for evaluating reliability of a sealing ring.
Background
In the manufacturing process of a semiconductor, after a wafer is processed, the wafer needs to be cut according to a preset dicing line (dicing line), and a large-size wafer is cut and decomposed into a plurality of semiconductor devices or semiconductor structures with electrical functions, wherein the devices or structures can be defined as Die, and then the Die is packaged into chips for application to an integrated circuit.
In order to reduce the damage to the chip from the dicing process during dicing, a seal ring is introduced between the chip and the dicing street. When the sealing ring is difficult to block microcracks which are expanded in the wafer cutting process, electronic components and circuits in the chip can be broken or electrically influenced. Currently, the reliability of the sealing ring is evaluated by performing slice testing on a molded sample to determine the reliability of the sealing ring, which greatly increases the testing time and has higher cost.
Disclosure of Invention
In view of the above, embodiments of the present application provide a method for evaluating reliability of a seal ring; the method comprises the following steps:
constructing a simulation model of the sealing ring according to the actual structure of the sealing ring; the simulation model at least comprises a plurality of metal layers which extend along a first direction and are stacked along a second direction, and metal vias positioned on two adjacent metal layers;
defining test stress and test temperature of the simulation model;
applying the test stress to the stress surface of the simulation model at the test temperature to determine the deformation performance of the metal layer in the sealing ring; the stress surface of the simulation model is parallel to a plane formed by the first direction and the second direction;
and under the condition that the deformation performance meets the preset condition, confirming that the reliability of the sealing ring meets the requirement.
In some embodiments, the test stress comprises: a first test stress and/or a second test stress;
applying the test stress to a force bearing surface of the simulation model to determine deformation properties of the metal layer in the seal ring, comprising:
applying the first test stress to a first stressed region of the simulation model to determine deformation properties of the metal layer in the seal ring; and/or the number of the groups of groups,
applying the second test stress to a second stress region of the simulation model to determine deformation properties of the metal layer in the seal ring;
the first stress area and the second stress area are both positioned in the stress surface of the simulation model, and the first stress area is positioned below the second stress area.
In some embodiments, the direction of action of the first test stress is perpendicular to the first stressed region; the second test stress acts in a direction parallel to the second stressed region.
In some embodiments, the force-receiving surface has a first predetermined distance from the metal layer along a direction of application of the first test stress.
In some embodiments, the deformation properties include Feng Misai s stress and/or displacement; under the condition that the deformation performance meets the preset condition, confirming that the reliability of the sealing ring meets the requirement comprises the following steps:
under the condition that the Feng Misai S stress is smaller than a preset stress, confirming that the reliability of the sealing ring meets the requirement; and/or the number of the groups of groups,
and under the condition that the displacement is larger than the preset displacement, confirming that the reliability of the sealing ring meets the requirement.
In some embodiments, constructing a simulation model of the seal ring from the seal ring actual structure includes:
defining a substrate having a first predetermined thickness;
defining a plurality of metal layers on the surface of the substrate; the metal layer at least comprises a first metal structure and a second metal structure which are alternately arranged at intervals; the first metal structure and the second metal structure extend along a first direction, and the second metal structure extends into the first metal structure along the first direction; the projection part of the first metal structure and the adjacent second metal structure in the direction perpendicular to the first direction is overlapped; the third direction is perpendicular to a plane formed by the first direction and the second direction;
and defining a plurality of metal column metal through holes between adjacent metal layers to construct a simulation model of the sealing ring.
In some embodiments, defining a plurality of the metal layers on the substrate surface includes:
defining a first dielectric layer with a second preset thickness on the surface of the substrate;
etching part of the first dielectric layer with the thickness through a mask with a preset pattern to form a first groove; the first grooves comprise first sub-grooves and second sub-grooves which are alternately arranged at intervals; and forming the first metal structure in the first sub-groove and forming the second metal structure in the second sub-groove.
In some embodiments, the first metal structure is i-shaped and the second metal structure is in-line.
In some embodiments, the first metal structure is double-lined and the second metal structure is lined.
In some embodiments, defining a plurality of metal pillar metal vias between adjacent ones of the metal layers to form a simulation model of a seal ring, comprising:
defining a second dielectric layer with a third preset thickness between adjacent first dielectric layers;
sequentially etching the metal layer, the first dielectric layer and the second dielectric layer until the bottommost metal layer is exposed, so as to form a plurality of second grooves;
and forming the metal post metal via hole in the second groove to form the simulation model.
In some embodiments, the simulation model is part of the actual structure of the seal ring.
The embodiment of the application provides a method for evaluating the reliability of a sealing ring, which comprises the following steps: constructing a simulation model of the sealing ring according to the actual structure of the sealing ring; the simulation model at least comprises a plurality of metal layers which extend along a first direction and are stacked along a second direction; defining test stress and test temperature of a simulation model; applying test stress to the stress surface of the simulation model at the test temperature to determine the deformation performance of the metal layer in the sealing ring; the stress surface of the simulation model is parallel to a plane formed by the first direction and the second direction; and under the condition that the deformation performance meets the preset condition, confirming that the reliability of the sealing ring meets the requirement. Because the embodiment of the application can define the simulation model of the sealing package based on the interconnection simulation tool, the stress distribution condition process of the actual cutting process can be simulated through the simulation model, so that the reliability of the sealing ring is evaluated, the testing time and the cost are reduced, and the method is simple, convenient and quick.
Drawings
In the drawings (which are not necessarily drawn to scale), like numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example and not by way of limitation, various embodiments discussed herein.
FIG. 1 is a schematic flow chart of a reliability evaluation method for a seal ring according to an embodiment of the present disclosure;
fig. 2 to 19 are schematic structural diagrams of a seal ring simulation model according to an embodiment of the present application.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application may be practiced without one or more of these details. In other instances, well-known features have not been described in detail so as not to obscure the application; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.
In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present application.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the wafer cutting process, microcracks which are easily germinated and expanded by a cutting interface and invade a chip circuit area can influence an electronic circuit in a chip, and mechanical damage is introduced to a bonded interface to cause disconnection. Therefore, it is common to provide a sealing ring between the chip and the dicing street to resist stress damage to the chip during dicing.
At present, the reliability of the sealing ring is evaluated only by actually cutting a molded sample and performing a series of electrical performance tests and structural tests on a chip after cutting, so that the reliability of the sealing ring is determined, the testing time is greatly prolonged, and the cost is high.
Based on this, the embodiment of the application provides a method for evaluating reliability of a sealing ring, which includes: constructing a simulation model of the sealing ring according to the actual structure of the sealing ring; the simulation model at least comprises a plurality of metal layers which extend along a first direction and are stacked along a second direction; defining test stress and test temperature of a simulation model; applying test stress to the stress surface of the simulation model at the test temperature to determine the deformation performance of the metal layer in the sealing ring; the stress surface of the simulation model is parallel to a plane formed by the first direction and the second direction; and under the condition that the deformation performance meets the preset condition, confirming that the reliability of the sealing ring meets the requirement. Because the embodiment of the application can define the simulation model of the sealing package based on the interconnection simulation tool, the stress distribution condition process of the actual cutting process can be simulated through the simulation model, so that the reliability of the sealing ring is evaluated, the testing time and the cost are reduced, and the method is simple, convenient and quick.
Fig. 1 is a flowchart of a method for evaluating reliability of a seal ring according to an embodiment of the present application, where, as shown in fig. 1, the method for evaluating reliability of a seal ring includes the following steps:
s101, constructing a simulation model of the sealing ring according to the actual structure of the sealing ring; the simulation model at least comprises a plurality of metal layers which extend along a first direction and are stacked along a second direction, and metal vias positioned on two adjacent metal layers;
it should be noted that, the seal ring reliability evaluation method provided in the embodiment of the present application may be implemented based on an interconnection simulation tool, and the interconnection simulation tool may be Sentaurus Sinterconnect and Sentaurus Svisual; sentaurus Sinterconnec, for constructing and testing the seal ring simulation model, sentaurus Svisual, for viewing the test results.
In the embodiment of the application, the sealing ring is formed between the chip and the dicing street on the wafer, and the sealing ring surrounds the semiconductor device, or the semiconductor structure, or the chip to provide protection. The shape of the sealing ring or the orthographic projection profile of the sealing ring along the thickness direction can comprise a closed pattern surrounded by a plurality of straight line segments, and two adjacent edges (or side walls) are connected by a corner. The shape of the sealing ring comprises an octagonal structure, and each edge comprises a plurality of interconnection layers formed by metal layers and first dielectric layers and metal through holes formed in the first dielectric layers and connected with two adjacent metal layers.
The metal layer in the seal ring is on the same layer as the metal layer in the chip (e.g., M0, M1, etc.), and the metal Via is on the same layer as the contact Via (Via) or contact plug, bond contact, contact pad, etc. structure in the chip. The metal vias may include, but are not limited to: conductive plugs extending in the thickness direction (X direction in fig. 2 and 3), coupling contacts, pads, bonding contacts, and the like. The metal layer may include, but is not limited to: wiring layers, interconnection layers, and the like extending along a surface perpendicular to the thickness direction. The metal via hole can be positioned between two adjacent metal layers and is connected with the two metal layers, so as to provide support and improve the mechanical stability and stress bearing of the sealing ring.
In this embodiment of the present application, the multiple metal layers in each side extend along a first direction, and are stacked along a second direction, where the second direction is a thickness direction of the semiconductor device, and the first direction is perpendicular to the second direction. The second direction may be the X-direction and the first direction may be the Z-direction or a direction perpendicular to the plane of the X-direction and at an angle to the Z-direction.
In this embodiment of the present application, the metal layer in the seal ring may be chain-shaped. In other embodiments, the metal layer in the seal ring may also be bulk. The constructed simulation model in the embodiment of the application is part of the actual structure of the sealing ring. For example, the sealing ring can be any one side of an octagonal sealing ring or can be a structure with a part of the length of any one side. Referring to fig. 2, which is a schematic view of a semiconductor device surrounded by a metal layer in a seal ring, the metal layer may have a chain-like structure and an octagonal structure, and corners of the structure may be rounded to reduce chipping caused by stress concentration of sharp corners. The simulation model of the metal layer (or seal ring) constructed in this embodiment may be one of the edges in fig. 2, or another shaped seal ring made up of one of the edges. The simulation model of the embodiment of the disclosure can be applied to actual manufacturing of sealing rings with various shapes. The sealing ring structure of the embodiment of the disclosure can be applied to all film structures of a semiconductor device, can be applied to a non-bonding device structure and can also be applied to a polycrystalline wafer bonding structure. For example, when a plurality of wafers or semiconductor structures are interconnected through hybrid bonding stack, the seal ring structure (e.g., metal via) in this embodiment may be disposed at the bonding interface or extend to other layers, so as to improve the stress resistance of the structure, reduce the risk of cracking and debonding of the bonding interface during the dicing process, and improve the device yield.
Step S102, defining test stress and test temperature of a simulation model;
in some embodiments, the test stress is an actual stress to which the seal ring is subjected during an actual dicing process. The test temperature is an actual temperature that simulates an actual dicing process of the wafer.
In some embodiments, testing the stress comprises: a first test stress and/or a second test stress; the first test stress and the second test stress may be decomposition stresses of the cutting stress in the actual cutting process.
The first test stress and the second test stress have different directions and different acting positions.
According to the embodiment of the application, the reliability of the simulation model can be tested through the first test stress or the second test stress.
In other embodiments, the reliability of the seal ring may also be tested by the first test stress and the second test stress, so that the test condition may be more similar to the real test condition, and the test structure may be more real and accurate.
In some embodiments, the test temperature is room temperature, e.g., 25 ℃.
Step S103, applying test stress to the stress surface of the simulation model at test temperature to determine the deformation performance of the metal layer in the sealing ring; the stress surface of the simulation model is parallel to a plane formed by the first direction and the second direction;
when the wafer is cut, the stress surface of the sealing ring is the outer surface of the sealing ring away from one side of the chip, and the direction of the stress surface can be parallel to the plane formed by the first direction and the second direction.
In the embodiment of the application, test stress is applied to the stress surface of the simulation model at a predefined test temperature, and the deformation performance of the metal layer in the sealed package is obtained through analysis of an interconnection simulation tool.
In some embodiments, step S103 may include the steps of:
a first test stress is applied to a first stressed region of the simulation model to determine deformation properties of the metal layer in the seal ring.
It should be noted that, the first stress area is a part of the stress surface of the simulation model, and the acting direction of the first test stress is perpendicular to the first stress area. In an embodiment of the present application, the first test stress may be a positive stress.
In some embodiments, step S103 may include the steps of:
applying a second test stress to a second stressed region of the simulation model to determine deformation properties of the metal layer in the seal ring;
it should be noted that the second stress area is another part of the stress surface of the simulation model, which is different from the first stress area, that is, the first stress area and the second stress area are both located in the stress surface of the simulation model. The acting direction of the second test stress is parallel to the second stress area, i.e. the acting direction of the second test stress is parallel to the stress surface of the simulation model. In an embodiment of the present application, the second test stress may be a shear stress.
In some embodiments, the direction of application of the positive stress may be along the Y direction in the drawing, i.e., perpendicular to the thickness direction and the extending direction of the metal layer. The positive stress can simulate the transverse pressure of the side wall of a diamond grinding wheel and other cutters to the sealing ring in the wafer cutting process, and the pressure direction can be perpendicular to the gravity direction. The shearing stress may be applied in the X direction in the drawing, i.e., in the thickness direction (or the gravitational direction) to the top of the seal ring. The shear stress can simulate the pressure applied to the sealing ring by a cutter such as a diamond grinding wheel in the gravity direction in the wafer cutting process. Specifically, taking the seal ring simulation model 40 with a chain structure in fig. 13 as an example, the section XZY can simulate a partial perspective view of a section of a semiconductor device or a chip that contacts a tool bit when the semiconductor device or the chip is cut, and the acting surface of normal stress and shearing stress is the section. Positive stress may be concentrated in the Y-direction in the central region of the cross-section and shear stress in the X-direction in the top region of the cross-section. The coordinate direction in this embodiment may correspond to modeled coordinates in simulation software.
The first stressed region in embodiments of the present disclosure may be the positive stress concentration region of the cross-section of fig. 13, without limiting the top or lower equal edge regions of the cross-section to also be positively stressed; the second stressed region may be a concentrated region of shear stress in the cross-section of fig. 13, without limiting the lower region thereof to shear stress.
In the embodiment of the application, the first stress area may be located below the second stress area.
In some embodiments, step S103 may include the steps of:
a first test stress is applied to a first stressed region of the simulation model and a second test stress is applied to a second stressed region of the simulation model to determine deformation properties of the metal layer in the seal ring.
In the embodiment of the application, the reliability of the sealing ring is tested through the first test stress vertical to the stress surface of the simulation model and the second test stress parallel to the stress surface of the simulation model, so that the test condition is more similar to the real test condition, and the test result is more real and accurate.
In some embodiments, the point of application of the first test stress has a first predetermined distance from the first stressed region.
It should be noted that, when the wafer is cut, a certain distance is provided between the area cut by the cutting knife and the sealing ring, and the cutting is not directly performed along the side wall of the sealing ring, the area of action of the first test stress may be a cutting point of the cutting knife acting on the cutting area, and the first stress area has a first preset distance from the metal layer along the action direction of the first test stress.
In this embodiment, the first preset distance may include, for example, 6.5 μm, that is, a distance between the cutting blade and the side wall of the seal ring.
In some embodiments, the point of action of the second test stress is at the top of the plane in which the second stressed region lies, both the normal stress and the shear stress being 6.5um from the seal ring sidewall.
In some embodiments, the deformation properties of the metal layer include Feng Misai s stress of the metal layer. In this embodiment of the present application, under the action of the first test stress or the second test stress, when the Feng Misai s stress (equivalent stress) at a certain point inside the seal ring simulation model reaches the yield stress, the seal ring will enter the yield state, and at this time, unrecoverable plastic deformation will occur. The sealing ring of the embodiment of the disclosure absorbs larger mechanical energy by utilizing the deformation of the sealing ring on the premise that the metal layer has no crack, so as to reduce the mechanical damage of the semiconductor device in the sealing ring.
In other embodiments, the deformation properties of the metal layer include displacement, the larger the metal layer displacement, the larger the deformation of the metal seal ring structure.
In other embodiments, the deformation properties of the metal layer include Feng Misai stress and displacement. The deformation performance of the metal layer is jointly confirmed from two dimensions through Feng Misai S stress and displacement, so that reliability data of the sealing ring are more comprehensive, and a reliability test result is more accurate.
Step S104, confirming that the reliability of the sealing ring meets the requirement under the condition that the deformation performance meets the preset condition.
In some embodiments, when the deformation performance of the metal layer includes Feng Misai s stress, applying a first test stress to a first stressed region of the simulation model and/or applying a second test stress to a second stressed region of the simulation model to determine Feng Misai s stress of the metal layer in the seal ring, and then determining Feng Misai whether the s stress is less than a preset stress; and under the condition that the Feng Misai S stress is smaller than the preset stress, confirming that the reliability of the sealing ring meets the requirement.
It should be noted that the preset stress may be a preset stress value, for example, may be less than or equal to the yield stress.
In some embodiments, when the deformation properties of the metal layer include displacement, applying a first test stress to a first stressed region of the simulation model and/or applying a second test stress to a second stressed region of the simulation model to determine displacement of the metal layer in the seal ring; and then judging whether the displacement is larger than the preset displacement, and confirming that the reliability of the sealing ring meets the requirement under the condition that the displacement is larger than the preset displacement.
It should be noted that the preset displacement may be a preset displacement value.
In some embodiments, when the deformation properties of the metal layer include Feng Misai s stress and displacement, applying a first test stress to a first stressed region of the simulation model and/or applying a second test stress to a second stressed region of the simulation model to determine Feng Misai s stress and displacement of the metal layer in the seal ring, then determining Feng Misai s stress is less than a preset stress and determining whether displacement is greater than a preset displacement; and under the condition that the Feng Misai S stress is smaller than the preset stress and the displacement is larger than the preset displacement, confirming that the reliability of the sealing ring meets the requirement.
Because the embodiment of the application can define the simulation model of the sealing package based on the interconnection simulation tool, the stress distribution condition process of the actual cutting process can be simulated through the simulation model, so that the reliability of the sealing ring is evaluated, the testing time and the cost are reduced, and the method is simple, convenient and quick.
Referring to fig. 3 to 13, the process of establishing the seal ring simulation model 40 having a chain-like structure is explained below.
In some embodiments, constructing a simulation model of the seal ring from the seal ring actual structure includes:
step 1, defining a substrate 20 (shown in fig. 3) with a first preset thickness;
here, the substrate 20 may be a silicon-based material. The first preset thickness may be, for example, 10 μm.
Step 2, defining a plurality of metal layers 21 on the surface of the substrate 20; the metal layer 21 includes at least a first metal structure 211 and a second metal structure 212 alternately arranged at intervals; the first metal structure 211 and the second metal structure 212 extend along a first direction, and the second metal structure 212 extends along the first direction to the inside of the first metal structure 211; the first metal structure 211 overlaps with a projection portion of the adjacent second metal structure 212 in the third direction (Z direction); the third direction is perpendicular to a plane formed by the first direction and the second direction.
In this embodiment, each metal layer 21 includes a first metal structure 211 and a second metal structure 212, where the first metal structure 211 and the second metal structure 212 are arranged at intervals, not being a whole, and can provide a deformation space between the first metal structure 211 and the second metal structure 212, when cutting a wafer, compared with a massive metal strip, the first metal structure 211 and the second metal structure 212 can utilize gaps between the first metal structure 211 and the second metal structure to slide and dislocation under the effect of radial stress, and absorb and consume mechanical energy introduced in the cutting process in the forms of plastic work, surface energy and the like, so as to weaken mechanical damage of the internal structure of the semiconductor device during cutting, absorb cutting stress, resist crack invasion, and improve the yield of chips after cutting. The spacers may comprise silicon oxide or silicon nitride.
The projection part of the first metal structure 211 and the adjacent second metal structure 212 in the Z direction is overlapped, and after the stress brought by cutting acts on the first metal structure 211 or the second metal structure 212, the first metal structure 211 and the second metal structure 212 mutually reinforce to absorb more cutting stress, so that the protection performance of the sealing ring on mechanical damage is improved.
The second metal structure 212 further extends into the first metal structure 211 along the first direction, and after the cutting stress is absorbed by a portion of the first metal structure 211 and a portion of the second metal structure 212, the cutting stress can be absorbed by another portion of the first metal structure 211. The sealing ring in the embodiment of the application has the effect of more effectively isolating stress, and can effectively absorb the cutting stress.
In some embodiments, step 2 may be formed by: defining a first dielectric layer 22 with a second preset thickness on the surface of the substrate 20; etching (or analog etching) a portion of the thickness of the first dielectric layer 22 through the mask 30 having the preset pattern H (as shown in fig. 4 and 6) to form a first trench 23 (as shown in fig. 5 and 7); the first trenches 23 include first and second sub-trenches 231 and 232 alternately arranged at intervals; the first sub-trench 231 corresponds to the first metal structure 211, and the second sub-trench 232 corresponds to the second metal structure 212; forming a first metal structure 211 in the first sub-trench 231 and a second metal structure 212 in the second sub-trench 232 (as shown in fig. 8 and 9); next, the above-described steps of forming the first dielectric layer 22, the first trench 23, and the metal layer 21 are repeated a plurality of times to form a multi-layered metal layer 21 as shown in fig. 10 and 11.
Illustratively, the first dielectric layer 22 may be silicon oxide or other insulating material. The second predetermined thickness is smaller than the first predetermined thickness, for example, the second predetermined thickness may be 2 μm. The depth of the first trench 23 may be 0.8 μm.
In this embodiment, the mask 30 is a positive lithography mask, and the preset pattern H is opposite to the patterns of the first metal structure 211 and the second metal structure 212. In other embodiments, the mask 30 may also be a negative mask, and the preset pattern H is the same as the patterns of the first metal structure 211 and the second metal structure 212.
In some embodiments, referring to fig. 5, the first sub-trench 231 may be i-shaped and the first metal structure 211 is i-shaped; the second sub-trench 232 may be in-line, and the second metal structure 212 is in-line. In other embodiments, referring to fig. 7, the first sub-trench 231 is double-linear, and the first metal structure 211 is double-linear; the second sub-trench 232 is in a line shape, and the second metal structure 212 is in a line shape.
In some embodiments, a metal layer 21 is formed in the first trench 23, and in particular, the first sub-trench 231 and the second sub-trench 232 are filled with a metal material, which may be copper, to form the metal layer 21.
Step 3, defining a plurality of metal vias 26 between adjacent metal layers 21 to construct a simulation model of the seal ring.
In some embodiments, step 3 may comprise the steps of: referring to fig. 10, a second dielectric layer 24 having a third preset thickness is defined between adjacent first dielectric layers 22; referring to fig. 11 to 12, the metal layer 21, the first dielectric layer 22 and the second dielectric layer 24 are sequentially etched until the lowermost metal layer 21 is exposed, forming a plurality of second trenches 25; metal vias 26 are formed in the second trenches 25 to form a seal ring simulation model 40 of the chain-like structure. The second trench 25 may also be an opening.
The second dielectric layer 24 may be made of another insulating material such as silicon nitride. The third preset thickness may be smaller than the second preset thickness, for example, the third preset thickness may be 1.5 μm.
In this embodiment, the metal layer 21, the first dielectric layer 22 and the second dielectric layer 24 are etched sequentially until the metal layer 21 at the bottommost layer is exposed, which specifically includes: forming a photoresist layer with a specific pattern G (as shown in fig. 11) on the surfaces of the topmost first dielectric layer 22 and the metal layer 21, wherein the specific pattern G exposes a part of the first metal structure 211; next, the metal layer 21, the first dielectric layer 22 and the second dielectric layer 24 are etched sequentially from top to bottom until the bottommost metal layer 21 is exposed, forming a second trench 26 as shown in fig. 12, and removing the photoresist layer, and finally, filling a metal material in the second trench 25, forming a metal via 26 connecting adjacent metal layers 21.
In other embodiments, metal vias 26 may also be connected between second metal structures 212.
It should be noted that, in the embodiment of the disclosure, the height of the metal via 26 is 2.7 μm, and 2.7 μm refers to the height of the metal via 26 between two adjacent metal layers 21, that is, the spacing distance between two adjacent metal layers 21. The formation process of the metal via 26 is shown by way of example only with respect to the metal layer 21 corresponding to fig. 8, and the metal via 26 may be formed on the metal layer 21 corresponding to fig. 9 in the same manner.
In addition, the positions of the metal vias 26 shown in fig. 13 are connected between the first metal structures 211, and in practice, the metal vias 26 may also be connected between the second metal structures 212, and the positions of the metal vias 26 in the embodiment of the present application are not specifically limited.
Next, referring to fig. 14 to 17, a process of establishing a simulation model 50 of a seal ring having a block structure is described.
In some embodiments, constructing a simulation model of the seal ring from the seal ring actual structure includes:
step 1, defining a substrate 20 (as shown in fig. 14) with a first preset thickness;
here, the substrate 20 may be a silicon-based material. The first preset thickness may be, for example, 10 μm.
Step 2, defining a plurality of metal layers 21 (shown in fig. 16) on the surface of the substrate 20;
in some embodiments, step 2 may be formed by: defining a first dielectric layer 22 with a second preset thickness on the surface of the substrate 20; etching a portion of the thickness of the first dielectric layer 22 to form a third trench 33 (as shown in fig. 14); next, a metal material is filled in the third trench 33 to form a metal layer 21 (as shown in fig. 15); the steps of forming the first dielectric layer 22, the third trench 33, and the metal layer 21 are cycled to form a multi-layered metal layer 21 shown by rabbit 15. Here, the first dielectric layer 22 may be silicon oxide or other insulating material. The second predetermined thickness is smaller than the first predetermined thickness, for example, the second predetermined thickness may be 2 μm.
The depth of the third trench 33 may be 0.8 μm.
Step 3, defining a plurality of metal vias 26 between adjacent metal layers 21 to construct a simulation model of the seal ring.
In some embodiments, step 3 may comprise: defining a second dielectric layer 24 having a third predetermined thickness between adjacent first dielectric layers 22; sequentially etching the metal layer 21, the first dielectric layer 22 and the second dielectric layer 24 until the metal layer 21 at the bottommost layer is exposed, and forming a plurality of fourth grooves (not shown); metal vias 26 (as shown in fig. 17) are formed in the fourth trenches to form a seal ring simulation model 50 having a block-like structure.
In the simulation building process of the seal ring model in the embodiment of the application, a plurality of metal layers (including chain or block) are firstly manufactured, then film layers such as the metal layers and the first dielectric layer are etched to form grooves or openings, and the grooves or openings are filled to form metal vias. For example, in some practical manufacturing processes, a metal layer may be formed first, and a metal via may be formed on the metal layer, so that the metal layer and the metal via are formed in a stacked manner, and the metal via connects two adjacent metal layers.
It should be noted that the second dielectric layer 24 may be made of other insulating materials such as silicon nitride, and the third preset thickness may be smaller than the second preset thickness, for example, the third preset thickness may be 1.5 μm. The height of the metal vias 26 may be, for example, 2.7 μm, and 2.7 μm refers to the height of the metal vias 26 between two adjacent metal layers 21, that is, the spacing distance between two adjacent metal layers 21.
Next, referring to fig. 18 and 19, the dimensions of each structure in the simulation model 40 and the simulation model 50 are defined.
Referring to fig. 18, in the simulation model 40 of the seal ring, the overall width a1 of the first metal structure 211 is 7 μm, the length a2 of the first metal structure 211 is 30 μm, the width a3 of the thin side of the first metal structure 211 is 1.5 μm, the spacing a4 between the first metal structure 211 and the second metal structure 212 is 2.5 μm, and the spacing a5 between the first metal structures 211 is 35 μm. The second metal structure 212 has a length a6 of 30 μm and a width a7 of 1.5 μm. The metal vias 26 are square with a side length a8 of 5 μm and the spacing a5 between the metal vias 26 is 35 μm. The first metal structure 211 is in an i shape, which is beneficial to improving the mechanical stability of the metal layer and improving the overall stress resistance of the sealing ring.
It should be noted that, the simulation model 40 in the embodiment of the present disclosure is a structure with a length of 200 μm in the seal ring, where the actual structure of the seal ring is 7 μm in ring width, and the total width of the first dielectric layer and the seal ring is 30 μm. The force application side during cutting is the outer side of the sealing ring and is 6.5 mu m away from the sealing ring, and the main chip side is 16.5 mu m away from the sealing ring.
Referring to fig. 19, in the dummy model 50 of the seal ring, the width b1 of the metal layer 21 is 7 μm, the length of the metal layer 21 is 190um, and the size of the metal via 26 is the same as that in the dummy model 40.
Next, in a simulation environment Sentaurus Sinterconnect, visual, simulation conditions are: under the condition that the ambient temperature is 25 ℃ and the fixing mode is that the bottom is fixed, respectively applying normal stress F1 and shearing stress F2 to the stress surfaces outside the simulation model 40 and the simulation model 50, wherein the total force of the normal stress F1 is 5000dyne (dyne), and the total force of the shearing stress F2 is 5000dyne. The application areas of the positive stress and the shear stress on the stressed section can be set by using a coordinate system integrated by simulation software, and the application areas of the positive stress and the shear stress can not be identical.
The following tables 1 and 2 show the deformation performance test results of the simulation model 40 and the simulation model 50 under the above-described normal stress F1 and shear stress F2, respectively.
Table 1:
| normal stress f1=5000 dyne | Displacement/. Mu.m | Von mises stress/Pa |
| Simulation model 50 | 1.578e -2 | 3.075e +8 |
| Simulation model 40 | 1.637e -2 | 2.972e +8 |
Table 2:
| shear stress f2=5000 dyne | Displacement/. Mu.m | Von mises stress/Pa |
| Simulation model 50 | 3.421e -2 | 5.139e +8 |
| Simulation model 40 | 3.443e -2 | 4.915e +8 |
The above simulation results show that the i-shaped chain structure (i.e. simulation model 40) has a larger displacement and a smaller Feng Misai s stress than the block structure (i.e. simulation model 50) when the two seal rings are subjected to 5000dyne of normal stress F1 and shear stress F2 at the same position at a horizontal distance of 6.5 μm from the seal rings.
According to the embodiment of the disclosure, by establishing two sealing ring structure models and respectively carrying out stress tests on the two structure models, the sealing ring with the chain-shaped metal layer has smaller Feng Misai S stress and larger stress resistance. The first metal structure and the second metal structure of the chain-shaped metal layer are distributed at intervals, when the wafer is cut, compared with a massive metal strip, the first metal structure and the second metal structure can slide and dislocation by utilizing gaps between the first metal structure and the second metal structure under the action of radial stress, mechanical energy introduced in the cutting process is absorbed and consumed in the modes of plastic work, surface energy and the like, mechanical damage of the internal structure of the semiconductor device in cutting is weakened, cutting stress is absorbed, invasion of cracks is resisted, and the yield of chips after cutting is improved. The spacer may comprise an insulating material. The first metal structure of the I-shaped structure has higher mechanical stability, and the metal via holes between the metal layers between two adjacent layers provide support for the metal layers, so that the overall mechanical stability and the stress resistance of the sealing ring are improved. In several embodiments provided herein, it should be understood that the disclosed structures and methods may be implemented in a non-targeted manner. The above-described structural embodiments are merely illustrative, and for example, the division of units is merely a logic function division, and there may be other division manners in actual implementation, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the components shown or discussed are coupled to each other or directly.
Features disclosed in several method or structural embodiments provided in the present application may be combined arbitrarily without any conflict to obtain new method embodiments or structural embodiments.
The foregoing is merely some embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes or substitutions should be covered in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (11)
1. A method of evaluating reliability of a seal ring, the method comprising:
constructing a simulation model of the sealing ring according to the actual structure of the sealing ring; the simulation model at least comprises a plurality of metal layers which extend along a first direction and are stacked along a second direction, and metal vias positioned on two adjacent metal layers;
defining test stress and test temperature of the simulation model;
applying the test stress to the stress surface of the simulation model at the test temperature to determine the deformation performance of the metal layer in the sealing ring; the stress surface of the simulation model is parallel to a plane formed by the first direction and the second direction;
and under the condition that the deformation performance meets the preset condition, confirming that the reliability of the sealing ring meets the requirement.
2. The method of claim 1, wherein the testing stress comprises: a first test stress and/or a second test stress;
applying the test stress to a force bearing surface of the simulation model to determine deformation properties of the metal layer in the seal ring, comprising:
applying the first test stress to a first stressed region of the simulation model to determine deformation properties of the metal layer in the seal ring; and/or
Applying the second test stress to a second stress region of the simulation model to determine deformation properties of the metal layer in the seal ring;
the first stress area and the second stress area are both positioned in the stress surface of the simulation model, and the first stress area is positioned below the second stress area.
3. The method of claim 2, wherein the first test stress acts in a direction perpendicular to the first stressed region; the second test stress acts in a direction parallel to the second stressed region.
4. A method according to claim 3, wherein the force-receiving surface has a first predetermined distance from the metal layer in the direction of action of the first test stress.
5. The method according to any one of claims 1 to 4, wherein the deformation properties comprise Feng Misai s stress and/or displacement; under the condition that the deformation performance meets the preset condition, confirming that the reliability of the sealing ring meets the requirement comprises the following steps:
under the condition that the Feng Misai S stress is smaller than a preset stress, confirming that the reliability of the sealing ring meets the requirement; and/or
And under the condition that the displacement is larger than the preset displacement, confirming that the reliability of the sealing ring meets the requirement.
6. The method of claim 1, wherein constructing a simulation model of the seal ring based on the seal ring actual structure comprises:
defining a substrate having a first predetermined thickness;
defining a plurality of metal layers on the surface of the substrate; the metal layer at least comprises a first metal structure and a second metal structure which are alternately arranged at intervals; the first metal structure and the second metal structure extend along a first direction, and the second metal structure extends into the first metal structure along the first direction; the projection part of the first metal structure and the adjacent second metal structure in the third direction is overlapped; the third direction is perpendicular to a plane formed by the first direction and the second direction;
and defining a plurality of metal through holes between adjacent metal layers to construct a simulation model of the sealing ring.
7. The method of claim 6, wherein defining a plurality of the metal layers on the substrate surface comprises:
defining a first dielectric layer with a second preset thickness on the surface of the substrate;
etching part of the first dielectric layer with the thickness through a mask with a preset pattern to form a first groove; the first grooves comprise first sub-grooves and second sub-grooves which are alternately arranged at intervals; and forming the first metal structure in the first sub-groove and forming the second metal structure in the second sub-groove.
8. The method of claim 7, wherein the first metal structure is i-shaped and the second metal structure is in-line.
9. The method of claim 7, wherein the first metal structure is double-lined and the second metal structure is lined.
10. The method of claim 7, wherein defining a plurality of metal vias between adjacent ones of the metal layers to form a simulation model of a seal ring comprises:
defining a second dielectric layer with a third preset thickness between adjacent first dielectric layers;
sequentially etching the metal layer, the first dielectric layer and the second dielectric layer until the bottommost metal layer is exposed, so as to form a plurality of second grooves;
and forming the metal via hole in the second groove to form the simulation model.
11. A method according to any one of claims 6 to 10, wherein the simulation model is part of the actual structure of the seal ring.
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070012117A1 (en) * | 2003-09-29 | 2007-01-18 | Tolyo Electron Limited | Sealing ring and its managing system |
| CN101355059A (en) * | 2004-11-16 | 2009-01-28 | 恩益禧电子股份有限公司 | Semiconductor device |
| US20090294897A1 (en) * | 2008-05-29 | 2009-12-03 | Tung-Hsing Lee | Seal ring structure for integrated circuits |
| US8093719B1 (en) * | 2004-12-10 | 2012-01-10 | Cypress Semiconductor Corporation | Seal ring for preventing crack propagation in integrated circuit devices |
| US20140246752A1 (en) * | 2013-03-01 | 2014-09-04 | International Business Machines Corporation | Segmented guard ring structures with electrically insulated gap structures and design structures thereof |
| CN105870069A (en) * | 2015-01-22 | 2016-08-17 | 中芯国际集成电路制造(上海)有限公司 | Protection structure for chip in cutting process |
| CN106252297A (en) * | 2015-06-10 | 2016-12-21 | 台湾积体电路制造股份有限公司 | Semiconductor device and manufacture method thereof |
| CN208706621U (en) * | 2018-09-20 | 2019-04-05 | 长鑫存储技术有限公司 | Chip seal ring structure and semiconductor chip |
| US20210384146A1 (en) * | 2020-05-25 | 2021-12-09 | United Microelectronics Corp. | Integrated circuit device and fabrication method thereof |
| CN115165182A (en) * | 2022-06-13 | 2022-10-11 | 长三角先进材料研究院 | High-efficiency and high-spatial-resolution residual stress measurement method |
-
2023
- 2023-08-31 CN CN202311125674.XA patent/CN117371171B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070012117A1 (en) * | 2003-09-29 | 2007-01-18 | Tolyo Electron Limited | Sealing ring and its managing system |
| CN101355059A (en) * | 2004-11-16 | 2009-01-28 | 恩益禧电子股份有限公司 | Semiconductor device |
| US8093719B1 (en) * | 2004-12-10 | 2012-01-10 | Cypress Semiconductor Corporation | Seal ring for preventing crack propagation in integrated circuit devices |
| US20090294897A1 (en) * | 2008-05-29 | 2009-12-03 | Tung-Hsing Lee | Seal ring structure for integrated circuits |
| US20140246752A1 (en) * | 2013-03-01 | 2014-09-04 | International Business Machines Corporation | Segmented guard ring structures with electrically insulated gap structures and design structures thereof |
| CN105870069A (en) * | 2015-01-22 | 2016-08-17 | 中芯国际集成电路制造(上海)有限公司 | Protection structure for chip in cutting process |
| CN106252297A (en) * | 2015-06-10 | 2016-12-21 | 台湾积体电路制造股份有限公司 | Semiconductor device and manufacture method thereof |
| CN208706621U (en) * | 2018-09-20 | 2019-04-05 | 长鑫存储技术有限公司 | Chip seal ring structure and semiconductor chip |
| US20210384146A1 (en) * | 2020-05-25 | 2021-12-09 | United Microelectronics Corp. | Integrated circuit device and fabrication method thereof |
| CN115165182A (en) * | 2022-06-13 | 2022-10-11 | 长三角先进材料研究院 | High-efficiency and high-spatial-resolution residual stress measurement method |
Non-Patent Citations (2)
| Title |
|---|
| IDIR RAID等: "Seal Rings Toughness Characterization by Numerical and Experimental Approaches", 2018 IEEE 68TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, 9 August 2018 (2018-08-09), pages 1 - 8 * |
| SÉBASTIEN GALLOIS-GARREIGNOT;VINCENT FIORI;GIL PROVENT;ROBERTO GONELLA;: "晶圆级封装:热机械失效模式和挑战及整改建议", 中国集成电路, no. 12, 5 December 2017 (2017-12-05), pages 70 - 75 * |
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