CN117316992A - A dual-gate structure silicon carbide MOSFET device and its preparation method - Google Patents
A dual-gate structure silicon carbide MOSFET device and its preparation method Download PDFInfo
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- CN117316992A CN117316992A CN202311609265.7A CN202311609265A CN117316992A CN 117316992 A CN117316992 A CN 117316992A CN 202311609265 A CN202311609265 A CN 202311609265A CN 117316992 A CN117316992 A CN 117316992A
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/512—Disposition of the gate electrodes, e.g. buried gates
- H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
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- H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
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- H10D12/031—Manufacture or treatment of IGBTs
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- H—ELECTRICITY
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- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/63—Vertical IGFETs
- H10D30/635—Vertical IGFETs having no inversion channels, e.g. vertical accumulation channel FETs [ACCUFET] or normally-on vertical IGFETs
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- H—ELECTRICITY
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- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
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Abstract
The application provides a silicon carbide MOSFET device with a double-gate structure and a preparation method thereof, wherein the device comprises a drain electrode, and N is arranged on the surface of the drain electrode + A substrate, the N + The surface of the substrate is provided with N ‑ Epitaxial layer of N ‑ An electric field modulation region is arranged in the epitaxial layer, and the electric field modulation region is arranged in the N ‑ The electric field modulation areas comprise an N area and a P area at two sides of the epitaxial layer; the N is ‑ The surface of the epitaxial layer is provided with a P well region, and N is arranged in the P well region + A source region; the P well region and the N + A source electrode is arranged on the surface of the source region; the P well region and the N + A trench is arranged in the center of the source region, and the bottom of the trench extends into the N ‑ An epitaxial layer; the electric field modulation region shortens the power when a current flows to the silicon carbide MOSFET deviceFlow from the P-well region to the N-well region + Distance of the substrate.
Description
Technical Field
The application relates to the field of semiconductors, in particular to a silicon carbide MOSFET device with a double-gate structure and a preparation method thereof.
Background
The characteristics of wide forbidden band, high thermal conductivity, high saturated electron velocity, high breakdown electric field and the like of the silicon carbide (SiC) material determine that the SiC device can work at high temperature and high power, and the SiC device has wide application in industrial production. SiC MOSFET products have key system advantages such as being able to achieve miniaturization, lighter weight, and higher integration, and thus are increasingly being used in industrial production.
In the field of reliability of gate oxide layers, gate SiO in SiC MOSFETs 2 The electric field intensity born by the surface is about 2.5 times of the corresponding electric field intensity of the SiC surface, and the silicon carbide material has high critical breakdown electric field intensity, so that the grid SiO in the SiC MOSFET 2 The intensity of the electric field is extremely high, compared with the grid SiO in the Si MOSFET 2 The strength of the electric field is an order of magnitude higher. Most of the problems of SiC MOSFETs are directly related to the gate oxide, and the early failure of a large number of gate oxide layers has been hampering the improvement of reliability of SiC MOSFETs for many years.
Disclosure of Invention
In view of the foregoing, the present application has been developed to provide a silicon carbide MOSFET device of a dual gate structure and a method of fabricating the same that overcome or at least partially solve the foregoing, comprising:
a silicon carbide MOSFET device with double gate structure comprises a drain electrode with N on its surface + A substrate, the N + The surface of the substrate is provided with N - Epitaxial layer of N - An electric field modulation region is arranged in the epitaxial layer, and the electric field modulation region is arranged in the N - The electric field modulation areas comprise an N area and a P area at two sides of the epitaxial layer; the N is - The surface of the epitaxial layer is provided with a P well region, and N is arranged in the P well region + A source region; the P well region and the N + A source electrode is arranged on the surface of the source region;
the P well region and the N + A groove is arranged in the center of the source region, the top of the groove stretches into the source electrode, and the bottom of the groove stretches into the N - And within the epitaxial layer.
Further, a bottom portion of the trench extends into the N - Within the epitaxial layer but not withThe electric field modulation areas are connected.
Further, a shielding grid and a control grid are arranged in the groove, the control grid is arranged above the shielding grid, shielding grid dielectric layers are filled around the shielding grid, grid source electrode dielectric layers are filled around the control grid, and a grid isolation oxide layer is arranged between the shielding grid and the control grid.
Further, the source electrode is provided with a source electrode contact hole, and the shielding grid is connected with the source electrode through the source electrode contact hole; the control gate is provided with a gate contact hole, and is connected with a gate metal electrode through the gate contact hole;
when avalanche occurs, displacement current flows directly from the shield gate to the source through the contact hole.
Further, polysilicon deposition and N-type implantation diffusion are carried out in the groove area of the shielding gate to form the shielding gate, and N-type implantation element ions are nitrogen, phosphorus and arsenic;
polysilicon is deposited in the groove of the control gate, P-type injection and diffusion are carried out to form the control gate, and P-type injection element ions are boron and aluminum; the distance between the shielding grid and the control grid is 0.4-0.8 mu m, and the thickness of the grid source electrode dielectric layer is 0.1-0.3 mu m.
Further, the shielding gate dielectric layer is formed by gate dielectric deposition injection, and the thickness of the shielding gate dielectric layer is 0.1-0.3 mu m; and depositing an oxide layer in the gate groove region where the shielding gate is deposited to form the gate isolation oxide layer, wherein the thickness of the gate isolation oxide layer is 0.3-0.5 mu m.
Further, the N is - The thickness of the epitaxial layer is 10-100 μm.
Further, in the electric field modulation region, the P region is close to a groove wall side and surrounded by the N region; the length of the electric field modulation region is 4-6 mu m, the distance between the bottom of the N region and the bottom of the N-epitaxial layer is more than 3 mu m, and the distance between the bottom of the P region and the bottom of the N region is 0.5-2 mu m.
Further, the N region implanted ions in the electric field modulation region are nitrogen ions, and the P region implanted ions in the electric field modulation region are boron ions.
The application also provides a preparation method of the silicon carbide MOSFET device with the double-gate structure, which comprises the following steps:
selecting heavily doped silicon carbide as the N + A substrate, and at said N + The N is grown on the surface of the substrate through epitaxy - An epitaxial layer;
at said N - Setting a mask on the epitaxial layer, carrying out trench photoetching and etching, and then respectively preparing an N region and a P region of the electric field modulation region in a deep ion implantation mode;
at said N - Carrying out groove photoetching and etching on the epitaxial layer to form the groove;
at said N - The surface of the epitaxial layer forms the P well region by means of aluminum injection and diffusion, and forms the N region by means of nitrogen ion injection and diffusion + A source region;
by etching and metal deposition, in the N + Preparing the drain electrode on the bottom surface of the substrate, and covering the P well region and the N well region + And preparing the source electrode on the surface of the source region.
The application has the following advantages:
in the embodiment of the present application, compared to the problem that the existing SiC MOSFET product is prone to breakdown during the application process, the present application provides a solution for a silicon carbide MOSFET device structure with a dual gate structure, specifically: comprises a drain electrode, the surface of the drain electrode is provided with N + A substrate, the N + The surface of the substrate is provided with N - Epitaxial layer of N - An electric field modulation region is arranged in the epitaxial layer, and the electric field modulation region is arranged in the N - The electric field modulation areas comprise an N area and a P area at two sides of the epitaxial layer; the N is - The surface of the epitaxial layer is provided with a P well region, and N is arranged in the P well region + A source region; the P well region and the N + A source electrode is arranged on the surface of the source region; the P well region and the N + A groove is arranged in the center of the source region, the top of the groove stretches into the source electrode, and the bottom of the groove stretches into the N - An epitaxial layer; the electric field modulation region shortens the current when the current flows to the silicon carbide MOSFET deviceFrom the P-well region to the N-well region + Distance of the substrate.
Drawings
For a clearer description of the technical solutions of the present application, the drawings that are needed in the description of the present application will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained from these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a conventional trench-gate MOSFET structure provided in an embodiment of the present application;
fig. 2 is a schematic structural diagram of a preparation electric field modulation region of a silicon carbide MOSFET device with a dual gate structure according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a dual-gate silicon carbide MOSFET device according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a control gate of a silicon carbide MOSFET device with a dual gate structure according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a silicon carbide MOSFET device with a dual gate structure according to an embodiment of the present disclosure;
fig. 6 is a flow chart illustrating steps of a method for fabricating a silicon carbide MOSFET device with a dual gate structure according to an embodiment of the present application.
In the figure, 101, drain; 102. n (N) + A substrate; 103. n (N) - An epitaxial layer; 104. an N region; 105. a P region; 106. a P well region; 107. n (N) + A source region; 108. a source electrode; 109. a shielding gate dielectric layer; 110. a shield grid; 111. a gate isolation oxide layer; 112. a control gate; 113. and a gate source electrode dielectric layer.
Detailed Description
In order that the manner in which the above recited objects, features and advantages of the present application are obtained will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to the appended drawings. It will be apparent that the embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
The inventors found by analyzing the prior art that:
conventional trench-gate MOSFET structure as shown in fig. 1, a silicon carbide trench MOSFET is a vertical MOSFET in which the source region is located on the top surface of the semiconductor substrate and the drain region is located on the bottom surface of the semiconductor substrate. A body region is formed in the semiconductor substrate between the source and drain. Since silicon carbide material has high critical breakdown field strength, gate SiO in SiC MOSFETs 2 The electric field intensity born is extremely high, breakdown is most likely to occur in the application process, so that better gate oxide protection needs to be explored, and the performance and reliability of the device are improved.
To this end, FIG. 5 shows a silicon carbide MOSFET device of a dual gate structure according to an embodiment of the present application, comprising a drain 101 having N on its surface + A substrate 102, the N + The surface of the substrate 102 is provided with N - Epitaxial layer 103, N - An electric field modulation region is arranged in the epitaxial layer 103, and the electric field modulation region is arranged in the N - The two sides of the epitaxial layer 103, the electric field modulation region comprises an N region 104 and a P region 105; the N is - The surface of the epitaxial layer 103 is provided with a P well region 106, and N is arranged in the P well region 106 + A source region 107; the P-well region 106 and the N-well region + The surface of the source region 107 is provided with a source 108;
the P-well region 106 and the N-well region + A trench is arranged in the center of the source region 107, the top of the trench extends into the source electrode 108, and the bottom of the trench extends into the N - Within epitaxial layer 103.
In the embodiment of the present application, compared to the problem that the existing SiC MOSFET product is prone to breakdown during the application process, the present application provides a solution for a silicon carbide MOSFET device structure with a dual gate structure, specifically: comprises a drain 101 with N on its surface + A substrate 102, the N + The surface of the substrate 102 is provided with N - Epitaxial layer 103, N - An electric field modulation region is arranged in the epitaxial layer 103, and the electric field modulation region is arranged in the N - Epitaxial layer 103The electric field modulation regions comprise an N region 104 and a P region 105; the N is - The surface of the epitaxial layer 103 is provided with a P well region 106, and N is arranged in the P well region 106 + A source region 107; the P-well region 106 and the N-well region + The surface of the source region 107 is provided with a source 108; the P-well region 106 and the N-well region + A trench is arranged in the center of the source region 107, the top of the trench extends into the source electrode 108, and the bottom of the trench extends into the N - Within epitaxial layer 103; when current flows to the silicon carbide MOSFET device, the electric field modulation region shortens the current flowing from the P-well region to the N-well region + Distance of the substrate.
Next, a silicon carbide MOSFET device of a double-gate structure in the present exemplary embodiment will be further described.
The silicon carbide MOSFET device with the double-gate structure of the embodiment comprises a drain electrode 101 and silicon carbide N + Substrate 102, N - Epitaxial layer 103, electric field modulation region, shielding gate dielectric layer 109, shielding gate 110, gate isolation oxide layer 111, control gate 112, P well region 106, N + Source region 107, gate source dielectric layer 113 and source 108.
In the present embodiment, N is etched + And (3) carrying out metal deposition on the back surface of the substrate 102 to form the drain electrode 101. The metal deposition thickness of the drain electrode is 20-200nm. Preferably, the electrode material is Ti/Ag, the deposition thickness of Ti metal is 20-50 nm, and the deposition thickness of Ag metal is 100-200 nm.
In the present embodiment, silicon carbide N + The substrate 102 is subjected to low temperature surface pretreatment and then to epitaxial growth of an epitaxial layer. The N is + The substrate 102 is a heavily doped silicon carbide wafer, and after low-temperature surface pretreatment, epitaxial growth of an epitaxial layer is performed on the substrate, and the substrate can provide mechanical support for each layer of material above the substrate so as to ensure the structural stability of the device.
In the present embodiment, N - The epitaxial layer 103 is obtained by epitaxial growth of silicon carbide. N (N) - Epitaxial layer 103 is located on silicon carbide N + On the substrate 102, N - The thickness of the epitaxial layer 103 is 10-100 μm. Before the epitaxial growth of the oxide layer, the oxide layer is subjected to low-temperature N 2 /NH 3 And the plasma (200-400 ℃) treatment and the inert Ar gas atmosphere low-temperature (600-1000 ℃) annealing effectively reduce the influence of surface impurity ions and interface states on the performance of the device. After surface treatment, in N - The upper surface of the epitaxial layer 103 is subjected to trench lithography and etching to form the trenches simultaneously.
N - Epitaxial layer 103 is at N + The surface of the substrate 102 after growth is flat and has no trenches thereon; the groove is N - The surface of the epitaxial layer 103 after growth is formed by photolithography and etching at specific positions. The trenches can be divided into active region trenches (P-well region/N + Source/gate, etc.), termination trenches, etc.
N - Epitaxial layer 103 is the main voltage bearing region of the SiCMOSFET. In the off state, the applied voltage falls mainly at N - On the epitaxial layer 103, in the on state, the current mainly passes through N - Epitaxial layer 103 conducts. By adjusting N - The doping concentration and thickness of the epitaxial layer 103 can optimize the switching speed, on-resistance, withstand voltage and other performances of the device.
In this embodiment, the electric field modulation region is located in the N - Within epitaxial layer 103, two portions are included, N region 104 and P region 105. Wherein the P region 105 is surrounded by the N region 104 on the near-groove wall side. The depth of the P region 105 and the N region 104 of the modulation region is controlled by a deep ion implantation method. Wherein the length of the electric field modulation region is 4-6 μm.
N region 104 in the electric field modulation region - Within epitaxial layer 103, a near-source structure is provided, preferably N regions 104 and N - The distance at the bottom of the epitaxial layer 103 is greater than 3 μm. The P region 105 is adjacent to the cell wall side and surrounded by the N region 104, and the distance from the bottom of the P region 105 to the bottom of the N region 104 is preferably 0.5-2 μm. The depth of the P region 105 and the N region 104 of the modulation region is controlled by deep ion implantation.
The N region 104 and the P region 105 of the electric field modulation region are used to control the current flow. The N region 104 is an N-type semiconductor region, in which electrons are the main carriers for electron injection or collection. The P region 105 is a P-type semiconductor region in which holes are the primary carriers for controlling the flow of electrons. The electric field modulation region controls the flow of electrons from the source 113 to the drain 101 by varying the electric field strength between the N region 104 and the P region 105.
By at N - Epitaxial layer 103 increases the electric field modulation region, thereby shortening the current flow from P-well region 106 through N + The distance of the substrate 102 can reduce the channel resistance, effectively shield the gate oxide electric field and reduce the damage degree at the gate oxide layer.
In this embodiment, the P-well region 106 is disposed in the N-well region - The upper surface of epitaxial layer 103, and the P-well region 106 is also connected to the electric field modulation region. The P-well region 106 isolates the electric field modulation by the P-type shielding layer and forms a P-well by means of aluminum injection and diffusion. P-well region 106 and N + A PN junction is formed between the source regions 107, and when a proper voltage is applied to the gate, the P-well region 106 forms an N-type channel on its surface, so that current conduction is achieved.
In this embodiment, the P-well region is provided with N + A source region 107; specifically, nitrogen implantation and diffusion are performed in the fixed region between the trench gate and the P-well region 106 to form N + Source region 107. When a suitable voltage is applied across the gate structure, a conductive path is formed between the source 108 and the drain 101, allowing electrons to flow from the source 108 to the drain 101, allowing current to flow. N (N) + Source region 107 is a highly doped N-type semiconductor that contains a large number of free electrons and can provide a source of large current. This highly doped design can increase the switching speed and current carrying capability of the MOSFET, thereby increasing its performance.
In the present embodiment, in the P-well region 106 and the N-well region + The source 108 is provided on the surface of the source region 107. Source 108 metal electrodes are prepared by metal deposition by forming source contact holes by photolithography and etching. The preferred electrode material is Ti/Ag, the deposition thickness of Ti metal is 20-50 nm, and the deposition thickness of Ag metal is 100-200 nm.
The source electrode 108 is provided with a source electrode contact hole, and the shielding gate 110 is connected with the source electrode 108 through the source electrode contact hole; the control gate 112 is provided with a gate contact hole, and the control gate 112 is connected with a gate metal electrode through the gate contact hole; when avalanche occurs, displacement current flows directly from the shield gate 110 to the source 108 through the contact hole connecting the shield gate and the source.
The contact holes are divided into a source contact hole and a gate (a control gate 112 and a shielding gate 110) contact hole, and the two contact holes are respectively opened at the top of the corresponding structure and respectively communicated with the source metal layer and the gate metal layer. The shield gate 110 is connected to the source 108 metal through a contact hole, and the control gate 112 is connected to the gate metal through a contact hole, which is divided into a source contact hole and a gate contact hole because the bottom positions of the contact holes are different.
In this embodiment, a shielding gate 110 and a control gate 112 are disposed in the trench, the control gate is disposed above the shielding gate 110, a shielding gate dielectric layer 109 is filled around the shielding gate 110, a gate source dielectric layer 113 is filled around the control gate 112, and a gate isolation oxide layer 111 is disposed between the shielding gate 110 and the control gate 112.
The present invention provides for two gates, a shield gate 110 and a control gate 112, wherein the shield gate 110 is located below the control gate 112. The shield gate 110 may reduce the miller capacitance Cgd, thereby reducing the power loss, i.e., switching loss, caused by the miller plateau. In addition, the polysilicon of the shielding gate 110 is connected with the metal of the source electrode 108 through the contact hole, the contact resistance between the shielding gate 110 and the source electrode 108 is uniform and much smaller than that of the conventional structure, when avalanche occurs, displacement current directly flows from the shielding gate 110 to the metal of the source electrode 108 through the contact hole, the induced potential distribution along the shielding gate 110 is low and uniform, and therefore, the current concentration caused by the fixed avalanche point due to non-uniform potential distribution can be effectively avoided. The control gate 112 is responsible for controlling the on and off of the main switch, thereby ensuring the normal use of the device performance.
The preparation of the double gate and the source electrode 108 is operated on the active region after the oxidation treatment, and a gate groove is formed through photoetching and etching; source and gate (control gate and shield gate) contact holes are formed by photolithography and etching. Different positions and depths can be selected when the contact holes are etched, so that different structures are connected.
The shielding gate 110 is obtained by polysilicon deposition, and nitrogen ion diffusion is performed to form the shielding gate 110, and the preferable N-type implanted element ions are nitrogen, phosphorus and arsenic; performing P-type implantation and diffusion to form a control gate 112 through polysilicon deposition, wherein preferred P-type implantation element ions are boron and aluminum; the gate isolation oxide layer 111 is formed through a gate oxide process.
In a specific implementation, gate dielectric deposition injection is performed in the etched gate trench region to form a shielding gate dielectric layer 109;
depositing a grid isolation oxide layer 111 in a grid groove region where the shielding grid 109 is deposited, and forming a control grid groove through photoetching and etching a window;
p-type polysilicon is deposited in the etched control gate groove to form a control gate 112, and a gate source dielectric layer 113 is formed between the control gate and the upper source 108 after surface treatment, wherein the step can be performed with the P well 106 and N + The source dielectric layers of source regions 107 are formed simultaneously.
Wherein the thickness of the shielding gate dielectric layer 109 and the gate source dielectric layer 113 is 0.1-0.3 μm, the distance between the shielding gate 110 and the control gate 112 is 0.4-0.8 μm, the thickness of the gate isolation oxide layer 111 is 0.3-0.5 μm, the shielding gate 110 is connected to the source 108 through a contact hole, the control gate 112 is led out to the gate metal electrode through a gate contact hole, and is isolated from the source 108 through the gate source dielectric layer 113.
The device performance after pretreatment before gate oxidation is stronger, the interface state density is reduced, and the comprehensive performance of the device is improved;
and by at N - Epitaxial layer 103 adds electric field modulation regions 104 and 105, thereby shortening the current flow from P-well region 106 through N + The distance of the substrate 102 can reduce the channel resistance, effectively shield the gate oxide electric field and reduce the damage degree of the gate oxide layer;
finally, by providing a double gate structure of the shield gate 110 and the control gate 112, the gate voltage resistance can be enhanced, the forward conduction current density can be increased, and the switching speed and avalanche resistance can be increased, thereby improving the performance of the silicon carbide MOSFET device.
Referring to fig. 6, the present invention further illustrates a method for manufacturing a silicon carbide MOSFET device with a dual gate structure according to an embodiment of the present application;
the method comprises the following steps:
selecting heavily doped silicon carbide as the N + A substrate 102, and at said N + The surface of the substrate 102 is grown by epitaxy - An epitaxial layer 103;
at said N - The epitaxial layer 103 is provided with a mask, is subjected to trench photoetching and etching, and then an N region 104 and a P region 105 of the electric field modulation region are respectively prepared in a deep ion implantation mode;
at said N - Carrying out groove photoetching and etching on the epitaxial layer 103 to form the groove;
at said N - The surface of the epitaxial layer 103 forms the P-well region 106 by aluminum implantation and diffusion, and forms the N by nitrogen ion implantation and diffusion + A source region 107;
by etching and metal deposition, in the N + The drain 101 is prepared on the bottom surface of the substrate 102 and covers the P-well region 106 and the N-well region + The source 108 is prepared on the surface of the source region 107.
Next, a method for manufacturing a silicon carbide MOSFET device of a double-gate structure in this exemplary embodiment will be further described.
First, regarding the selected silicon carbide as N + The substrate 102 is subjected to a pre-oxidation cleaning and pretreatment process.
In silicon carbide N + Growth of N by epitaxy on substrate 102 - An epitaxial layer 103 on the oxidized active region, and surface-treated with N - Carrying out groove photoetching and etching on the epitaxial layer 103, and etching a gate groove by arranging different mask patterns;
by deep ion implantation method - N regions 104 of the electric field modulation region are respectively prepared on two sides of the interior of the epitaxial layer 103, as shown in fig. 2, and after surface treatment, P regions 105 are generated in the N regions 104 close to the groove wall side in an ion implantation mode;
in the P well region and the N + A shielding gate dielectric layer 1 is manufactured in the trench in the center of the source region 10709, photoetching and etching to form a shielding gate window, then carrying out polysilicon deposition on the etched gate groove window, and carrying out nitrogen ion implantation diffusion to form an N-type shielding gate 110, wherein the N-type shielding gate 110 is connected to a source electrode 108 through a contact hole as shown in fig. 3;
depositing a grid isolation oxide layer 111 in a grid groove region where the shielding grid 110 is deposited, forming a groove of a control grid 112 through photoetching and etching, depositing polysilicon in the etched control grid groove, and then forming a P-type control grid 112 through aluminum ion implantation diffusion, wherein the P-type control grid 112 is connected to a grid metal electrode through a grid contact hole as shown in fig. 4;
by means of aluminium ion implantation and diffusion in N - A P-well region 106 is formed on the surface of the epitaxial layer 103 to N + Source region 107 is lithographically implanted with nitrogen ions and diffused to form N + A source region 107;
after surface treatment, a gate source dielectric layer 113 is formed, and contact holes are formed through photoetching and etching;
etching N + Manufacturing a drain electrode 101 alloy on the back of a substrate 102 to form a drain electrode metal electrode; source 108 metal is deposited to form a source metal electrode, the structure of which is shown in fig. 5.
While preferred embodiments of the present embodiments have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the present application.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.
The silicon carbide MOSFET device with the double-gate structure and the preparation method thereof provided by the application are described in detail, and specific examples are applied to illustrate the principles and the implementation modes of the application, and the description of the examples is only used for helping to understand the method and the core idea of the application; meanwhile, as those skilled in the art will have modifications in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.
Claims (10)
1. The silicon carbide MOSFET device with the double-gate structure is characterized by comprising a drain electrode, wherein N is arranged on the surface of the drain electrode + A substrate, the N + The surface of the substrate is provided with N - Epitaxial layer of N - An electric field modulation region is arranged in the epitaxial layer, and the electric field modulation region is arranged in the N - The electric field modulation areas comprise an N area and a P area at two sides of the epitaxial layer; the N is - The surface of the epitaxial layer is provided with a P well region, and N is arranged in the P well region + A source region; the P well region and the N + A source electrode is arranged on the surface of the source region;
the P well region and the N + A trench is arranged in the center of the source region, and the bottom of the trench extends into the N - And within the epitaxial layer.
2. The dual gate silicon carbide MOSFET device of claim 1, wherein a bottom portion of said trench extends into said N - Within the epitaxial layer but not connected to said electric field modulation region.
3. The silicon carbide MOSFET device with the double-gate structure according to claim 1, wherein a shielding gate and a control gate are arranged in the groove, the control gate is arranged above the shielding gate, a shielding gate dielectric layer is filled around the shielding gate, a gate source dielectric layer is filled around the control gate, and a gate isolation oxide layer is arranged between the shielding gate and the control gate.
4. A silicon carbide MOSFET device according to claim 3 wherein said source is provided with a source contact hole and said shield gate is connected to said source through said source contact hole; the control gate is provided with a gate contact hole, and is connected with a gate metal electrode through the gate contact hole;
when avalanche occurs, displacement current flows directly from the shield gate to the source through the contact hole.
5. The silicon carbide MOSFET device of claim 3, wherein polysilicon deposition and N-type implant diffusion are performed in a trench region of said shield gate to form said shield gate, N-type implant elemental ions being nitrogen, phosphorus, and arsenic;
polysilicon is deposited in the groove of the control gate, P-type implantation diffusion is carried out to form the control gate, and P-type implantation element ions are boron and aluminum; the distance between the shielding grid and the control grid is 0.4-0.8 mu m, and the thickness of the grid source electrode dielectric layer is 0.1-0.3 mu m.
6. The silicon carbide MOSFET device with the double-gate structure according to claim 3, wherein the shielding gate dielectric layer is formed by gate dielectric deposition injection, and the thickness of the shielding gate dielectric layer is 0.1-0.3 μm; and depositing an oxide layer in the gate groove region where the shielding gate is deposited to form the gate isolation oxide layer, wherein the thickness of the gate isolation oxide layer is 0.3-0.5 mu m.
7. The dual gate silicon carbide MOSFET device of claim 1, wherein said N - The thickness of the epitaxial layer is 10-100 μm.
8.The silicon carbide MOSFET device of claim 1, wherein in said electric field modulation region, said P region is adjacent to a sidewall of a trench and surrounded by said N region; wherein the length of the electric field modulation region is 4-6 μm, the bottom of the N region and the N - The distance from the bottom of the epitaxial layer to the bottom of the N region is 0.5-2 mu m, and the distance from the bottom of the P region to the bottom of the N region is more than 3 mu m.
9. The dual gate silicon carbide MOSFET device of claim 8, wherein the N-region implanted ions in the electric field modulation region are nitrogen ions and the P-region implanted ions in the electric field modulation region are boron ions.
10. A method of fabricating a silicon carbide MOSFET device of the dual gate structure of claim 1, comprising the steps of:
selecting heavily doped silicon carbide as the N + A substrate, and at said N + The N is grown on the surface of the substrate through epitaxy - An epitaxial layer;
at said N - Setting a mask on the epitaxial layer, carrying out trench photoetching and etching, and then respectively preparing an N region and a P region of the electric field modulation region in a deep ion implantation mode;
at said N - Carrying out groove photoetching and etching on the epitaxial layer to form the groove;
at said N - The surface of the epitaxial layer forms the P well region by means of aluminum injection and diffusion, and forms the N region by means of nitrogen ion injection and diffusion + A source region;
by etching and metal deposition, in the N + And preparing the drain electrode on the bottom surface of the substrate, and preparing the source electrode on the surface of the P well region and the N+ source region.
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