CN117270245A - Display substrate, display device and test equipment - Google Patents

Abstract

The invention relates to a display substrate, which includes a display area and a frame area located around the display area. The display area includes a plurality of data lines and a plurality of gate lines, and is crossed by a plurality of data lines and a plurality of gate lines. In a defined pixel area, along the first direction, the frame area includes a test area located on one side of the display area, and the test area includes at least one row of multiple first test electrodes and multiple second test electrodes arranged side by side. electrode; the test area also includes a plurality of test transistors, one of the test transistors is connected to three of the first test electrodes; a plurality of the second test electrodes are connected to the data lines through signal lines. The invention also relates to a display device and test equipment.

Description

Display substrate, display device and test equipment

Technical field

The present invention relates to the technical field of testing of display products, and in particular, to a display substrate, a display device and testing equipment.

Background technique

As flat panel displays have an increasing impact on people's production and life, TFT, as its core device, also needs to be continuously improved to meet the increasing market demand. In TFT research experiments, the characterization of the electrical characteristics of the device is of great significance. On the one hand, it is a direct test of material evaluation and process development, and at the same time, it guides the design of subsequent circuit functions. The current technology takes a relatively long time to test a TFT, which results in that only random inspections can be carried out during the mass production of actual flat panel displays, and all electrical parameters of the product cannot be fully monitored. How to shorten the electrical parameter testing time in actual production and improve Testing efficiency and expanding product TFT electrical test coverage have become urgent issues to be solved.

Contents of the invention

In order to solve the above technical problems, the present invention provides a display substrate, a display device and a testing equipment to solve the problem of low testing efficiency.

In order to achieve the above object, the technical solution adopted in the embodiment of the present invention is: a display substrate, including a display area and a frame area located at the periphery of the display area, the display area including a plurality of data lines and a plurality of gate lines, and a pixel area defined by the intersection of a plurality of data lines and a plurality of gate lines. Along the first direction, the frame area includes a test area located on one side of the display area, and the test area includes at least one row arranged side by side. a plurality of first test electrodes and a plurality of second test electrodes;

The test area also includes a plurality of test transistors, one of the test transistors is correspondingly connected to a plurality of the first test electrodes;

A plurality of second test electrodes are connected to the data lines through signal lines.

Optionally, a plurality of the first test electrodes and a plurality of the second test electrodes are arranged side by side along a second direction, and the second direction intersects the first direction.

Optionally, three first test electrodes corresponding to the same test transistor are arranged adjacently.

Optionally, along the second direction, the plurality of first test electrodes are located on the same side of the plurality of second test electrodes, and the second direction is the arrangement direction of the plurality of second test electrodes.

Optionally, along the second direction, a plurality of second test electrodes are respectively disposed on opposite sides of a plurality of second test electrodes.

Optionally, in the first direction, the test transistor is located on one side of the first test electrode, and the test transistor includes a dummy gate, a dummy source and a dummy drain. In one direction, the first test electrode connected to the dummy gate is located between the first test electrode connected to the dummy source and the second test electrode connected to the dummy drain.

Optionally, one second test electrode is connected to a plurality of the data lines through a switching element.

Optionally, each of the pixel areas includes a pixel transistor, the test transistor and the pixel transistor have the same structure, and the test transistor and the pixel transistor are formed using a synchronous patterning process.

An embodiment of the present invention also provides a display device, including the above display substrate.

An embodiment of the present invention also provides a test equipment, including the above-mentioned display substrate and a test device. The test device includes a probe. The probe includes at least one row of probes. Each row of probes is connected to the same row of probes. The first test electrode and the second test electrode are arranged in one-to-one correspondence.

The beneficial effects of the present invention are: integrating the first test electrode that cooperates with the electrical parameter testing machine (Electrical Parameter Monitoring) for testing and the second test electrode that cooperates with the array detector (Array Test) for testing, so that the first test electrode Arranged side by side with the second test electrode, the pixel transistor in the display area and the test transistor in the test area can be tested simultaneously, thereby improving test efficiency.

Description of the drawings

Figure 1 shows a schematic diagram of a display substrate in the related art;

Figure 2 shows a schematic distribution diagram of the first test electrode in the related art;

Figure 3 shows a schematic diagram 1 of the arrangement of the first test electrode and the second test electrode in the embodiment of the present invention;

Figure 4 shows a schematic diagram 2 of the arrangement of the first test electrode and the second test electrode in the embodiment of the present invention;

Figure 5 shows a schematic diagram 3 of the arrangement of the first test electrode and the second test electrode in the embodiment of the present invention;

Figure 6 shows a schematic diagram of a display substrate in an embodiment of the present invention.

1 first test electrode; 2 second test electrode; 3 transistor for test; 4 signal line; 10 gate line; 20 data line; 30 pixel area; 31 pixel transistor; 32 pixel electrode.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present disclosure.

Unless otherwise defined, technical terms or scientific terms used in this disclosure shall have the usual meaning understood by a person with ordinary skill in the art to which this disclosure belongs. "First", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Likewise, similar words such as "a", "an" or "the" do not indicate a quantitative limitation but rather indicate the presence of at least one. Words such as "include" or "comprising" mean that the elements or things appearing before the word include the elements or things listed after the word and their equivalents, without excluding other elements or things. Words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", etc. are only used to express relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

Referring to FIGS. 3-6 , this embodiment provides a display substrate, including a display area A and a frame area located at the periphery of the display area A. The display area A includes a plurality of data lines 20 and a plurality of gate lines 10 , and a pixel area 30 defined by the intersection of a plurality of data lines 20 and a plurality of gate lines 10. A pixel transistor 31 and a pixel electrode 32 are provided in the pixel area 30. The gate electrode of the pixel transistor 31 and the The gate line 1 corresponding to the pixel area 30 is connected, and the source of the pixel transistor 31 is connected to the data line 2 corresponding to the pixel area 30 where it is located, along the first direction (that is, with the data line 20 in FIG. 6 direction parallel to the extension direction (refer to the X direction in Figure 6), the frame area includes a test area B located on one side of the display area A, and the test area B includes at least one row of multiple A first test electrode 1 and a plurality of second test electrodes 2;

The test area B also includes a plurality of test transistors 3, and one of the test transistors 3 is correspondingly connected to a plurality of the first test electrodes 1;

The plurality of second test electrodes 2 are connected to the data lines 2 through signal lines 4 .

The first test electrode 1 and the second test electrode 2 used for different functional tests are integrated and arranged, that is, compared to the separate test methods of the AT test and the EPM test in the related art. In this embodiment, the test area includes At least one row of multiple first test electrodes 1 and multiple second test electrodes 2 arranged side by side enables simultaneous testing of pixel detection of array lines in the AA area and electrical testing of transistors in the TEG area; this integration method is used in the original related technologies, such as AT testing and EPM testing are conducted separately, breaking the limitations of single-point testing. The single HEAD mode of EPM equipment is improved to the BAR test mode, which can quickly test all points of Glass, which not only shortens the test time, but also greatly improves the test accuracy.

The array tester (Array Test) electrical test equipment (EPM) is integrated into an integrated structure, and the integration is set up as a Bar structure, and the first test electrodes corresponding to the array test machine (Array Test) electrical test equipment (EPM) are respectively The distribution of 1 and the second test electrode 2 is also integrated, so that during testing, when testing the same row of test electrodes, the corresponding probes can be connected to the first test electrode 1 and the second test electrode 2 at the same time, and then Realize simultaneous testing of AA area array line pixel detection and TEG area transistor electrical testing. This integration method breaks the limitation of traditional AT testing and EPM testing being conducted separately, and integrates the two testing methods into one testing process, greatly improving testing efficiency.

In the related art, the first test electrode 1 and the second test electrode 2 are arranged separately. Referring to Figure 1, in this embodiment, the first test electrode 1 and the second test electrode 2 are integratedly arranged. ,The advantage of this design strategy is that it significantly ,saves the physical space required for testing, and achieves ,efficient utilization of space compared to the traditional design ,shown in Figure 1.

In an exemplary embodiment, a plurality of the first test electrodes 1 and a plurality of the second test electrodes 2 are arranged side by side along a second direction (refer to the Y direction in FIG. 6 ), and the second direction and the The first direction intersects.

In an exemplary embodiment, a plurality of the first test electrodes 1 and a plurality of the second test electrodes 2 are arranged side by side along a second direction (refer to the Y direction in FIG. 6 ), and the second direction and the The first direction is set vertically.

Referring to FIG. 6 , the second test electrode 2 is connected to the data line 20 through the signal line 4 . The extension direction of the data line 20 is parallel to the first direction. The extension direction of the data line 20 is parallel to the first direction. Extending in a direction perpendicular to the first direction can shorten the length of the signal line 4, facilitate the arrangement of the signal line 4, and reduce the space occupied by the signal line 4, thereby facilitating the realization of a narrow frame .

In the first direction, the test area B is located on one side of the display area A. The length of the test area B in the first direction is limited, and the test area B is located on one side of the display area A. The length in the second direction is much longer than the length of the test area B in the first direction. Therefore, a plurality of first test electrodes 1 and a plurality of second test electrodes 2 are arranged side by side along the second direction. With reference to FIG. 6 , the length of the display substrate in the first direction can be reduced, which is beneficial to the arrangement of a narrow frame. And the plurality of first test electrodes 1 and the plurality of second test electrodes 2 are arranged side by side along the second direction, which will not affect the length of the display substrate in the second direction.

For example, the number of first test electrodes 1 corresponding to the same test transistor 3 is three, wherein one first test electrode 1 is used to connect the virtual gate of the test transistor 3 , one of the first test electrodes 1 is used to connect the virtual source of the test transistor 3 , and one of the first test electrodes 1 is used to connect the virtual drain of the test transistor 3 . In an exemplary embodiment, three first test electrodes 1 corresponding to the same test transistor 3 are arranged adjacently.

The test transistor 3 includes a dummy gate G, a dummy source S and a dummy drain D. Referring to Figure 5, three first test electrodes 1 corresponding to the same test transistor 3 are arranged adjacently, so that The purpose of the design is to optimize the circuit distribution and make the circuit more concise and compact, thereby facilitating the efficient and stable operation of the test transistor 3. Through this layout, signal transmission delay can be greatly reduced and the working efficiency of the entire circuit can be improved.

In an exemplary embodiment, along the second direction, the plurality of first test electrodes 1 are located on the same side of the plurality of second test electrodes 2 , and the second direction is the plurality of second test electrodes 2 . the arrangement direction.

In an exemplary embodiment, along the second direction, the plurality of first test electrodes 1 are located on one side of the plurality of second test electrodes 2 , and the second direction is the plurality of second test electrodes 2 the arrangement direction.

In an exemplary embodiment, along the second direction, the plurality of second test electrodes 2 are respectively disposed on opposite sides of the plurality of second test electrodes 2 , and the second direction is the plurality of second test electrodes 2 . 2. For the arrangement direction of the test electrodes 2, refer to the Y direction in Figure 6.

In an exemplary embodiment, when the first test electrodes 1 are disposed on opposite sides of the second test electrode 2 along the second direction, a plurality of the second test electrodes 2 The number of the first test electrodes 1 on the opposite sides may be the same, that is, the corresponding second test electrodes 2 form a symmetrical pattern on the opposite sides of the plurality of second test electrodes 2. Layout; when the first test electrodes 1 are provided on opposite sides of the second test electrode 2, the number of the first test electrodes 1 on the opposite sides of the plurality of second test electrodes 2 It can also be different.

Furthermore, the second direction actually refers to the arrangement direction of a plurality of second test electrodes 2 . In other words, if we look at this layout from a specific angle, the plurality of first test electrodes 1 will form a straight line on the same side of the plurality of second test electrodes 2 . This arrangement is more conducive to allowing the first test electrode 1 and the second test electrode 2 to be connected to probes at the same time for testing.

It should be emphasized that the implementations described here are only exemplary and do not constitute a limitation on all possible implementations. In practical applications, the positions and numbers of the first test electrode 1 and the second test electrode 2 in the second direction can be adjusted according to actual needs, so as to obtain the best application effect.

It should be noted that among the first test electrodes 1 and the second test electrodes 2 arranged in the same row, the position and number of the first test electrodes 1 can be set according to actual needs, as shown in Figure 3 In the distribution mode of the first test electrodes 1 and the second test electrodes 2, in the second direction, all the first test electrodes 1 are located on one side of the second test electrodes 2, In the distribution manner of the first test electrodes 1 and the second test electrodes 2 shown in Figure 4, in the second direction, a plurality of the first test electrodes 1 are respectively disposed on a plurality of the On the opposite sides of the second test electrode 2, in the distribution manner of the first test electrode 1 and the second test electrode 2 shown in Figure 5, in the second direction, a plurality of the A test electrode 1 is respectively disposed on opposite sides of a plurality of second test electrodes 2 . In the distribution mode of the first test electrodes 1 and the second test electrodes 2 shown in Figure 3, in the second direction, 12 second test electrodes 2 are arranged on one side of the plurality of second test electrodes 2. The first test electrode 1. In the distribution mode of the first test electrode 1 and the second test electrode 2 shown in Figure 4, in the second direction, a plurality of second test electrodes 2 are arranged on opposite sides respectively. There are three first test electrodes 1 . In the distribution mode of the first test electrode 1 and the second test electrode 2 shown in Figure 5, in the second direction, a plurality of second test electrodes 2 are arranged on opposite sides. There are 6 first test electrodes 1 .

In the distribution mode of the first test electrodes 1 and the second test electrodes 2 shown in Figure 4, in the same row of test electrodes, there are 6 first test electrodes 1, and in multiple Three first test electrodes 1 are respectively arranged on opposite sides of the second test electrode 2, and the three first test electrodes corresponding to one test transistor 3 are located on the same side of the plurality of second test electrodes 2. In Figure 3 and Figure 5, the same row of test electrodes is configured to include 12 first test electrodes 1, which are respectively connected to 4 test transistors, which is equivalent to the corresponding head structure in the EPM test in the related technology. The first test electrode in a pin card is integrated into the AT test in the related art, and the second test electrode 2 in a pin card in a Bar-type structure is incorporated, but is not limited to this. This merger and integration not only improves the efficiency of testing, but also makes the entire testing process more convenient and accurate. Of course, the above description is not the only setting method, but only some possible examples, and is not limited thereto.

Referring to FIGS. 3-6 , in an exemplary embodiment, in the first direction, the test transistor 3 is located on one side of the first test electrode 1 , and the test transistor 3 includes a virtual gate. G. Virtual source S and virtual drain D. Along the first direction, the first test electrode 1 connected to the virtual gate G is located at the first test electrode 1 connected to the virtual source S. and between the first test electrode 1 connected to the virtual drain D.

The purpose of adopting the above technical solution is to optimize the circuit distribution, make the circuit more concise and compact, thereby facilitate the efficient and stable operation of the test transistor 3, and reduce the size of the first test electrode 1 and the test transistor 3 and the space occupied by the connection lead connected between the first test electrode 1 and the test transistor 3 .

In an exemplary embodiment, one second test electrode 2 is connected to a plurality of data lines through a switching element. Using the above method, the number of the second test electrodes 2 can be reduced, saving space and cost.

In some embodiments, a plurality of second test electrodes 2 and a plurality of data lines 20 may be arranged in one-to-one correspondence, see FIG. 6 . In this way, the number of the second test electrodes 2 needs to be the same as the number of the data lines. Such a connection method increases the space occupied by multiple second test electrodes 2 and also increases the number of connections between the second test electrodes 2 and the data lines. The distribution difficulty of the signal line 4 between the second test electrode 2 and the corresponding data line 20 is tested.

In an exemplary implementation, in order to fully utilize space and reduce costs, one second test electrode 2 is connected to a plurality of data lines through switching elements. By adopting this implementation, it is possible to reduce the number of the second test electrodes 2 while still making signal connections with all data lines for testing.

It should be noted that the number of data lines 20 connected to one second test electrode 2 can be set according to actual needs.

In an exemplary embodiment, the spacing between the plurality of first test electrodes 1 is the same as the spacing between the plurality of second test electrodes 2, and one of the first test electrodes 1 is arranged adjacent to it. The spacing between the second test electrodes 2 is the same as the spacing between the plurality of first test electrodes 1, which facilitates the connection between the probe and the corresponding test electrode.

In an exemplary embodiment, each pixel area 30 includes a pixel transistor 31 , the testing transistor 3 and the pixel transistor 31 have the same structure, and the testing transistor 3 and the pixel transistor 31 adopt a synchronous The composition process is formed.

The structure of the test transistor 3 is exactly the same as that of the pixel transistor 31. Since the structure and material of the test transistor 3 and the pixel transistor 31 are the same, their impedance characteristics are consistent. The impedance characteristics of the test transistor 3 It can reflect the real impedance characteristics of the pixel transistor 31 . This structural similarity allows test transistor 3 to effectively simulate the behavior of pixel transistor 31, thereby providing more accurate results during the testing phase.

When testing the test transistor 3 through the first test electrode 1, a certain voltage is applied between the first test electrode 1 pair and a virtual source and a virtual drain of the test transistor 3. voltage, so that a conductive electrical loop is formed between the virtual source and virtual drain of the testing transistor 3, and then, the first testing electrode 1 can be applied to the virtual gate of the testing transistor 3 Scan the voltage to slowly change the voltage, gradually conduct between the virtual source and the virtual drain, detect the drain current-gate voltage curve in the process, and then measure the characteristic value of the test transistor 3 Make judgments. Furthermore, the characteristic values of a plurality of the test transistors 3 measured simultaneously can be averaged, and the properties of the test transistor 3 can be measured more accurately.

In the process of forming the test transistor 3 and the pixel transistor 31, a synchronous patterning process is adopted. This process involves a series of complex steps, including film deposition, photolithography, doping, and electroplating, which all require precise control and optimization to ensure the performance and quality of the final product. Through this process, the test transistor 3 and the pixel transistor 31 can be accurately constructed on the display substrate and ensure that they have consistent performance characteristics.

The manufacturing process of the pixel transistor 31 and the testing transistor 3 is as follows.

1): First make the corresponding Flexible layer and buffer layer on the glass substrate;

2): On the buffer layer, use physical vapor deposition (PVD) or chemical vapor deposition (CVD) technology to deposit A-Si (ACT layer, i.e. active layer). The material of the buffer layer can be silicon oxide, nitride Silicon, silicon oxynitride and other insulating materials, the material of the Act layer can be metal oxide materials, such as IGZO materials;

3): Perform ElA (Excimer Laser Annealing) and Doping (Doping) processes on the ACT layer to adjust its electrical properties. This step is a key link in transistor manufacturing and requires precise control of the annealing temperature and the type and dose of the dopant. ;

4): After gluing, developing, etching, and cleaning, the ACT Pattern is obtained. That is, through the steps of gluing, developing, etching, and cleaning, the ACT layer is formed into the required pattern. This step requires precise control of time and temperature. Ensure pattern accuracy and consistency;

5): Deposit an insulating layer GI1 layer on the formed ACT layer pattern to completely cover the ACTlayer; the material of the GI1 layer can be silicon oxide, silicon nitride, silicon oxynitride and other insulating materials;

6): Plate a Gate1 layer (first gate metal layer) on the GI1 layer, and obtain the pattern required for the Gate1 layer through glue coating, development, etching, and cleaning. The material of the Gate1 layer can be Mo, Al, or Ti. , Au, Cu, Hf, Ta and other common metals, and can also be made by Cu process, such as MoNd/Cu/MoNd;

7): Deposit an insulating layer GI2 layer on the formed Gate1 layer pattern to completely cover the Gate1layer. The material of the GI2 layer can be silicon oxide, silicon nitride, silicon oxynitride and other insulating materials;

8): Plate a Gate2 layer (second gate metal layer) on the GI2 layer, and obtain the pattern required for the Gate2 layer through glue coating, development, etching, and cleaning. The material of the Gate2 layer can be Mo, Al, or Ti. , Au, Cu, Hf, Ta and other common metals, and can also be made by Cu process, such as MoNd/Cu/MoNd;

9): Deposit an insulating layer ILD layer on the formed Gate1 layer pattern, and obtain the Hole (via hole) after glue coating, development, etching, and cleaning;

10): After DEP, SD1 (source and drain metal layer) is glued, developed, etched, and cleaned to obtain the pattern required for SD 1layer.

Each step of the process requires precise control of process parameters to ensure transistor performance and quality. Among them, annealing temperature, dopant type and dosage, film deposition temperature and time, pattern shape and size, etc. are all key factors that need to be strictly controlled.

Through the above steps, the manufacturing process flow of the pixel transistor and the test transistor 3 is completed.

An embodiment of the present invention also provides a display device, including the above display substrate.

Along the first direction, the frame area includes a test area B located on one side of the display area A. The test area B includes at least one row of a plurality of first test electrodes 1 and a plurality of second test electrodes arranged side by side. 2. The three first test electrodes 1 are commonly connected to a test transistor 3 .

The test transistor 3 includes a virtual gate G, a virtual source S and a virtual drain D. The test process through the test transistor 3 and the second test electrode 2 is as follows: the corresponding virtual gate G is , the first test electrode 1 of the virtual source S and the virtual drain D provides a signal. At this time, a level of -5.1V is applied to the virtual gate, so that the virtual drain maintains a scanning range of 15 to -15V for scanning. The gradient is 0.2V. The required data is obtained from the virtual source. Finally, the SUM module of the device is used to detect and record the electrical parameters of the device. The IDVG curve is drawn to obtain electrical parameters such as VTH, MOB, SS2, and IOFF. value.

The process of testing through the second test electrode 2 is as follows: apply a driving signal to the second test electrode 2, such as VDD, VINIT, VGL, VGH, etc., and drive the AA area through the GOA area on the display substrate. The voltage fed back by the Pixel is simulated as a digital signal and converted into a grayscale image to determine the TFT working status of the Pixel in the entire AA area.

The display device may be any product or component with a display function such as an LCD TV, an LCD monitor, a digital photo frame, a mobile phone, a tablet computer, etc. The display device further includes a flexible circuit board, a printed circuit board and a backplane.

An embodiment of the present invention also provides a test equipment, including the above-mentioned display substrate and a test device. The test device includes a probe. The probe includes at least one row of probes. Each row of probes is connected to the same row of probes. The first test electrode 1 and the second test electrode 2 are arranged in one-to-one correspondence.

It can be understood that the above embodiments are only exemplary embodiments adopted to illustrate the principles of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims (10)

1. A display substrate comprising a display region and a frame region at the periphery of the display region, wherein the display region comprises a plurality of data lines, a plurality of gate lines and a pixel region defined by the intersections of the plurality of data lines and the plurality of gate lines, and the display substrate is characterized in that the frame region comprises a test region at one side of the display region along a first direction, and the test region comprises at least one row of a plurality of first test electrodes and a plurality of second test electrodes which are arranged side by side;

the test area further comprises a plurality of test transistors, and one test transistor is correspondingly connected with the plurality of first test electrodes;

the plurality of second test electrodes are connected with the data line through signal lines.

2. The display substrate of claim 1, wherein a plurality of the first test electrodes and a plurality of the second test electrodes are disposed side by side along a second direction, the second direction intersecting the first direction.

3. The display substrate according to claim 1, wherein three of the first test electrodes connected to the same test transistor are disposed adjacently.

4. The display substrate according to claim 1, wherein the plurality of first test electrodes are located on the same side as the plurality of second test electrodes in a second direction, the second direction being an arrangement direction of the plurality of second test electrodes.

5. A display substrate according to claim 3, wherein a plurality of the second test electrodes are disposed on opposite sides of the plurality of second test electrodes, respectively, along the second direction.

6. The display substrate according to claim 1, wherein the test transistor is located at one side of the first test electrode in the first direction, the test transistor includes a dummy gate, a dummy source, and a dummy drain, and the first test electrode connected to the dummy gate is located between the first test electrode connected to the dummy source and the second test electrode connected to the dummy drain in the first direction.

7. The display substrate according to claim 1, wherein one of the second test electrodes is connected to a plurality of the data lines through a switching element.

8. The display substrate according to claim 1, wherein each of the pixel regions includes a pixel transistor, the test transistor and the pixel transistor have the same structure, and the test transistor and the pixel transistor are formed using a synchronous patterning process.

9. A display device comprising the display substrate according to any one of claims 1 to 8.

10. A test apparatus comprising the display substrate of any one of claims 1-8 and a test device, the test device comprising a probe head comprising at least one row of probes, each row of probes being arranged in one-to-one correspondence with the first test electrodes and the second test electrodes arranged in the same row.