CN117199152A - A solar cell and its preparation method - Google Patents

Abstract

The invention discloses a solar cell and a preparation method thereof, which belong to the technical field of solar cells and comprise a silicon wafer and a plurality of rows of auxiliary grids, wherein the same row of auxiliary grids consists of a long positive electrode auxiliary grid and a short negative electrode auxiliary grid or consists of a long negative electrode auxiliary grid and a short positive electrode auxiliary grid; the adjacent two rows of auxiliary grids are respectively provided with a long positive auxiliary grid and a long negative auxiliary grid; the short negative electrode auxiliary grid is provided with a negative electrode main grid region in the length direction of the auxiliary grid and the long negative electrode auxiliary grid at the corresponding position; the short positive electrode auxiliary grid is provided with a positive electrode main grid area in the length direction of the auxiliary grid and a long positive electrode auxiliary grid at a corresponding position; the negative electrode main gate regions and the positive electrode main gate regions are alternately arranged; PAD points are distributed between the cathode main gate region and the anode main gate region. By the design of the long and short auxiliary grids, a positive main grid region and a negative main grid region are respectively formed at the short positive auxiliary grid and the short negative auxiliary grid, and connecting wires are not printed in the main grid regions, so that silver paste can be saved; meanwhile, due to the arrangement of the short positive electrode auxiliary grid and the short negative electrode auxiliary grid, poor welding short circuit can be prevented.

Description

A solar cell and its preparation method

Technical field

The present invention relates to the technical field of solar cells, specifically, to a solar cell and a preparation method thereof.

Background technique

Against the background of increasingly severe problems such as global warming and the increasing shortage of non-renewable energy sources such as oil and natural gas, the development of new energy is urgent, and solar energy, as an inexhaustible clean energy, is the first to bear the brunt. Improving photoelectric conversion efficiency is the focus of solar technology. Back-contact solar technology prints the front grid lines and electrodes of the battery to the back through special technical means, forming a cross arrangement of positive and negative electrodes on the back of the battery. This technology can effectively improve the efficiency of solar cells and make solar cells more beautiful. It is also compatible with PERC, TOPCON, HJT and other technologies.

The positive electrode fine grid 101 and the negative electrode fine grid 201 are arranged crosswise on the back of the existing back contact battery, and the positive electrode main grid 100 and the negative electrode main grid 200 are arranged vertically crosswise. The intersection of the positive electrode and the negative electrode fine grid 201 is disconnected and insulating glue is printed. The intersection of the negative electrode and the positive electrode fine grid 101 is disconnected and insulating glue is printed. As shown in Figure 1, pad points 300 are provided in the length direction of the positive electrode main grid 100 and the negative electrode main grid 200. When welding, the back of the battery piece is facing up, and the positive electrode is Lay a tin-lead soldering strip directly above the negative electrode, press the soldering strip with a spring pressure pin, and use an infrared lamp to heat it to achieve soldering. This structure has the following problems: (1) When the soldering ribbon is placed in an offset position, contact with the insulating area will damage the insulating glue and cause a short circuit; (2) The infrared welding temperature is too high, and single-sided soldering is due to the deviation of the thermal expansion coefficient between the tin-lead soldering ribbon and the battery piece. If the battery is too large, the battery cells will be severely warped after welding, which may lead to cracks during lamination; (3) There is stress in the warping of the battery cells, and there is a risk of failure due to factors such as high and low temperature alternating, moisture, etc. when subsequent components are used outdoors. .

In view of this, the inventor conducted in-depth research on this demand, and this case came about.

Contents of the invention

In order to overcome the problem in the prior art that when the soldering strip on the back of the back contact battery is placed in an offset position, it will damage the insulating glue and cause a short circuit when it contacts the insulating area. After the soldering strip is welded, the battery sheet will be severely warped, causing cracks during lamination, and the battery sheet will be damaged. There is stress in warping, and there is a risk of failure during outdoor use. The present invention provides a back contact battery, which is a screen BC battery, including a silicon wafer and a number of cells arranged on the back of the silicon wafer facing a first direction. Rows of auxiliary grids, each row of auxiliary grids alternately arranged with spaced positive auxiliary grids and negative auxiliary grids along its length direction; the positive auxiliary grids include long positive auxiliary grids and short positive auxiliary grids, and the negative auxiliary grids Including long negative auxiliary gate and short negative auxiliary gate;

The secondary grids in the same row are composed of a long positive secondary grid and a short negative secondary grid, or a long negative secondary grid and a short positive secondary grid; the secondary grids in two adjacent rows are respectively provided with a long positive secondary grid and a short negative secondary grid. Long negative electrode sub-gate; all the short negative electrode sub-gates form more than one negative electrode main grid area in the length direction of the sub-gate and the corresponding position of the long negative electrode sub-gate, and each of the negative electrode main grid areas has a plurality of short negative electrode sub-gates. The negative auxiliary gates are arranged along a first direction perpendicular to the length direction of the auxiliary gate; all the short positive auxiliary gates form more than one positive main main gate in the length direction of the auxiliary gate and the long positive auxiliary gate at a corresponding position. In the gate region, a plurality of short positive sub-gates are arranged along the first direction on each positive main gate region; and the negative main gate region and the positive main gate region are alternately arranged in the length direction of the sub-gates.

Negative main grid PAD points are arranged along the first direction in the middle of the negative main grid area, and positive main grid PAD points are arranged along the first direction in the middle of the positive main grid area.

Through the design of long and short auxiliary gates, the positive main gate area and the negative main gate area are respectively formed at the short positive auxiliary gate and the short negative auxiliary gate, and no connecting lines are printed in the main gate area, which can save silver paste; at the same time, due to the short positive electrode The setting of the auxiliary grid and the short negative auxiliary grid can prevent poor welding short circuit.

Preferably, the width of the auxiliary gate is 10-30um and the height is 10-15um.

Preferably, the number of PAD points here is at least 6, including 3 negative main grid PAD points and positive main grid PAD points, and the width of the negative main grid PAD point and the positive main grid PAD point is 80-120um. , the length is 60-80um, and the thickness is 3-10um; the height of the negative main grid PAD point and the positive main grid PAD point is not lower than the height of the secondary grid.

The short negative sub-gates on both sides of the negative main gate region and the long positive sub-gate are spaced apart to form an insulating area; the short positive sub-gates on both sides of the positive main gate region are spaced apart from the long negative sub-gate. An insulating area is formed; and the distance between the PAD points of the negative electrode main grid corresponding to the distance between the two ends of the short negative electrode auxiliary gate is 50-100um, and the distance between the PAD points of the positive electrode main grid corresponds to the distance between the two ends of the short positive electrode auxiliary gate. It is 50-100um, which can avoid short circuit caused by the deviation of the solder strip causing the positive and negative sub-gates to connect, and the negative and positive sub-gates to connect. At the same time, the short sub-gate can collect carriers in the breakpoint area and reduce efficiency loss.

Preferably, solder paste with a width of 60-100um and a thickness of 5-10um is printed between the negative main grid PAD point, the positive main grid PAD point and the surface of the silicon chip directly below;

Solder paste with a thickness of 3-5um, a width of 10-30um, and a length of 80-120um is printed between the negative main grid PAD point, the positive main grid PAD point, and the auxiliary grid. The printed solder paste The purpose is to enhance the welding tension at the fine grid and improve component reliability.

Preferably, the negative electrode main grid area is welded with a welding ribbon along its length direction, and the positive electrode main grid area is welded with a welding ribbon along its length direction; the width of the welding ribbon is 60-100um, and the thickness is 200-270um. Lay the low-temperature conductive welding strip in the middle of the PAD point. The welding strip is mainly composed of tin, lead, bismuth, silver, and rare earth elements in a certain ratio. Laser spot welding has good local heating uniformity and is only welded at the PAD point. The welding area has expansion space, which can greatly reduce cell warping caused by single-sided welding and enable conductive EL imaging.

Preferably, the negative main gate regions and the positive main gate regions are alternately arranged along a second direction perpendicular to the first direction, and the distance from the negative main gate region to two adjacent positive main gate regions is equal.

The invention also provides a method for preparing the above-mentioned screen BC battery, which includes the following steps:

Step 1: Print the secondary grid on the back of the silicon wafer;

Step 2: Print solder paste on the negative main grid PAD point in the negative main grid area of the silicon wafer and on the positive main grid PAD point in the positive main grid area; use a steel mesh to paste the positive electrode on the negative main grid PAD point and the positive main grid PAD point. Print solder paste on all sub-gate positions below;

Step 3: After the solder paste is dried, lay the solder ribbon directly above the positive main grid area and negative main grid area of the silicon wafer, use a pressing net to press the solder ribbon, and use laser spot welding technology to locally and rapidly heat the PAD point area. welding;

Step 4: Use a laminator to heat and melt the solder strip at the non-PAD point and the auxiliary gate to form an alloy.

Among them, in step two, use an infrared lamp heating furnace to dry the solder paste, the drying temperature is 170-240°C, and the drying time is 15-60s;

Preferably, in step three, laser spot welding technology is used to locally and rapidly heat and weld in the PAD point area. The welding temperature is 200-240°C and the welding time is 1-3 seconds. The laser spot welding can prevent warping and cracking of the welding.

Preferably, in step four, the lamination temperature is set to 145-155°C, and the lamination pressure is divided into three stages. The first stage has a pressure of 10-20kp and a holding time of 10-30s, and the second stage has a pressure of 40-50kp and a holding time of 10-30s. 10-30s, the third stage pressure is 70-80kp, and the holding time is 600-800s. During the lamination process, the lamination temperature and pressure can be used to form an alloy between the low-temperature conductive ribbon and the auxiliary grid.

Beneficial effects:

The beneficial effects produced by adopting the technical solution of the present invention are as follows:

(1) Through the design of long and short auxiliary gates, the positive main gate area and the negative main gate area are formed at the short positive auxiliary gate and the short negative auxiliary gate respectively, and no connecting lines are printed in the main gate area, which can save silver paste.

(2) The distance between the PAD points of the negative electrode main grid corresponds to the distance between the two ends of the short negative electrode sub-grid of 50-100um, and the distance between the PAD points of the positive electrode main grid corresponds to the distance between the two ends of the short positive electrode sub-grid of 50-100um, which can avoid welding. The band offset causes the positive and negative sub-gates to connect, and the negative and positive sub-gates to connect to cause a short circuit. At the same time, the short sub-gate can collect carriers in the breakpoint area and reduce efficiency loss.

(3) Lay the low-temperature conductive welding tape in the middle of the PAD point, and only weld at the PAD point. The welding tape in the non-welding area has expansion space, which can greatly reduce the warping of the cell sheet caused by single-sided welding, and can achieve conductive EL imaging.

Description of the drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore do not It should be regarded as a limitation of the scope. For those of ordinary skill in the art, other relevant drawings can be obtained based on these drawings without exerting creative efforts.

Figure 1 is a schematic diagram of the back structure of an existing BC battery in the prior art;

Figure 2 is a schematic diagram of the back structure of a preferred BC battery of the present invention;

Figure 3 is a flow chart of a preferred BC battery preparation process of the present invention.

In the figure, 1. Silicon wafer; 2. Sub-gate; 21. Positive sub-gate; 211. Long positive sub-gate; 212. Short positive sub-gate; 22. Negative sub-gate; 221. Long negative sub-gate; 222. Short negative electrode. Sub-grid; 3. Negative main grid area; 31. Negative main grid PAD point; 4. Positive main grid PAD point;

41. Positive main grid PAD point.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments These are some embodiments of the present invention, but not all embodiments. Accordingly, the following detailed description of embodiments of the invention provided in the appended drawings is not intended to limit the scope of the claimed invention, but rather to represent selected embodiments of the invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

Through the design of long and short auxiliary grids, the present invention forms a positive main grid area and a negative main grid area at the short positive auxiliary grid and the short negative auxiliary grid respectively, and does not print connecting lines in the main grid area, which can save silver paste; at the same time, because The setting of short positive auxiliary grid and short negative auxiliary grid can prevent poor welding short circuit. The specific technical solutions are as follows:

As shown in Figure 2, a screen BC battery includes a silicon wafer 1 and several rows of auxiliary grids 2 arranged on the back side of the silicon wafer 1 facing a first direction. The auxiliary grids 2 in each row are alternately arranged along its length direction. There are a positive sub-gate 21 and a negative sub-gate 22 arranged at intervals; the positive sub-gate 21 includes a long positive sub-gate 211 and a short positive sub-gate 212, and the negative sub-gate 22 includes a long negative sub-gate 221 and a short negative sub-gate. 222;

The sub-gates 2 in the same row are composed of a long positive sub-gate 211 and a short negative sub-gate 222, or are composed of a long negative sub-gate 221 and a short positive sub-gate 212; the sub-gates 2 in two adjacent rows are respectively provided with There is a long positive sub-gate 211 and a long negative sub-gate 221; all the short negative sub-gates 222 form more than one negative main gate region 3 in the length direction of the sub-gate 2 and the long negative sub-gate 221 at the corresponding position. , a plurality of short negative sub-gates 222 on each negative main gate region 3 are arranged along the first direction perpendicular to the length direction of the sub-gate 2; all the short positive sub-gates 212 are arranged in the length direction of the sub-gate 2 More than one positive main gate region 4 is formed with the long positive sub-gate 211 at the corresponding position, and a plurality of short positive sub-gates 212 are arranged along the first direction on each positive main gate region 4; and the negative main gate region 4 The gate regions 3 and the positive main gate regions 4 are alternately arranged in the length direction of the sub-gate 2 .

Negative main gate PAD points 31 are arranged in the middle of the negative main gate region 3 along the first direction, and positive main gate PAD points 41 are arranged in the middle of the positive main gate region 4 along the first direction.

As a preferred embodiment, the width of the auxiliary gate 2 is 10-30um and the height is 10-15um.

The number of PAD points here is at least 6, including 3 negative main grid PAD points 31 and positive main grid PAD points 41. The widths of the negative main grid PAD points 31 and the positive main grid PAD points 41 are 80 - 120um, length 60-80um, thickness 3-10um; the height of the negative main grid PAD point 31 and the positive main grid PAD point 41 is not lower than the height of the sub-grid 2 .

Insulating regions 5 are formed at intervals between the short negative sub-gates 222 on both sides of the negative main gate region 3 and the long positive sub-gate 211; the short positive sub-gates 212 on both sides of the positive main gate region 4 and the long positive sub-gate 211 Insulation areas 5 are formed at intervals between the negative electrode sub-gates 221; and the distance between the negative electrode main grid PAD points 31 corresponds to the distance between the two ends of the short negative electrode sub-gate 222, which is 50-100um, and the distance between the positive electrode main grid PAD points 41 Correspondingly, the distance between the two ends of the short positive sub-grid 212 is 50-100um, which can avoid the deviation of the solder ribbon causing the connection between the positive and negative sub-grids, and the connection between the negative and positive sub-grids, resulting in short circuits. At the same time, the short sub-grid can collect the breakpoint area. carriers, reducing efficiency losses.

As a preferred implementation mode, a silicon wafer with a width of 60-100um and a thickness of 5-10um is printed between the negative electrode main grid PAD point 31, the positive electrode main grid PAD point 41 and the surface of the silicon wafer 1. solder paste;

A solder paste with a thickness of 3-5um, a width of 10-30um, and a length of 80-120um is printed between the negative main grid PAD point 31, the positive main grid PAD point 41 and the sub-grid 2. The printed tin The purpose of the paste is to enhance the welding tension at the fine grid and improve component reliability.

As a preferred embodiment, the negative main grid region 3 has a welding strip (not shown in the figure) welded along its length direction, and the positive main grid region 4 has a welding strip welded along its length direction; and The width of the soldering strip is 60-100um and the thickness is 200-270um. Lay the low-temperature conductive welding strip in the middle of the PAD point. The welding strip is mainly composed of tin, lead, bismuth, silver, and rare earth elements in a certain ratio. Laser spot welding has good local heating uniformity and is only welded at the PAD point. The welding area has expansion space, which can greatly reduce cell warping caused by single-sided welding and enable conductive EL imaging.

As a preferred embodiment, the negative main gate regions 3 and the positive main gate regions 4 are alternately arranged along a second direction perpendicular to the first direction, and the negative main gate regions 3 are connected to two adjacent ones. The distance between the positive main grid regions 4 is equal.

This embodiment also provides a method for preparing the above-mentioned screen BC battery, which includes the following steps:

Step S101, print a secondary grid on the back of the silicon wafer;

Step S102: Print solder paste on the negative main grid PAD points in the negative main grid area of the silicon chip and on the positive main grid PAD points in the positive main grid area; use a steel mesh to positively paste the negative main grid PAD points and the positive main grid PAD points. Print solder paste on all sub-gate positions below;

Step S103, after the solder paste is dried, lay the solder ribbon directly above the positive main grid area and negative main grid area of the silicon wafer, use a pressing net to press the solder ribbon, and use laser spot welding technology to locally and rapidly heat the PAD point area. welding;

Step S104: Use a laminator to heat and melt the solder strip at the non-PAD point and the auxiliary gate to form an alloy.

Among them, in step S102, the solder paste is dried using an infrared lamp heating furnace, the drying temperature is 170-240°C, and the drying time is 15-60s;

Preferably, in step S103, laser spot welding technology is used for local rapid heating and welding in the PAD point area. The welding temperature is 200-240°C and the welding time is 1-3 s. The laser spot welding can prevent warping and cracking of the welding.

Preferably, in step S104, the lamination temperature is set to 145-155°C, and the lamination pressure is divided into three stages. The first stage has a pressure of 10-20kp and a holding time of 10-30s, and the second stage has a pressure of 40-50kp and a holding time of 10-30s. 10-30s, the third stage pressure is 70-80kp, and the holding time is 600-800s. During the lamination process, the lamination temperature and pressure can be used to form an alloy between the low-temperature conductive ribbon and the auxiliary grid.

The above descriptions are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection scope of the present invention.

Claims (10)

1. A solar cell, characterized in that it includes a silicon wafer and several rows of auxiliary grids arranged on the back side of the silicon wafer facing a first direction. Each row of auxiliary grids is alternately arranged with positive electrode pairs arranged at intervals along its length direction. gate and negative auxiliary gate; the positive auxiliary gate includes a long positive auxiliary gate and a short positive auxiliary gate, and the negative auxiliary gate includes a long negative auxiliary gate and a short negative auxiliary gate; The secondary grids in the same row are composed of a long positive secondary grid and a short negative secondary grid, or a long negative secondary grid and a short positive secondary grid; the secondary grids in two adjacent rows are respectively provided with a long positive secondary grid and a short negative secondary grid. Long negative electrode sub-gate; all the short negative electrode sub-gates form more than one negative electrode main grid area in the length direction of the sub-gate and the corresponding position of the long negative electrode sub-gate, and each of the negative electrode main grid areas has a plurality of short negative electrode sub-gates. The negative auxiliary gates are arranged along a first direction perpendicular to the length direction of the auxiliary gates; all the short positive auxiliary gates form more than one positive main gate region in the length direction of the auxiliary gates and the long positive auxiliary gates at corresponding positions. , a plurality of short positive sub-gates are arranged along the first direction on each positive main gate area; and the negative main grid area and the positive main grid area are alternately arranged in the length direction of the sub-gates; Negative main grid PAD points are arranged along the first direction in the middle of the negative main grid area, and positive main grid PAD points are arranged along the first direction in the middle of the positive main grid area. 2. A solar cell according to claim 1, characterized in that the width of the sub-grid is 10-30um and the height is 10-15um. 3. A solar cell according to claim 1, characterized in that the width of the negative electrode main grid PAD point and the positive electrode main grid PAD point is 80-120um, the length is 60-80um, and the thickness is 3- 10um; the height of the negative main grid PAD point and the positive main grid PAD point is not lower than the height of the secondary gate; An insulation area is formed at intervals between the short negative sub-gates on both sides of the negative main gate region and the long positive sub-gate; between the short positive sub-gates on both sides of the positive main gate region and the long negative sub-gate Insulating areas are formed at intervals; and the PAD point distance of the negative main grid corresponds to the distance between the two ends of the short negative sub-gate, which is 50-100um, and the PAD point distance of the positive main grid corresponds to the two ends of the short positive sub-gate. The endpoint distance is 50-100um. 4. A solar cell according to claim 3, characterized in that there are printed lines with a width of 60-100um between the negative electrode main grid PAD points, the positive electrode main grid PAD points directly below and the surface of the silicon wafer. , solder paste with a thickness of 5-10um; Solder paste with a thickness of 3-5um, a width of 10-30um, and a length of 80-120um is printed between the negative main grid PAD point, the positive main grid PAD point and the sub-grid. 5. A solar cell according to claim 1, characterized in that the negative electrode main grid area is welded with a welding strip along its length direction, and the positive electrode main grid area is welded with a welding strip along its length direction; The width of the welding strip is 60-100um and the thickness is 200-270um. 6. A solar cell according to claim 1, characterized in that the negative electrode main grid region and the positive electrode main grid region are alternately arranged along a second direction perpendicular to the first direction, and the negative electrode main grid region The distance to two adjacent positive electrode main grid regions is equal. 7. A method for preparing a solar cell according to any one of claims 1 to 6, characterized in that it includes the following steps: Step 1: Print the secondary gate on the back of the silicon wafer; Step 2: Print solder paste on the negative main grid PAD point in the negative main grid area of the silicon wafer and on the positive main grid PAD point in the positive main grid area; use a steel mesh to paste the positive electrode on the negative main grid PAD point and the positive main grid PAD point. Print solder paste on all sub-gate positions below; Step 3: After the solder paste is dried, lay the solder ribbon directly above the positive main grid area and negative main grid area of the silicon wafer, use a pressing net to press the solder ribbon, and use laser spot welding technology to locally and rapidly heat the PAD point area. welding; Step 4: Use a laminator to heat and melt the solder strip at the non-PAD point and the auxiliary gate to form an alloy. 8. The preparation method of a solar cell according to claim 7, characterized in that, in step two, the solder paste is dried using an infrared lamp heating furnace, the drying temperature is 170-240°C, and the drying time is 15- 60s. 9. A method for preparing a solar cell according to claim 7, characterized in that in step three, laser spot welding technology is used to rapidly locally heat and weld the PAD point area, the welding temperature is 200-240°C, and the welding time is 1- 3s. 10. A method for preparing a solar cell according to claim 7, characterized in that in step four, the lamination temperature is set to 145-155°C, the lamination pressure is divided into three stages, and the first stage pressure is 10-20kp , the holding time is 10-30s, the second stage pressure is 40-50kp, the holding time is 10-30s, the third stage pressure is 70-80kp, the holding time is 600-800s.