CN117057305A - Wafer-level chip system architecture design method and device based on software and hardware cooperation - Google Patents

Abstract

The invention relates to the technical field of chip system architecture design, and discloses a wafer-level chip system architecture design method and device based on software and hardware cooperation. Based on double constraints of process characteristics and service characteristics, the invention aims at high robustness, high flexibility, high efficiency and the like, adopts a software and hardware collaborative design method, researches dynamic mapping and application evolution from a complex system macroscopic logic structure to a wafer-level circuit microscopic physical structure, and explores a design methodology of a wafer-level chip software and hardware collaborative system architecture.

Description

Wafer-level chip system architecture design method and device based on software and hardware collaboration

Technical field

The present invention relates to the technical field of chip system architecture design, and in particular to a wafer-level chip system architecture design method and device based on software and hardware collaboration.

Background technique

In 2017, the U.S. DARPA (Defense Advanced Research Projects Agency) planned a Chiplet project called "Common Heterogeneous Integration and IP Reuse Strategies (CHIPS)" in the "Electronics Renaissance Plan". Participants include Intel, Micron, Cadence, Synopsys, etc. It is a type of die that meets specific functions. We call it a module chip. Chiplet mode is a mode that uses die-to-die internal interconnection technology to package multiple module chips and underlying basic chips together to form a multi-functional heterogeneous System in Packages (SiPs) chip. In recent years, chiplet has become a hot word in the semiconductor industry. As Moore's Law approaches the physical limits of 7 nanometers, 3 nanometers, and 1 nanometer, the cost and development time required for process reduction will increase significantly. The post-Moore's Law era has arrived. Chiplet is one of several efforts made by the industry to make up for the slowdown in the growth of silicon process technology. It is considered to be the most effective solution to delay the failure of Moore's Law, slow down the process time, and support the continued development of the semiconductor industry.

Wafer-level chips have an order-of-magnitude doubling of resource scale. Physical failures of connections and functional units are inevitably introduced during production, processing, integration and other processes. System-level robustness and availability require that the architecture must be variable; wafer-level chips Integrating heterogeneous resources with different functions and mixed strengths, different tasks and different times will show highly dynamic characteristics of services. The high flexibility and high performance of system services must dynamically evolve the architecture. The design space exploration of the dynamic evolution architecture of wafer-level chips is the primary scientific problem to be solved. Currently, there is no on-chip system architecture design method for wafer-level chips.

Contents of the invention

Aiming at the problem that there is currently no on-chip system architecture design method for wafer-level chips, the present invention provides a wafer-level chip system architecture design method and device based on software and hardware collaboration, which are used to solve the problem of wafer-level chip system architecture design for specific fields (such as Encryption, decryption, deep learning, etc.) on-chip system optimization architecture design.

In order to achieve the above objects, the present invention adopts the following technical solutions:

On the one hand, the present invention proposes a wafer-level chip system architecture design device based on software and hardware collaboration, including a wafer-level chip architecture iterative design module, a compilation simulation platform building module, a simulation model library design module, and a heterogeneous simulation simulation platform. Build and simulate modules;

The wafer-level chip architecture iterative design module is used to complete the architectural design of the entire system-level development environment, guide the design of the compilation simulation platform and heterogeneous simulation platform, study the iterative optimization method of the architecture for wafer-level chips, and design Generate executable programs or configuration codes from algorithm input to the simulation platform, which simulates and outputs performance results, and optimizes the entire design process through iterative optimization; the designed architecture includes two parts: software architecture and hardware architecture, and The software architecture is delivered to the compilation simulation platform building module, and the hardware architecture is delivered to the simulation model library design module and heterogeneous simulation platform building and simulation modules;

The compilation simulation platform building module is used to build a software compiler framework based on the software architecture provided by the wafer-level chip architecture iterative design module to obtain a compilation simulation platform; and process the software architecture to deliver the construction of a heterogeneous simulation simulation platform and use of simulation modules;

The simulation model library design module is used to complete the design of the simulation model library. Specifically, it abstracts multiple models of wafer-level chips and builds models of typical application systems based on the hardware architecture provided by the wafer-level chip architecture iterative design module. And deliver the constructed computing model to the heterogeneous simulation platform construction and simulation module calling;

The heterogeneous simulation platform construction and simulation module are used to complete the construction of the basic simulation framework of the hardware simulation platform and obtain the heterogeneous simulation platform. Specifically, the hardware simulation platform foundation is based on the hardware architecture delivered by the wafer-level chip architecture iterative design module. The construction of the framework is based on the information delivered by the compilation simulation platform building module, and the simulation of the hardware part is realized by calling the computing model of the simulation model library design module and the operation of the basic simulation platform.

Further, it also includes a system verification and evaluation module; the system verification and evaluation module is used for system verification and evaluation based on the heterogeneous simulation platform construction and the simulation running results and performance power consumption data of the simulation module.

Further, the software architecture includes application programs and hardware resource detection information.

Further, in the hardware architecture, the wafer-level chip architecture iterative design module delivers calculation library construction guidance to the simulation model library design module, and provides overall architecture guidance for the hardware simulation environment for heterogeneous simulation simulation platform construction and simulation modules. .

Further, the compilation simulation platform building module is specifically used to receive the hardware resource detection information delivered by the wafer-level chip architecture iterative design module, perform resource mapping and task scheduling on the software compilation environment, and perform the wafer-level chip architecture iterative design. The application program input by the module is translated into the required target code and executable program, and delivered to the heterogeneous simulation platform for construction and simulation module use.

Further, the heterogeneous simulation platform construction and simulation module implements the hardware part by calling the calculation model of the simulation model library design module and the operation of the basic simulation platform according to the target code and executable program delivered by the compilation simulation platform construction module. simulation.

On the other hand, the present invention proposes a wafer-level chip system architecture design method based on software and hardware collaboration, including:

Step 1: The user selects the algorithm set, constraints, and constraint goals to be used;

Step 2: During initialization, intelligently extract different layout solutions that meet process constraints, and intelligently select optimization methods based on the iterative process;

Step 3: If the algorithm set is not empty, continue automatic compilation and scheduling of the algorithm, otherwise return the average execution time, throughput, and power consumption;

Step 4: The compilation and simulation platform compiles into executable code that can be recognized by the heterogeneous simulation platform based on the algorithm input by the user;

Step 5: The heterogeneous simulation platform receives the executable code generated in step 4, performs simulation execution, and feeds back the execution time, throughput, and power consumption of the current algorithm;

Step 6: If the optimization goal required by the user is achieved, the final system layout diagram is generated.

Further, the step 6 includes:

System verification and evaluation are performed based on simulation running results and performance and power consumption data.

Compared with the prior art, the present invention has the following beneficial effects:

Based on the dual constraints of process characteristics and service characteristics, this invention aims at high robustness, high flexibility, high efficiency, etc., and adopts software and hardware collaborative design methods to study the dynamic mapping of complex system macro logical structures to wafer-level circuit peripheral physical structures and Apply evolution to explore the design methodology of wafer-level chip software and hardware collaborative system architecture.

Description of the drawings

Figure 1 is a block diagram of a wafer-level chip system architecture design based on software and hardware collaboration according to an embodiment of the present invention;

Figure 2 is a flow chart of a wafer-level chip system architecture design based on software and hardware collaboration according to an embodiment of the present invention.

Detailed ways

The present invention will be further explained below in conjunction with the accompanying drawings and specific embodiments:

As shown in Figure 1, a wafer-level chip system architecture design device based on software and hardware collaboration includes a wafer-level chip architecture iterative design module (referred to as module 1), a compilation simulation platform building module (referred to as module 2) ), simulation model library design module (referred to as module 3), heterogeneous simulation platform construction and simulation module (referred to as module 4);

Module 1 mainly completes the architectural design of the entire system-level development environment, guides the design of the system compilation simulation platform and system simulation simulation platform, studies the iterative optimization method of the architecture for wafer-level chips, and designs the generation of executable programs or configuration codes from algorithm input. The simulation platform performs simulation and outputs performance results, and optimizes the entire design process through iterative optimization. The designed architecture includes two parts: software architecture and hardware architecture. Module 1 delivers the software architecture part to module 2, of which the final The main content is application-specific procedures. The hardware architecture part is delivered to modules 3 and 4. In the hardware architecture, module 1 will deliver computing library construction guidance for module 3, and provide overall architecture guidance for the hardware simulation environment for module 4.

Module 2 builds the software compiler framework based on the software architecture provided by module 1 to obtain a compilation simulation platform. Module 2 receives the hardware resource detection information delivered by module 1, performs resource mapping and task scheduling on the software compilation environment, and translates the application program input by module 1 into the required target code and executable program, and delivers it to module 4 for use to facilitate the system. simulation simulation;

Module 3 and module 4 jointly realize the design of the hardware simulation platform, which is used to equivalent the actual system hardware entity. Module 3 completes the design of the simulation model library. Based on the application hardware architecture provided by module 1, module 3 designs many models of wafer-level chips (mainly including some chiplets, such as Feiteng, Shenwei and other CPU dies, NMS3210, etc. Interconnect dies and storage chips, etc.) are abstracted and modeled with typical application systems (such as encryption and decryption, deep learning, etc.), and the constructed computing model is delivered to module 4 for calling.

Module 4 completes the construction of the basic simulation framework of the hardware simulation platform and obtains a heterogeneous simulation platform. Module 4 builds the basic framework of the hardware simulation platform based on the hardware architecture delivered by module 1 and supports the operation of basic simulation programs. Module 4 uses the target code and executable program delivered by module 2 to call the computing model and basic simulation of module 3. The operation of the platform realizes the simulation of the hardware part. The simulation operation results and performance and power consumption data of module 4 will be delivered to module 5 for system verification and evaluation.

On the other hand, the present invention also proposes a wafer-level chip system architecture design method based on software and hardware collaboration. The corresponding process is shown in Figure 2, including:

Step 1: The user selects the algorithm set he uses (such as md5, sha1, des and other algorithms in the field of encryption and decryption; CNN, RNN and other algorithms in deep learning) and constraints (such as 8-inch wafer), constraint goals ( Such as the shortest average execution time), etc.;

Step 2: During initialization, different layout plans that meet process constraints are intelligently extracted, and optimization methods can be intelligently selected based on the iterative process;

Step 3: If the algorithm set is not empty, continue automatic compilation and scheduling of the algorithm, otherwise return the average execution time, throughput, power consumption, etc.;

Step 4: The compilation and simulation platform compiles into executable code that can be recognized by the heterogeneous simulation platform based on the algorithm input by the user;

Step 5: The heterogeneous simulation platform receives the executable code generated in step 4, performs simulation execution, and feeds back the execution time of the current algorithm as well as parameters such as throughput and power consumption;

Step 6: If the optimization goal required by the user is achieved, the final system layout diagram is generated.

Further, the step 6 includes:

System verification and evaluation are performed based on simulation running results and performance and power consumption data.

In summary, the present invention is based on the dual constraints of process characteristics and service characteristics, aims at high robustness, high flexibility, and high efficiency, and uses software and hardware co-design methods to study the macroscopic logical structure of complex systems to the physical structure of wafer-level circuits. Dynamic mapping and application evolution, exploring the design methodology of wafer-level chip software and hardware collaborative system architecture.

What is shown above is only the preferred embodiment of the present invention. It should be pointed out that those skilled in the art can also make several improvements and modifications without departing from the principles of the present invention. These improvements and modifications can also be made. should be regarded as the protection scope of the present invention.

Claims (8)

1. A wafer-level chip system architecture design device based on software and hardware collaboration, which is characterized by including a wafer-level chip architecture iterative design module, a compilation simulation platform building module, a simulation model library design module, and heterogeneous simulation simulation Platform construction and simulation module; The wafer-level chip architecture iterative design module is used to complete the architectural design of the entire system-level development environment, guide the design of the compilation simulation platform and heterogeneous simulation platform, study the iterative optimization method of the architecture for wafer-level chips, and design Generate executable programs or configuration codes from algorithm input to the simulation platform, which simulates and outputs performance results, and optimizes the entire design process through iterative optimization; the designed architecture includes two parts: software architecture and hardware architecture, and The software architecture is delivered to the compilation simulation platform building module, and the hardware architecture is delivered to the simulation model library design module and heterogeneous simulation platform building and simulation modules; The compilation simulation platform building module is used to build a software compiler framework based on the software architecture provided by the wafer-level chip architecture iterative design module to obtain a compilation simulation platform; and process the software architecture to deliver the construction of a heterogeneous simulation simulation platform and use of simulation modules; The simulation model library design module is used to complete the design of the simulation model library. Specifically, it abstracts multiple models of wafer-level chips and builds models of typical application systems based on the hardware architecture provided by the wafer-level chip architecture iterative design module. And deliver the constructed computing model to the heterogeneous simulation platform construction and simulation module calling; The heterogeneous simulation platform construction and simulation module are used to complete the construction of the basic simulation framework of the hardware simulation platform and obtain the heterogeneous simulation platform. Specifically, the hardware simulation platform foundation is based on the hardware architecture delivered by the wafer-level chip architecture iterative design module. The construction of the framework is based on the information delivered by the compilation simulation platform building module, and the simulation of the hardware part is realized by calling the computing model of the simulation model library design module and the operation of the basic simulation platform. 2. The wafer-level chip system architecture design device based on software and hardware collaboration according to claim 1, characterized in that it also includes a system verification and evaluation module; the system verification and evaluation module is used to build and build a system based on a heterogeneous simulation platform. The simulation running results and performance and power consumption data of the simulation module are used for system verification and evaluation. 3. The wafer-level chip system architecture design device based on software and hardware collaboration according to claim 1, characterized in that the software architecture includes application programs and hardware resource detection information. 4. The wafer-level chip system architecture design device based on software and hardware collaboration according to claim 1, characterized in that, in the hardware architecture, the wafer-level chip architecture iterative design module is a simulation model library design module Deliver computing library construction guidance and provide overall architecture guidance for the hardware simulation environment for heterogeneous simulation platform construction and simulation modules. 5. The wafer-level chip system architecture design device based on software and hardware collaboration according to claim 3 or 4, characterized in that the compilation simulation platform building module is specifically used to receive a wafer-level chip architecture iterative design module The delivered hardware resource detection information performs resource mapping and task scheduling on the software compilation environment, and translates the application programs input by the wafer-level chip architecture iterative design module into the required target code and executable programs to deliver a heterogeneous simulation platform. Build and simulate module usage. 6. The wafer-level chip system architecture design device based on software and hardware collaboration according to claim 5, characterized in that the heterogeneous simulation platform construction and simulation module are compiled according to the target code delivered by the simulation platform construction module and The executable program realizes the simulation of the hardware part by calling the calculation model of the simulation model library design module and the operation of the basic simulation platform. 7. A wafer-level chip system architecture design method based on software and hardware collaboration, which is characterized by including: Step 1: The user selects the algorithm set, constraints, and constraint goals to be used; Step 2: During initialization, intelligently extract different layout solutions that meet process constraints, and intelligently select optimization methods based on the iterative process; Step 3: If the algorithm set is not empty, continue automatic compilation and scheduling of the algorithm, otherwise return the average execution time, throughput, and power consumption; Step 4: The compilation and simulation platform compiles into executable code that can be recognized by the heterogeneous simulation platform based on the algorithm input by the user; Step 5: The heterogeneous simulation platform receives the executable code generated in step 4, performs simulation execution, and feeds back the execution time, throughput, and power consumption of the current algorithm; Step 6: If the optimization goal required by the user is achieved, the final system layout diagram is generated. 8. A wafer-level chip system architecture design method based on software and hardware collaboration according to claim 7, characterized in that the step 6 includes: System verification and evaluation are performed based on simulation running results and performance and power consumption data.