CN116936679A - Solar cell, preparation method thereof and solar cell production equipment - Google Patents

Abstract

The invention relates to a solar cell, a preparation method thereof and solar cell production equipment. The preparation method sequentially deposits an intrinsic amorphous silicon layer, a doped microcrystalline silicon layer and a transparent conductive layer on a monocrystalline silicon wafer and comprises one or more of the following steps: carrying out first annealing treatment on the first silicon wafer before depositing the doped microcrystalline silicon layer; carrying out second annealing treatment on the second silicon wafer before depositing the transparent conductive layer; and carrying out third annealing treatment on the third silicon wafer. The preparation method can improve the photoelectric conversion efficiency of the battery.

Description

Solar cells and preparation methods thereof, solar cell production equipment

Technical field

The present invention relates to the field of photovoltaic technology, and in particular to a solar cell, a preparation method thereof, and solar cell production equipment.

Background technique

Heterojunction solar cells (HJT cells) include stacked monocrystalline silicon wafers, intrinsic amorphous silicon layers, doped microcrystalline silicon layers, transparent conductive layers and other structures. The preparation process of heterojunction solar cells includes cleaning and texturing, silicon-based film deposition, transparent conductive film deposition, and screen printing. The photoelectric conversion efficiency of cells prepared by traditional methods still needs to be improved.

Contents of the invention

Based on this, it is necessary to provide a solar cell, a preparation method thereof, and solar cell production equipment to improve the cell conversion efficiency.

A method for preparing a solar cell, including the following steps:

Deposit an intrinsic amorphous silicon layer on the single crystal silicon wafer to obtain the first silicon wafer;

Deposit a doped microcrystalline silicon layer on the intrinsic amorphous silicon layer to obtain a second silicon wafer;

Deposit a transparent conductive layer on the doped microcrystalline silicon layer to obtain a third silicon wafer;

The preparation method also includes one or more of the following steps:

Before depositing the doped microcrystalline silicon layer, performing a first annealing treatment on the first silicon wafer;

Before depositing the transparent conductive layer, perform a second annealing treatment on the second silicon wafer;

Perform a third annealing process on the third silicon wafer.

In one embodiment, the first annealing treatment is performed in a hydrogen atmosphere.

In one embodiment, in the first annealing process, the flow rate of hydrogen is 50 SLM to 80 SLM.

In one embodiment, the temperature of the first annealing treatment is 150°C to 180°C, and the time is 10min to 20min.

In one embodiment, the second annealing treatment is performed in a hydrogen atmosphere.

In one embodiment, in the second annealing process, the flow rate of hydrogen is 50 SLM to 80 SLM.

In one embodiment, the temperature of the second annealing treatment is 150°C to 180°C, and the time is 10min to 20min.

In one embodiment, the third annealing treatment is performed in a nitrogen atmosphere.

In one embodiment, in the third annealing process, the flow rate of nitrogen is 50 SLM to 80 SLM.

In one embodiment, the third annealing treatment has a temperature of 150°C to 180°C and a time of 10min to 20min.

In one embodiment, the intrinsic amorphous silicon layer is deposited by PECVD (Plasma Enhanced Chemical Vapor Deposition).

In one embodiment, the doped microcrystalline silicon layer is deposited by PECVD.

In one embodiment, the transparent conductive layer is deposited by PVD (physical vapor deposition process).

In one embodiment, the intrinsic amorphous silicon layer includes a first intrinsic layer and a second intrinsic layer respectively arranged on both sides of the single crystal silicon wafer, and the doped microcrystalline silicon layer includes An N-type doped layer on the first intrinsic layer and a P-type doped layer on the second intrinsic layer. The transparent conductive layer includes an N-type doped layer on the N-type doped layer. a first conductive layer and a second conductive layer disposed on the P-type doped layer.

In one of the embodiments, the preparation method further includes the following steps:

An electrode is formed on the transparent conductive layer.

A solar cell is prepared by the above preparation method.

A solar cell production equipment including a first deposition device, a second deposition device and a third deposition device;

The first deposition device is used to deposit an intrinsic amorphous silicon layer on a single crystal silicon wafer to obtain a first silicon wafer;

The second deposition device is used to deposit a doped microcrystalline silicon layer on the intrinsic amorphous silicon layer to obtain a second silicon wafer;

The third deposition device is used to deposit a transparent conductive layer on the doped microcrystalline silicon layer to obtain a third silicon wafer;

The solar cell production equipment further includes one or more of a first annealing device, a second annealing device, and a third annealing device;

The first annealing device is used to perform a first annealing treatment on the first silicon wafer before depositing the doped microcrystalline silicon layer;

The second annealing device is used to perform a second annealing treatment on the second silicon wafer before depositing the transparent conductive layer;

The third annealing device is used to perform a third annealing treatment on the third silicon wafer.

Compared with traditional solutions, the above-mentioned solar cells, their preparation methods, and solar cell production equipment have the following beneficial effects:

The above method for preparing a solar cell sequentially deposits an intrinsic amorphous silicon layer, a doped microcrystalline silicon layer and a transparent conductive layer on a single crystal silicon wafer, and includes one or more of the following steps: before depositing the doped microcrystalline silicon layer Before depositing the crystalline silicon layer, perform a first annealing treatment on the first silicon wafer; before depositing the transparent conductive layer, perform a second annealing treatment on the second silicon wafer; and perform a third annealing treatment on the third silicon wafer. Annealing treatment.

By performing the first annealing treatment on the first silicon wafer, it is conducive to the dangling bonds and defects on the surface of the intrinsic amorphous silicon layer to combine with free hydrogen. When the subsequent deposition of the doped microcrystalline silicon layer can effectively avoid P-type ions or The recombination of defects caused by the diffusion of N-type ions, and the unstable silicon-hydrogen bonds gain energy and rearrange, making the silicon-hydrogen bonds in the film layer more stable, thereby improving the passivation of the intrinsic amorphous silicon layer. The chemical effect increases the lifetime of minority carriers, thereby improving the open circuit voltage of the battery and improving the photoelectric conversion efficiency of the battery.

By performing a second annealing treatment on the second silicon wafer, similar to the first annealing treatment, the unstable silicon-hydrogen bonds in the doped microcrystalline silicon layer can gain energy and activate free hydrogen and weak silicon-hydrogen bonds to rearrange. , making the silicon-hydrogen bonds in the doped microcrystalline silicon layer more stable and improving the passivation effect. At the same time, after the second annealing treatment, the crystallinity of the doped microcrystalline silicon layer increases and the crystallization rate increases, thereby improving the conductivity of the doped microcrystalline silicon layer. Since the weak bonds on the surface of the doped microcrystalline silicon layer are broken and rearranged to form strong bonds, and the crystallization rate of the surface is increased, the surface is more stable and less likely to be damaged by particle bombardment during the subsequent deposition of the transparent conductive layer, which can further improve passivation. transformation effect. Therefore, the second annealing treatment can improve the open circuit voltage and fill factor of the solar cell, and improve the photoelectric conversion efficiency of the solar cell.

By performing the third annealing treatment on the third silicon wafer, the crystallinity of the deposited transparent conductive layer and the doped microcrystalline silicon layer is improved, and the crystallization rate is increased, thereby improving the conductivity of the deposited transparent conductive layer and the doped microcrystalline silicon layer. Ultimately improving the photoelectric conversion efficiency of solar cells.

The above-mentioned solar cell production equipment can perform the above-mentioned first annealing process, second annealing process and/or third annealing process, and thus can obtain corresponding technical effects.

Description of the drawings

Figure 1 is a schematic structural diagram of a solar cell according to an embodiment;

Figure 2 is a schematic flow chart of a method for manufacturing a solar cell according to an embodiment;

Figure 3 is a schematic structural diagram of solar cell production equipment according to an embodiment;

Figure 4 is a schematic structural diagram of the first module of the solar cell production equipment without the first annealing device;

Figure 5 is a schematic structural diagram of the first module of the solar cell production equipment equipped with the first annealing device;

Figure 6 is a schematic structural diagram of the first annealing device in the solar cell production equipment according to an embodiment;

Figure 7 is a schematic structural diagram of the second module of the solar cell production equipment without a second annealing device;

Figure 8 is a schematic structural diagram of the second module of the solar cell production equipment provided with the second annealing device;

Figure 9 is a schematic structural diagram of the second annealing device in the solar cell production equipment according to an embodiment;

Figure 10 is a schematic structural diagram of the third module of the solar cell production equipment without a third annealing device;

Figure 11 is a schematic structural diagram of the third module of solar cell production equipment equipped with a third annealing device;

Figure 12 is a schematic structural diagram of the third annealing device in the solar cell production equipment according to an embodiment.

Explanation of reference symbols:

100. Solar cell; 110. Monocrystalline silicon wafer; 120. Intrinsic amorphous silicon layer; 121. First intrinsic layer; 122. Second intrinsic layer; 130. Doped microcrystalline silicon layer; 131. N-type Doped layer; 132, P-type doped layer; 140, transparent conductive layer; 141, first conductive layer; 142, second conductive layer; 150, electrode; 151, first electrode; 152, second electrode; 200, Solar cell production equipment; 210, first deposition device; 211, first deposition chamber; 212, first preheating chamber; 220, second deposition device; 221, second deposition chamber; 222, third deposition chamber chamber; 223, the first discharging chamber; 224, the second preheating chamber; 225, the second discharging chamber; 230, the third deposition device; 231, the fourth deposition chamber; 232, the fifth deposition chamber chamber; 233. The third preheating chamber; 234. The third discharging chamber; 240. The first annealing device; 250. The second annealing device; 260. The third annealing device; 270. Isolation chamber; 241. An annealing chamber; 242, the first temperature control component; 243, the first horizontal transmission mechanism; 244, the first lifting transmission mechanism; 2441, the first vertical circulating conveyor belt; 2442, the first bracket; 251, the second annealing Chamber; 252, second temperature control component; 253, second horizontal transmission mechanism; 254, second lifting transmission mechanism; 2541, second vertical circulating conveyor belt; 2542, second bracket; 261, third annealing chamber ; 262. The third temperature control component; 263. The third horizontal transmission mechanism; 264. The third lifting transmission mechanism; 2641. The third vertical circulation conveyor belt; 2642. The third bracket.

Detailed ways

In order to facilitate understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that a thorough understanding of the present disclosure will be provided.

It should be noted that when an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is said to be "connected" to another element, it can be directly connected to the other element or there may also be intervening elements present. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only and do not represent the only implementation manner.

In the description of the present invention, it should be understood that the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features or order.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which the invention belongs. The terminology used herein in the description of the invention is for the purpose of describing specific embodiments only and is not intended to limit the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Please refer to Figures 1 and 2, a method 10 for manufacturing a solar cell 100 according to an embodiment of the present invention includes the following steps:

Step S1, deposit the intrinsic amorphous silicon layer 120 on the single crystal silicon wafer 110 to obtain the first silicon wafer;

Step S2, deposit a doped microcrystalline silicon layer 130 on the intrinsic amorphous silicon layer 120 to obtain a second silicon wafer;

Step S3: deposit the transparent conductive layer 140 on the doped microcrystalline silicon layer 130 to obtain a third silicon wafer.

In particular, the manufacturing method 10 of the solar cell 100 also includes one or more of the following steps S11 to S31:

Step S11, before depositing the doped microcrystalline silicon layer 130 (step S2), perform a first annealing treatment on the first silicon wafer;

Step S21, before depositing the transparent conductive layer 140 (step S3), perform a second annealing treatment on the second silicon wafer;

Step S31, perform a third annealing treatment on the third silicon wafer.

When depositing the doped microcrystalline silicon layer 130 , P-type ions or N-type ions in the doped microcrystalline silicon layer 130 will diffuse into the intrinsic amorphous silicon layer 120 , causing the intrinsic amorphous silicon layer 120 to passivate. The chemical effect is reduced, resulting in a low minority carrier lifetime, which in turn limits the increase in the open circuit voltage of the solar cell and affects the photoelectric conversion efficiency of the cell. And if the doped microcrystalline silicon layer 130 is deposited directly on the intrinsic amorphous silicon layer 120 after depositing the intrinsic amorphous silicon layer 120, the free hydrogen and unstable silicon hydrogen in the intrinsic amorphous silicon layer 120 will be The inability of the bonds to be activated and recombined will also affect the passivation performance of the intrinsic amorphous silicon layer 120, fail to improve the minority carrier lifetime of the silicon wafer, and affect the efficiency of the cell wafer.

In step S11, by performing the first annealing treatment on the first silicon wafer, it is beneficial for the dangling bonds and defects on the surface of the intrinsic amorphous silicon layer 120 to combine with free hydrogen. When the doped microcrystalline silicon layer 130 is subsequently deposited, it can Effectively avoid recombination caused by defects caused by the diffusion of P-type ions or N-type ions. Moreover, the unstable silicon-hydrogen bonds gain energy and rearrange, making the silicon-hydrogen bonds in the film layer more stable, thereby improving the passivation effect of the intrinsic amorphous silicon layer 120, increasing the minority carrier lifetime, and thus improving the battery. The open circuit voltage improves the photoelectric conversion efficiency of the battery.

In one example, the first annealing process is performed in a hydrogen atmosphere.

Performing the first annealing treatment in a hydrogen atmosphere can more effectively activate the free hydrogen in the intrinsic amorphous silicon layer 120 and combine it with defects and dangling bonds on the surface of the intrinsic amorphous silicon layer 120 to better protect the intrinsic amorphous silicon layer 120 . Amorphous silicon layer 120 is passivated. Compared with other gas atmospheres, in a hydrogen atmosphere, free hydrogen will not be released to the outside world, ensuring the hydrogen content of the intrinsic amorphous silicon layer 120. Therefore, through the first annealing treatment in the hydrogen atmosphere, it can be better The passivation performance of the intrinsic amorphous silicon layer 120 is greatly improved.

Further, in step S11, the flow rate of hydrogen during the first annealing process is 50SLM to 80SLM, specifically, for example, 50SLM, 55SLM, 60SLM, 65SLM, 70SLM, 75SLM, 80SLM, etc. An appropriate hydrogen gas flow rate can more effectively improve the effect of activating free hydrogen in the intrinsic amorphous silicon layer 120 and better prevent the release of free hydrogen to the outside world, thus ensuring the hydrogen content of the intrinsic amorphous silicon layer 120 .

Optionally, in step S11, the temperature of the first annealing treatment is 150°C to 180°C, specifically, for example, 150°C, 155°C, 160°C, 165°C, 170°C, 175°C, 180°C, etc.; the first annealing The treatment time is 10 min to 20 min, specific examples are 10 min, 12 min, 14 min, 16 min, 18 min, 20 min, etc. By optimizing the temperature, time and other conditions of the first annealing treatment, the dangling bonds and defects on the surface of the intrinsic amorphous silicon layer 120 are more effectively combined with free hydrogen, promoting the rearrangement of silicon-hydrogen bonds, and improving the efficiency of the first annealing treatment. Effect.

In step S21 , by performing a second annealing treatment on the second silicon wafer, similar to the first annealing treatment, the unstable silicon-hydrogen bonds in the doped microcrystalline silicon layer 130 can gain energy, and activate free hydrogen and weak The silicon-hydrogen bonds are rearranged, making the silicon-hydrogen bonds in the doped microcrystalline silicon layer 130 more stable and improving the passivation effect. At the same time, after the second annealing treatment, the crystallinity of the doped microcrystalline silicon layer 130 increases and the crystallization rate increases, thereby improving the conductivity of the doped microcrystalline silicon layer 130 .

Since the weak bonds on the surface of the doped microcrystalline silicon layer 130 are broken and rearranged to form strong bonds, and the crystallization rate of the surface is increased, the surface is more stable and is not easily destroyed by particle bombardment when the transparent conductive layer 140 is subsequently deposited, so that it can be further Improve passivation effect. Therefore, the second annealing treatment can improve the open circuit voltage and fill factor of the solar cell 100 and increase the photoelectric conversion efficiency of the solar cell 100 .

In one example, the second annealing process is performed under a hydrogen atmosphere.

Performing the second annealing treatment in a hydrogen atmosphere can more effectively activate the free hydrogen in the doped microcrystalline silicon layer 130 and combine it with defects and dangling bonds on the surface of the doped microcrystalline silicon layer 130 to better treat the intrinsic Amorphous silicon layer 120 is passivated. Compared with other gas atmospheres, in a hydrogen atmosphere, free hydrogen will not be released to the outside world, ensuring the hydrogen content of the doped microcrystalline silicon layer 130. Therefore, thermal annealing in a hydrogen atmosphere can better improve the Passivation properties of doped microcrystalline silicon layer 130 .

Optionally, in step S21, the flow rate of hydrogen during the second annealing process is 50SLM to 80SLM, specifically, for example, 50SLM, 55SLM, 60SLM, 65SLM, 70SLM, 75SLM, 80SLM, etc. An appropriate hydrogen gas flow rate can more effectively improve the effect of activating free hydrogen in the doped microcrystalline silicon layer 130 and better prevent the release of free hydrogen to the outside world, thus ensuring the hydrogen content of the doped microcrystalline silicon layer 130 .

Optionally, in step S21, the temperature of the second annealing treatment is 150°C to 180°C, specifically, for example, 150°C, 155°C, 160°C, 165°C, 170°C, 175°C, 180°C, etc.; the second annealing The treatment time is 10 min to 20 min, specific examples are 10 min, 12 min, 14 min, 16 min, 18 min, 20 min, etc. By optimizing the temperature, time and other conditions of the first annealing treatment, the dangling bonds and defects on the surface of the doped microcrystalline silicon layer 130 are more effectively combined with free hydrogen, promoting the rearrangement of silicon-hydrogen bonds and improving the efficiency of the second annealing treatment. Effect.

In step S31, by performing a third annealing treatment on the third silicon wafer, the crystallinity of the deposited transparent conductive layer 140 and the doped microcrystalline silicon layer 130 is improved, and the crystallization rate is increased, thereby improving the deposited transparent conductive layer 140 and the doped microcrystalline silicon layer 130. The conductivity of the microcrystalline silicon layer 130 ultimately improves the photoelectric conversion efficiency of the solar cell 100 .

In one example, the third annealing process is performed under a nitrogen atmosphere.

During the third annealing process in a nitrogen atmosphere, the crystallinity of the transparent conductive layer 140 changes. Due to the addition of nitrogen atoms, the crystal orientation of the transparent conductive layer 140 changes. The crystal orientation is selected in a better way, and the crystal grains become Large, the transmittance and conductivity of the transparent conductive layer 140 are improved. For the commonly used transparent conductive layer 140 made of ITO, annealing in a nitrogen atmosphere can stimulate the free oxygen atoms in the transparent conductive layer 140 to combine with In and Sn to produce an ideal chemical ratio of oxides, thereby improving the performance of the transparent conductive layer 140 The transmittance is high, and the reaction between oxygen in the air and In and Sn in the film layer is avoided, causing the film to be oxidized, resulting in a reduction in the conductivity of the film layer and a reduction in efficiency. Therefore, through the third annealing treatment, the short-circuit current and filling factor of the solar cell 100 can be improved, and the photoelectric conversion efficiency of the solar cell 100 can be improved.

Optionally, in step S31, the flow rate of nitrogen during the third annealing process is 50SLM to 80SLM, specifically, for example, 50SLM, 55SLM, 60SLM, 65SLM, 70SLM, 75SLM, 80SLM, etc. Appropriate nitrogen flow can better change the crystal orientation of the transparent conductive layer 140, improve the transmittance and conductivity of the transparent conductive layer 140, and prevent oxygen in the air from reacting with In and Sn in the film layer, thereby avoiding oxidation of the film.

Optionally, in step S31, the temperature of the third annealing treatment is 150°C to 180°C, specifically, for example, 150°C, 155°C, 160°C, 165°C, 170°C, 175°C, 180°C, etc.; the third annealing The treatment time is 10 min to 20 min, specific examples are 10 min, 12 min, 14 min, 16 min, 18 min, 20 min, etc. By optimizing the temperature, time and other conditions of the first annealing process, the crystallinity of the deposited transparent conductive layer 140 and the doped microcrystalline silicon layer 130 can be more effectively improved, and the effect of the third annealing process can be improved.

In one example, in step S1 , the intrinsic amorphous silicon layer 120 is deposited by PECVD (plasma enhanced chemical vapor deposition process).

In one example, in step S2 , the doped microcrystalline silicon layer 130 is deposited by PECVD.

In one example, in step S3, the transparent conductive layer 140 is deposited by PVD (physical vapor deposition process).

In one example, in step S1, the thickness of the intrinsic amorphous silicon layer 120 is 5 nm to 10 nm, specifically, it is 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, etc.

In one example, in step S2, the thickness of the doped microcrystalline silicon layer 130 is 10 nm to 30 nm, specifically, it is 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, etc.

In one example, in step S3, the thickness of the transparent conductive layer 140 is 95 nm to 105 nm, specifically, it is 95 nm, 98 nm, 100 nm, 102 nm, 104 nm, 105 nm, etc.

As shown in FIG. 1 , in one example, the intrinsic amorphous silicon layer 120 includes a first intrinsic layer 121 and a second intrinsic layer 122 respectively disposed on both sides of the single crystal silicon wafer 110 .

In one example, the doped microcrystalline silicon layer 130 includes an N-type doped layer 131 disposed on the first intrinsic layer 121 and a P-type doped layer 132 disposed on the second intrinsic layer 122 .

In one example, the transparent conductive layer 140 includes a first conductive layer 141 disposed on the N-type doped layer 131 and a second conductive layer 142 disposed on the P-type doped layer 132 .

In one example, the method of preparing the solar cell 100 further includes step S4 of forming the electrode 150 on the transparent conductive layer 140 .

In one example, the electrode 150 includes a first electrode 151 disposed on the first conductive layer 141 and a second electrode 152 disposed on the second conductive layer 142 .

In one example, in step S4, the electrode 150 is made by screen printing.

In one example, the solar cell preparation method 10 includes the following steps:

Step S1, deposit the intrinsic amorphous silicon layer 120 on the single crystal silicon wafer 110 to form the first intrinsic layer 121 and the second intrinsic layer 122 on both sides of the single crystal silicon wafer 110 to obtain the first silicon wafer;

Step S11, perform a first annealing treatment on the first silicon wafer in a hydrogen atmosphere;

Step S2, deposit a doped microcrystalline silicon layer 130 on the intrinsic amorphous silicon layer 120 to form an N-type doped layer 131 on the first intrinsic layer 121 and a P-type doped layer on the second intrinsic layer 122. Hybrid layer 132 to obtain the second silicon wafer;

Step S21, perform a second annealing treatment on the second silicon wafer in a hydrogen atmosphere;

Step S3, deposit the transparent conductive layer 140 on the doped microcrystalline silicon layer 130 to form the first conductive layer 141 on the N-type doped layer 131, and form the second conductive layer 142 on the P-type doped layer 132 to obtain third silicon wafer;

Step S31, perform a third annealing treatment on the third silicon wafer under a nitrogen atmosphere;

Step S4, prepare the first electrode 151 on the first conductive layer 141, and prepare the second electrode 152 on the second conductive layer 142.

Furthermore, the present invention also provides a solar cell, which is prepared by the preparation method of any of the above examples.

The above-mentioned solar cells may be, but are not limited to, heterojunction cells.

Further, as shown in FIG. 3 , the present invention also provides a solar cell production equipment 200 including a first deposition device 210 , a second deposition device 220 and a third deposition device 230 .

The first deposition device 210 is used to deposit the intrinsic amorphous silicon layer 120 on the single crystal silicon wafer 110 to obtain the first silicon wafer. The second deposition device 220 is used to deposit the doped microcrystalline silicon layer 130 on the intrinsic amorphous silicon layer 120 to obtain a second silicon wafer. The third deposition device 230 is used to deposit the transparent conductive layer 140 on the doped microcrystalline silicon layer 130 to obtain a third silicon wafer.

The solar cell production equipment 200 also includes one or more of a first annealing device 240, a second annealing device 250, and a third annealing device 260.

The first annealing device 240 is used to perform a first annealing treatment on the first silicon wafer before depositing the doped microcrystalline silicon layer 130 . The second annealing device 250 is used to perform a second annealing treatment on the second silicon wafer before depositing the transparent conductive layer 140 . The third annealing device 260 is used to perform a third annealing treatment on the third silicon wafer.

The above-mentioned solar cell production equipment 200 can perform the above-mentioned first annealing process, second annealing process and/or third annealing process, and thus can obtain corresponding technical effects.

It can be understood that the first deposition device 210, the first annealing device 240, the second deposition device 220, the second annealing device 250, the third deposition device 230 and the third annealing device 260 may be a continuous integrated design or may be segmented. modular design.

FIG. 4 shows the structure of the first module of the solar cell production equipment 200 without the first annealing device. FIG. 5 shows the structure of the first module of the solar cell production equipment 200 provided with the first annealing device 240.

In one example, the first deposition device 210 includes a first deposition chamber 211 . Further, the first deposition device 210 may also include a first preheating chamber 212 . The first preheating chamber 212 is used to preheat the single crystal silicon wafer 110, and the first deposition chamber 211 is used to deposit the intrinsic amorphous silicon layer 120 on the preheated single crystal silicon wafer 110 to obtain the first silicon wafer. It can be understood that the first intrinsic layer 121 and the second intrinsic layer 122 can be deposited and formed simultaneously in the first deposition chamber 211 .

In one example, an isolation chamber 270 is provided between the first deposition device 210 and the second deposition device 220 . More specifically, an isolation chamber 270 is provided between the first deposition chamber 211 and the second deposition device 220 .

As shown in FIG. 4 , there is no first annealing device between the first deposition device 210 and the second deposition device 220 , and the first silicon wafer output from the first deposition chamber 211 is input into the isolation chamber 270 to wait without being processed. The first annealing process is then input into the second deposition device 220 to deposit the doped microcrystalline silicon layer 130 .

As shown in FIG. 5 , a first annealing device 240 is provided between the first deposition device 210 and the second deposition device 220 , and the first annealing device 240 is provided between the first deposition chamber 211 and the isolation chamber 270 .

As shown in FIG. 6 , in one example, the first annealing device 240 includes a first annealing chamber 241 , a first temperature control component 242 and a first loading component. The first loading component is disposed in the first annealing chamber 241 for loading the first silicon wafer to pass through the first annealing chamber 241. At the same time, the first loading component can also buffer the first silicon wafer to meet the production cycle. The first temperature control component 242 is used to control the temperature in the first annealing chamber 241.

In one example, the first loading component includes a first horizontal transmission mechanism 243 and a first lifting transmission mechanism 244 . The first lifting and conveying mechanism 244 is used to carry the first silicon wafer and lift the first silicon wafer. The first lifting and conveying mechanism 244 includes a pair of first vertical circulating conveyor belts 2441, and a plurality of first brackets 2442 are distributed on the first vertical circulating conveyor belts 2441. The first brackets 2442 on the two first vertical circulating conveyor belts 2441 are arranged in pairs for cooperatively carrying the first silicon wafers. The plurality of pairs of first brackets 2442 can respectively carry a plurality of first silicon wafers.

The first horizontal transfer mechanism 243 is used to transport the first silicon wafer to be subjected to the first annealing process to the first bracket 2442 located at the lower end. As the first annealing process proceeds, the first lifting transfer mechanism 244 transfers a plurality of The first silicon wafer is gradually raised. The first horizontal transfer mechanism 243 is also used to transport the first silicon wafer located at the upper end out of the first annealing chamber 241 . By controlling the operating speed of the first lifting and lowering transfer mechanism 244, the first annealing process is completed when the first silicon wafer reaches the first horizontal transfer mechanism 243 at the upper end. The first horizontal transfer mechanism 243 has a telescopic carrying component that can extend or retract to realize the transfer of the first silicon wafer between the first lifting transfer mechanism 244 and the first horizontal transfer mechanism 243 .

In one example, first temperature control component 242 includes a heating plate. The heating plate may be disposed on the inner wall of the first annealing chamber 241. The number of heating plates may be multiple. For example, heating plates may be provided on the top wall, bottom wall, and side wall of the first annealing chamber 241 respectively.

Further, in one example, the first annealing device 240 further includes a first ventilation component (not shown in the figure) and a first vacuum component (not shown in the figure). The first ventilation component is connected to the first annealing chamber 241 and is used to introduce gas, such as hydrogen, into the first annealing chamber 241 . The first vacuuming component is connected to the first annealing chamber 241 for evacuating the first annealing chamber 241 .

FIG. 7 shows the structure of the second module of the solar cell production equipment 200 without the second annealing device. FIG. 8 shows the structure of the second module of the solar cell production equipment 200 provided with the second annealing device 250.

In one example, the second deposition device 220 includes a second deposition chamber 221 and a third deposition chamber 222 . The second deposition chamber 221 is used to deposit the N-type doped layer 131 on the first intrinsic layer 121 , and the third deposition chamber 222 is used to deposit the P-type doped layer 132 on the second intrinsic layer 122 .

In one example, a first discharging chamber 223 is provided downstream of the second deposition chamber 221 . After the N-type doping layer 131 is deposited on the first silicon wafer, it is discharged through the first discharge chamber 223 . The second deposition chamber 221 and the first discharging chamber 223 may be provided in the first module.

In one example, a second preheating chamber 224 is provided upstream of the third deposition chamber 222 . After the N-type doping layer 131 is deposited on the first silicon wafer, it is input into the second preheating chamber 224 for preheating. After preheating, it is input into the third deposition chamber 222 to deposit the P-type doping layer 132 to obtain the second silicon wafer. piece.

In one example, a second discharging chamber 225 is provided downstream of the third deposition chamber 222 . The second silicon wafer is discharged through the second discharge chamber 225 .

As shown in FIG. 7 , the solar cell production equipment 200 is not provided with a second annealing device, and the second silicon wafer output from the third deposition chamber 222 is discharged through the second discharging chamber 225 .

As shown in FIG. 8 , the solar cell production equipment 200 is provided with a second annealing device 250 , and the second annealing device 250 is located between the third deposition chamber 222 and the second discharging chamber 225 . The second silicon wafer output from the third deposition chamber 222 is input into the second annealing device 250 for a second annealing treatment, and then is discharged through the second discharging chamber 225 .

As shown in FIG. 9 , in one example, the second annealing device 250 includes a second annealing chamber 251 , a second temperature control component 252 and a second loading component. The second loading component is disposed in the second annealing chamber 251 for loading the second silicon wafer to pass through the second annealing chamber 251. At the same time, the second loading component can also buffer the second silicon wafer to meet the production cycle. The second temperature control component 252 is used to control the temperature in the second annealing chamber 251.

In one example, the second loading component includes a second horizontal conveying mechanism 253 and a second lifting conveying mechanism 254 . The second lifting and conveying mechanism 254 is used to carry the second silicon wafer and lift the second silicon wafer. The second lifting and conveying mechanism 254 includes a pair of second vertical circulating conveyor belts 2541, and a plurality of second brackets 2542 are distributed on the second vertical circulating conveyor belts 2541. The second brackets 2542 on the two second vertical circulating conveyor belts 2541 are arranged in pairs for cooperatively carrying the second silicon wafers. The plurality of pairs of second brackets 2542 can respectively carry a plurality of second silicon wafers.

The second horizontal transfer mechanism 253 is used to transport the second silicon wafer to be subjected to the second annealing process to the second bracket 2542 located at the lower end. As the second annealing process proceeds, the second lifting transfer mechanism 254 transfers a plurality of The second silicon wafer gradually lifts up. The second horizontal transfer mechanism 253 is also used to transport the second silicon wafer located at the upper end out of the second annealing chamber 251 . By controlling the operating speed of the second lifting and lowering transfer mechanism 254, the second annealing process is completed when the second silicon wafer reaches the second horizontal transfer mechanism 253 at the upper end. The second horizontal transfer mechanism 253 has a telescopic carrying component that can extend or retract to realize the transfer of the second silicon wafer between the second lifting transfer mechanism 254 and the second horizontal transfer mechanism 253 .

In one example, the second temperature control component 252 includes a heating plate. The heating plate may be disposed on the inner wall of the second annealing chamber 251. The number of heating plates may be multiple. For example, heating plates may be provided on the top wall, bottom wall, and side wall of the second annealing chamber 251 respectively.

Further, in one example, the second annealing device 250 further includes a second ventilation component (not shown in the figure) and a second vacuuming component (not shown in the figure). The second ventilation component is connected to the second annealing chamber 251 and is used to introduce gas, such as hydrogen, into the second annealing chamber 251 . The second vacuuming component is connected to the second annealing chamber 251 for evacuating the second annealing chamber 251 .

FIG. 10 shows the structure of the third module of the solar cell production equipment 200 without the third annealing device. FIG. 11 shows the structure of the third module of the solar cell production equipment 200 provided with the third annealing device 260.

In one example, the third deposition device 230 includes a fourth deposition chamber 231 and a fifth deposition chamber 232 . The fourth deposition chamber 231 is used to deposit the first conductive layer 141 on the N-type doped layer 131 , and the fifth deposition chamber 232 is used to deposit the second conductive layer 142 on the P-type doped layer 132 . The fourth deposition chamber 231 and the fifth deposition chamber 232 are connected.

In one example, the third deposition device 230 further includes a third preheating chamber 233 located upstream of the fourth deposition chamber 231 and the fifth deposition chamber 232 . In one example, the third deposition device 230 further includes a third discharging chamber 234 located downstream of the fourth deposition chamber 231 and the fifth deposition chamber 232 .

As shown in FIG. 10 , the solar cell production equipment 200 is not provided with a third annealing device, and the third silicon wafer output from the fifth deposition chamber 232 is discharged through the third discharging chamber 234 .

As shown in Figure 11, the solar cell production equipment 200 is provided with a third annealing device 260. The third silicon wafer output from the fifth deposition chamber 232 is input into the third annealing device 260 for the third annealing treatment, and then passes through the third discharging process. Chamber 234 discharges material.

As shown in FIG. 12 , in one example, the third annealing device 260 includes a third annealing chamber 261 , a third temperature control component 262 and a third loading component. The third loading component is disposed in the third annealing chamber 261 for loading the third silicon wafer to pass through the third annealing chamber 261. At the same time, the third loading component can also buffer the third silicon wafer to meet the production cycle. The third temperature control component 262 is used to control the temperature in the third annealing chamber 261.

In one example, the third loading component includes a third horizontal conveying mechanism 263 and a third lifting conveying mechanism 264 . The third lifting and conveying mechanism 264 is used to carry the third silicon wafer and lift the third silicon wafer. The third lifting and conveying mechanism 264 includes a pair of third vertical circulating conveyor belts 2641, and a plurality of third brackets 2642 are distributed on the third vertical circulating conveyor belts 2641. The third brackets 2642 on the two third vertical circulating conveyor belts 2641 are arranged in pairs for cooperatively carrying the third silicon wafers. The plurality of pairs of third brackets 2642 can respectively carry a plurality of third silicon wafers.

The third horizontal transfer mechanism 263 is used to transport the third silicon wafer to be subjected to the third annealing process to the third bracket 2642 located at the lower end. As the third annealing process proceeds, the third lifting transfer mechanism 264 transfers a plurality of The third silicon wafer gradually lifts up. The third horizontal transfer mechanism 263 is also used to transport the third silicon wafer located at the upper end out of the third annealing chamber 261 . By controlling the operating speed of the third lifting and conveying mechanism 264, the third annealing process is completed when the third silicon wafer reaches the third horizontal conveying mechanism 263 at the upper end. The third horizontal transfer mechanism 263 has a telescopic carrying component that can extend or retract to realize the transfer of the third silicon wafer between the third lifting transfer mechanism 264 and the third horizontal transfer mechanism 263 .

In one example, third temperature control component 262 includes a heating plate. The heating plate may be disposed on the inner wall of the third annealing chamber 261. The number of heating plates may be multiple. For example, heating plates may be provided on the top wall, bottom wall, and side wall of the third annealing chamber 261 respectively.

Further, in one example, the third annealing device 260 further includes a third ventilation component (not shown in the figure) and a third vacuuming component (not shown in the figure). The third ventilation component is connected to the third annealing chamber 261 for introducing gas, such as nitrogen, into the third annealing chamber 261 . The third vacuuming component is connected to the third annealing chamber 261 for evacuating the third annealing chamber 261 .

Specific examples are provided below to further illustrate the present invention.

Example 1

The method for preparing a solar cell provided in this embodiment includes the following steps:

Step 1: Provide an N-type monocrystalline silicon wafer with a thickness of 150 μm and perform surface texturing and cleaning treatment.

Step 2: Deposit intrinsic amorphous silicon layer coatings on both sides of the N-type single crystal silicon wafer through a PECVD process to form a first intrinsic layer and a second intrinsic layer to obtain a first silicon wafer.

Step 3: Perform the first annealing treatment on the above-mentioned first silicon wafer in a hydrogen atmosphere. The flow rate of hydrogen is 70 SLM, the annealing temperature is 160°C, and the annealing time is 15 minutes.

Step 4: Deposit a doped microcrystalline silicon layer on the first silicon wafer that has undergone the first annealing treatment through a PECVD process to form an N-type doped layer on the first intrinsic layer and an N-type doped layer on the second intrinsic layer. P-type doped layer to obtain the second silicon wafer.

Step 5: Deposit an ITO transparent conductive layer on the second silicon wafer through a magnetron sputtering process to form a first conductive layer on the N-type doped layer and a second conductive layer on the P-type doped layer to obtain The third silicon wafer.

Step 6: Use a screen printing process to screen silver paste on the third silicon wafer and solidify it to form a first electrode on the first conductive layer and a second electrode on the second conductive layer.

Example 2

The method for preparing a solar cell provided in this embodiment includes the following steps:

Step 1: Provide an N-type monocrystalline silicon wafer with a thickness of 150 μm and perform surface texturing and cleaning treatment.

Step 2: Deposit intrinsic amorphous silicon layer coatings on both sides of the N-type single crystal silicon wafer through a PECVD process to form a first intrinsic layer and a second intrinsic layer to obtain a first silicon wafer.

Step 3: Perform the first annealing treatment on the above-mentioned first silicon wafer in a hydrogen atmosphere. The flow rate of hydrogen is 70 SLM, the annealing temperature is 160°C, and the annealing time is 15 minutes.

Step 4: Deposit a doped microcrystalline silicon layer on the first silicon wafer that has undergone the first annealing treatment through a PECVD process to form an N-type doped layer on the first intrinsic layer and an N-type doped layer on the second intrinsic layer. P-type doped layer to obtain the second silicon wafer.

Step 5: The above-mentioned second silicon wafer is subjected to a second annealing process in a hydrogen atmosphere. The flow rate of hydrogen is 70 SLM, the annealing temperature is 160°C, and the annealing time is 15 minutes.

Step 6: Deposit an ITO transparent conductive layer on the second silicon wafer that has undergone the second annealing treatment through a magnetron sputtering process to form a first conductive layer on the N-type doped layer and a first conductive layer on the P-type doped layer. The second conductive layer is used to obtain the third silicon wafer.

Step 7: Use a screen printing process to screen silver paste on the third silicon wafer and solidify it to form a first electrode on the first conductive layer and a second electrode on the second conductive layer.

Example 3

The method for preparing a solar cell provided in this embodiment includes the following steps:

Step 1: Provide an N-type monocrystalline silicon wafer with a thickness of 150 μm and perform surface texturing and cleaning treatment.

Step 2: Deposit intrinsic amorphous silicon layer coatings on both sides of the N-type single crystal silicon wafer through a PECVD process to form a first intrinsic layer and a second intrinsic layer to obtain a first silicon wafer.

Step 3: Perform the first annealing treatment on the above-mentioned first silicon wafer in a hydrogen atmosphere. The flow rate of hydrogen is 70 SLM, the annealing temperature is 160°C, and the annealing time is 15 minutes.

Step 4: Deposit a doped microcrystalline silicon layer on the first silicon wafer that has undergone the first annealing treatment through a PECVD process to form an N-type doped layer on the first intrinsic layer and an N-type doped layer on the second intrinsic layer. P-type doped layer to obtain the second silicon wafer.

Step 5: The above-mentioned second silicon wafer is subjected to a second annealing process in a hydrogen atmosphere. The flow rate of hydrogen is 70 SLM, the annealing temperature is 160°C, and the annealing time is 15 minutes.

Step 6: Deposit an ITO transparent conductive layer on the second silicon wafer that has undergone the second annealing treatment through a magnetron sputtering process to form a first conductive layer on the N-type doped layer and a first conductive layer on the P-type doped layer. The second conductive layer is used to obtain the third silicon wafer.

Step 7: Perform the third annealing treatment on the above-mentioned third silicon wafer in a nitrogen atmosphere. The flow rate of the nitrogen gas is 70 SLM, the annealing temperature is 170°C, and the annealing time is 15 minutes.

Step 8: Use a screen printing process to screen silver paste on the third silicon wafer that has undergone the third annealing treatment and solidify it to form a first electrode on the first conductive layer and a second electrode on the second conductive layer.

Comparative example 1

The difference between the preparation method of the solar cell in this comparative example and Example 1 is that the first annealing treatment, the second annealing treatment and the third annealing treatment are not performed during the preparation process.

The solar cells prepared in the above Example 1 and Comparative Example 1 were subjected to electrical performance testing. The test results are shown in Table 1, and the test data were normalized.

Table 1 Electrical properties of solar cells of Example 1 and Comparative Example 1 (data after normalization)

It can be seen from the results in Table 1 that compared with Comparative Example 1, the conversion efficiency Eta of the solar cell prepared in Example 1 increased by 0.15%, the short-circuit current Isc decreased by 0.01%, the open-circuit voltage Voc increased by 0.07%, and the fill factor FF increased by 0.10 %, the series resistance is reduced by 0.80%.

Compared with Comparative Example 1, the solar cell prepared in Example 2 has the conversion efficiency Eta increased by 0.48%, the short-circuit current Isc increased by 0.02%, the open-circuit voltage Voc increased by 0.12%, the fill factor FF increased by 0.34%, and the series resistance was reduced. 4.78%.

Compared with Comparative Example 1, the solar cell prepared in Example 3 has the conversion efficiency Eta increased by 0.81%, the short-circuit current Isc increased by 0.07%, the open-circuit voltage Voc increased by 0.17%, the fill factor FF increased by 0.57%, and the series resistance was reduced. 12.24%. Generally speaking, Embodiment 3 has the best effect.

From the perspective of short-circuit current Isc, Example 3 increased by 0.07% compared with Comparative Example 1, indicating that through the third annealing treatment, free oxygen atoms in the ITO film are combined with In and Sn to produce an oxide with an ideal chemical ratio. This increases the transmittance of the ITO film and increases the short-circuit current.

From the perspective of open circuit voltage Voc, Example 3 increased by 0.17% compared with Comparative Example 1, indicating that through the first annealing treatment, the second annealing treatment and the third annealing treatment, the passivation performance of the film layer was improved, and the open circuit voltage was improved. Voltage.

From the perspective of filling factor FF, Example 3 increased by 0.57% compared to Comparative Example 1, indicating that the crystallinity of the doped microcrystalline silicon layer and the transparent conductive layer can be improved through the second annealing treatment and the third annealing treatment, so that The conductivity of the film layer is improved, which reduces the series resistance and increases the fill factor.

The technical features of the above-described embodiments can be combined in any way. To simplify the description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, All should be considered to be within the scope of this manual.

The above-mentioned embodiments only express several implementation modes of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention. It should be noted that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the scope of protection of the patent of the present invention should be determined by the appended claims.

Claims (15)

1. A method of manufacturing a solar cell, comprising the steps of:

depositing an intrinsic amorphous silicon layer on a monocrystalline silicon wafer to obtain a first silicon wafer;

depositing a doped microcrystalline silicon layer on the intrinsic amorphous silicon layer to obtain a second silicon wafer;

depositing a transparent conductive layer on the doped microcrystalline silicon layer to obtain a third silicon wafer;

the preparation method further comprises one or more of the following steps:

carrying out first annealing treatment on the first silicon wafer before depositing the doped microcrystalline silicon layer;

carrying out second annealing treatment on the second silicon wafer before depositing the transparent conductive layer;

and carrying out third annealing treatment on the third silicon wafer.

2. The method for producing a solar cell according to claim 1, wherein the first annealing treatment is performed under a hydrogen atmosphere.

3. The method of manufacturing a solar cell according to claim 1, wherein the flow rate of hydrogen in the first annealing treatment is 50SLM to 80SLM.

4. The method for producing a solar cell according to any one of claims 1 to 3, wherein the temperature of the first annealing treatment is 150 to 180 ℃ for 10 to 20 minutes.

5. The method for producing a solar cell according to claim 1, wherein the second annealing treatment is performed under a hydrogen atmosphere.

6. The method of manufacturing a solar cell according to claim 1, wherein the flow rate of hydrogen in the second annealing treatment is 50SLM to 80SLM.

7. The method of any one of claims 1, 5, and 6, wherein the second annealing treatment is performed at a temperature of 150 ℃ to 180 ℃ for a time of 10min to 20min.

8. The method for producing a solar cell according to claim 1, wherein the third annealing treatment is performed under a nitrogen atmosphere.

9. The method of manufacturing a solar cell according to claim 1, wherein the flow rate of nitrogen gas in the third annealing treatment is 50SLM to 80SLM.

10. The method for producing a solar cell according to any one of claims 1 to 3, 5, 6, 8, and 9, wherein the temperature of the third annealing treatment is 150 to 180 ℃ for 10 to 20 minutes.

11. The method of manufacturing a solar cell according to any one of claims 1 to 3, 5, 6, 8, 9, wherein the intrinsic amorphous silicon layer is deposited by PECVD; and/or

The mode of depositing the doped microcrystalline silicon layer is PECVD; and/or

The transparent conductive layer is deposited by PVD.

12. The method of any one of claims 1 to 3, 5, 6, 8, 9, wherein the intrinsic amorphous silicon layer comprises a first intrinsic layer and a second intrinsic layer disposed on both sides of the single crystal silicon wafer, the doped microcrystalline silicon layer comprises an N-type doped layer disposed on the first intrinsic layer and a P-type doped layer disposed on the second intrinsic layer, and the transparent conductive layer comprises a first conductive layer disposed on the N-type doped layer and a second conductive layer disposed on the P-type doped layer.

13. The method of manufacturing a solar cell according to any one of claims 1 to 3, 5, 6, 8, 9, further comprising the steps of:

and manufacturing an electrode on the transparent conductive layer.

14. A solar cell prepared by the preparation method of any one of claims 1 to 13.

15. A solar cell production apparatus, characterized by comprising a first deposition device, a second deposition device, and a third deposition device;

the first deposition device is used for depositing an intrinsic amorphous silicon layer on the monocrystalline silicon piece to obtain a first silicon piece;

the second deposition device is used for depositing a doped microcrystalline silicon layer on the intrinsic amorphous silicon layer to obtain a second silicon wafer;

the third deposition device is used for depositing a transparent conductive layer on the doped microcrystalline silicon layer to obtain a third silicon wafer;

the solar cell production equipment further comprises one or more of a first annealing device, a second annealing device and a third annealing device;

the first annealing device is used for carrying out first annealing treatment on the first silicon wafer before the doped microcrystalline silicon layer is deposited;

the second annealing device is used for carrying out second annealing treatment on the second silicon wafer before the transparent conductive layer is deposited;

and the third annealing device is used for carrying out third annealing treatment on the third silicon wafer.